include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 enum {
  36         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  37         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  38         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  39         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  40         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  41         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  42         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  43         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  44         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  45         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  46         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  47         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  48         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  49         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  50         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  51         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  52         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  53         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  54         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  56         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  57         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  58         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  59         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
  60 };
  61
  62 enum {
  63         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  64         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  65         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  66         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  67 };
  68
  69 enum {
  70         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  71         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  72 };
  73
  74 enum {
  75         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  76         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  77         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  78         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  79         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  80         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  81         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  82         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  83         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  84         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  85         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  86         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  87         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  88         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  89         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  90         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  91         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  92         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  93         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  94         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  95         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
  96         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
  97         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
  98         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
  99         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 100         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 101         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 102         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 103         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 104         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 105         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 106         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 107         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 108         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 109         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 110         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 111         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 112         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 113         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 114         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 115         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 116         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 117         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 118         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 119         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 120         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 121         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 122         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 123         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 124         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 125         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 126         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 127         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 128         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 129         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 130         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 131         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 132         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 133         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 134         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 135         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 136         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 137         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 138         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 139         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 140         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 141         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 142         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 143         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 144         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 145         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 146         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 147         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 148         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 149         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 150         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 151         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 152         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 153         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 154         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 155         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 156         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 157         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 158         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 159         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 160         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 161         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 162         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 163         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 164         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 165         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 166         MLX5_CMD_OP_NOP                           = 0x80d,
 167         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 168         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 169         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 170         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 171         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 172         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 173         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 174         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 175         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 176         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 177         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 178         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 179         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 180         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 181         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 182         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 183         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 184         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 185         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 186         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 187         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 188         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 189         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 190         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 191         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 192         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 193         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 194         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 195         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 196         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 197         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 198         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 199         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 200         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 201         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 202         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 203         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 204         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 205         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 206         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 207         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 208         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 209         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 210         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 211         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 212         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 213         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 214         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 215         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 216         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 217         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 218         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 219         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 220         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 221         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 222         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 223         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 224         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 225         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 226         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 227         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 228         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 229         MLX5_CMD_OP_MAX
 230 };
 231
 232 struct mlx5_ifc_flow_table_fields_supported_bits {
 233         u8         outer_dmac[0x1];
 234         u8         outer_smac[0x1];
 235         u8         outer_ether_type[0x1];
 236         u8         reserved_at_3[0x1];
 237         u8         outer_first_prio[0x1];
 238         u8         outer_first_cfi[0x1];
 239         u8         outer_first_vid[0x1];
 240         u8         reserved_at_7[0x1];
 241         u8         outer_second_prio[0x1];
 242         u8         outer_second_cfi[0x1];
 243         u8         outer_second_vid[0x1];
 244         u8         reserved_at_b[0x1];
 245         u8         outer_sip[0x1];
 246         u8         outer_dip[0x1];
 247         u8         outer_frag[0x1];
 248         u8         outer_ip_protocol[0x1];
 249         u8         outer_ip_ecn[0x1];
 250         u8         outer_ip_dscp[0x1];
 251         u8         outer_udp_sport[0x1];
 252         u8         outer_udp_dport[0x1];
 253         u8         outer_tcp_sport[0x1];
 254         u8         outer_tcp_dport[0x1];
 255         u8         outer_tcp_flags[0x1];
 256         u8         outer_gre_protocol[0x1];
 257         u8         outer_gre_key[0x1];
 258         u8         outer_vxlan_vni[0x1];
 259         u8         reserved_at_1a[0x5];
 260         u8         source_eswitch_port[0x1];
 261
 262         u8         inner_dmac[0x1];
 263         u8         inner_smac[0x1];
 264         u8         inner_ether_type[0x1];
 265         u8         reserved_at_23[0x1];
 266         u8         inner_first_prio[0x1];
 267         u8         inner_first_cfi[0x1];
 268         u8         inner_first_vid[0x1];
 269         u8         reserved_at_27[0x1];
 270         u8         inner_second_prio[0x1];
 271         u8         inner_second_cfi[0x1];
 272         u8         inner_second_vid[0x1];
 273         u8         reserved_at_2b[0x1];
 274         u8         inner_sip[0x1];
 275         u8         inner_dip[0x1];
 276         u8         inner_frag[0x1];
 277         u8         inner_ip_protocol[0x1];
 278         u8         inner_ip_ecn[0x1];
 279         u8         inner_ip_dscp[0x1];
 280         u8         inner_udp_sport[0x1];
 281         u8         inner_udp_dport[0x1];
 282         u8         inner_tcp_sport[0x1];
 283         u8         inner_tcp_dport[0x1];
 284         u8         inner_tcp_flags[0x1];
 285         u8         reserved_at_37[0x9];
 286
 287         u8         reserved_at_40[0x40];
 288 };
 289
 290 struct mlx5_ifc_flow_table_prop_layout_bits {
 291         u8         ft_support[0x1];
 292         u8         reserved_at_1[0x1];
 293         u8         flow_counter[0x1];
 294         u8         flow_modify_en[0x1];
 295         u8         modify_root[0x1];
 296         u8         identified_miss_table_mode[0x1];
 297         u8         flow_table_modify[0x1];
 298         u8         encap[0x1];
 299         u8         decap[0x1];
 300         u8         reserved_at_9[0x17];
 301
 302         u8         reserved_at_20[0x2];
 303         u8         log_max_ft_size[0x6];
 304         u8         reserved_at_28[0x10];
 305         u8         max_ft_level[0x8];
 306
 307         u8         reserved_at_40[0x20];
 308
 309         u8         reserved_at_60[0x18];
 310         u8         log_max_ft_num[0x8];
 311
 312         u8         reserved_at_80[0x18];
 313         u8         log_max_destination[0x8];
 314
 315         u8         reserved_at_a0[0x18];
 316         u8         log_max_flow[0x8];
 317
 318         u8         reserved_at_c0[0x40];
 319
 320         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 321
 322         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 323 };
 324
 325 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 326         u8         send[0x1];
 327         u8         receive[0x1];
 328         u8         write[0x1];
 329         u8         read[0x1];
 330         u8         reserved_at_4[0x1];
 331         u8         srq_receive[0x1];
 332         u8         reserved_at_6[0x1a];
 333 };
 334
 335 struct mlx5_ifc_ipv4_layout_bits {
 336         u8         reserved_at_0[0x60];
 337
 338         u8         ipv4[0x20];
 339 };
 340
 341 struct mlx5_ifc_ipv6_layout_bits {
 342         u8         ipv6[16][0x8];
 343 };
 344
 345 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 346         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 347         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 348         u8         reserved_at_0[0x80];
 349 };
 350
 351 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 352         u8         smac_47_16[0x20];
 353
 354         u8         smac_15_0[0x10];
 355         u8         ethertype[0x10];
 356
 357         u8         dmac_47_16[0x20];
 358
 359         u8         dmac_15_0[0x10];
 360         u8         first_prio[0x3];
 361         u8         first_cfi[0x1];
 362         u8         first_vid[0xc];
 363
 364         u8         ip_protocol[0x8];
 365         u8         ip_dscp[0x6];
 366         u8         ip_ecn[0x2];
 367         u8         vlan_tag[0x1];
 368         u8         reserved_at_91[0x1];
 369         u8         frag[0x1];
 370         u8         reserved_at_93[0x4];
 371         u8         tcp_flags[0x9];
 372
 373         u8         tcp_sport[0x10];
 374         u8         tcp_dport[0x10];
 375
 376         u8         reserved_at_c0[0x20];
 377
 378         u8         udp_sport[0x10];
 379         u8         udp_dport[0x10];
 380
 381         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 382
 383         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 384 };
 385
 386 struct mlx5_ifc_fte_match_set_misc_bits {
 387         u8         reserved_at_0[0x8];
 388         u8         source_sqn[0x18];
 389
 390         u8         reserved_at_20[0x10];
 391         u8         source_port[0x10];
 392
 393         u8         outer_second_prio[0x3];
 394         u8         outer_second_cfi[0x1];
 395         u8         outer_second_vid[0xc];
 396         u8         inner_second_prio[0x3];
 397         u8         inner_second_cfi[0x1];
 398         u8         inner_second_vid[0xc];
 399
 400         u8         outer_second_vlan_tag[0x1];
 401         u8         inner_second_vlan_tag[0x1];
 402         u8         reserved_at_62[0xe];
 403         u8         gre_protocol[0x10];
 404
 405         u8         gre_key_h[0x18];
 406         u8         gre_key_l[0x8];
 407
 408         u8         vxlan_vni[0x18];
 409         u8         reserved_at_b8[0x8];
 410
 411         u8         reserved_at_c0[0x20];
 412
 413         u8         reserved_at_e0[0xc];
 414         u8         outer_ipv6_flow_label[0x14];
 415
 416         u8         reserved_at_100[0xc];
 417         u8         inner_ipv6_flow_label[0x14];
 418
 419         u8         reserved_at_120[0xe0];
 420 };
 421
 422 struct mlx5_ifc_cmd_pas_bits {
 423         u8         pa_h[0x20];
 424
 425         u8         pa_l[0x14];
 426         u8         reserved_at_34[0xc];
 427 };
 428
 429 struct mlx5_ifc_uint64_bits {
 430         u8         hi[0x20];
 431
 432         u8         lo[0x20];
 433 };
 434
 435 enum {
 436         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 437         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 438         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 439         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 440         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 441         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 442         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 443         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 444         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 445         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 446 };
 447
 448 struct mlx5_ifc_ads_bits {
 449         u8         fl[0x1];
 450         u8         free_ar[0x1];
 451         u8         reserved_at_2[0xe];
 452         u8         pkey_index[0x10];
 453
 454         u8         reserved_at_20[0x8];
 455         u8         grh[0x1];
 456         u8         mlid[0x7];
 457         u8         rlid[0x10];
 458
 459         u8         ack_timeout[0x5];
 460         u8         reserved_at_45[0x3];
 461         u8         src_addr_index[0x8];
 462         u8         reserved_at_50[0x4];
 463         u8         stat_rate[0x4];
 464         u8         hop_limit[0x8];
 465
 466         u8         reserved_at_60[0x4];
 467         u8         tclass[0x8];
 468         u8         flow_label[0x14];
 469
 470         u8         rgid_rip[16][0x8];
 471
 472         u8         reserved_at_100[0x4];
 473         u8         f_dscp[0x1];
 474         u8         f_ecn[0x1];
 475         u8         reserved_at_106[0x1];
 476         u8         f_eth_prio[0x1];
 477         u8         ecn[0x2];
 478         u8         dscp[0x6];
 479         u8         udp_sport[0x10];
 480
 481         u8         dei_cfi[0x1];
 482         u8         eth_prio[0x3];
 483         u8         sl[0x4];
 484         u8         port[0x8];
 485         u8         rmac_47_32[0x10];
 486
 487         u8         rmac_31_0[0x20];
 488 };
 489
 490 struct mlx5_ifc_flow_table_nic_cap_bits {
 491         u8         nic_rx_multi_path_tirs[0x1];
 492         u8         nic_rx_multi_path_tirs_fts[0x1];
 493         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 494         u8         reserved_at_3[0x1fd];
 495
 496         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 497
 498         u8         reserved_at_400[0x200];
 499
 500         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 501
 502         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 503
 504         u8         reserved_at_a00[0x200];
 505
 506         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 507
 508         u8         reserved_at_e00[0x7200];
 509 };
 510
 511 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 512         u8     reserved_at_0[0x200];
 513
 514         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 515
 516         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 517
 518         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 519
 520         u8      reserved_at_800[0x7800];
 521 };
 522
 523 struct mlx5_ifc_e_switch_cap_bits {
 524         u8         vport_svlan_strip[0x1];
 525         u8         vport_cvlan_strip[0x1];
 526         u8         vport_svlan_insert[0x1];
 527         u8         vport_cvlan_insert_if_not_exist[0x1];
 528         u8         vport_cvlan_insert_overwrite[0x1];
 529         u8         reserved_at_5[0x19];
 530         u8         nic_vport_node_guid_modify[0x1];
 531         u8         nic_vport_port_guid_modify[0x1];
 532
 533         u8         vxlan_encap_decap[0x1];
 534         u8         nvgre_encap_decap[0x1];
 535         u8         reserved_at_22[0x9];
 536         u8         log_max_encap_headers[0x5];
 537         u8         reserved_2b[0x6];
 538         u8         max_encap_header_size[0xa];
 539
 540         u8         reserved_40[0x7c0];
 541
 542 };
 543
 544 struct mlx5_ifc_qos_cap_bits {
 545         u8         packet_pacing[0x1];
 546         u8         esw_scheduling[0x1];
 547         u8         reserved_at_2[0x1e];
 548
 549         u8         reserved_at_20[0x20];
 550
 551         u8         packet_pacing_max_rate[0x20];
 552
 553         u8         packet_pacing_min_rate[0x20];
 554
 555         u8         reserved_at_80[0x10];
 556         u8         packet_pacing_rate_table_size[0x10];
 557
 558         u8         esw_element_type[0x10];
 559         u8         esw_tsar_type[0x10];
 560
 561         u8         reserved_at_c0[0x10];
 562         u8         max_qos_para_vport[0x10];
 563
 564         u8         max_tsar_bw_share[0x20];
 565
 566         u8         reserved_at_100[0x700];
 567 };
 568
 569 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 570         u8         csum_cap[0x1];
 571         u8         vlan_cap[0x1];
 572         u8         lro_cap[0x1];
 573         u8         lro_psh_flag[0x1];
 574         u8         lro_time_stamp[0x1];
 575         u8         reserved_at_5[0x3];
 576         u8         self_lb_en_modifiable[0x1];
 577         u8         reserved_at_9[0x2];
 578         u8         max_lso_cap[0x5];
 579         u8         reserved_at_10[0x2];
 580         u8         wqe_inline_mode[0x2];
 581         u8         rss_ind_tbl_cap[0x4];
 582         u8         reg_umr_sq[0x1];
 583         u8         scatter_fcs[0x1];
 584         u8         reserved_at_1a[0x1];
 585         u8         tunnel_lso_const_out_ip_id[0x1];
 586         u8         reserved_at_1c[0x2];
 587         u8         tunnel_statless_gre[0x1];
 588         u8         tunnel_stateless_vxlan[0x1];
 589
 590         u8         reserved_at_20[0x20];
 591
 592         u8         reserved_at_40[0x10];
 593         u8         lro_min_mss_size[0x10];
 594
 595         u8         reserved_at_60[0x120];
 596
 597         u8         lro_timer_supported_periods[4][0x20];
 598
 599         u8         reserved_at_200[0x600];
 600 };
 601
 602 struct mlx5_ifc_roce_cap_bits {
 603         u8         roce_apm[0x1];
 604         u8         reserved_at_1[0x1f];
 605
 606         u8         reserved_at_20[0x60];
 607
 608         u8         reserved_at_80[0xc];
 609         u8         l3_type[0x4];
 610         u8         reserved_at_90[0x8];
 611         u8         roce_version[0x8];
 612
 613         u8         reserved_at_a0[0x10];
 614         u8         r_roce_dest_udp_port[0x10];
 615
 616         u8         r_roce_max_src_udp_port[0x10];
 617         u8         r_roce_min_src_udp_port[0x10];
 618
 619         u8         reserved_at_e0[0x10];
 620         u8         roce_address_table_size[0x10];
 621
 622         u8         reserved_at_100[0x700];
 623 };
 624
 625 enum {
 626         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 627         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 628         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 629         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 630         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 631         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 632         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 633         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 634         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 635 };
 636
 637 enum {
 638         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 639         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 640         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 641         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 642         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 643         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 644         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 645         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 646         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 647 };
 648
 649 struct mlx5_ifc_atomic_caps_bits {
 650         u8         reserved_at_0[0x40];
 651
 652         u8         atomic_req_8B_endianess_mode[0x2];
 653         u8         reserved_at_42[0x4];
 654         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 655
 656         u8         reserved_at_47[0x19];
 657
 658         u8         reserved_at_60[0x20];
 659
 660         u8         reserved_at_80[0x10];
 661         u8         atomic_operations[0x10];
 662
 663         u8         reserved_at_a0[0x10];
 664         u8         atomic_size_qp[0x10];
 665
 666         u8         reserved_at_c0[0x10];
 667         u8         atomic_size_dc[0x10];
 668
 669         u8         reserved_at_e0[0x720];
 670 };
 671
 672 struct mlx5_ifc_odp_cap_bits {
 673         u8         reserved_at_0[0x40];
 674
 675         u8         sig[0x1];
 676         u8         reserved_at_41[0x1f];
 677
 678         u8         reserved_at_60[0x20];
 679
 680         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 681
 682         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 683
 684         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 685
 686         u8         reserved_at_e0[0x720];
 687 };
 688
 689 struct mlx5_ifc_calc_op {
 690         u8        reserved_at_0[0x10];
 691         u8        reserved_at_10[0x9];
 692         u8        op_swap_endianness[0x1];
 693         u8        op_min[0x1];
 694         u8        op_xor[0x1];
 695         u8        op_or[0x1];
 696         u8        op_and[0x1];
 697         u8        op_max[0x1];
 698         u8        op_add[0x1];
 699 };
 700
 701 struct mlx5_ifc_vector_calc_cap_bits {
 702         u8         calc_matrix[0x1];
 703         u8         reserved_at_1[0x1f];
 704         u8         reserved_at_20[0x8];
 705         u8         max_vec_count[0x8];
 706         u8         reserved_at_30[0xd];
 707         u8         max_chunk_size[0x3];
 708         struct mlx5_ifc_calc_op calc0;
 709         struct mlx5_ifc_calc_op calc1;
 710         struct mlx5_ifc_calc_op calc2;
 711         struct mlx5_ifc_calc_op calc3;
 712
 713         u8         reserved_at_e0[0x720];
 714 };
 715
 716 enum {
 717         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 718         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 719         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 720 };
 721
 722 enum {
 723         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 724         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 725 };
 726
 727 enum {
 728         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 729         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 730         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 731         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 732         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 733 };
 734
 735 enum {
 736         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 737         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 738         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 739         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 740         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 741         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 742 };
 743
 744 enum {
 745         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 746         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 747 };
 748
 749 enum {
 750         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 751         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 752         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 753 };
 754
 755 enum {
 756         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 757         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 758 };
 759
 760 struct mlx5_ifc_cmd_hca_cap_bits {
 761         u8         reserved_at_0[0x80];
 762
 763         u8         log_max_srq_sz[0x8];
 764         u8         log_max_qp_sz[0x8];
 765         u8         reserved_at_90[0xb];
 766         u8         log_max_qp[0x5];
 767
 768         u8         reserved_at_a0[0xb];
 769         u8         log_max_srq[0x5];
 770         u8         reserved_at_b0[0x10];
 771
 772         u8         reserved_at_c0[0x8];
 773         u8         log_max_cq_sz[0x8];
 774         u8         reserved_at_d0[0xb];
 775         u8         log_max_cq[0x5];
 776
 777         u8         log_max_eq_sz[0x8];
 778         u8         reserved_at_e8[0x2];
 779         u8         log_max_mkey[0x6];
 780         u8         reserved_at_f0[0xc];
 781         u8         log_max_eq[0x4];
 782
 783         u8         max_indirection[0x8];
 784         u8         reserved_at_108[0x1];
 785         u8         log_max_mrw_sz[0x7];
 786         u8         reserved_at_110[0x2];
 787         u8         log_max_bsf_list_size[0x6];
 788         u8         reserved_at_118[0x2];
 789         u8         log_max_klm_list_size[0x6];
 790
 791         u8         reserved_at_120[0xa];
 792         u8         log_max_ra_req_dc[0x6];
 793         u8         reserved_at_130[0xa];
 794         u8         log_max_ra_res_dc[0x6];
 795
 796         u8         reserved_at_140[0xa];
 797         u8         log_max_ra_req_qp[0x6];
 798         u8         reserved_at_150[0xa];
 799         u8         log_max_ra_res_qp[0x6];
 800
 801         u8         pad_cap[0x1];
 802         u8         cc_query_allowed[0x1];
 803         u8         cc_modify_allowed[0x1];
 804         u8         reserved_at_163[0xd];
 805         u8         gid_table_size[0x10];
 806
 807         u8         out_of_seq_cnt[0x1];
 808         u8         vport_counters[0x1];
 809         u8         retransmission_q_counters[0x1];
 810         u8         reserved_at_183[0x1];
 811         u8         modify_rq_counter_set_id[0x1];
 812         u8         reserved_at_185[0x1];
 813         u8         max_qp_cnt[0xa];
 814         u8         pkey_table_size[0x10];
 815
 816         u8         vport_group_manager[0x1];
 817         u8         vhca_group_manager[0x1];
 818         u8         ib_virt[0x1];
 819         u8         eth_virt[0x1];
 820         u8         reserved_at_1a4[0x1];
 821         u8         ets[0x1];
 822         u8         nic_flow_table[0x1];
 823         u8         eswitch_flow_table[0x1];
 824         u8         early_vf_enable[0x1];
 825         u8         reserved_at_1a9[0x2];
 826         u8         local_ca_ack_delay[0x5];
 827         u8         port_module_event[0x1];
 828         u8         reserved_at_1b0[0x1];
 829         u8         ports_check[0x1];
 830         u8         reserved_at_1b2[0x1];
 831         u8         disable_link_up[0x1];
 832         u8         beacon_led[0x1];
 833         u8         port_type[0x2];
 834         u8         num_ports[0x8];
 835
 836         u8         reserved_at_1c0[0x3];
 837         u8         log_max_msg[0x5];
 838         u8         reserved_at_1c8[0x4];
 839         u8         max_tc[0x4];
 840         u8         reserved_at_1d0[0x1];
 841         u8         dcbx[0x1];
 842         u8         reserved_at_1d2[0x4];
 843         u8         rol_s[0x1];
 844         u8         rol_g[0x1];
 845         u8         reserved_at_1d8[0x1];
 846         u8         wol_s[0x1];
 847         u8         wol_g[0x1];
 848         u8         wol_a[0x1];
 849         u8         wol_b[0x1];
 850         u8         wol_m[0x1];
 851         u8         wol_u[0x1];
 852         u8         wol_p[0x1];
 853
 854         u8         stat_rate_support[0x10];
 855         u8         reserved_at_1f0[0xc];
 856         u8         cqe_version[0x4];
 857
 858         u8         compact_address_vector[0x1];
 859         u8         striding_rq[0x1];
 860         u8         reserved_at_201[0x2];
 861         u8         ipoib_basic_offloads[0x1];
 862         u8         reserved_at_205[0xa];
 863         u8         drain_sigerr[0x1];
 864         u8         cmdif_checksum[0x2];
 865         u8         sigerr_cqe[0x1];
 866         u8         reserved_at_213[0x1];
 867         u8         wq_signature[0x1];
 868         u8         sctr_data_cqe[0x1];
 869         u8         reserved_at_216[0x1];
 870         u8         sho[0x1];
 871         u8         tph[0x1];
 872         u8         rf[0x1];
 873         u8         dct[0x1];
 874         u8         qos[0x1];
 875         u8         eth_net_offloads[0x1];
 876         u8         roce[0x1];
 877         u8         atomic[0x1];
 878         u8         reserved_at_21f[0x1];
 879
 880         u8         cq_oi[0x1];
 881         u8         cq_resize[0x1];
 882         u8         cq_moderation[0x1];
 883         u8         reserved_at_223[0x3];
 884         u8         cq_eq_remap[0x1];
 885         u8         pg[0x1];
 886         u8         block_lb_mc[0x1];
 887         u8         reserved_at_229[0x1];
 888         u8         scqe_break_moderation[0x1];
 889         u8         cq_period_start_from_cqe[0x1];
 890         u8         cd[0x1];
 891         u8         reserved_at_22d[0x1];
 892         u8         apm[0x1];
 893         u8         vector_calc[0x1];
 894         u8         umr_ptr_rlky[0x1];
 895         u8         imaicl[0x1];
 896         u8         reserved_at_232[0x4];
 897         u8         qkv[0x1];
 898         u8         pkv[0x1];
 899         u8         set_deth_sqpn[0x1];
 900         u8         reserved_at_239[0x3];
 901         u8         xrc[0x1];
 902         u8         ud[0x1];
 903         u8         uc[0x1];
 904         u8         rc[0x1];
 905
 906         u8         reserved_at_240[0xa];
 907         u8         uar_sz[0x6];
 908         u8         reserved_at_250[0x8];
 909         u8         log_pg_sz[0x8];
 910
 911         u8         bf[0x1];
 912         u8         reserved_at_261[0x1];
 913         u8         pad_tx_eth_packet[0x1];
 914         u8         reserved_at_263[0x8];
 915         u8         log_bf_reg_size[0x5];
 916
 917         u8         reserved_at_270[0xb];
 918         u8         lag_master[0x1];
 919         u8         num_lag_ports[0x4];
 920
 921         u8         reserved_at_280[0x10];
 922         u8         max_wqe_sz_sq[0x10];
 923
 924         u8         reserved_at_2a0[0x10];
 925         u8         max_wqe_sz_rq[0x10];
 926
 927         u8         reserved_at_2c0[0x10];
 928         u8         max_wqe_sz_sq_dc[0x10];
 929
 930         u8         reserved_at_2e0[0x7];
 931         u8         max_qp_mcg[0x19];
 932
 933         u8         reserved_at_300[0x18];
 934         u8         log_max_mcg[0x8];
 935
 936         u8         reserved_at_320[0x3];
 937         u8         log_max_transport_domain[0x5];
 938         u8         reserved_at_328[0x3];
 939         u8         log_max_pd[0x5];
 940         u8         reserved_at_330[0xb];
 941         u8         log_max_xrcd[0x5];
 942
 943         u8         reserved_at_340[0x8];
 944         u8         log_max_flow_counter_bulk[0x8];
 945         u8         max_flow_counter[0x10];
 946
 947
 948         u8         reserved_at_360[0x3];
 949         u8         log_max_rq[0x5];
 950         u8         reserved_at_368[0x3];
 951         u8         log_max_sq[0x5];
 952         u8         reserved_at_370[0x3];
 953         u8         log_max_tir[0x5];
 954         u8         reserved_at_378[0x3];
 955         u8         log_max_tis[0x5];
 956
 957         u8         basic_cyclic_rcv_wqe[0x1];
 958         u8         reserved_at_381[0x2];
 959         u8         log_max_rmp[0x5];
 960         u8         reserved_at_388[0x3];
 961         u8         log_max_rqt[0x5];
 962         u8         reserved_at_390[0x3];
 963         u8         log_max_rqt_size[0x5];
 964         u8         reserved_at_398[0x3];
 965         u8         log_max_tis_per_sq[0x5];
 966
 967         u8         reserved_at_3a0[0x3];
 968         u8         log_max_stride_sz_rq[0x5];
 969         u8         reserved_at_3a8[0x3];
 970         u8         log_min_stride_sz_rq[0x5];
 971         u8         reserved_at_3b0[0x3];
 972         u8         log_max_stride_sz_sq[0x5];
 973         u8         reserved_at_3b8[0x3];
 974         u8         log_min_stride_sz_sq[0x5];
 975
 976         u8         reserved_at_3c0[0x1b];
 977         u8         log_max_wq_sz[0x5];
 978
 979         u8         nic_vport_change_event[0x1];
 980         u8         reserved_at_3e1[0xa];
 981         u8         log_max_vlan_list[0x5];
 982         u8         reserved_at_3f0[0x3];
 983         u8         log_max_current_mc_list[0x5];
 984         u8         reserved_at_3f8[0x3];
 985         u8         log_max_current_uc_list[0x5];
 986
 987         u8         reserved_at_400[0x80];
 988
 989         u8         reserved_at_480[0x3];
 990         u8         log_max_l2_table[0x5];
 991         u8         reserved_at_488[0x8];
 992         u8         log_uar_page_sz[0x10];
 993
 994         u8         reserved_at_4a0[0x20];
 995         u8         device_frequency_mhz[0x20];
 996         u8         device_frequency_khz[0x20];
 997
 998         u8         reserved_at_500[0x80];
 999
1000         u8         reserved_at_580[0x3f];
1001         u8         cqe_compression[0x1];
1002
1003         u8         cqe_compression_timeout[0x10];
1004         u8         cqe_compression_max_num[0x10];
1005
1006         u8         reserved_at_5e0[0x10];
1007         u8         tag_matching[0x1];
1008         u8         rndv_offload_rc[0x1];
1009         u8         rndv_offload_dc[0x1];
1010         u8         log_tag_matching_list_sz[0x5];
1011         u8         reserved_at_5e8[0x3];
1012         u8         log_max_xrq[0x5];
1013
1014         u8         reserved_at_5f0[0x200];
1015 };
1016
1017 enum mlx5_flow_destination_type {
1018         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1019         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1020         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1021
1022         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1023 };
1024
1025 struct mlx5_ifc_dest_format_struct_bits {
1026         u8         destination_type[0x8];
1027         u8         destination_id[0x18];
1028
1029         u8         reserved_at_20[0x20];
1030 };
1031
1032 struct mlx5_ifc_flow_counter_list_bits {
1033         u8         clear[0x1];
1034         u8         num_of_counters[0xf];
1035         u8         flow_counter_id[0x10];
1036
1037         u8         reserved_at_20[0x20];
1038 };
1039
1040 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1041         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1042         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1043         u8         reserved_at_0[0x40];
1044 };
1045
1046 struct mlx5_ifc_fte_match_param_bits {
1047         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1048
1049         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1050
1051         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1052
1053         u8         reserved_at_600[0xa00];
1054 };
1055
1056 enum {
1057         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1058         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1059         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1060         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1061         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1062 };
1063
1064 struct mlx5_ifc_rx_hash_field_select_bits {
1065         u8         l3_prot_type[0x1];
1066         u8         l4_prot_type[0x1];
1067         u8         selected_fields[0x1e];
1068 };
1069
1070 enum {
1071         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1072         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1073 };
1074
1075 enum {
1076         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1077         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1078 };
1079
1080 struct mlx5_ifc_wq_bits {
1081         u8         wq_type[0x4];
1082         u8         wq_signature[0x1];
1083         u8         end_padding_mode[0x2];
1084         u8         cd_slave[0x1];
1085         u8         reserved_at_8[0x18];
1086
1087         u8         hds_skip_first_sge[0x1];
1088         u8         log2_hds_buf_size[0x3];
1089         u8         reserved_at_24[0x7];
1090         u8         page_offset[0x5];
1091         u8         lwm[0x10];
1092
1093         u8         reserved_at_40[0x8];
1094         u8         pd[0x18];
1095
1096         u8         reserved_at_60[0x8];
1097         u8         uar_page[0x18];
1098
1099         u8         dbr_addr[0x40];
1100
1101         u8         hw_counter[0x20];
1102
1103         u8         sw_counter[0x20];
1104
1105         u8         reserved_at_100[0xc];
1106         u8         log_wq_stride[0x4];
1107         u8         reserved_at_110[0x3];
1108         u8         log_wq_pg_sz[0x5];
1109         u8         reserved_at_118[0x3];
1110         u8         log_wq_sz[0x5];
1111
1112         u8         reserved_at_120[0x15];
1113         u8         log_wqe_num_of_strides[0x3];
1114         u8         two_byte_shift_en[0x1];
1115         u8         reserved_at_139[0x4];
1116         u8         log_wqe_stride_size[0x3];
1117
1118         u8         reserved_at_140[0x4c0];
1119
1120         struct mlx5_ifc_cmd_pas_bits pas[0];
1121 };
1122
1123 struct mlx5_ifc_rq_num_bits {
1124         u8         reserved_at_0[0x8];
1125         u8         rq_num[0x18];
1126 };
1127
1128 struct mlx5_ifc_mac_address_layout_bits {
1129         u8         reserved_at_0[0x10];
1130         u8         mac_addr_47_32[0x10];
1131
1132         u8         mac_addr_31_0[0x20];
1133 };
1134
1135 struct mlx5_ifc_vlan_layout_bits {
1136         u8         reserved_at_0[0x14];
1137         u8         vlan[0x0c];
1138
1139         u8         reserved_at_20[0x20];
1140 };
1141
1142 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1143         u8         reserved_at_0[0xa0];
1144
1145         u8         min_time_between_cnps[0x20];
1146
1147         u8         reserved_at_c0[0x12];
1148         u8         cnp_dscp[0x6];
1149         u8         reserved_at_d8[0x5];
1150         u8         cnp_802p_prio[0x3];
1151
1152         u8         reserved_at_e0[0x720];
1153 };
1154
1155 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1156         u8         reserved_at_0[0x60];
1157
1158         u8         reserved_at_60[0x4];
1159         u8         clamp_tgt_rate[0x1];
1160         u8         reserved_at_65[0x3];
1161         u8         clamp_tgt_rate_after_time_inc[0x1];
1162         u8         reserved_at_69[0x17];
1163
1164         u8         reserved_at_80[0x20];
1165
1166         u8         rpg_time_reset[0x20];
1167
1168         u8         rpg_byte_reset[0x20];
1169
1170         u8         rpg_threshold[0x20];
1171
1172         u8         rpg_max_rate[0x20];
1173
1174         u8         rpg_ai_rate[0x20];
1175
1176         u8         rpg_hai_rate[0x20];
1177
1178         u8         rpg_gd[0x20];
1179
1180         u8         rpg_min_dec_fac[0x20];
1181
1182         u8         rpg_min_rate[0x20];
1183
1184         u8         reserved_at_1c0[0xe0];
1185
1186         u8         rate_to_set_on_first_cnp[0x20];
1187
1188         u8         dce_tcp_g[0x20];
1189
1190         u8         dce_tcp_rtt[0x20];
1191
1192         u8         rate_reduce_monitor_period[0x20];
1193
1194         u8         reserved_at_320[0x20];
1195
1196         u8         initial_alpha_value[0x20];
1197
1198         u8         reserved_at_360[0x4a0];
1199 };
1200
1201 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1202         u8         reserved_at_0[0x80];
1203
1204         u8         rppp_max_rps[0x20];
1205
1206         u8         rpg_time_reset[0x20];
1207
1208         u8         rpg_byte_reset[0x20];
1209
1210         u8         rpg_threshold[0x20];
1211
1212         u8         rpg_max_rate[0x20];
1213
1214         u8         rpg_ai_rate[0x20];
1215
1216         u8         rpg_hai_rate[0x20];
1217
1218         u8         rpg_gd[0x20];
1219
1220         u8         rpg_min_dec_fac[0x20];
1221
1222         u8         rpg_min_rate[0x20];
1223
1224         u8         reserved_at_1c0[0x640];
1225 };
1226
1227 enum {
1228         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1229         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1230         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1231 };
1232
1233 struct mlx5_ifc_resize_field_select_bits {
1234         u8         resize_field_select[0x20];
1235 };
1236
1237 enum {
1238         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1239         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1240         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1241         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1242 };
1243
1244 struct mlx5_ifc_modify_field_select_bits {
1245         u8         modify_field_select[0x20];
1246 };
1247
1248 struct mlx5_ifc_field_select_r_roce_np_bits {
1249         u8         field_select_r_roce_np[0x20];
1250 };
1251
1252 struct mlx5_ifc_field_select_r_roce_rp_bits {
1253         u8         field_select_r_roce_rp[0x20];
1254 };
1255
1256 enum {
1257         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1258         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1259         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1260         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1261         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1262         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1263         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1264         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1265         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1266         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1267 };
1268
1269 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1270         u8         field_select_8021qaurp[0x20];
1271 };
1272
1273 struct mlx5_ifc_phys_layer_cntrs_bits {
1274         u8         time_since_last_clear_high[0x20];
1275
1276         u8         time_since_last_clear_low[0x20];
1277
1278         u8         symbol_errors_high[0x20];
1279
1280         u8         symbol_errors_low[0x20];
1281
1282         u8         sync_headers_errors_high[0x20];
1283
1284         u8         sync_headers_errors_low[0x20];
1285
1286         u8         edpl_bip_errors_lane0_high[0x20];
1287
1288         u8         edpl_bip_errors_lane0_low[0x20];
1289
1290         u8         edpl_bip_errors_lane1_high[0x20];
1291
1292         u8         edpl_bip_errors_lane1_low[0x20];
1293
1294         u8         edpl_bip_errors_lane2_high[0x20];
1295
1296         u8         edpl_bip_errors_lane2_low[0x20];
1297
1298         u8         edpl_bip_errors_lane3_high[0x20];
1299
1300         u8         edpl_bip_errors_lane3_low[0x20];
1301
1302         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1303
1304         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1305
1306         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1307
1308         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1309
1310         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1311
1312         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1313
1314         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1315
1316         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1317
1318         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1319
1320         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1321
1322         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1323
1324         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1325
1326         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1327
1328         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1329
1330         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1331
1332         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1333
1334         u8         rs_fec_corrected_blocks_high[0x20];
1335
1336         u8         rs_fec_corrected_blocks_low[0x20];
1337
1338         u8         rs_fec_uncorrectable_blocks_high[0x20];
1339
1340         u8         rs_fec_uncorrectable_blocks_low[0x20];
1341
1342         u8         rs_fec_no_errors_blocks_high[0x20];
1343
1344         u8         rs_fec_no_errors_blocks_low[0x20];
1345
1346         u8         rs_fec_single_error_blocks_high[0x20];
1347
1348         u8         rs_fec_single_error_blocks_low[0x20];
1349
1350         u8         rs_fec_corrected_symbols_total_high[0x20];
1351
1352         u8         rs_fec_corrected_symbols_total_low[0x20];
1353
1354         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1355
1356         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1357
1358         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1359
1360         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1361
1362         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1363
1364         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1365
1366         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1367
1368         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1369
1370         u8         link_down_events[0x20];
1371
1372         u8         successful_recovery_events[0x20];
1373
1374         u8         reserved_at_640[0x180];
1375 };
1376
1377 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1378         u8         symbol_error_counter[0x10];
1379
1380         u8         link_error_recovery_counter[0x8];
1381
1382         u8         link_downed_counter[0x8];
1383
1384         u8         port_rcv_errors[0x10];
1385
1386         u8         port_rcv_remote_physical_errors[0x10];
1387
1388         u8         port_rcv_switch_relay_errors[0x10];
1389
1390         u8         port_xmit_discards[0x10];
1391
1392         u8         port_xmit_constraint_errors[0x8];
1393
1394         u8         port_rcv_constraint_errors[0x8];
1395
1396         u8         reserved_at_70[0x8];
1397
1398         u8         link_overrun_errors[0x8];
1399
1400         u8         reserved_at_80[0x10];
1401
1402         u8         vl_15_dropped[0x10];
1403
1404         u8         reserved_at_a0[0xa0];
1405 };
1406
1407 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1408         u8         transmit_queue_high[0x20];
1409
1410         u8         transmit_queue_low[0x20];
1411
1412         u8         reserved_at_40[0x780];
1413 };
1414
1415 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1416         u8         rx_octets_high[0x20];
1417
1418         u8         rx_octets_low[0x20];
1419
1420         u8         reserved_at_40[0xc0];
1421
1422         u8         rx_frames_high[0x20];
1423
1424         u8         rx_frames_low[0x20];
1425
1426         u8         tx_octets_high[0x20];
1427
1428         u8         tx_octets_low[0x20];
1429
1430         u8         reserved_at_180[0xc0];
1431
1432         u8         tx_frames_high[0x20];
1433
1434         u8         tx_frames_low[0x20];
1435
1436         u8         rx_pause_high[0x20];
1437
1438         u8         rx_pause_low[0x20];
1439
1440         u8         rx_pause_duration_high[0x20];
1441
1442         u8         rx_pause_duration_low[0x20];
1443
1444         u8         tx_pause_high[0x20];
1445
1446         u8         tx_pause_low[0x20];
1447
1448         u8         tx_pause_duration_high[0x20];
1449
1450         u8         tx_pause_duration_low[0x20];
1451
1452         u8         rx_pause_transition_high[0x20];
1453
1454         u8         rx_pause_transition_low[0x20];
1455
1456         u8         reserved_at_3c0[0x400];
1457 };
1458
1459 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1460         u8         port_transmit_wait_high[0x20];
1461
1462         u8         port_transmit_wait_low[0x20];
1463
1464         u8         reserved_at_40[0x780];
1465 };
1466
1467 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1468         u8         dot3stats_alignment_errors_high[0x20];
1469
1470         u8         dot3stats_alignment_errors_low[0x20];
1471
1472         u8         dot3stats_fcs_errors_high[0x20];
1473
1474         u8         dot3stats_fcs_errors_low[0x20];
1475
1476         u8         dot3stats_single_collision_frames_high[0x20];
1477
1478         u8         dot3stats_single_collision_frames_low[0x20];
1479
1480         u8         dot3stats_multiple_collision_frames_high[0x20];
1481
1482         u8         dot3stats_multiple_collision_frames_low[0x20];
1483
1484         u8         dot3stats_sqe_test_errors_high[0x20];
1485
1486         u8         dot3stats_sqe_test_errors_low[0x20];
1487
1488         u8         dot3stats_deferred_transmissions_high[0x20];
1489
1490         u8         dot3stats_deferred_transmissions_low[0x20];
1491
1492         u8         dot3stats_late_collisions_high[0x20];
1493
1494         u8         dot3stats_late_collisions_low[0x20];
1495
1496         u8         dot3stats_excessive_collisions_high[0x20];
1497
1498         u8         dot3stats_excessive_collisions_low[0x20];
1499
1500         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1501
1502         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1503
1504         u8         dot3stats_carrier_sense_errors_high[0x20];
1505
1506         u8         dot3stats_carrier_sense_errors_low[0x20];
1507
1508         u8         dot3stats_frame_too_longs_high[0x20];
1509
1510         u8         dot3stats_frame_too_longs_low[0x20];
1511
1512         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1513
1514         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1515
1516         u8         dot3stats_symbol_errors_high[0x20];
1517
1518         u8         dot3stats_symbol_errors_low[0x20];
1519
1520         u8         dot3control_in_unknown_opcodes_high[0x20];
1521
1522         u8         dot3control_in_unknown_opcodes_low[0x20];
1523
1524         u8         dot3in_pause_frames_high[0x20];
1525
1526         u8         dot3in_pause_frames_low[0x20];
1527
1528         u8         dot3out_pause_frames_high[0x20];
1529
1530         u8         dot3out_pause_frames_low[0x20];
1531
1532         u8         reserved_at_400[0x3c0];
1533 };
1534
1535 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1536         u8         ether_stats_drop_events_high[0x20];
1537
1538         u8         ether_stats_drop_events_low[0x20];
1539
1540         u8         ether_stats_octets_high[0x20];
1541
1542         u8         ether_stats_octets_low[0x20];
1543
1544         u8         ether_stats_pkts_high[0x20];
1545
1546         u8         ether_stats_pkts_low[0x20];
1547
1548         u8         ether_stats_broadcast_pkts_high[0x20];
1549
1550         u8         ether_stats_broadcast_pkts_low[0x20];
1551
1552         u8         ether_stats_multicast_pkts_high[0x20];
1553
1554         u8         ether_stats_multicast_pkts_low[0x20];
1555
1556         u8         ether_stats_crc_align_errors_high[0x20];
1557
1558         u8         ether_stats_crc_align_errors_low[0x20];
1559
1560         u8         ether_stats_undersize_pkts_high[0x20];
1561
1562         u8         ether_stats_undersize_pkts_low[0x20];
1563
1564         u8         ether_stats_oversize_pkts_high[0x20];
1565
1566         u8         ether_stats_oversize_pkts_low[0x20];
1567
1568         u8         ether_stats_fragments_high[0x20];
1569
1570         u8         ether_stats_fragments_low[0x20];
1571
1572         u8         ether_stats_jabbers_high[0x20];
1573
1574         u8         ether_stats_jabbers_low[0x20];
1575
1576         u8         ether_stats_collisions_high[0x20];
1577
1578         u8         ether_stats_collisions_low[0x20];
1579
1580         u8         ether_stats_pkts64octets_high[0x20];
1581
1582         u8         ether_stats_pkts64octets_low[0x20];
1583
1584         u8         ether_stats_pkts65to127octets_high[0x20];
1585
1586         u8         ether_stats_pkts65to127octets_low[0x20];
1587
1588         u8         ether_stats_pkts128to255octets_high[0x20];
1589
1590         u8         ether_stats_pkts128to255octets_low[0x20];
1591
1592         u8         ether_stats_pkts256to511octets_high[0x20];
1593
1594         u8         ether_stats_pkts256to511octets_low[0x20];
1595
1596         u8         ether_stats_pkts512to1023octets_high[0x20];
1597
1598         u8         ether_stats_pkts512to1023octets_low[0x20];
1599
1600         u8         ether_stats_pkts1024to1518octets_high[0x20];
1601
1602         u8         ether_stats_pkts1024to1518octets_low[0x20];
1603
1604         u8         ether_stats_pkts1519to2047octets_high[0x20];
1605
1606         u8         ether_stats_pkts1519to2047octets_low[0x20];
1607
1608         u8         ether_stats_pkts2048to4095octets_high[0x20];
1609
1610         u8         ether_stats_pkts2048to4095octets_low[0x20];
1611
1612         u8         ether_stats_pkts4096to8191octets_high[0x20];
1613
1614         u8         ether_stats_pkts4096to8191octets_low[0x20];
1615
1616         u8         ether_stats_pkts8192to10239octets_high[0x20];
1617
1618         u8         ether_stats_pkts8192to10239octets_low[0x20];
1619
1620         u8         reserved_at_540[0x280];
1621 };
1622
1623 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1624         u8         if_in_octets_high[0x20];
1625
1626         u8         if_in_octets_low[0x20];
1627
1628         u8         if_in_ucast_pkts_high[0x20];
1629
1630         u8         if_in_ucast_pkts_low[0x20];
1631
1632         u8         if_in_discards_high[0x20];
1633
1634         u8         if_in_discards_low[0x20];
1635
1636         u8         if_in_errors_high[0x20];
1637
1638         u8         if_in_errors_low[0x20];
1639
1640         u8         if_in_unknown_protos_high[0x20];
1641
1642         u8         if_in_unknown_protos_low[0x20];
1643
1644         u8         if_out_octets_high[0x20];
1645
1646         u8         if_out_octets_low[0x20];
1647
1648         u8         if_out_ucast_pkts_high[0x20];
1649
1650         u8         if_out_ucast_pkts_low[0x20];
1651
1652         u8         if_out_discards_high[0x20];
1653
1654         u8         if_out_discards_low[0x20];
1655
1656         u8         if_out_errors_high[0x20];
1657
1658         u8         if_out_errors_low[0x20];
1659
1660         u8         if_in_multicast_pkts_high[0x20];
1661
1662         u8         if_in_multicast_pkts_low[0x20];
1663
1664         u8         if_in_broadcast_pkts_high[0x20];
1665
1666         u8         if_in_broadcast_pkts_low[0x20];
1667
1668         u8         if_out_multicast_pkts_high[0x20];
1669
1670         u8         if_out_multicast_pkts_low[0x20];
1671
1672         u8         if_out_broadcast_pkts_high[0x20];
1673
1674         u8         if_out_broadcast_pkts_low[0x20];
1675
1676         u8         reserved_at_340[0x480];
1677 };
1678
1679 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1680         u8         a_frames_transmitted_ok_high[0x20];
1681
1682         u8         a_frames_transmitted_ok_low[0x20];
1683
1684         u8         a_frames_received_ok_high[0x20];
1685
1686         u8         a_frames_received_ok_low[0x20];
1687
1688         u8         a_frame_check_sequence_errors_high[0x20];
1689
1690         u8         a_frame_check_sequence_errors_low[0x20];
1691
1692         u8         a_alignment_errors_high[0x20];
1693
1694         u8         a_alignment_errors_low[0x20];
1695
1696         u8         a_octets_transmitted_ok_high[0x20];
1697
1698         u8         a_octets_transmitted_ok_low[0x20];
1699
1700         u8         a_octets_received_ok_high[0x20];
1701
1702         u8         a_octets_received_ok_low[0x20];
1703
1704         u8         a_multicast_frames_xmitted_ok_high[0x20];
1705
1706         u8         a_multicast_frames_xmitted_ok_low[0x20];
1707
1708         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1709
1710         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1711
1712         u8         a_multicast_frames_received_ok_high[0x20];
1713
1714         u8         a_multicast_frames_received_ok_low[0x20];
1715
1716         u8         a_broadcast_frames_received_ok_high[0x20];
1717
1718         u8         a_broadcast_frames_received_ok_low[0x20];
1719
1720         u8         a_in_range_length_errors_high[0x20];
1721
1722         u8         a_in_range_length_errors_low[0x20];
1723
1724         u8         a_out_of_range_length_field_high[0x20];
1725
1726         u8         a_out_of_range_length_field_low[0x20];
1727
1728         u8         a_frame_too_long_errors_high[0x20];
1729
1730         u8         a_frame_too_long_errors_low[0x20];
1731
1732         u8         a_symbol_error_during_carrier_high[0x20];
1733
1734         u8         a_symbol_error_during_carrier_low[0x20];
1735
1736         u8         a_mac_control_frames_transmitted_high[0x20];
1737
1738         u8         a_mac_control_frames_transmitted_low[0x20];
1739
1740         u8         a_mac_control_frames_received_high[0x20];
1741
1742         u8         a_mac_control_frames_received_low[0x20];
1743
1744         u8         a_unsupported_opcodes_received_high[0x20];
1745
1746         u8         a_unsupported_opcodes_received_low[0x20];
1747
1748         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1749
1750         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1751
1752         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1753
1754         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1755
1756         u8         reserved_at_4c0[0x300];
1757 };
1758
1759 struct mlx5_ifc_cmd_inter_comp_event_bits {
1760         u8         command_completion_vector[0x20];
1761
1762         u8         reserved_at_20[0xc0];
1763 };
1764
1765 struct mlx5_ifc_stall_vl_event_bits {
1766         u8         reserved_at_0[0x18];
1767         u8         port_num[0x1];
1768         u8         reserved_at_19[0x3];
1769         u8         vl[0x4];
1770
1771         u8         reserved_at_20[0xa0];
1772 };
1773
1774 struct mlx5_ifc_db_bf_congestion_event_bits {
1775         u8         event_subtype[0x8];
1776         u8         reserved_at_8[0x8];
1777         u8         congestion_level[0x8];
1778         u8         reserved_at_18[0x8];
1779
1780         u8         reserved_at_20[0xa0];
1781 };
1782
1783 struct mlx5_ifc_gpio_event_bits {
1784         u8         reserved_at_0[0x60];
1785
1786         u8         gpio_event_hi[0x20];
1787
1788         u8         gpio_event_lo[0x20];
1789
1790         u8         reserved_at_a0[0x40];
1791 };
1792
1793 struct mlx5_ifc_port_state_change_event_bits {
1794         u8         reserved_at_0[0x40];
1795
1796         u8         port_num[0x4];
1797         u8         reserved_at_44[0x1c];
1798
1799         u8         reserved_at_60[0x80];
1800 };
1801
1802 struct mlx5_ifc_dropped_packet_logged_bits {
1803         u8         reserved_at_0[0xe0];
1804 };
1805
1806 enum {
1807         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1808         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1809 };
1810
1811 struct mlx5_ifc_cq_error_bits {
1812         u8         reserved_at_0[0x8];
1813         u8         cqn[0x18];
1814
1815         u8         reserved_at_20[0x20];
1816
1817         u8         reserved_at_40[0x18];
1818         u8         syndrome[0x8];
1819
1820         u8         reserved_at_60[0x80];
1821 };
1822
1823 struct mlx5_ifc_rdma_page_fault_event_bits {
1824         u8         bytes_committed[0x20];
1825
1826         u8         r_key[0x20];
1827
1828         u8         reserved_at_40[0x10];
1829         u8         packet_len[0x10];
1830
1831         u8         rdma_op_len[0x20];
1832
1833         u8         rdma_va[0x40];
1834
1835         u8         reserved_at_c0[0x5];
1836         u8         rdma[0x1];
1837         u8         write[0x1];
1838         u8         requestor[0x1];
1839         u8         qp_number[0x18];
1840 };
1841
1842 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1843         u8         bytes_committed[0x20];
1844
1845         u8         reserved_at_20[0x10];
1846         u8         wqe_index[0x10];
1847
1848         u8         reserved_at_40[0x10];
1849         u8         len[0x10];
1850
1851         u8         reserved_at_60[0x60];
1852
1853         u8         reserved_at_c0[0x5];
1854         u8         rdma[0x1];
1855         u8         write_read[0x1];
1856         u8         requestor[0x1];
1857         u8         qpn[0x18];
1858 };
1859
1860 struct mlx5_ifc_qp_events_bits {
1861         u8         reserved_at_0[0xa0];
1862
1863         u8         type[0x8];
1864         u8         reserved_at_a8[0x18];
1865
1866         u8         reserved_at_c0[0x8];
1867         u8         qpn_rqn_sqn[0x18];
1868 };
1869
1870 struct mlx5_ifc_dct_events_bits {
1871         u8         reserved_at_0[0xc0];
1872
1873         u8         reserved_at_c0[0x8];
1874         u8         dct_number[0x18];
1875 };
1876
1877 struct mlx5_ifc_comp_event_bits {
1878         u8         reserved_at_0[0xc0];
1879
1880         u8         reserved_at_c0[0x8];
1881         u8         cq_number[0x18];
1882 };
1883
1884 enum {
1885         MLX5_QPC_STATE_RST        = 0x0,
1886         MLX5_QPC_STATE_INIT       = 0x1,
1887         MLX5_QPC_STATE_RTR        = 0x2,
1888         MLX5_QPC_STATE_RTS        = 0x3,
1889         MLX5_QPC_STATE_SQER       = 0x4,
1890         MLX5_QPC_STATE_ERR        = 0x6,
1891         MLX5_QPC_STATE_SQD        = 0x7,
1892         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1893 };
1894
1895 enum {
1896         MLX5_QPC_ST_RC            = 0x0,
1897         MLX5_QPC_ST_UC            = 0x1,
1898         MLX5_QPC_ST_UD            = 0x2,
1899         MLX5_QPC_ST_XRC           = 0x3,
1900         MLX5_QPC_ST_DCI           = 0x5,
1901         MLX5_QPC_ST_QP0           = 0x7,
1902         MLX5_QPC_ST_QP1           = 0x8,
1903         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1904         MLX5_QPC_ST_REG_UMR       = 0xc,
1905 };
1906
1907 enum {
1908         MLX5_QPC_PM_STATE_ARMED     = 0x0,
1909         MLX5_QPC_PM_STATE_REARM     = 0x1,
1910         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1911         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1912 };
1913
1914 enum {
1915         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1916         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1917 };
1918
1919 enum {
1920         MLX5_QPC_MTU_256_BYTES        = 0x1,
1921         MLX5_QPC_MTU_512_BYTES        = 0x2,
1922         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1923         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1924         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1925         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1926 };
1927
1928 enum {
1929         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1930         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1931         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1932         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1933         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1934         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1935         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1936         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1937 };
1938
1939 enum {
1940         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1941         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1942         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1943 };
1944
1945 enum {
1946         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1947         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1948         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1949 };
1950
1951 struct mlx5_ifc_qpc_bits {
1952         u8         state[0x4];
1953         u8         lag_tx_port_affinity[0x4];
1954         u8         st[0x8];
1955         u8         reserved_at_10[0x3];
1956         u8         pm_state[0x2];
1957         u8         reserved_at_15[0x7];
1958         u8         end_padding_mode[0x2];
1959         u8         reserved_at_1e[0x2];
1960
1961         u8         wq_signature[0x1];
1962         u8         block_lb_mc[0x1];
1963         u8         atomic_like_write_en[0x1];
1964         u8         latency_sensitive[0x1];
1965         u8         reserved_at_24[0x1];
1966         u8         drain_sigerr[0x1];
1967         u8         reserved_at_26[0x2];
1968         u8         pd[0x18];
1969
1970         u8         mtu[0x3];
1971         u8         log_msg_max[0x5];
1972         u8         reserved_at_48[0x1];
1973         u8         log_rq_size[0x4];
1974         u8         log_rq_stride[0x3];
1975         u8         no_sq[0x1];
1976         u8         log_sq_size[0x4];
1977         u8         reserved_at_55[0x6];
1978         u8         rlky[0x1];
1979         u8         ulp_stateless_offload_mode[0x4];
1980
1981         u8         counter_set_id[0x8];
1982         u8         uar_page[0x18];
1983
1984         u8         reserved_at_80[0x8];
1985         u8         user_index[0x18];
1986
1987         u8         reserved_at_a0[0x3];
1988         u8         log_page_size[0x5];
1989         u8         remote_qpn[0x18];
1990
1991         struct mlx5_ifc_ads_bits primary_address_path;
1992
1993         struct mlx5_ifc_ads_bits secondary_address_path;
1994
1995         u8         log_ack_req_freq[0x4];
1996         u8         reserved_at_384[0x4];
1997         u8         log_sra_max[0x3];
1998         u8         reserved_at_38b[0x2];
1999         u8         retry_count[0x3];
2000         u8         rnr_retry[0x3];
2001         u8         reserved_at_393[0x1];
2002         u8         fre[0x1];
2003         u8         cur_rnr_retry[0x3];
2004         u8         cur_retry_count[0x3];
2005         u8         reserved_at_39b[0x5];
2006
2007         u8         reserved_at_3a0[0x20];
2008
2009         u8         reserved_at_3c0[0x8];
2010         u8         next_send_psn[0x18];
2011
2012         u8         reserved_at_3e0[0x8];
2013         u8         cqn_snd[0x18];
2014
2015         u8         reserved_at_400[0x8];
2016         u8         deth_sqpn[0x18];
2017
2018         u8         reserved_at_420[0x20];
2019
2020         u8         reserved_at_440[0x8];
2021         u8         last_acked_psn[0x18];
2022
2023         u8         reserved_at_460[0x8];
2024         u8         ssn[0x18];
2025
2026         u8         reserved_at_480[0x8];
2027         u8         log_rra_max[0x3];
2028         u8         reserved_at_48b[0x1];
2029         u8         atomic_mode[0x4];
2030         u8         rre[0x1];
2031         u8         rwe[0x1];
2032         u8         rae[0x1];
2033         u8         reserved_at_493[0x1];
2034         u8         page_offset[0x6];
2035         u8         reserved_at_49a[0x3];
2036         u8         cd_slave_receive[0x1];
2037         u8         cd_slave_send[0x1];
2038         u8         cd_master[0x1];
2039
2040         u8         reserved_at_4a0[0x3];
2041         u8         min_rnr_nak[0x5];
2042         u8         next_rcv_psn[0x18];
2043
2044         u8         reserved_at_4c0[0x8];
2045         u8         xrcd[0x18];
2046
2047         u8         reserved_at_4e0[0x8];
2048         u8         cqn_rcv[0x18];
2049
2050         u8         dbr_addr[0x40];
2051
2052         u8         q_key[0x20];
2053
2054         u8         reserved_at_560[0x5];
2055         u8         rq_type[0x3];
2056         u8         srqn_rmpn_xrqn[0x18];
2057
2058         u8         reserved_at_580[0x8];
2059         u8         rmsn[0x18];
2060
2061         u8         hw_sq_wqebb_counter[0x10];
2062         u8         sw_sq_wqebb_counter[0x10];
2063
2064         u8         hw_rq_counter[0x20];
2065
2066         u8         sw_rq_counter[0x20];
2067
2068         u8         reserved_at_600[0x20];
2069
2070         u8         reserved_at_620[0xf];
2071         u8         cgs[0x1];
2072         u8         cs_req[0x8];
2073         u8         cs_res[0x8];
2074
2075         u8         dc_access_key[0x40];
2076
2077         u8         reserved_at_680[0xc0];
2078 };
2079
2080 struct mlx5_ifc_roce_addr_layout_bits {
2081         u8         source_l3_address[16][0x8];
2082
2083         u8         reserved_at_80[0x3];
2084         u8         vlan_valid[0x1];
2085         u8         vlan_id[0xc];
2086         u8         source_mac_47_32[0x10];
2087
2088         u8         source_mac_31_0[0x20];
2089
2090         u8         reserved_at_c0[0x14];
2091         u8         roce_l3_type[0x4];
2092         u8         roce_version[0x8];
2093
2094         u8         reserved_at_e0[0x20];
2095 };
2096
2097 union mlx5_ifc_hca_cap_union_bits {
2098         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2099         struct mlx5_ifc_odp_cap_bits odp_cap;
2100         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2101         struct mlx5_ifc_roce_cap_bits roce_cap;
2102         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2103         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2104         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2105         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2106         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2107         struct mlx5_ifc_qos_cap_bits qos_cap;
2108         u8         reserved_at_0[0x8000];
2109 };
2110
2111 enum {
2112         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2113         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2114         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2115         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2116         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2117         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2118 };
2119
2120 struct mlx5_ifc_flow_context_bits {
2121         u8         reserved_at_0[0x20];
2122
2123         u8         group_id[0x20];
2124
2125         u8         reserved_at_40[0x8];
2126         u8         flow_tag[0x18];
2127
2128         u8         reserved_at_60[0x10];
2129         u8         action[0x10];
2130
2131         u8         reserved_at_80[0x8];
2132         u8         destination_list_size[0x18];
2133
2134         u8         reserved_at_a0[0x8];
2135         u8         flow_counter_list_size[0x18];
2136
2137         u8         encap_id[0x20];
2138
2139         u8         reserved_at_e0[0x120];
2140
2141         struct mlx5_ifc_fte_match_param_bits match_value;
2142
2143         u8         reserved_at_1200[0x600];
2144
2145         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2146 };
2147
2148 enum {
2149         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2150         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2151 };
2152
2153 struct mlx5_ifc_xrc_srqc_bits {
2154         u8         state[0x4];
2155         u8         log_xrc_srq_size[0x4];
2156         u8         reserved_at_8[0x18];
2157
2158         u8         wq_signature[0x1];
2159         u8         cont_srq[0x1];
2160         u8         reserved_at_22[0x1];
2161         u8         rlky[0x1];
2162         u8         basic_cyclic_rcv_wqe[0x1];
2163         u8         log_rq_stride[0x3];
2164         u8         xrcd[0x18];
2165
2166         u8         page_offset[0x6];
2167         u8         reserved_at_46[0x2];
2168         u8         cqn[0x18];
2169
2170         u8         reserved_at_60[0x20];
2171
2172         u8         user_index_equal_xrc_srqn[0x1];
2173         u8         reserved_at_81[0x1];
2174         u8         log_page_size[0x6];
2175         u8         user_index[0x18];
2176
2177         u8         reserved_at_a0[0x20];
2178
2179         u8         reserved_at_c0[0x8];
2180         u8         pd[0x18];
2181
2182         u8         lwm[0x10];
2183         u8         wqe_cnt[0x10];
2184
2185         u8         reserved_at_100[0x40];
2186
2187         u8         db_record_addr_h[0x20];
2188
2189         u8         db_record_addr_l[0x1e];
2190         u8         reserved_at_17e[0x2];
2191
2192         u8         reserved_at_180[0x80];
2193 };
2194
2195 struct mlx5_ifc_traffic_counter_bits {
2196         u8         packets[0x40];
2197
2198         u8         octets[0x40];
2199 };
2200
2201 struct mlx5_ifc_tisc_bits {
2202         u8         strict_lag_tx_port_affinity[0x1];
2203         u8         reserved_at_1[0x3];
2204         u8         lag_tx_port_affinity[0x04];
2205
2206         u8         reserved_at_8[0x4];
2207         u8         prio[0x4];
2208         u8         reserved_at_10[0x10];
2209
2210         u8         reserved_at_20[0x100];
2211
2212         u8         reserved_at_120[0x8];
2213         u8         transport_domain[0x18];
2214
2215         u8         reserved_at_140[0x3c0];
2216 };
2217
2218 enum {
2219         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2220         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2221 };
2222
2223 enum {
2224         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2225         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2226 };
2227
2228 enum {
2229         MLX5_RX_HASH_FN_NONE           = 0x0,
2230         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2231         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2232 };
2233
2234 enum {
2235         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2236         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2237 };
2238
2239 struct mlx5_ifc_tirc_bits {
2240         u8         reserved_at_0[0x20];
2241
2242         u8         disp_type[0x4];
2243         u8         reserved_at_24[0x1c];
2244
2245         u8         reserved_at_40[0x40];
2246
2247         u8         reserved_at_80[0x4];
2248         u8         lro_timeout_period_usecs[0x10];
2249         u8         lro_enable_mask[0x4];
2250         u8         lro_max_ip_payload_size[0x8];
2251
2252         u8         reserved_at_a0[0x40];
2253
2254         u8         reserved_at_e0[0x8];
2255         u8         inline_rqn[0x18];
2256
2257         u8         rx_hash_symmetric[0x1];
2258         u8         reserved_at_101[0x1];
2259         u8         tunneled_offload_en[0x1];
2260         u8         reserved_at_103[0x5];
2261         u8         indirect_table[0x18];
2262
2263         u8         rx_hash_fn[0x4];
2264         u8         reserved_at_124[0x2];
2265         u8         self_lb_block[0x2];
2266         u8         transport_domain[0x18];
2267
2268         u8         rx_hash_toeplitz_key[10][0x20];
2269
2270         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2271
2272         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2273
2274         u8         reserved_at_2c0[0x4c0];
2275 };
2276
2277 enum {
2278         MLX5_SRQC_STATE_GOOD   = 0x0,
2279         MLX5_SRQC_STATE_ERROR  = 0x1,
2280 };
2281
2282 struct mlx5_ifc_srqc_bits {
2283         u8         state[0x4];
2284         u8         log_srq_size[0x4];
2285         u8         reserved_at_8[0x18];
2286
2287         u8         wq_signature[0x1];
2288         u8         cont_srq[0x1];
2289         u8         reserved_at_22[0x1];
2290         u8         rlky[0x1];
2291         u8         reserved_at_24[0x1];
2292         u8         log_rq_stride[0x3];
2293         u8         xrcd[0x18];
2294
2295         u8         page_offset[0x6];
2296         u8         reserved_at_46[0x2];
2297         u8         cqn[0x18];
2298
2299         u8         reserved_at_60[0x20];
2300
2301         u8         reserved_at_80[0x2];
2302         u8         log_page_size[0x6];
2303         u8         reserved_at_88[0x18];
2304
2305         u8         reserved_at_a0[0x20];
2306
2307         u8         reserved_at_c0[0x8];
2308         u8         pd[0x18];
2309
2310         u8         lwm[0x10];
2311         u8         wqe_cnt[0x10];
2312
2313         u8         reserved_at_100[0x40];
2314
2315         u8         dbr_addr[0x40];
2316
2317         u8         reserved_at_180[0x80];
2318 };
2319
2320 enum {
2321         MLX5_SQC_STATE_RST  = 0x0,
2322         MLX5_SQC_STATE_RDY  = 0x1,
2323         MLX5_SQC_STATE_ERR  = 0x3,
2324 };
2325
2326 struct mlx5_ifc_sqc_bits {
2327         u8         rlky[0x1];
2328         u8         cd_master[0x1];
2329         u8         fre[0x1];
2330         u8         flush_in_error_en[0x1];
2331         u8         reserved_at_4[0x1];
2332         u8         min_wqe_inline_mode[0x3];
2333         u8         state[0x4];
2334         u8         reg_umr[0x1];
2335         u8         reserved_at_d[0x13];
2336
2337         u8         reserved_at_20[0x8];
2338         u8         user_index[0x18];
2339
2340         u8         reserved_at_40[0x8];
2341         u8         cqn[0x18];
2342
2343         u8         reserved_at_60[0x90];
2344
2345         u8         packet_pacing_rate_limit_index[0x10];
2346         u8         tis_lst_sz[0x10];
2347         u8         reserved_at_110[0x10];
2348
2349         u8         reserved_at_120[0x40];
2350
2351         u8         reserved_at_160[0x8];
2352         u8         tis_num_0[0x18];
2353
2354         struct mlx5_ifc_wq_bits wq;
2355 };
2356
2357 enum {
2358         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2359         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2360         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2361         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2362 };
2363
2364 struct mlx5_ifc_scheduling_context_bits {
2365         u8         element_type[0x8];
2366         u8         reserved_at_8[0x18];
2367
2368         u8         element_attributes[0x20];
2369
2370         u8         parent_element_id[0x20];
2371
2372         u8         reserved_at_60[0x40];
2373
2374         u8         bw_share[0x20];
2375
2376         u8         max_average_bw[0x20];
2377
2378         u8         reserved_at_e0[0x120];
2379 };
2380
2381 struct mlx5_ifc_rqtc_bits {
2382         u8         reserved_at_0[0xa0];
2383
2384         u8         reserved_at_a0[0x10];
2385         u8         rqt_max_size[0x10];
2386
2387         u8         reserved_at_c0[0x10];
2388         u8         rqt_actual_size[0x10];
2389
2390         u8         reserved_at_e0[0x6a0];
2391
2392         struct mlx5_ifc_rq_num_bits rq_num[0];
2393 };
2394
2395 enum {
2396         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2397         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2398 };
2399
2400 enum {
2401         MLX5_RQC_STATE_RST  = 0x0,
2402         MLX5_RQC_STATE_RDY  = 0x1,
2403         MLX5_RQC_STATE_ERR  = 0x3,
2404 };
2405
2406 struct mlx5_ifc_rqc_bits {
2407         u8         rlky[0x1];
2408         u8         reserved_at_1[0x1];
2409         u8         scatter_fcs[0x1];
2410         u8         vsd[0x1];
2411         u8         mem_rq_type[0x4];
2412         u8         state[0x4];
2413         u8         reserved_at_c[0x1];
2414         u8         flush_in_error_en[0x1];
2415         u8         reserved_at_e[0x12];
2416
2417         u8         reserved_at_20[0x8];
2418         u8         user_index[0x18];
2419
2420         u8         reserved_at_40[0x8];
2421         u8         cqn[0x18];
2422
2423         u8         counter_set_id[0x8];
2424         u8         reserved_at_68[0x18];
2425
2426         u8         reserved_at_80[0x8];
2427         u8         rmpn[0x18];
2428
2429         u8         reserved_at_a0[0xe0];
2430
2431         struct mlx5_ifc_wq_bits wq;
2432 };
2433
2434 enum {
2435         MLX5_RMPC_STATE_RDY  = 0x1,
2436         MLX5_RMPC_STATE_ERR  = 0x3,
2437 };
2438
2439 struct mlx5_ifc_rmpc_bits {
2440         u8         reserved_at_0[0x8];
2441         u8         state[0x4];
2442         u8         reserved_at_c[0x14];
2443
2444         u8         basic_cyclic_rcv_wqe[0x1];
2445         u8         reserved_at_21[0x1f];
2446
2447         u8         reserved_at_40[0x140];
2448
2449         struct mlx5_ifc_wq_bits wq;
2450 };
2451
2452 struct mlx5_ifc_nic_vport_context_bits {
2453         u8         reserved_at_0[0x5];
2454         u8         min_wqe_inline_mode[0x3];
2455         u8         reserved_at_8[0x17];
2456         u8         roce_en[0x1];
2457
2458         u8         arm_change_event[0x1];
2459         u8         reserved_at_21[0x1a];
2460         u8         event_on_mtu[0x1];
2461         u8         event_on_promisc_change[0x1];
2462         u8         event_on_vlan_change[0x1];
2463         u8         event_on_mc_address_change[0x1];
2464         u8         event_on_uc_address_change[0x1];
2465
2466         u8         reserved_at_40[0xf0];
2467
2468         u8         mtu[0x10];
2469
2470         u8         system_image_guid[0x40];
2471         u8         port_guid[0x40];
2472         u8         node_guid[0x40];
2473
2474         u8         reserved_at_200[0x140];
2475         u8         qkey_violation_counter[0x10];
2476         u8         reserved_at_350[0x430];
2477
2478         u8         promisc_uc[0x1];
2479         u8         promisc_mc[0x1];
2480         u8         promisc_all[0x1];
2481         u8         reserved_at_783[0x2];
2482         u8         allowed_list_type[0x3];
2483         u8         reserved_at_788[0xc];
2484         u8         allowed_list_size[0xc];
2485
2486         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2487
2488         u8         reserved_at_7e0[0x20];
2489
2490         u8         current_uc_mac_address[0][0x40];
2491 };
2492
2493 enum {
2494         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2495         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2496         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2497 };
2498
2499 struct mlx5_ifc_mkc_bits {
2500         u8         reserved_at_0[0x1];
2501         u8         free[0x1];
2502         u8         reserved_at_2[0xd];
2503         u8         small_fence_on_rdma_read_response[0x1];
2504         u8         umr_en[0x1];
2505         u8         a[0x1];
2506         u8         rw[0x1];
2507         u8         rr[0x1];
2508         u8         lw[0x1];
2509         u8         lr[0x1];
2510         u8         access_mode[0x2];
2511         u8         reserved_at_18[0x8];
2512
2513         u8         qpn[0x18];
2514         u8         mkey_7_0[0x8];
2515
2516         u8         reserved_at_40[0x20];
2517
2518         u8         length64[0x1];
2519         u8         bsf_en[0x1];
2520         u8         sync_umr[0x1];
2521         u8         reserved_at_63[0x2];
2522         u8         expected_sigerr_count[0x1];
2523         u8         reserved_at_66[0x1];
2524         u8         en_rinval[0x1];
2525         u8         pd[0x18];
2526
2527         u8         start_addr[0x40];
2528
2529         u8         len[0x40];
2530
2531         u8         bsf_octword_size[0x20];
2532
2533         u8         reserved_at_120[0x80];
2534
2535         u8         translations_octword_size[0x20];
2536
2537         u8         reserved_at_1c0[0x1b];
2538         u8         log_page_size[0x5];
2539
2540         u8         reserved_at_1e0[0x20];
2541 };
2542
2543 struct mlx5_ifc_pkey_bits {
2544         u8         reserved_at_0[0x10];
2545         u8         pkey[0x10];
2546 };
2547
2548 struct mlx5_ifc_array128_auto_bits {
2549         u8         array128_auto[16][0x8];
2550 };
2551
2552 struct mlx5_ifc_hca_vport_context_bits {
2553         u8         field_select[0x20];
2554
2555         u8         reserved_at_20[0xe0];
2556
2557         u8         sm_virt_aware[0x1];
2558         u8         has_smi[0x1];
2559         u8         has_raw[0x1];
2560         u8         grh_required[0x1];
2561         u8         reserved_at_104[0xc];
2562         u8         port_physical_state[0x4];
2563         u8         vport_state_policy[0x4];
2564         u8         port_state[0x4];
2565         u8         vport_state[0x4];
2566
2567         u8         reserved_at_120[0x20];
2568
2569         u8         system_image_guid[0x40];
2570
2571         u8         port_guid[0x40];
2572
2573         u8         node_guid[0x40];
2574
2575         u8         cap_mask1[0x20];
2576
2577         u8         cap_mask1_field_select[0x20];
2578
2579         u8         cap_mask2[0x20];
2580
2581         u8         cap_mask2_field_select[0x20];
2582
2583         u8         reserved_at_280[0x80];
2584
2585         u8         lid[0x10];
2586         u8         reserved_at_310[0x4];
2587         u8         init_type_reply[0x4];
2588         u8         lmc[0x3];
2589         u8         subnet_timeout[0x5];
2590
2591         u8         sm_lid[0x10];
2592         u8         sm_sl[0x4];
2593         u8         reserved_at_334[0xc];
2594
2595         u8         qkey_violation_counter[0x10];
2596         u8         pkey_violation_counter[0x10];
2597
2598         u8         reserved_at_360[0xca0];
2599 };
2600
2601 struct mlx5_ifc_esw_vport_context_bits {
2602         u8         reserved_at_0[0x3];
2603         u8         vport_svlan_strip[0x1];
2604         u8         vport_cvlan_strip[0x1];
2605         u8         vport_svlan_insert[0x1];
2606         u8         vport_cvlan_insert[0x2];
2607         u8         reserved_at_8[0x18];
2608
2609         u8         reserved_at_20[0x20];
2610
2611         u8         svlan_cfi[0x1];
2612         u8         svlan_pcp[0x3];
2613         u8         svlan_id[0xc];
2614         u8         cvlan_cfi[0x1];
2615         u8         cvlan_pcp[0x3];
2616         u8         cvlan_id[0xc];
2617
2618         u8         reserved_at_60[0x7a0];
2619 };
2620
2621 enum {
2622         MLX5_EQC_STATUS_OK                = 0x0,
2623         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2624 };
2625
2626 enum {
2627         MLX5_EQC_ST_ARMED  = 0x9,
2628         MLX5_EQC_ST_FIRED  = 0xa,
2629 };
2630
2631 struct mlx5_ifc_eqc_bits {
2632         u8         status[0x4];
2633         u8         reserved_at_4[0x9];
2634         u8         ec[0x1];
2635         u8         oi[0x1];
2636         u8         reserved_at_f[0x5];
2637         u8         st[0x4];
2638         u8         reserved_at_18[0x8];
2639
2640         u8         reserved_at_20[0x20];
2641
2642         u8         reserved_at_40[0x14];
2643         u8         page_offset[0x6];
2644         u8         reserved_at_5a[0x6];
2645
2646         u8         reserved_at_60[0x3];
2647         u8         log_eq_size[0x5];
2648         u8         uar_page[0x18];
2649
2650         u8         reserved_at_80[0x20];
2651
2652         u8         reserved_at_a0[0x18];
2653         u8         intr[0x8];
2654
2655         u8         reserved_at_c0[0x3];
2656         u8         log_page_size[0x5];
2657         u8         reserved_at_c8[0x18];
2658
2659         u8         reserved_at_e0[0x60];
2660
2661         u8         reserved_at_140[0x8];
2662         u8         consumer_counter[0x18];
2663
2664         u8         reserved_at_160[0x8];
2665         u8         producer_counter[0x18];
2666
2667         u8         reserved_at_180[0x80];
2668 };
2669
2670 enum {
2671         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2672         MLX5_DCTC_STATE_DRAINING  = 0x1,
2673         MLX5_DCTC_STATE_DRAINED   = 0x2,
2674 };
2675
2676 enum {
2677         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2678         MLX5_DCTC_CS_RES_NA         = 0x1,
2679         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2680 };
2681
2682 enum {
2683         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2684         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2685         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2686         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2687         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2688 };
2689
2690 struct mlx5_ifc_dctc_bits {
2691         u8         reserved_at_0[0x4];
2692         u8         state[0x4];
2693         u8         reserved_at_8[0x18];
2694
2695         u8         reserved_at_20[0x8];
2696         u8         user_index[0x18];
2697
2698         u8         reserved_at_40[0x8];
2699         u8         cqn[0x18];
2700
2701         u8         counter_set_id[0x8];
2702         u8         atomic_mode[0x4];
2703         u8         rre[0x1];
2704         u8         rwe[0x1];
2705         u8         rae[0x1];
2706         u8         atomic_like_write_en[0x1];
2707         u8         latency_sensitive[0x1];
2708         u8         rlky[0x1];
2709         u8         free_ar[0x1];
2710         u8         reserved_at_73[0xd];
2711
2712         u8         reserved_at_80[0x8];
2713         u8         cs_res[0x8];
2714         u8         reserved_at_90[0x3];
2715         u8         min_rnr_nak[0x5];
2716         u8         reserved_at_98[0x8];
2717
2718         u8         reserved_at_a0[0x8];
2719         u8         srqn_xrqn[0x18];
2720
2721         u8         reserved_at_c0[0x8];
2722         u8         pd[0x18];
2723
2724         u8         tclass[0x8];
2725         u8         reserved_at_e8[0x4];
2726         u8         flow_label[0x14];
2727
2728         u8         dc_access_key[0x40];
2729
2730         u8         reserved_at_140[0x5];
2731         u8         mtu[0x3];
2732         u8         port[0x8];
2733         u8         pkey_index[0x10];
2734
2735         u8         reserved_at_160[0x8];
2736         u8         my_addr_index[0x8];
2737         u8         reserved_at_170[0x8];
2738         u8         hop_limit[0x8];
2739
2740         u8         dc_access_key_violation_count[0x20];
2741
2742         u8         reserved_at_1a0[0x14];
2743         u8         dei_cfi[0x1];
2744         u8         eth_prio[0x3];
2745         u8         ecn[0x2];
2746         u8         dscp[0x6];
2747
2748         u8         reserved_at_1c0[0x40];
2749 };
2750
2751 enum {
2752         MLX5_CQC_STATUS_OK             = 0x0,
2753         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2754         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2755 };
2756
2757 enum {
2758         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2759         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2760 };
2761
2762 enum {
2763         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2764         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2765         MLX5_CQC_ST_FIRED                                 = 0xa,
2766 };
2767
2768 enum {
2769         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2770         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2771         MLX5_CQ_PERIOD_NUM_MODES
2772 };
2773
2774 struct mlx5_ifc_cqc_bits {
2775         u8         status[0x4];
2776         u8         reserved_at_4[0x4];
2777         u8         cqe_sz[0x3];
2778         u8         cc[0x1];
2779         u8         reserved_at_c[0x1];
2780         u8         scqe_break_moderation_en[0x1];
2781         u8         oi[0x1];
2782         u8         cq_period_mode[0x2];
2783         u8         cqe_comp_en[0x1];
2784         u8         mini_cqe_res_format[0x2];
2785         u8         st[0x4];
2786         u8         reserved_at_18[0x8];
2787
2788         u8         reserved_at_20[0x20];
2789
2790         u8         reserved_at_40[0x14];
2791         u8         page_offset[0x6];
2792         u8         reserved_at_5a[0x6];
2793
2794         u8         reserved_at_60[0x3];
2795         u8         log_cq_size[0x5];
2796         u8         uar_page[0x18];
2797
2798         u8         reserved_at_80[0x4];
2799         u8         cq_period[0xc];
2800         u8         cq_max_count[0x10];
2801
2802         u8         reserved_at_a0[0x18];
2803         u8         c_eqn[0x8];
2804
2805         u8         reserved_at_c0[0x3];
2806         u8         log_page_size[0x5];
2807         u8         reserved_at_c8[0x18];
2808
2809         u8         reserved_at_e0[0x20];
2810
2811         u8         reserved_at_100[0x8];
2812         u8         last_notified_index[0x18];
2813
2814         u8         reserved_at_120[0x8];
2815         u8         last_solicit_index[0x18];
2816
2817         u8         reserved_at_140[0x8];
2818         u8         consumer_counter[0x18];
2819
2820         u8         reserved_at_160[0x8];
2821         u8         producer_counter[0x18];
2822
2823         u8         reserved_at_180[0x40];
2824
2825         u8         dbr_addr[0x40];
2826 };
2827
2828 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2829         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2830         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2831         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2832         u8         reserved_at_0[0x800];
2833 };
2834
2835 struct mlx5_ifc_query_adapter_param_block_bits {
2836         u8         reserved_at_0[0xc0];
2837
2838         u8         reserved_at_c0[0x8];
2839         u8         ieee_vendor_id[0x18];
2840
2841         u8         reserved_at_e0[0x10];
2842         u8         vsd_vendor_id[0x10];
2843
2844         u8         vsd[208][0x8];
2845
2846         u8         vsd_contd_psid[16][0x8];
2847 };
2848
2849 enum {
2850         MLX5_XRQC_STATE_GOOD   = 0x0,
2851         MLX5_XRQC_STATE_ERROR  = 0x1,
2852 };
2853
2854 enum {
2855         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2856         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
2857 };
2858
2859 enum {
2860         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2861 };
2862
2863 struct mlx5_ifc_tag_matching_topology_context_bits {
2864         u8         log_matching_list_sz[0x4];
2865         u8         reserved_at_4[0xc];
2866         u8         append_next_index[0x10];
2867
2868         u8         sw_phase_cnt[0x10];
2869         u8         hw_phase_cnt[0x10];
2870
2871         u8         reserved_at_40[0x40];
2872 };
2873
2874 struct mlx5_ifc_xrqc_bits {
2875         u8         state[0x4];
2876         u8         rlkey[0x1];
2877         u8         reserved_at_5[0xf];
2878         u8         topology[0x4];
2879         u8         reserved_at_18[0x4];
2880         u8         offload[0x4];
2881
2882         u8         reserved_at_20[0x8];
2883         u8         user_index[0x18];
2884
2885         u8         reserved_at_40[0x8];
2886         u8         cqn[0x18];
2887
2888         u8         reserved_at_60[0xa0];
2889
2890         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2891
2892         u8         reserved_at_180[0x880];
2893
2894         struct mlx5_ifc_wq_bits wq;
2895 };
2896
2897 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2898         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2899         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2900         u8         reserved_at_0[0x20];
2901 };
2902
2903 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2904         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2905         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2906         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2907         u8         reserved_at_0[0x20];
2908 };
2909
2910 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2911         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2912         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2913         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2914         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2915         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2916         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2917         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2918         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2919         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2920         u8         reserved_at_0[0x7c0];
2921 };
2922
2923 union mlx5_ifc_event_auto_bits {
2924         struct mlx5_ifc_comp_event_bits comp_event;
2925         struct mlx5_ifc_dct_events_bits dct_events;
2926         struct mlx5_ifc_qp_events_bits qp_events;
2927         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2928         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2929         struct mlx5_ifc_cq_error_bits cq_error;
2930         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2931         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2932         struct mlx5_ifc_gpio_event_bits gpio_event;
2933         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2934         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2935         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2936         u8         reserved_at_0[0xe0];
2937 };
2938
2939 struct mlx5_ifc_health_buffer_bits {
2940         u8         reserved_at_0[0x100];
2941
2942         u8         assert_existptr[0x20];
2943
2944         u8         assert_callra[0x20];
2945
2946         u8         reserved_at_140[0x40];
2947
2948         u8         fw_version[0x20];
2949
2950         u8         hw_id[0x20];
2951
2952         u8         reserved_at_1c0[0x20];
2953
2954         u8         irisc_index[0x8];
2955         u8         synd[0x8];
2956         u8         ext_synd[0x10];
2957 };
2958
2959 struct mlx5_ifc_register_loopback_control_bits {
2960         u8         no_lb[0x1];
2961         u8         reserved_at_1[0x7];
2962         u8         port[0x8];
2963         u8         reserved_at_10[0x10];
2964
2965         u8         reserved_at_20[0x60];
2966 };
2967
2968 struct mlx5_ifc_vport_tc_element_bits {
2969         u8         traffic_class[0x4];
2970         u8         reserved_at_4[0xc];
2971         u8         vport_number[0x10];
2972 };
2973
2974 struct mlx5_ifc_vport_element_bits {
2975         u8         reserved_at_0[0x10];
2976         u8         vport_number[0x10];
2977 };
2978
2979 enum {
2980         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
2981         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
2982         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
2983 };
2984
2985 struct mlx5_ifc_tsar_element_bits {
2986         u8         reserved_at_0[0x8];
2987         u8         tsar_type[0x8];
2988         u8         reserved_at_10[0x10];
2989 };
2990
2991 struct mlx5_ifc_teardown_hca_out_bits {
2992         u8         status[0x8];
2993         u8         reserved_at_8[0x18];
2994
2995         u8         syndrome[0x20];
2996
2997         u8         reserved_at_40[0x40];
2998 };
2999
3000 enum {
3001         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3002         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
3003 };
3004
3005 struct mlx5_ifc_teardown_hca_in_bits {
3006         u8         opcode[0x10];
3007         u8         reserved_at_10[0x10];
3008
3009         u8         reserved_at_20[0x10];
3010         u8         op_mod[0x10];
3011
3012         u8         reserved_at_40[0x10];
3013         u8         profile[0x10];
3014
3015         u8         reserved_at_60[0x20];
3016 };
3017
3018 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3019         u8         status[0x8];
3020         u8         reserved_at_8[0x18];
3021
3022         u8         syndrome[0x20];
3023
3024         u8         reserved_at_40[0x40];
3025 };
3026
3027 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3028         u8         opcode[0x10];
3029         u8         reserved_at_10[0x10];
3030
3031         u8         reserved_at_20[0x10];
3032         u8         op_mod[0x10];
3033
3034         u8         reserved_at_40[0x8];
3035         u8         qpn[0x18];
3036
3037         u8         reserved_at_60[0x20];
3038
3039         u8         opt_param_mask[0x20];
3040
3041         u8         reserved_at_a0[0x20];
3042
3043         struct mlx5_ifc_qpc_bits qpc;
3044
3045         u8         reserved_at_800[0x80];
3046 };
3047
3048 struct mlx5_ifc_sqd2rts_qp_out_bits {
3049         u8         status[0x8];
3050         u8         reserved_at_8[0x18];
3051
3052         u8         syndrome[0x20];
3053
3054         u8         reserved_at_40[0x40];
3055 };
3056
3057 struct mlx5_ifc_sqd2rts_qp_in_bits {
3058         u8         opcode[0x10];
3059         u8         reserved_at_10[0x10];
3060
3061         u8         reserved_at_20[0x10];
3062         u8         op_mod[0x10];
3063
3064         u8         reserved_at_40[0x8];
3065         u8         qpn[0x18];
3066
3067         u8         reserved_at_60[0x20];
3068
3069         u8         opt_param_mask[0x20];
3070
3071         u8         reserved_at_a0[0x20];
3072
3073         struct mlx5_ifc_qpc_bits qpc;
3074
3075         u8         reserved_at_800[0x80];
3076 };
3077
3078 struct mlx5_ifc_set_roce_address_out_bits {
3079         u8         status[0x8];
3080         u8         reserved_at_8[0x18];
3081
3082         u8         syndrome[0x20];
3083
3084         u8         reserved_at_40[0x40];
3085 };
3086
3087 struct mlx5_ifc_set_roce_address_in_bits {
3088         u8         opcode[0x10];
3089         u8         reserved_at_10[0x10];
3090
3091         u8         reserved_at_20[0x10];
3092         u8         op_mod[0x10];
3093
3094         u8         roce_address_index[0x10];
3095         u8         reserved_at_50[0x10];
3096
3097         u8         reserved_at_60[0x20];
3098
3099         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3100 };
3101
3102 struct mlx5_ifc_set_mad_demux_out_bits {
3103         u8         status[0x8];
3104         u8         reserved_at_8[0x18];
3105
3106         u8         syndrome[0x20];
3107
3108         u8         reserved_at_40[0x40];
3109 };
3110
3111 enum {
3112         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3113         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3114 };
3115
3116 struct mlx5_ifc_set_mad_demux_in_bits {
3117         u8         opcode[0x10];
3118         u8         reserved_at_10[0x10];
3119
3120         u8         reserved_at_20[0x10];
3121         u8         op_mod[0x10];
3122
3123         u8         reserved_at_40[0x20];
3124
3125         u8         reserved_at_60[0x6];
3126         u8         demux_mode[0x2];
3127         u8         reserved_at_68[0x18];
3128 };
3129
3130 struct mlx5_ifc_set_l2_table_entry_out_bits {
3131         u8         status[0x8];
3132         u8         reserved_at_8[0x18];
3133
3134         u8         syndrome[0x20];
3135
3136         u8         reserved_at_40[0x40];
3137 };
3138
3139 struct mlx5_ifc_set_l2_table_entry_in_bits {
3140         u8         opcode[0x10];
3141         u8         reserved_at_10[0x10];
3142
3143         u8         reserved_at_20[0x10];
3144         u8         op_mod[0x10];
3145
3146         u8         reserved_at_40[0x60];
3147
3148         u8         reserved_at_a0[0x8];
3149         u8         table_index[0x18];
3150
3151         u8         reserved_at_c0[0x20];
3152
3153         u8         reserved_at_e0[0x13];
3154         u8         vlan_valid[0x1];
3155         u8         vlan[0xc];
3156
3157         struct mlx5_ifc_mac_address_layout_bits mac_address;
3158
3159         u8         reserved_at_140[0xc0];
3160 };
3161
3162 struct mlx5_ifc_set_issi_out_bits {
3163         u8         status[0x8];
3164         u8         reserved_at_8[0x18];
3165
3166         u8         syndrome[0x20];
3167
3168         u8         reserved_at_40[0x40];
3169 };
3170
3171 struct mlx5_ifc_set_issi_in_bits {
3172         u8         opcode[0x10];
3173         u8         reserved_at_10[0x10];
3174
3175         u8         reserved_at_20[0x10];
3176         u8         op_mod[0x10];
3177
3178         u8         reserved_at_40[0x10];
3179         u8         current_issi[0x10];
3180
3181         u8         reserved_at_60[0x20];
3182 };
3183
3184 struct mlx5_ifc_set_hca_cap_out_bits {
3185         u8         status[0x8];
3186         u8         reserved_at_8[0x18];
3187
3188         u8         syndrome[0x20];
3189
3190         u8         reserved_at_40[0x40];
3191 };
3192
3193 struct mlx5_ifc_set_hca_cap_in_bits {
3194         u8         opcode[0x10];
3195         u8         reserved_at_10[0x10];
3196
3197         u8         reserved_at_20[0x10];
3198         u8         op_mod[0x10];
3199
3200         u8         reserved_at_40[0x40];
3201
3202         union mlx5_ifc_hca_cap_union_bits capability;
3203 };
3204
3205 enum {
3206         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3207         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3208         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3209         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3210 };
3211
3212 struct mlx5_ifc_set_fte_out_bits {
3213         u8         status[0x8];
3214         u8         reserved_at_8[0x18];
3215
3216         u8         syndrome[0x20];
3217
3218         u8         reserved_at_40[0x40];
3219 };
3220
3221 struct mlx5_ifc_set_fte_in_bits {
3222         u8         opcode[0x10];
3223         u8         reserved_at_10[0x10];
3224
3225         u8         reserved_at_20[0x10];
3226         u8         op_mod[0x10];
3227
3228         u8         other_vport[0x1];
3229         u8         reserved_at_41[0xf];
3230         u8         vport_number[0x10];
3231
3232         u8         reserved_at_60[0x20];
3233
3234         u8         table_type[0x8];
3235         u8         reserved_at_88[0x18];
3236
3237         u8         reserved_at_a0[0x8];
3238         u8         table_id[0x18];
3239
3240         u8         reserved_at_c0[0x18];
3241         u8         modify_enable_mask[0x8];
3242
3243         u8         reserved_at_e0[0x20];
3244
3245         u8         flow_index[0x20];
3246
3247         u8         reserved_at_120[0xe0];
3248
3249         struct mlx5_ifc_flow_context_bits flow_context;
3250 };
3251
3252 struct mlx5_ifc_rts2rts_qp_out_bits {
3253         u8         status[0x8];
3254         u8         reserved_at_8[0x18];
3255
3256         u8         syndrome[0x20];
3257
3258         u8         reserved_at_40[0x40];
3259 };
3260
3261 struct mlx5_ifc_rts2rts_qp_in_bits {
3262         u8         opcode[0x10];
3263         u8         reserved_at_10[0x10];
3264
3265         u8         reserved_at_20[0x10];
3266         u8         op_mod[0x10];
3267
3268         u8         reserved_at_40[0x8];
3269         u8         qpn[0x18];
3270
3271         u8         reserved_at_60[0x20];
3272
3273         u8         opt_param_mask[0x20];
3274
3275         u8         reserved_at_a0[0x20];
3276
3277         struct mlx5_ifc_qpc_bits qpc;
3278
3279         u8         reserved_at_800[0x80];
3280 };
3281
3282 struct mlx5_ifc_rtr2rts_qp_out_bits {
3283         u8         status[0x8];
3284         u8         reserved_at_8[0x18];
3285
3286         u8         syndrome[0x20];
3287
3288         u8         reserved_at_40[0x40];
3289 };
3290
3291 struct mlx5_ifc_rtr2rts_qp_in_bits {
3292         u8         opcode[0x10];
3293         u8         reserved_at_10[0x10];
3294
3295         u8         reserved_at_20[0x10];
3296         u8         op_mod[0x10];
3297
3298         u8         reserved_at_40[0x8];
3299         u8         qpn[0x18];
3300
3301         u8         reserved_at_60[0x20];
3302
3303         u8         opt_param_mask[0x20];
3304
3305         u8         reserved_at_a0[0x20];
3306
3307         struct mlx5_ifc_qpc_bits qpc;
3308
3309         u8         reserved_at_800[0x80];
3310 };
3311
3312 struct mlx5_ifc_rst2init_qp_out_bits {
3313         u8         status[0x8];
3314         u8         reserved_at_8[0x18];
3315
3316         u8         syndrome[0x20];
3317
3318         u8         reserved_at_40[0x40];
3319 };
3320
3321 struct mlx5_ifc_rst2init_qp_in_bits {
3322         u8         opcode[0x10];
3323         u8         reserved_at_10[0x10];
3324
3325         u8         reserved_at_20[0x10];
3326         u8         op_mod[0x10];
3327
3328         u8         reserved_at_40[0x8];
3329         u8         qpn[0x18];
3330
3331         u8         reserved_at_60[0x20];
3332
3333         u8         opt_param_mask[0x20];
3334
3335         u8         reserved_at_a0[0x20];
3336
3337         struct mlx5_ifc_qpc_bits qpc;
3338
3339         u8         reserved_at_800[0x80];
3340 };
3341
3342 struct mlx5_ifc_query_xrq_out_bits {
3343         u8         status[0x8];
3344         u8         reserved_at_8[0x18];
3345
3346         u8         syndrome[0x20];
3347
3348         u8         reserved_at_40[0x40];
3349
3350         struct mlx5_ifc_xrqc_bits xrq_context;
3351 };
3352
3353 struct mlx5_ifc_query_xrq_in_bits {
3354         u8         opcode[0x10];
3355         u8         reserved_at_10[0x10];
3356
3357         u8         reserved_at_20[0x10];
3358         u8         op_mod[0x10];
3359
3360         u8         reserved_at_40[0x8];
3361         u8         xrqn[0x18];
3362
3363         u8         reserved_at_60[0x20];
3364 };
3365
3366 struct mlx5_ifc_query_xrc_srq_out_bits {
3367         u8         status[0x8];
3368         u8         reserved_at_8[0x18];
3369
3370         u8         syndrome[0x20];
3371
3372         u8         reserved_at_40[0x40];
3373
3374         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3375
3376         u8         reserved_at_280[0x600];
3377
3378         u8         pas[0][0x40];
3379 };
3380
3381 struct mlx5_ifc_query_xrc_srq_in_bits {
3382         u8         opcode[0x10];
3383         u8         reserved_at_10[0x10];
3384
3385         u8         reserved_at_20[0x10];
3386         u8         op_mod[0x10];
3387
3388         u8         reserved_at_40[0x8];
3389         u8         xrc_srqn[0x18];
3390
3391         u8         reserved_at_60[0x20];
3392 };
3393
3394 enum {
3395         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3396         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3397 };
3398
3399 struct mlx5_ifc_query_vport_state_out_bits {
3400         u8         status[0x8];
3401         u8         reserved_at_8[0x18];
3402
3403         u8         syndrome[0x20];
3404
3405         u8         reserved_at_40[0x20];
3406
3407         u8         reserved_at_60[0x18];
3408         u8         admin_state[0x4];
3409         u8         state[0x4];
3410 };
3411
3412 enum {
3413         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3414         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3415 };
3416
3417 struct mlx5_ifc_query_vport_state_in_bits {
3418         u8         opcode[0x10];
3419         u8         reserved_at_10[0x10];
3420
3421         u8         reserved_at_20[0x10];
3422         u8         op_mod[0x10];
3423
3424         u8         other_vport[0x1];
3425         u8         reserved_at_41[0xf];
3426         u8         vport_number[0x10];
3427
3428         u8         reserved_at_60[0x20];
3429 };
3430
3431 struct mlx5_ifc_query_vport_counter_out_bits {
3432         u8         status[0x8];
3433         u8         reserved_at_8[0x18];
3434
3435         u8         syndrome[0x20];
3436
3437         u8         reserved_at_40[0x40];
3438
3439         struct mlx5_ifc_traffic_counter_bits received_errors;
3440
3441         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3442
3443         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3444
3445         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3446
3447         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3448
3449         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3450
3451         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3452
3453         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3454
3455         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3456
3457         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3458
3459         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3460
3461         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3462
3463         u8         reserved_at_680[0xa00];
3464 };
3465
3466 enum {
3467         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3468 };
3469
3470 struct mlx5_ifc_query_vport_counter_in_bits {
3471         u8         opcode[0x10];
3472         u8         reserved_at_10[0x10];
3473
3474         u8         reserved_at_20[0x10];
3475         u8         op_mod[0x10];
3476
3477         u8         other_vport[0x1];
3478         u8         reserved_at_41[0xb];
3479         u8         port_num[0x4];
3480         u8         vport_number[0x10];
3481
3482         u8         reserved_at_60[0x60];
3483
3484         u8         clear[0x1];
3485         u8         reserved_at_c1[0x1f];
3486
3487         u8         reserved_at_e0[0x20];
3488 };
3489
3490 struct mlx5_ifc_query_tis_out_bits {
3491         u8         status[0x8];
3492         u8         reserved_at_8[0x18];
3493
3494         u8         syndrome[0x20];
3495
3496         u8         reserved_at_40[0x40];
3497
3498         struct mlx5_ifc_tisc_bits tis_context;
3499 };
3500
3501 struct mlx5_ifc_query_tis_in_bits {
3502         u8         opcode[0x10];
3503         u8         reserved_at_10[0x10];
3504
3505         u8         reserved_at_20[0x10];
3506         u8         op_mod[0x10];
3507
3508         u8         reserved_at_40[0x8];
3509         u8         tisn[0x18];
3510
3511         u8         reserved_at_60[0x20];
3512 };
3513
3514 struct mlx5_ifc_query_tir_out_bits {
3515         u8         status[0x8];
3516         u8         reserved_at_8[0x18];
3517
3518         u8         syndrome[0x20];
3519
3520         u8         reserved_at_40[0xc0];
3521
3522         struct mlx5_ifc_tirc_bits tir_context;
3523 };
3524
3525 struct mlx5_ifc_query_tir_in_bits {
3526         u8         opcode[0x10];
3527         u8         reserved_at_10[0x10];
3528
3529         u8         reserved_at_20[0x10];
3530         u8         op_mod[0x10];
3531
3532         u8         reserved_at_40[0x8];
3533         u8         tirn[0x18];
3534
3535         u8         reserved_at_60[0x20];
3536 };
3537
3538 struct mlx5_ifc_query_srq_out_bits {
3539         u8         status[0x8];
3540         u8         reserved_at_8[0x18];
3541
3542         u8         syndrome[0x20];
3543
3544         u8         reserved_at_40[0x40];
3545
3546         struct mlx5_ifc_srqc_bits srq_context_entry;
3547
3548         u8         reserved_at_280[0x600];
3549
3550         u8         pas[0][0x40];
3551 };
3552
3553 struct mlx5_ifc_query_srq_in_bits {
3554         u8         opcode[0x10];
3555         u8         reserved_at_10[0x10];
3556
3557         u8         reserved_at_20[0x10];
3558         u8         op_mod[0x10];
3559
3560         u8         reserved_at_40[0x8];
3561         u8         srqn[0x18];
3562
3563         u8         reserved_at_60[0x20];
3564 };
3565
3566 struct mlx5_ifc_query_sq_out_bits {
3567         u8         status[0x8];
3568         u8         reserved_at_8[0x18];
3569
3570         u8         syndrome[0x20];
3571
3572         u8         reserved_at_40[0xc0];
3573
3574         struct mlx5_ifc_sqc_bits sq_context;
3575 };
3576
3577 struct mlx5_ifc_query_sq_in_bits {
3578         u8         opcode[0x10];
3579         u8         reserved_at_10[0x10];
3580
3581         u8         reserved_at_20[0x10];
3582         u8         op_mod[0x10];
3583
3584         u8         reserved_at_40[0x8];
3585         u8         sqn[0x18];
3586
3587         u8         reserved_at_60[0x20];
3588 };
3589
3590 struct mlx5_ifc_query_special_contexts_out_bits {
3591         u8         status[0x8];
3592         u8         reserved_at_8[0x18];
3593
3594         u8         syndrome[0x20];
3595
3596         u8         dump_fill_mkey[0x20];
3597
3598         u8         resd_lkey[0x20];
3599 };
3600
3601 struct mlx5_ifc_query_special_contexts_in_bits {
3602         u8         opcode[0x10];
3603         u8         reserved_at_10[0x10];
3604
3605         u8         reserved_at_20[0x10];
3606         u8         op_mod[0x10];
3607
3608         u8         reserved_at_40[0x40];
3609 };
3610
3611 struct mlx5_ifc_query_scheduling_element_out_bits {
3612         u8         opcode[0x10];
3613         u8         reserved_at_10[0x10];
3614
3615         u8         reserved_at_20[0x10];
3616         u8         op_mod[0x10];
3617
3618         u8         reserved_at_40[0xc0];
3619
3620         struct mlx5_ifc_scheduling_context_bits scheduling_context;
3621
3622         u8         reserved_at_300[0x100];
3623 };
3624
3625 enum {
3626         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3627 };
3628
3629 struct mlx5_ifc_query_scheduling_element_in_bits {
3630         u8         opcode[0x10];
3631         u8         reserved_at_10[0x10];
3632
3633         u8         reserved_at_20[0x10];
3634         u8         op_mod[0x10];
3635
3636         u8         scheduling_hierarchy[0x8];
3637         u8         reserved_at_48[0x18];
3638
3639         u8         scheduling_element_id[0x20];
3640
3641         u8         reserved_at_80[0x180];
3642 };
3643
3644 struct mlx5_ifc_query_rqt_out_bits {
3645         u8         status[0x8];
3646         u8         reserved_at_8[0x18];
3647
3648         u8         syndrome[0x20];
3649
3650         u8         reserved_at_40[0xc0];
3651
3652         struct mlx5_ifc_rqtc_bits rqt_context;
3653 };
3654
3655 struct mlx5_ifc_query_rqt_in_bits {
3656         u8         opcode[0x10];
3657         u8         reserved_at_10[0x10];
3658
3659         u8         reserved_at_20[0x10];
3660         u8         op_mod[0x10];
3661
3662         u8         reserved_at_40[0x8];
3663         u8         rqtn[0x18];
3664
3665         u8         reserved_at_60[0x20];
3666 };
3667
3668 struct mlx5_ifc_query_rq_out_bits {
3669         u8         status[0x8];
3670         u8         reserved_at_8[0x18];
3671
3672         u8         syndrome[0x20];
3673
3674         u8         reserved_at_40[0xc0];
3675
3676         struct mlx5_ifc_rqc_bits rq_context;
3677 };
3678
3679 struct mlx5_ifc_query_rq_in_bits {
3680         u8         opcode[0x10];
3681         u8         reserved_at_10[0x10];
3682
3683         u8         reserved_at_20[0x10];
3684         u8         op_mod[0x10];
3685
3686         u8         reserved_at_40[0x8];
3687         u8         rqn[0x18];
3688
3689         u8         reserved_at_60[0x20];
3690 };
3691
3692 struct mlx5_ifc_query_roce_address_out_bits {
3693         u8         status[0x8];
3694         u8         reserved_at_8[0x18];
3695
3696         u8         syndrome[0x20];
3697
3698         u8         reserved_at_40[0x40];
3699
3700         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3701 };
3702
3703 struct mlx5_ifc_query_roce_address_in_bits {
3704         u8         opcode[0x10];
3705         u8         reserved_at_10[0x10];
3706
3707         u8         reserved_at_20[0x10];
3708         u8         op_mod[0x10];
3709
3710         u8         roce_address_index[0x10];
3711         u8         reserved_at_50[0x10];
3712
3713         u8         reserved_at_60[0x20];
3714 };
3715
3716 struct mlx5_ifc_query_rmp_out_bits {
3717         u8         status[0x8];
3718         u8         reserved_at_8[0x18];
3719
3720         u8         syndrome[0x20];
3721
3722         u8         reserved_at_40[0xc0];
3723
3724         struct mlx5_ifc_rmpc_bits rmp_context;
3725 };
3726
3727 struct mlx5_ifc_query_rmp_in_bits {
3728         u8         opcode[0x10];
3729         u8         reserved_at_10[0x10];
3730
3731         u8         reserved_at_20[0x10];
3732         u8         op_mod[0x10];
3733
3734         u8         reserved_at_40[0x8];
3735         u8         rmpn[0x18];
3736
3737         u8         reserved_at_60[0x20];
3738 };
3739
3740 struct mlx5_ifc_query_qp_out_bits {
3741         u8         status[0x8];
3742         u8         reserved_at_8[0x18];
3743
3744         u8         syndrome[0x20];
3745
3746         u8         reserved_at_40[0x40];
3747
3748         u8         opt_param_mask[0x20];
3749
3750         u8         reserved_at_a0[0x20];
3751
3752         struct mlx5_ifc_qpc_bits qpc;
3753
3754         u8         reserved_at_800[0x80];
3755
3756         u8         pas[0][0x40];
3757 };
3758
3759 struct mlx5_ifc_query_qp_in_bits {
3760         u8         opcode[0x10];
3761         u8         reserved_at_10[0x10];
3762
3763         u8         reserved_at_20[0x10];
3764         u8         op_mod[0x10];
3765
3766         u8         reserved_at_40[0x8];
3767         u8         qpn[0x18];
3768
3769         u8         reserved_at_60[0x20];
3770 };
3771
3772 struct mlx5_ifc_query_q_counter_out_bits {
3773         u8         status[0x8];
3774         u8         reserved_at_8[0x18];
3775
3776         u8         syndrome[0x20];
3777
3778         u8         reserved_at_40[0x40];
3779
3780         u8         rx_write_requests[0x20];
3781
3782         u8         reserved_at_a0[0x20];
3783
3784         u8         rx_read_requests[0x20];
3785
3786         u8         reserved_at_e0[0x20];
3787
3788         u8         rx_atomic_requests[0x20];
3789
3790         u8         reserved_at_120[0x20];
3791
3792         u8         rx_dct_connect[0x20];
3793
3794         u8         reserved_at_160[0x20];
3795
3796         u8         out_of_buffer[0x20];
3797
3798         u8         reserved_at_1a0[0x20];
3799
3800         u8         out_of_sequence[0x20];
3801
3802         u8         reserved_at_1e0[0x20];
3803
3804         u8         duplicate_request[0x20];
3805
3806         u8         reserved_at_220[0x20];
3807
3808         u8         rnr_nak_retry_err[0x20];
3809
3810         u8         reserved_at_260[0x20];
3811
3812         u8         packet_seq_err[0x20];
3813
3814         u8         reserved_at_2a0[0x20];
3815
3816         u8         implied_nak_seq_err[0x20];
3817
3818         u8         reserved_at_2e0[0x20];
3819
3820         u8         local_ack_timeout_err[0x20];
3821
3822         u8         reserved_at_320[0x4e0];
3823 };
3824
3825 struct mlx5_ifc_query_q_counter_in_bits {
3826         u8         opcode[0x10];
3827         u8         reserved_at_10[0x10];
3828
3829         u8         reserved_at_20[0x10];
3830         u8         op_mod[0x10];
3831
3832         u8         reserved_at_40[0x80];
3833
3834         u8         clear[0x1];
3835         u8         reserved_at_c1[0x1f];
3836
3837         u8         reserved_at_e0[0x18];
3838         u8         counter_set_id[0x8];
3839 };
3840
3841 struct mlx5_ifc_query_pages_out_bits {
3842         u8         status[0x8];
3843         u8         reserved_at_8[0x18];
3844
3845         u8         syndrome[0x20];
3846
3847         u8         reserved_at_40[0x10];
3848         u8         function_id[0x10];
3849
3850         u8         num_pages[0x20];
3851 };
3852
3853 enum {
3854         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3855         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3856         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3857 };
3858
3859 struct mlx5_ifc_query_pages_in_bits {
3860         u8         opcode[0x10];
3861         u8         reserved_at_10[0x10];
3862
3863         u8         reserved_at_20[0x10];
3864         u8         op_mod[0x10];
3865
3866         u8         reserved_at_40[0x10];
3867         u8         function_id[0x10];
3868
3869         u8         reserved_at_60[0x20];
3870 };
3871
3872 struct mlx5_ifc_query_nic_vport_context_out_bits {
3873         u8         status[0x8];
3874         u8         reserved_at_8[0x18];
3875
3876         u8         syndrome[0x20];
3877
3878         u8         reserved_at_40[0x40];
3879
3880         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3881 };
3882
3883 struct mlx5_ifc_query_nic_vport_context_in_bits {
3884         u8         opcode[0x10];
3885         u8         reserved_at_10[0x10];
3886
3887         u8         reserved_at_20[0x10];
3888         u8         op_mod[0x10];
3889
3890         u8         other_vport[0x1];
3891         u8         reserved_at_41[0xf];
3892         u8         vport_number[0x10];
3893
3894         u8         reserved_at_60[0x5];
3895         u8         allowed_list_type[0x3];
3896         u8         reserved_at_68[0x18];
3897 };
3898
3899 struct mlx5_ifc_query_mkey_out_bits {
3900         u8         status[0x8];
3901         u8         reserved_at_8[0x18];
3902
3903         u8         syndrome[0x20];
3904
3905         u8         reserved_at_40[0x40];
3906
3907         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3908
3909         u8         reserved_at_280[0x600];
3910
3911         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
3912
3913         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
3914 };
3915
3916 struct mlx5_ifc_query_mkey_in_bits {
3917         u8         opcode[0x10];
3918         u8         reserved_at_10[0x10];
3919
3920         u8         reserved_at_20[0x10];
3921         u8         op_mod[0x10];
3922
3923         u8         reserved_at_40[0x8];
3924         u8         mkey_index[0x18];
3925
3926         u8         pg_access[0x1];
3927         u8         reserved_at_61[0x1f];
3928 };
3929
3930 struct mlx5_ifc_query_mad_demux_out_bits {
3931         u8         status[0x8];
3932         u8         reserved_at_8[0x18];
3933
3934         u8         syndrome[0x20];
3935
3936         u8         reserved_at_40[0x40];
3937
3938         u8         mad_dumux_parameters_block[0x20];
3939 };
3940
3941 struct mlx5_ifc_query_mad_demux_in_bits {
3942         u8         opcode[0x10];
3943         u8         reserved_at_10[0x10];
3944
3945         u8         reserved_at_20[0x10];
3946         u8         op_mod[0x10];
3947
3948         u8         reserved_at_40[0x40];
3949 };
3950
3951 struct mlx5_ifc_query_l2_table_entry_out_bits {
3952         u8         status[0x8];
3953         u8         reserved_at_8[0x18];
3954
3955         u8         syndrome[0x20];
3956
3957         u8         reserved_at_40[0xa0];
3958
3959         u8         reserved_at_e0[0x13];
3960         u8         vlan_valid[0x1];
3961         u8         vlan[0xc];
3962
3963         struct mlx5_ifc_mac_address_layout_bits mac_address;
3964
3965         u8         reserved_at_140[0xc0];
3966 };
3967
3968 struct mlx5_ifc_query_l2_table_entry_in_bits {
3969         u8         opcode[0x10];
3970         u8         reserved_at_10[0x10];
3971
3972         u8         reserved_at_20[0x10];
3973         u8         op_mod[0x10];
3974
3975         u8         reserved_at_40[0x60];
3976
3977         u8         reserved_at_a0[0x8];
3978         u8         table_index[0x18];
3979
3980         u8         reserved_at_c0[0x140];
3981 };
3982
3983 struct mlx5_ifc_query_issi_out_bits {
3984         u8         status[0x8];
3985         u8         reserved_at_8[0x18];
3986
3987         u8         syndrome[0x20];
3988
3989         u8         reserved_at_40[0x10];
3990         u8         current_issi[0x10];
3991
3992         u8         reserved_at_60[0xa0];
3993
3994         u8         reserved_at_100[76][0x8];
3995         u8         supported_issi_dw0[0x20];
3996 };
3997
3998 struct mlx5_ifc_query_issi_in_bits {
3999         u8         opcode[0x10];
4000         u8         reserved_at_10[0x10];
4001
4002         u8         reserved_at_20[0x10];
4003         u8         op_mod[0x10];
4004
4005         u8         reserved_at_40[0x40];
4006 };
4007
4008 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4009         u8         status[0x8];
4010         u8         reserved_at_8[0x18];
4011
4012         u8         syndrome[0x20];
4013
4014         u8         reserved_at_40[0x40];
4015
4016         struct mlx5_ifc_pkey_bits pkey[0];
4017 };
4018
4019 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4020         u8         opcode[0x10];
4021         u8         reserved_at_10[0x10];
4022
4023         u8         reserved_at_20[0x10];
4024         u8         op_mod[0x10];
4025
4026         u8         other_vport[0x1];
4027         u8         reserved_at_41[0xb];
4028         u8         port_num[0x4];
4029         u8         vport_number[0x10];
4030
4031         u8         reserved_at_60[0x10];
4032         u8         pkey_index[0x10];
4033 };
4034
4035 enum {
4036         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4037         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4038         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4039 };
4040
4041 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4042         u8         status[0x8];
4043         u8         reserved_at_8[0x18];
4044
4045         u8         syndrome[0x20];
4046
4047         u8         reserved_at_40[0x20];
4048
4049         u8         gids_num[0x10];
4050         u8         reserved_at_70[0x10];
4051
4052         struct mlx5_ifc_array128_auto_bits gid[0];
4053 };
4054
4055 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4056         u8         opcode[0x10];
4057         u8         reserved_at_10[0x10];
4058
4059         u8         reserved_at_20[0x10];
4060         u8         op_mod[0x10];
4061
4062         u8         other_vport[0x1];
4063         u8         reserved_at_41[0xb];
4064         u8         port_num[0x4];
4065         u8         vport_number[0x10];
4066
4067         u8         reserved_at_60[0x10];
4068         u8         gid_index[0x10];
4069 };
4070
4071 struct mlx5_ifc_query_hca_vport_context_out_bits {
4072         u8         status[0x8];
4073         u8         reserved_at_8[0x18];
4074
4075         u8         syndrome[0x20];
4076
4077         u8         reserved_at_40[0x40];
4078
4079         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4080 };
4081
4082 struct mlx5_ifc_query_hca_vport_context_in_bits {
4083         u8         opcode[0x10];
4084         u8         reserved_at_10[0x10];
4085
4086         u8         reserved_at_20[0x10];
4087         u8         op_mod[0x10];
4088
4089         u8         other_vport[0x1];
4090         u8         reserved_at_41[0xb];
4091         u8         port_num[0x4];
4092         u8         vport_number[0x10];
4093
4094         u8         reserved_at_60[0x20];
4095 };
4096
4097 struct mlx5_ifc_query_hca_cap_out_bits {
4098         u8         status[0x8];
4099         u8         reserved_at_8[0x18];
4100
4101         u8         syndrome[0x20];
4102
4103         u8         reserved_at_40[0x40];
4104
4105         union mlx5_ifc_hca_cap_union_bits capability;
4106 };
4107
4108 struct mlx5_ifc_query_hca_cap_in_bits {
4109         u8         opcode[0x10];
4110         u8         reserved_at_10[0x10];
4111
4112         u8         reserved_at_20[0x10];
4113         u8         op_mod[0x10];
4114
4115         u8         reserved_at_40[0x40];
4116 };
4117
4118 struct mlx5_ifc_query_flow_table_out_bits {
4119         u8         status[0x8];
4120         u8         reserved_at_8[0x18];
4121
4122         u8         syndrome[0x20];
4123
4124         u8         reserved_at_40[0x80];
4125
4126         u8         reserved_at_c0[0x8];
4127         u8         level[0x8];
4128         u8         reserved_at_d0[0x8];
4129         u8         log_size[0x8];
4130
4131         u8         reserved_at_e0[0x120];
4132 };
4133
4134 struct mlx5_ifc_query_flow_table_in_bits {
4135         u8         opcode[0x10];
4136         u8         reserved_at_10[0x10];
4137
4138         u8         reserved_at_20[0x10];
4139         u8         op_mod[0x10];
4140
4141         u8         reserved_at_40[0x40];
4142
4143         u8         table_type[0x8];
4144         u8         reserved_at_88[0x18];
4145
4146         u8         reserved_at_a0[0x8];
4147         u8         table_id[0x18];
4148
4149         u8         reserved_at_c0[0x140];
4150 };
4151
4152 struct mlx5_ifc_query_fte_out_bits {
4153         u8         status[0x8];
4154         u8         reserved_at_8[0x18];
4155
4156         u8         syndrome[0x20];
4157
4158         u8         reserved_at_40[0x1c0];
4159
4160         struct mlx5_ifc_flow_context_bits flow_context;
4161 };
4162
4163 struct mlx5_ifc_query_fte_in_bits {
4164         u8         opcode[0x10];
4165         u8         reserved_at_10[0x10];
4166
4167         u8         reserved_at_20[0x10];
4168         u8         op_mod[0x10];
4169
4170         u8         reserved_at_40[0x40];
4171
4172         u8         table_type[0x8];
4173         u8         reserved_at_88[0x18];
4174
4175         u8         reserved_at_a0[0x8];
4176         u8         table_id[0x18];
4177
4178         u8         reserved_at_c0[0x40];
4179
4180         u8         flow_index[0x20];
4181
4182         u8         reserved_at_120[0xe0];
4183 };
4184
4185 enum {
4186         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4187         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4188         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4189 };
4190
4191 struct mlx5_ifc_query_flow_group_out_bits {
4192         u8         status[0x8];
4193         u8         reserved_at_8[0x18];
4194
4195         u8         syndrome[0x20];
4196
4197         u8         reserved_at_40[0xa0];
4198
4199         u8         start_flow_index[0x20];
4200
4201         u8         reserved_at_100[0x20];
4202
4203         u8         end_flow_index[0x20];
4204
4205         u8         reserved_at_140[0xa0];
4206
4207         u8         reserved_at_1e0[0x18];
4208         u8         match_criteria_enable[0x8];
4209
4210         struct mlx5_ifc_fte_match_param_bits match_criteria;
4211
4212         u8         reserved_at_1200[0xe00];
4213 };
4214
4215 struct mlx5_ifc_query_flow_group_in_bits {
4216         u8         opcode[0x10];
4217         u8         reserved_at_10[0x10];
4218
4219         u8         reserved_at_20[0x10];
4220         u8         op_mod[0x10];
4221
4222         u8         reserved_at_40[0x40];
4223
4224         u8         table_type[0x8];
4225         u8         reserved_at_88[0x18];
4226
4227         u8         reserved_at_a0[0x8];
4228         u8         table_id[0x18];
4229
4230         u8         group_id[0x20];
4231
4232         u8         reserved_at_e0[0x120];
4233 };
4234
4235 struct mlx5_ifc_query_flow_counter_out_bits {
4236         u8         status[0x8];
4237         u8         reserved_at_8[0x18];
4238
4239         u8         syndrome[0x20];
4240
4241         u8         reserved_at_40[0x40];
4242
4243         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4244 };
4245
4246 struct mlx5_ifc_query_flow_counter_in_bits {
4247         u8         opcode[0x10];
4248         u8         reserved_at_10[0x10];
4249
4250         u8         reserved_at_20[0x10];
4251         u8         op_mod[0x10];
4252
4253         u8         reserved_at_40[0x80];
4254
4255         u8         clear[0x1];
4256         u8         reserved_at_c1[0xf];
4257         u8         num_of_counters[0x10];
4258
4259         u8         reserved_at_e0[0x10];
4260         u8         flow_counter_id[0x10];
4261 };
4262
4263 struct mlx5_ifc_query_esw_vport_context_out_bits {
4264         u8         status[0x8];
4265         u8         reserved_at_8[0x18];
4266
4267         u8         syndrome[0x20];
4268
4269         u8         reserved_at_40[0x40];
4270
4271         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4272 };
4273
4274 struct mlx5_ifc_query_esw_vport_context_in_bits {
4275         u8         opcode[0x10];
4276         u8         reserved_at_10[0x10];
4277
4278         u8         reserved_at_20[0x10];
4279         u8         op_mod[0x10];
4280
4281         u8         other_vport[0x1];
4282         u8         reserved_at_41[0xf];
4283         u8         vport_number[0x10];
4284
4285         u8         reserved_at_60[0x20];
4286 };
4287
4288 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4289         u8         status[0x8];
4290         u8         reserved_at_8[0x18];
4291
4292         u8         syndrome[0x20];
4293
4294         u8         reserved_at_40[0x40];
4295 };
4296
4297 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4298         u8         reserved_at_0[0x1c];
4299         u8         vport_cvlan_insert[0x1];
4300         u8         vport_svlan_insert[0x1];
4301         u8         vport_cvlan_strip[0x1];
4302         u8         vport_svlan_strip[0x1];
4303 };
4304
4305 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4306         u8         opcode[0x10];
4307         u8         reserved_at_10[0x10];
4308
4309         u8         reserved_at_20[0x10];
4310         u8         op_mod[0x10];
4311
4312         u8         other_vport[0x1];
4313         u8         reserved_at_41[0xf];
4314         u8         vport_number[0x10];
4315
4316         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4317
4318         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4319 };
4320
4321 struct mlx5_ifc_query_eq_out_bits {
4322         u8         status[0x8];
4323         u8         reserved_at_8[0x18];
4324
4325         u8         syndrome[0x20];
4326
4327         u8         reserved_at_40[0x40];
4328
4329         struct mlx5_ifc_eqc_bits eq_context_entry;
4330
4331         u8         reserved_at_280[0x40];
4332
4333         u8         event_bitmask[0x40];
4334
4335         u8         reserved_at_300[0x580];
4336
4337         u8         pas[0][0x40];
4338 };
4339
4340 struct mlx5_ifc_query_eq_in_bits {
4341         u8         opcode[0x10];
4342         u8         reserved_at_10[0x10];
4343
4344         u8         reserved_at_20[0x10];
4345         u8         op_mod[0x10];
4346
4347         u8         reserved_at_40[0x18];
4348         u8         eq_number[0x8];
4349
4350         u8         reserved_at_60[0x20];
4351 };
4352
4353 struct mlx5_ifc_encap_header_in_bits {
4354         u8         reserved_at_0[0x5];
4355         u8         header_type[0x3];
4356         u8         reserved_at_8[0xe];
4357         u8         encap_header_size[0xa];
4358
4359         u8         reserved_at_20[0x10];
4360         u8         encap_header[2][0x8];
4361
4362         u8         more_encap_header[0][0x8];
4363 };
4364
4365 struct mlx5_ifc_query_encap_header_out_bits {
4366         u8         status[0x8];
4367         u8         reserved_at_8[0x18];
4368
4369         u8         syndrome[0x20];
4370
4371         u8         reserved_at_40[0xa0];
4372
4373         struct mlx5_ifc_encap_header_in_bits encap_header[0];
4374 };
4375
4376 struct mlx5_ifc_query_encap_header_in_bits {
4377         u8         opcode[0x10];
4378         u8         reserved_at_10[0x10];
4379
4380         u8         reserved_at_20[0x10];
4381         u8         op_mod[0x10];
4382
4383         u8         encap_id[0x20];
4384
4385         u8         reserved_at_60[0xa0];
4386 };
4387
4388 struct mlx5_ifc_alloc_encap_header_out_bits {
4389         u8         status[0x8];
4390         u8         reserved_at_8[0x18];
4391
4392         u8         syndrome[0x20];
4393
4394         u8         encap_id[0x20];
4395
4396         u8         reserved_at_60[0x20];
4397 };
4398
4399 struct mlx5_ifc_alloc_encap_header_in_bits {
4400         u8         opcode[0x10];
4401         u8         reserved_at_10[0x10];
4402
4403         u8         reserved_at_20[0x10];
4404         u8         op_mod[0x10];
4405
4406         u8         reserved_at_40[0xa0];
4407
4408         struct mlx5_ifc_encap_header_in_bits encap_header;
4409 };
4410
4411 struct mlx5_ifc_dealloc_encap_header_out_bits {
4412         u8         status[0x8];
4413         u8         reserved_at_8[0x18];
4414
4415         u8         syndrome[0x20];
4416
4417         u8         reserved_at_40[0x40];
4418 };
4419
4420 struct mlx5_ifc_dealloc_encap_header_in_bits {
4421         u8         opcode[0x10];
4422         u8         reserved_at_10[0x10];
4423
4424         u8         reserved_20[0x10];
4425         u8         op_mod[0x10];
4426
4427         u8         encap_id[0x20];
4428
4429         u8         reserved_60[0x20];
4430 };
4431
4432 struct mlx5_ifc_query_dct_out_bits {
4433         u8         status[0x8];
4434         u8         reserved_at_8[0x18];
4435
4436         u8         syndrome[0x20];
4437
4438         u8         reserved_at_40[0x40];
4439
4440         struct mlx5_ifc_dctc_bits dct_context_entry;
4441
4442         u8         reserved_at_280[0x180];
4443 };
4444
4445 struct mlx5_ifc_query_dct_in_bits {
4446         u8         opcode[0x10];
4447         u8         reserved_at_10[0x10];
4448
4449         u8         reserved_at_20[0x10];
4450         u8         op_mod[0x10];
4451
4452         u8         reserved_at_40[0x8];
4453         u8         dctn[0x18];
4454
4455         u8         reserved_at_60[0x20];
4456 };
4457
4458 struct mlx5_ifc_query_cq_out_bits {
4459         u8         status[0x8];
4460         u8         reserved_at_8[0x18];
4461
4462         u8         syndrome[0x20];
4463
4464         u8         reserved_at_40[0x40];
4465
4466         struct mlx5_ifc_cqc_bits cq_context;
4467
4468         u8         reserved_at_280[0x600];
4469
4470         u8         pas[0][0x40];
4471 };
4472
4473 struct mlx5_ifc_query_cq_in_bits {
4474         u8         opcode[0x10];
4475         u8         reserved_at_10[0x10];
4476
4477         u8         reserved_at_20[0x10];
4478         u8         op_mod[0x10];
4479
4480         u8         reserved_at_40[0x8];
4481         u8         cqn[0x18];
4482
4483         u8         reserved_at_60[0x20];
4484 };
4485
4486 struct mlx5_ifc_query_cong_status_out_bits {
4487         u8         status[0x8];
4488         u8         reserved_at_8[0x18];
4489
4490         u8         syndrome[0x20];
4491
4492         u8         reserved_at_40[0x20];
4493
4494         u8         enable[0x1];
4495         u8         tag_enable[0x1];
4496         u8         reserved_at_62[0x1e];
4497 };
4498
4499 struct mlx5_ifc_query_cong_status_in_bits {
4500         u8         opcode[0x10];
4501         u8         reserved_at_10[0x10];
4502
4503         u8         reserved_at_20[0x10];
4504         u8         op_mod[0x10];
4505
4506         u8         reserved_at_40[0x18];
4507         u8         priority[0x4];
4508         u8         cong_protocol[0x4];
4509
4510         u8         reserved_at_60[0x20];
4511 };
4512
4513 struct mlx5_ifc_query_cong_statistics_out_bits {
4514         u8         status[0x8];
4515         u8         reserved_at_8[0x18];
4516
4517         u8         syndrome[0x20];
4518
4519         u8         reserved_at_40[0x40];
4520
4521         u8         cur_flows[0x20];
4522
4523         u8         sum_flows[0x20];
4524
4525         u8         cnp_ignored_high[0x20];
4526
4527         u8         cnp_ignored_low[0x20];
4528
4529         u8         cnp_handled_high[0x20];
4530
4531         u8         cnp_handled_low[0x20];
4532
4533         u8         reserved_at_140[0x100];
4534
4535         u8         time_stamp_high[0x20];
4536
4537         u8         time_stamp_low[0x20];
4538
4539         u8         accumulators_period[0x20];
4540
4541         u8         ecn_marked_roce_packets_high[0x20];
4542
4543         u8         ecn_marked_roce_packets_low[0x20];
4544
4545         u8         cnps_sent_high[0x20];
4546
4547         u8         cnps_sent_low[0x20];
4548
4549         u8         reserved_at_320[0x560];
4550 };
4551
4552 struct mlx5_ifc_query_cong_statistics_in_bits {
4553         u8         opcode[0x10];
4554         u8         reserved_at_10[0x10];
4555
4556         u8         reserved_at_20[0x10];
4557         u8         op_mod[0x10];
4558
4559         u8         clear[0x1];
4560         u8         reserved_at_41[0x1f];
4561
4562         u8         reserved_at_60[0x20];
4563 };
4564
4565 struct mlx5_ifc_query_cong_params_out_bits {
4566         u8         status[0x8];
4567         u8         reserved_at_8[0x18];
4568
4569         u8         syndrome[0x20];
4570
4571         u8         reserved_at_40[0x40];
4572
4573         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4574 };
4575
4576 struct mlx5_ifc_query_cong_params_in_bits {
4577         u8         opcode[0x10];
4578         u8         reserved_at_10[0x10];
4579
4580         u8         reserved_at_20[0x10];
4581         u8         op_mod[0x10];
4582
4583         u8         reserved_at_40[0x1c];
4584         u8         cong_protocol[0x4];
4585
4586         u8         reserved_at_60[0x20];
4587 };
4588
4589 struct mlx5_ifc_query_adapter_out_bits {
4590         u8         status[0x8];
4591         u8         reserved_at_8[0x18];
4592
4593         u8         syndrome[0x20];
4594
4595         u8         reserved_at_40[0x40];
4596
4597         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4598 };
4599
4600 struct mlx5_ifc_query_adapter_in_bits {
4601         u8         opcode[0x10];
4602         u8         reserved_at_10[0x10];
4603
4604         u8         reserved_at_20[0x10];
4605         u8         op_mod[0x10];
4606
4607         u8         reserved_at_40[0x40];
4608 };
4609
4610 struct mlx5_ifc_qp_2rst_out_bits {
4611         u8         status[0x8];
4612         u8         reserved_at_8[0x18];
4613
4614         u8         syndrome[0x20];
4615
4616         u8         reserved_at_40[0x40];
4617 };
4618
4619 struct mlx5_ifc_qp_2rst_in_bits {
4620         u8         opcode[0x10];
4621         u8         reserved_at_10[0x10];
4622
4623         u8         reserved_at_20[0x10];
4624         u8         op_mod[0x10];
4625
4626         u8         reserved_at_40[0x8];
4627         u8         qpn[0x18];
4628
4629         u8         reserved_at_60[0x20];
4630 };
4631
4632 struct mlx5_ifc_qp_2err_out_bits {
4633         u8         status[0x8];
4634         u8         reserved_at_8[0x18];
4635
4636         u8         syndrome[0x20];
4637
4638         u8         reserved_at_40[0x40];
4639 };
4640
4641 struct mlx5_ifc_qp_2err_in_bits {
4642         u8         opcode[0x10];
4643         u8         reserved_at_10[0x10];
4644
4645         u8         reserved_at_20[0x10];
4646         u8         op_mod[0x10];
4647
4648         u8         reserved_at_40[0x8];
4649         u8         qpn[0x18];
4650
4651         u8         reserved_at_60[0x20];
4652 };
4653
4654 struct mlx5_ifc_page_fault_resume_out_bits {
4655         u8         status[0x8];
4656         u8         reserved_at_8[0x18];
4657
4658         u8         syndrome[0x20];
4659
4660         u8         reserved_at_40[0x40];
4661 };
4662
4663 struct mlx5_ifc_page_fault_resume_in_bits {
4664         u8         opcode[0x10];
4665         u8         reserved_at_10[0x10];
4666
4667         u8         reserved_at_20[0x10];
4668         u8         op_mod[0x10];
4669
4670         u8         error[0x1];
4671         u8         reserved_at_41[0x4];
4672         u8         rdma[0x1];
4673         u8         read_write[0x1];
4674         u8         req_res[0x1];
4675         u8         qpn[0x18];
4676
4677         u8         reserved_at_60[0x20];
4678 };
4679
4680 struct mlx5_ifc_nop_out_bits {
4681         u8         status[0x8];
4682         u8         reserved_at_8[0x18];
4683
4684         u8         syndrome[0x20];
4685
4686         u8         reserved_at_40[0x40];
4687 };
4688
4689 struct mlx5_ifc_nop_in_bits {
4690         u8         opcode[0x10];
4691         u8         reserved_at_10[0x10];
4692
4693         u8         reserved_at_20[0x10];
4694         u8         op_mod[0x10];
4695
4696         u8         reserved_at_40[0x40];
4697 };
4698
4699 struct mlx5_ifc_modify_vport_state_out_bits {
4700         u8         status[0x8];
4701         u8         reserved_at_8[0x18];
4702
4703         u8         syndrome[0x20];
4704
4705         u8         reserved_at_40[0x40];
4706 };
4707
4708 struct mlx5_ifc_modify_vport_state_in_bits {
4709         u8         opcode[0x10];
4710         u8         reserved_at_10[0x10];
4711
4712         u8         reserved_at_20[0x10];
4713         u8         op_mod[0x10];
4714
4715         u8         other_vport[0x1];
4716         u8         reserved_at_41[0xf];
4717         u8         vport_number[0x10];
4718
4719         u8         reserved_at_60[0x18];
4720         u8         admin_state[0x4];
4721         u8         reserved_at_7c[0x4];
4722 };
4723
4724 struct mlx5_ifc_modify_tis_out_bits {
4725         u8         status[0x8];
4726         u8         reserved_at_8[0x18];
4727
4728         u8         syndrome[0x20];
4729
4730         u8         reserved_at_40[0x40];
4731 };
4732
4733 struct mlx5_ifc_modify_tis_bitmask_bits {
4734         u8         reserved_at_0[0x20];
4735
4736         u8         reserved_at_20[0x1d];
4737         u8         lag_tx_port_affinity[0x1];
4738         u8         strict_lag_tx_port_affinity[0x1];
4739         u8         prio[0x1];
4740 };
4741
4742 struct mlx5_ifc_modify_tis_in_bits {
4743         u8         opcode[0x10];
4744         u8         reserved_at_10[0x10];
4745
4746         u8         reserved_at_20[0x10];
4747         u8         op_mod[0x10];
4748
4749         u8         reserved_at_40[0x8];
4750         u8         tisn[0x18];
4751
4752         u8         reserved_at_60[0x20];
4753
4754         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4755
4756         u8         reserved_at_c0[0x40];
4757
4758         struct mlx5_ifc_tisc_bits ctx;
4759 };
4760
4761 struct mlx5_ifc_modify_tir_bitmask_bits {
4762         u8         reserved_at_0[0x20];
4763
4764         u8         reserved_at_20[0x1b];
4765         u8         self_lb_en[0x1];
4766         u8         reserved_at_3c[0x1];
4767         u8         hash[0x1];
4768         u8         reserved_at_3e[0x1];
4769         u8         lro[0x1];
4770 };
4771
4772 struct mlx5_ifc_modify_tir_out_bits {
4773         u8         status[0x8];
4774         u8         reserved_at_8[0x18];
4775
4776         u8         syndrome[0x20];
4777
4778         u8         reserved_at_40[0x40];
4779 };
4780
4781 struct mlx5_ifc_modify_tir_in_bits {
4782         u8         opcode[0x10];
4783         u8         reserved_at_10[0x10];
4784
4785         u8         reserved_at_20[0x10];
4786         u8         op_mod[0x10];
4787
4788         u8         reserved_at_40[0x8];
4789         u8         tirn[0x18];
4790
4791         u8         reserved_at_60[0x20];
4792
4793         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4794
4795         u8         reserved_at_c0[0x40];
4796
4797         struct mlx5_ifc_tirc_bits ctx;
4798 };
4799
4800 struct mlx5_ifc_modify_sq_out_bits {
4801         u8         status[0x8];
4802         u8         reserved_at_8[0x18];
4803
4804         u8         syndrome[0x20];
4805
4806         u8         reserved_at_40[0x40];
4807 };
4808
4809 struct mlx5_ifc_modify_sq_in_bits {
4810         u8         opcode[0x10];
4811         u8         reserved_at_10[0x10];
4812
4813         u8         reserved_at_20[0x10];
4814         u8         op_mod[0x10];
4815
4816         u8         sq_state[0x4];
4817         u8         reserved_at_44[0x4];
4818         u8         sqn[0x18];
4819
4820         u8         reserved_at_60[0x20];
4821
4822         u8         modify_bitmask[0x40];
4823
4824         u8         reserved_at_c0[0x40];
4825
4826         struct mlx5_ifc_sqc_bits ctx;
4827 };
4828
4829 struct mlx5_ifc_modify_scheduling_element_out_bits {
4830         u8         status[0x8];
4831         u8         reserved_at_8[0x18];
4832
4833         u8         syndrome[0x20];
4834
4835         u8         reserved_at_40[0x1c0];
4836 };
4837
4838 enum {
4839         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
4840         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
4841 };
4842
4843 struct mlx5_ifc_modify_scheduling_element_in_bits {
4844         u8         opcode[0x10];
4845         u8         reserved_at_10[0x10];
4846
4847         u8         reserved_at_20[0x10];
4848         u8         op_mod[0x10];
4849
4850         u8         scheduling_hierarchy[0x8];
4851         u8         reserved_at_48[0x18];
4852
4853         u8         scheduling_element_id[0x20];
4854
4855         u8         reserved_at_80[0x20];
4856
4857         u8         modify_bitmask[0x20];
4858
4859         u8         reserved_at_c0[0x40];
4860
4861         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4862
4863         u8         reserved_at_300[0x100];
4864 };
4865
4866 struct mlx5_ifc_modify_rqt_out_bits {
4867         u8         status[0x8];
4868         u8         reserved_at_8[0x18];
4869
4870         u8         syndrome[0x20];
4871
4872         u8         reserved_at_40[0x40];
4873 };
4874
4875 struct mlx5_ifc_rqt_bitmask_bits {
4876         u8         reserved_at_0[0x20];
4877
4878         u8         reserved_at_20[0x1f];
4879         u8         rqn_list[0x1];
4880 };
4881
4882 struct mlx5_ifc_modify_rqt_in_bits {
4883         u8         opcode[0x10];
4884         u8         reserved_at_10[0x10];
4885
4886         u8         reserved_at_20[0x10];
4887         u8         op_mod[0x10];
4888
4889         u8         reserved_at_40[0x8];
4890         u8         rqtn[0x18];
4891
4892         u8         reserved_at_60[0x20];
4893
4894         struct mlx5_ifc_rqt_bitmask_bits bitmask;
4895
4896         u8         reserved_at_c0[0x40];
4897
4898         struct mlx5_ifc_rqtc_bits ctx;
4899 };
4900
4901 struct mlx5_ifc_modify_rq_out_bits {
4902         u8         status[0x8];
4903         u8         reserved_at_8[0x18];
4904
4905         u8         syndrome[0x20];
4906
4907         u8         reserved_at_40[0x40];
4908 };
4909
4910 enum {
4911         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
4912         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
4913 };
4914
4915 struct mlx5_ifc_modify_rq_in_bits {
4916         u8         opcode[0x10];
4917         u8         reserved_at_10[0x10];
4918
4919         u8         reserved_at_20[0x10];
4920         u8         op_mod[0x10];
4921
4922         u8         rq_state[0x4];
4923         u8         reserved_at_44[0x4];
4924         u8         rqn[0x18];
4925
4926         u8         reserved_at_60[0x20];
4927
4928         u8         modify_bitmask[0x40];
4929
4930         u8         reserved_at_c0[0x40];
4931
4932         struct mlx5_ifc_rqc_bits ctx;
4933 };
4934
4935 struct mlx5_ifc_modify_rmp_out_bits {
4936         u8         status[0x8];
4937         u8         reserved_at_8[0x18];
4938
4939         u8         syndrome[0x20];
4940
4941         u8         reserved_at_40[0x40];
4942 };
4943
4944 struct mlx5_ifc_rmp_bitmask_bits {
4945         u8         reserved_at_0[0x20];
4946
4947         u8         reserved_at_20[0x1f];
4948         u8         lwm[0x1];
4949 };
4950
4951 struct mlx5_ifc_modify_rmp_in_bits {
4952         u8         opcode[0x10];
4953         u8         reserved_at_10[0x10];
4954
4955         u8         reserved_at_20[0x10];
4956         u8         op_mod[0x10];
4957
4958         u8         rmp_state[0x4];
4959         u8         reserved_at_44[0x4];
4960         u8         rmpn[0x18];
4961
4962         u8         reserved_at_60[0x20];
4963
4964         struct mlx5_ifc_rmp_bitmask_bits bitmask;
4965
4966         u8         reserved_at_c0[0x40];
4967
4968         struct mlx5_ifc_rmpc_bits ctx;
4969 };
4970
4971 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4972         u8         status[0x8];
4973         u8         reserved_at_8[0x18];
4974
4975         u8         syndrome[0x20];
4976
4977         u8         reserved_at_40[0x40];
4978 };
4979
4980 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4981         u8         reserved_at_0[0x16];
4982         u8         node_guid[0x1];
4983         u8         port_guid[0x1];
4984         u8         min_inline[0x1];
4985         u8         mtu[0x1];
4986         u8         change_event[0x1];
4987         u8         promisc[0x1];
4988         u8         permanent_address[0x1];
4989         u8         addresses_list[0x1];
4990         u8         roce_en[0x1];
4991         u8         reserved_at_1f[0x1];
4992 };
4993
4994 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4995         u8         opcode[0x10];
4996         u8         reserved_at_10[0x10];
4997
4998         u8         reserved_at_20[0x10];
4999         u8         op_mod[0x10];
5000
5001         u8         other_vport[0x1];
5002         u8         reserved_at_41[0xf];
5003         u8         vport_number[0x10];
5004
5005         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5006
5007         u8         reserved_at_80[0x780];
5008
5009         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5010 };
5011
5012 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5013         u8         status[0x8];
5014         u8         reserved_at_8[0x18];
5015
5016         u8         syndrome[0x20];
5017
5018         u8         reserved_at_40[0x40];
5019 };
5020
5021 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5022         u8         opcode[0x10];
5023         u8         reserved_at_10[0x10];
5024
5025         u8         reserved_at_20[0x10];
5026         u8         op_mod[0x10];
5027
5028         u8         other_vport[0x1];
5029         u8         reserved_at_41[0xb];
5030         u8         port_num[0x4];
5031         u8         vport_number[0x10];
5032
5033         u8         reserved_at_60[0x20];
5034
5035         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5036 };
5037
5038 struct mlx5_ifc_modify_cq_out_bits {
5039         u8         status[0x8];
5040         u8         reserved_at_8[0x18];
5041
5042         u8         syndrome[0x20];
5043
5044         u8         reserved_at_40[0x40];
5045 };
5046
5047 enum {
5048         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5049         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5050 };
5051
5052 struct mlx5_ifc_modify_cq_in_bits {
5053         u8         opcode[0x10];
5054         u8         reserved_at_10[0x10];
5055
5056         u8         reserved_at_20[0x10];
5057         u8         op_mod[0x10];
5058
5059         u8         reserved_at_40[0x8];
5060         u8         cqn[0x18];
5061
5062         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5063
5064         struct mlx5_ifc_cqc_bits cq_context;
5065
5066         u8         reserved_at_280[0x600];
5067
5068         u8         pas[0][0x40];
5069 };
5070
5071 struct mlx5_ifc_modify_cong_status_out_bits {
5072         u8         status[0x8];
5073         u8         reserved_at_8[0x18];
5074
5075         u8         syndrome[0x20];
5076
5077         u8         reserved_at_40[0x40];
5078 };
5079
5080 struct mlx5_ifc_modify_cong_status_in_bits {
5081         u8         opcode[0x10];
5082         u8         reserved_at_10[0x10];
5083
5084         u8         reserved_at_20[0x10];
5085         u8         op_mod[0x10];
5086
5087         u8         reserved_at_40[0x18];
5088         u8         priority[0x4];
5089         u8         cong_protocol[0x4];
5090
5091         u8         enable[0x1];
5092         u8         tag_enable[0x1];
5093         u8         reserved_at_62[0x1e];
5094 };
5095
5096 struct mlx5_ifc_modify_cong_params_out_bits {
5097         u8         status[0x8];
5098         u8         reserved_at_8[0x18];
5099
5100         u8         syndrome[0x20];
5101
5102         u8         reserved_at_40[0x40];
5103 };
5104
5105 struct mlx5_ifc_modify_cong_params_in_bits {
5106         u8         opcode[0x10];
5107         u8         reserved_at_10[0x10];
5108
5109         u8         reserved_at_20[0x10];
5110         u8         op_mod[0x10];
5111
5112         u8         reserved_at_40[0x1c];
5113         u8         cong_protocol[0x4];
5114
5115         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5116
5117         u8         reserved_at_80[0x80];
5118
5119         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5120 };
5121
5122 struct mlx5_ifc_manage_pages_out_bits {
5123         u8         status[0x8];
5124         u8         reserved_at_8[0x18];
5125
5126         u8         syndrome[0x20];
5127
5128         u8         output_num_entries[0x20];
5129
5130         u8         reserved_at_60[0x20];
5131
5132         u8         pas[0][0x40];
5133 };
5134
5135 enum {
5136         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5137         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5138         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5139 };
5140
5141 struct mlx5_ifc_manage_pages_in_bits {
5142         u8         opcode[0x10];
5143         u8         reserved_at_10[0x10];
5144
5145         u8         reserved_at_20[0x10];
5146         u8         op_mod[0x10];
5147
5148         u8         reserved_at_40[0x10];
5149         u8         function_id[0x10];
5150
5151         u8         input_num_entries[0x20];
5152
5153         u8         pas[0][0x40];
5154 };
5155
5156 struct mlx5_ifc_mad_ifc_out_bits {
5157         u8         status[0x8];
5158         u8         reserved_at_8[0x18];
5159
5160         u8         syndrome[0x20];
5161
5162         u8         reserved_at_40[0x40];
5163
5164         u8         response_mad_packet[256][0x8];
5165 };
5166
5167 struct mlx5_ifc_mad_ifc_in_bits {
5168         u8         opcode[0x10];
5169         u8         reserved_at_10[0x10];
5170
5171         u8         reserved_at_20[0x10];
5172         u8         op_mod[0x10];
5173
5174         u8         remote_lid[0x10];
5175         u8         reserved_at_50[0x8];
5176         u8         port[0x8];
5177
5178         u8         reserved_at_60[0x20];
5179
5180         u8         mad[256][0x8];
5181 };
5182
5183 struct mlx5_ifc_init_hca_out_bits {
5184         u8         status[0x8];
5185         u8         reserved_at_8[0x18];
5186
5187         u8         syndrome[0x20];
5188
5189         u8         reserved_at_40[0x40];
5190 };
5191
5192 struct mlx5_ifc_init_hca_in_bits {
5193         u8         opcode[0x10];
5194         u8         reserved_at_10[0x10];
5195
5196         u8         reserved_at_20[0x10];
5197         u8         op_mod[0x10];
5198
5199         u8         reserved_at_40[0x40];
5200 };
5201
5202 struct mlx5_ifc_init2rtr_qp_out_bits {
5203         u8         status[0x8];
5204         u8         reserved_at_8[0x18];
5205
5206         u8         syndrome[0x20];
5207
5208         u8         reserved_at_40[0x40];
5209 };
5210
5211 struct mlx5_ifc_init2rtr_qp_in_bits {
5212         u8         opcode[0x10];
5213         u8         reserved_at_10[0x10];
5214
5215         u8         reserved_at_20[0x10];
5216         u8         op_mod[0x10];
5217
5218         u8         reserved_at_40[0x8];
5219         u8         qpn[0x18];
5220
5221         u8         reserved_at_60[0x20];
5222
5223         u8         opt_param_mask[0x20];
5224
5225         u8         reserved_at_a0[0x20];
5226
5227         struct mlx5_ifc_qpc_bits qpc;
5228
5229         u8         reserved_at_800[0x80];
5230 };
5231
5232 struct mlx5_ifc_init2init_qp_out_bits {
5233         u8         status[0x8];
5234         u8         reserved_at_8[0x18];
5235
5236         u8         syndrome[0x20];
5237
5238         u8         reserved_at_40[0x40];
5239 };
5240
5241 struct mlx5_ifc_init2init_qp_in_bits {
5242         u8         opcode[0x10];
5243         u8         reserved_at_10[0x10];
5244
5245         u8         reserved_at_20[0x10];
5246         u8         op_mod[0x10];
5247
5248         u8         reserved_at_40[0x8];
5249         u8         qpn[0x18];
5250
5251         u8         reserved_at_60[0x20];
5252
5253         u8         opt_param_mask[0x20];
5254
5255         u8         reserved_at_a0[0x20];
5256
5257         struct mlx5_ifc_qpc_bits qpc;
5258
5259         u8         reserved_at_800[0x80];
5260 };
5261
5262 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5263         u8         status[0x8];
5264         u8         reserved_at_8[0x18];
5265
5266         u8         syndrome[0x20];
5267
5268         u8         reserved_at_40[0x40];
5269
5270         u8         packet_headers_log[128][0x8];
5271
5272         u8         packet_syndrome[64][0x8];
5273 };
5274
5275 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5276         u8         opcode[0x10];
5277         u8         reserved_at_10[0x10];
5278
5279         u8         reserved_at_20[0x10];
5280         u8         op_mod[0x10];
5281
5282         u8         reserved_at_40[0x40];
5283 };
5284
5285 struct mlx5_ifc_gen_eqe_in_bits {
5286         u8         opcode[0x10];
5287         u8         reserved_at_10[0x10];
5288
5289         u8         reserved_at_20[0x10];
5290         u8         op_mod[0x10];
5291
5292         u8         reserved_at_40[0x18];
5293         u8         eq_number[0x8];
5294
5295         u8         reserved_at_60[0x20];
5296
5297         u8         eqe[64][0x8];
5298 };
5299
5300 struct mlx5_ifc_gen_eq_out_bits {
5301         u8         status[0x8];
5302         u8         reserved_at_8[0x18];
5303
5304         u8         syndrome[0x20];
5305
5306         u8         reserved_at_40[0x40];
5307 };
5308
5309 struct mlx5_ifc_enable_hca_out_bits {
5310         u8         status[0x8];
5311         u8         reserved_at_8[0x18];
5312
5313         u8         syndrome[0x20];
5314
5315         u8         reserved_at_40[0x20];
5316 };
5317
5318 struct mlx5_ifc_enable_hca_in_bits {
5319         u8         opcode[0x10];
5320         u8         reserved_at_10[0x10];
5321
5322         u8         reserved_at_20[0x10];
5323         u8         op_mod[0x10];
5324
5325         u8         reserved_at_40[0x10];
5326         u8         function_id[0x10];
5327
5328         u8         reserved_at_60[0x20];
5329 };
5330
5331 struct mlx5_ifc_drain_dct_out_bits {
5332         u8         status[0x8];
5333         u8         reserved_at_8[0x18];
5334
5335         u8         syndrome[0x20];
5336
5337         u8         reserved_at_40[0x40];
5338 };
5339
5340 struct mlx5_ifc_drain_dct_in_bits {
5341         u8         opcode[0x10];
5342         u8         reserved_at_10[0x10];
5343
5344         u8         reserved_at_20[0x10];
5345         u8         op_mod[0x10];
5346
5347         u8         reserved_at_40[0x8];
5348         u8         dctn[0x18];
5349
5350         u8         reserved_at_60[0x20];
5351 };
5352
5353 struct mlx5_ifc_disable_hca_out_bits {
5354         u8         status[0x8];
5355         u8         reserved_at_8[0x18];
5356
5357         u8         syndrome[0x20];
5358
5359         u8         reserved_at_40[0x20];
5360 };
5361
5362 struct mlx5_ifc_disable_hca_in_bits {
5363         u8         opcode[0x10];
5364         u8         reserved_at_10[0x10];
5365
5366         u8         reserved_at_20[0x10];
5367         u8         op_mod[0x10];
5368
5369         u8         reserved_at_40[0x10];
5370         u8         function_id[0x10];
5371
5372         u8         reserved_at_60[0x20];
5373 };
5374
5375 struct mlx5_ifc_detach_from_mcg_out_bits {
5376         u8         status[0x8];
5377         u8         reserved_at_8[0x18];
5378
5379         u8         syndrome[0x20];
5380
5381         u8         reserved_at_40[0x40];
5382 };
5383
5384 struct mlx5_ifc_detach_from_mcg_in_bits {
5385         u8         opcode[0x10];
5386         u8         reserved_at_10[0x10];
5387
5388         u8         reserved_at_20[0x10];
5389         u8         op_mod[0x10];
5390
5391         u8         reserved_at_40[0x8];
5392         u8         qpn[0x18];
5393
5394         u8         reserved_at_60[0x20];
5395
5396         u8         multicast_gid[16][0x8];
5397 };
5398
5399 struct mlx5_ifc_destroy_xrq_out_bits {
5400         u8         status[0x8];
5401         u8         reserved_at_8[0x18];
5402
5403         u8         syndrome[0x20];
5404
5405         u8         reserved_at_40[0x40];
5406 };
5407
5408 struct mlx5_ifc_destroy_xrq_in_bits {
5409         u8         opcode[0x10];
5410         u8         reserved_at_10[0x10];
5411
5412         u8         reserved_at_20[0x10];
5413         u8         op_mod[0x10];
5414
5415         u8         reserved_at_40[0x8];
5416         u8         xrqn[0x18];
5417
5418         u8         reserved_at_60[0x20];
5419 };
5420
5421 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5422         u8         status[0x8];
5423         u8         reserved_at_8[0x18];
5424
5425         u8         syndrome[0x20];
5426
5427         u8         reserved_at_40[0x40];
5428 };
5429
5430 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5431         u8         opcode[0x10];
5432         u8         reserved_at_10[0x10];
5433
5434         u8         reserved_at_20[0x10];
5435         u8         op_mod[0x10];
5436
5437         u8         reserved_at_40[0x8];
5438         u8         xrc_srqn[0x18];
5439
5440         u8         reserved_at_60[0x20];
5441 };
5442
5443 struct mlx5_ifc_destroy_tis_out_bits {
5444         u8         status[0x8];
5445         u8         reserved_at_8[0x18];
5446
5447         u8         syndrome[0x20];
5448
5449         u8         reserved_at_40[0x40];
5450 };
5451
5452 struct mlx5_ifc_destroy_tis_in_bits {
5453         u8         opcode[0x10];
5454         u8         reserved_at_10[0x10];
5455
5456         u8         reserved_at_20[0x10];
5457         u8         op_mod[0x10];
5458
5459         u8         reserved_at_40[0x8];
5460         u8         tisn[0x18];
5461
5462         u8         reserved_at_60[0x20];
5463 };
5464
5465 struct mlx5_ifc_destroy_tir_out_bits {
5466         u8         status[0x8];
5467         u8         reserved_at_8[0x18];
5468
5469         u8         syndrome[0x20];
5470
5471         u8         reserved_at_40[0x40];
5472 };
5473
5474 struct mlx5_ifc_destroy_tir_in_bits {
5475         u8         opcode[0x10];
5476         u8         reserved_at_10[0x10];
5477
5478         u8         reserved_at_20[0x10];
5479         u8         op_mod[0x10];
5480
5481         u8         reserved_at_40[0x8];
5482         u8         tirn[0x18];
5483
5484         u8         reserved_at_60[0x20];
5485 };
5486
5487 struct mlx5_ifc_destroy_srq_out_bits {
5488         u8         status[0x8];
5489         u8         reserved_at_8[0x18];
5490
5491         u8         syndrome[0x20];
5492
5493         u8         reserved_at_40[0x40];
5494 };
5495
5496 struct mlx5_ifc_destroy_srq_in_bits {
5497         u8         opcode[0x10];
5498         u8         reserved_at_10[0x10];
5499
5500         u8         reserved_at_20[0x10];
5501         u8         op_mod[0x10];
5502
5503         u8         reserved_at_40[0x8];
5504         u8         srqn[0x18];
5505
5506         u8         reserved_at_60[0x20];
5507 };
5508
5509 struct mlx5_ifc_destroy_sq_out_bits {
5510         u8         status[0x8];
5511         u8         reserved_at_8[0x18];
5512
5513         u8         syndrome[0x20];
5514
5515         u8         reserved_at_40[0x40];
5516 };
5517
5518 struct mlx5_ifc_destroy_sq_in_bits {
5519         u8         opcode[0x10];
5520         u8         reserved_at_10[0x10];
5521
5522         u8         reserved_at_20[0x10];
5523         u8         op_mod[0x10];
5524
5525         u8         reserved_at_40[0x8];
5526         u8         sqn[0x18];
5527
5528         u8         reserved_at_60[0x20];
5529 };
5530
5531 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5532         u8         status[0x8];
5533         u8         reserved_at_8[0x18];
5534
5535         u8         syndrome[0x20];
5536
5537         u8         reserved_at_40[0x1c0];
5538 };
5539
5540 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5541         u8         opcode[0x10];
5542         u8         reserved_at_10[0x10];
5543
5544         u8         reserved_at_20[0x10];
5545         u8         op_mod[0x10];
5546
5547         u8         scheduling_hierarchy[0x8];
5548         u8         reserved_at_48[0x18];
5549
5550         u8         scheduling_element_id[0x20];
5551
5552         u8         reserved_at_80[0x180];
5553 };
5554
5555 struct mlx5_ifc_destroy_rqt_out_bits {
5556         u8         status[0x8];
5557         u8         reserved_at_8[0x18];
5558
5559         u8         syndrome[0x20];
5560
5561         u8         reserved_at_40[0x40];
5562 };
5563
5564 struct mlx5_ifc_destroy_rqt_in_bits {
5565         u8         opcode[0x10];
5566         u8         reserved_at_10[0x10];
5567
5568         u8         reserved_at_20[0x10];
5569         u8         op_mod[0x10];
5570
5571         u8         reserved_at_40[0x8];
5572         u8         rqtn[0x18];
5573
5574         u8         reserved_at_60[0x20];
5575 };
5576
5577 struct mlx5_ifc_destroy_rq_out_bits {
5578         u8         status[0x8];
5579         u8         reserved_at_8[0x18];
5580
5581         u8         syndrome[0x20];
5582
5583         u8         reserved_at_40[0x40];
5584 };
5585
5586 struct mlx5_ifc_destroy_rq_in_bits {
5587         u8         opcode[0x10];
5588         u8         reserved_at_10[0x10];
5589
5590         u8         reserved_at_20[0x10];
5591         u8         op_mod[0x10];
5592
5593         u8         reserved_at_40[0x8];
5594         u8         rqn[0x18];
5595
5596         u8         reserved_at_60[0x20];
5597 };
5598
5599 struct mlx5_ifc_destroy_rmp_out_bits {
5600         u8         status[0x8];
5601         u8         reserved_at_8[0x18];
5602
5603         u8         syndrome[0x20];
5604
5605         u8         reserved_at_40[0x40];
5606 };
5607
5608 struct mlx5_ifc_destroy_rmp_in_bits {
5609         u8         opcode[0x10];
5610         u8         reserved_at_10[0x10];
5611
5612         u8         reserved_at_20[0x10];
5613         u8         op_mod[0x10];
5614
5615         u8         reserved_at_40[0x8];
5616         u8         rmpn[0x18];
5617
5618         u8         reserved_at_60[0x20];
5619 };
5620
5621 struct mlx5_ifc_destroy_qp_out_bits {
5622         u8         status[0x8];
5623         u8         reserved_at_8[0x18];
5624
5625         u8         syndrome[0x20];
5626
5627         u8         reserved_at_40[0x40];
5628 };
5629
5630 struct mlx5_ifc_destroy_qp_in_bits {
5631         u8         opcode[0x10];
5632         u8         reserved_at_10[0x10];
5633
5634         u8         reserved_at_20[0x10];
5635         u8         op_mod[0x10];
5636
5637         u8         reserved_at_40[0x8];
5638         u8         qpn[0x18];
5639
5640         u8         reserved_at_60[0x20];
5641 };
5642
5643 struct mlx5_ifc_destroy_psv_out_bits {
5644         u8         status[0x8];
5645         u8         reserved_at_8[0x18];
5646
5647         u8         syndrome[0x20];
5648
5649         u8         reserved_at_40[0x40];
5650 };
5651
5652 struct mlx5_ifc_destroy_psv_in_bits {
5653         u8         opcode[0x10];
5654         u8         reserved_at_10[0x10];
5655
5656         u8         reserved_at_20[0x10];
5657         u8         op_mod[0x10];
5658
5659         u8         reserved_at_40[0x8];
5660         u8         psvn[0x18];
5661
5662         u8         reserved_at_60[0x20];
5663 };
5664
5665 struct mlx5_ifc_destroy_mkey_out_bits {
5666         u8         status[0x8];
5667         u8         reserved_at_8[0x18];
5668
5669         u8         syndrome[0x20];
5670
5671         u8         reserved_at_40[0x40];
5672 };
5673
5674 struct mlx5_ifc_destroy_mkey_in_bits {
5675         u8         opcode[0x10];
5676         u8         reserved_at_10[0x10];
5677
5678         u8         reserved_at_20[0x10];
5679         u8         op_mod[0x10];
5680
5681         u8         reserved_at_40[0x8];
5682         u8         mkey_index[0x18];
5683
5684         u8         reserved_at_60[0x20];
5685 };
5686
5687 struct mlx5_ifc_destroy_flow_table_out_bits {
5688         u8         status[0x8];
5689         u8         reserved_at_8[0x18];
5690
5691         u8         syndrome[0x20];
5692
5693         u8         reserved_at_40[0x40];
5694 };
5695
5696 struct mlx5_ifc_destroy_flow_table_in_bits {
5697         u8         opcode[0x10];
5698         u8         reserved_at_10[0x10];
5699
5700         u8         reserved_at_20[0x10];
5701         u8         op_mod[0x10];
5702
5703         u8         other_vport[0x1];
5704         u8         reserved_at_41[0xf];
5705         u8         vport_number[0x10];
5706
5707         u8         reserved_at_60[0x20];
5708
5709         u8         table_type[0x8];
5710         u8         reserved_at_88[0x18];
5711
5712         u8         reserved_at_a0[0x8];
5713         u8         table_id[0x18];
5714
5715         u8         reserved_at_c0[0x140];
5716 };
5717
5718 struct mlx5_ifc_destroy_flow_group_out_bits {
5719         u8         status[0x8];
5720         u8         reserved_at_8[0x18];
5721
5722         u8         syndrome[0x20];
5723
5724         u8         reserved_at_40[0x40];
5725 };
5726
5727 struct mlx5_ifc_destroy_flow_group_in_bits {
5728         u8         opcode[0x10];
5729         u8         reserved_at_10[0x10];
5730
5731         u8         reserved_at_20[0x10];
5732         u8         op_mod[0x10];
5733
5734         u8         other_vport[0x1];
5735         u8         reserved_at_41[0xf];
5736         u8         vport_number[0x10];
5737
5738         u8         reserved_at_60[0x20];
5739
5740         u8         table_type[0x8];
5741         u8         reserved_at_88[0x18];
5742
5743         u8         reserved_at_a0[0x8];
5744         u8         table_id[0x18];
5745
5746         u8         group_id[0x20];
5747
5748         u8         reserved_at_e0[0x120];
5749 };
5750
5751 struct mlx5_ifc_destroy_eq_out_bits {
5752         u8         status[0x8];
5753         u8         reserved_at_8[0x18];
5754
5755         u8         syndrome[0x20];
5756
5757         u8         reserved_at_40[0x40];
5758 };
5759
5760 struct mlx5_ifc_destroy_eq_in_bits {
5761         u8         opcode[0x10];
5762         u8         reserved_at_10[0x10];
5763
5764         u8         reserved_at_20[0x10];
5765         u8         op_mod[0x10];
5766
5767         u8         reserved_at_40[0x18];
5768         u8         eq_number[0x8];
5769
5770         u8         reserved_at_60[0x20];
5771 };
5772
5773 struct mlx5_ifc_destroy_dct_out_bits {
5774         u8         status[0x8];
5775         u8         reserved_at_8[0x18];
5776
5777         u8         syndrome[0x20];
5778
5779         u8         reserved_at_40[0x40];
5780 };
5781
5782 struct mlx5_ifc_destroy_dct_in_bits {
5783         u8         opcode[0x10];
5784         u8         reserved_at_10[0x10];
5785
5786         u8         reserved_at_20[0x10];
5787         u8         op_mod[0x10];
5788
5789         u8         reserved_at_40[0x8];
5790         u8         dctn[0x18];
5791
5792         u8         reserved_at_60[0x20];
5793 };
5794
5795 struct mlx5_ifc_destroy_cq_out_bits {
5796         u8         status[0x8];
5797         u8         reserved_at_8[0x18];
5798
5799         u8         syndrome[0x20];
5800
5801         u8         reserved_at_40[0x40];
5802 };
5803
5804 struct mlx5_ifc_destroy_cq_in_bits {
5805         u8         opcode[0x10];
5806         u8         reserved_at_10[0x10];
5807
5808         u8         reserved_at_20[0x10];
5809         u8         op_mod[0x10];
5810
5811         u8         reserved_at_40[0x8];
5812         u8         cqn[0x18];
5813
5814         u8         reserved_at_60[0x20];
5815 };
5816
5817 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5818         u8         status[0x8];
5819         u8         reserved_at_8[0x18];
5820
5821         u8         syndrome[0x20];
5822
5823         u8         reserved_at_40[0x40];
5824 };
5825
5826 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5827         u8         opcode[0x10];
5828         u8         reserved_at_10[0x10];
5829
5830         u8         reserved_at_20[0x10];
5831         u8         op_mod[0x10];
5832
5833         u8         reserved_at_40[0x20];
5834
5835         u8         reserved_at_60[0x10];
5836         u8         vxlan_udp_port[0x10];
5837 };
5838
5839 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5840         u8         status[0x8];
5841         u8         reserved_at_8[0x18];
5842
5843         u8         syndrome[0x20];
5844
5845         u8         reserved_at_40[0x40];
5846 };
5847
5848 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5849         u8         opcode[0x10];
5850         u8         reserved_at_10[0x10];
5851
5852         u8         reserved_at_20[0x10];
5853         u8         op_mod[0x10];
5854
5855         u8         reserved_at_40[0x60];
5856
5857         u8         reserved_at_a0[0x8];
5858         u8         table_index[0x18];
5859
5860         u8         reserved_at_c0[0x140];
5861 };
5862
5863 struct mlx5_ifc_delete_fte_out_bits {
5864         u8         status[0x8];
5865         u8         reserved_at_8[0x18];
5866
5867         u8         syndrome[0x20];
5868
5869         u8         reserved_at_40[0x40];
5870 };
5871
5872 struct mlx5_ifc_delete_fte_in_bits {
5873         u8         opcode[0x10];
5874         u8         reserved_at_10[0x10];
5875
5876         u8         reserved_at_20[0x10];
5877         u8         op_mod[0x10];
5878
5879         u8         other_vport[0x1];
5880         u8         reserved_at_41[0xf];
5881         u8         vport_number[0x10];
5882
5883         u8         reserved_at_60[0x20];
5884
5885         u8         table_type[0x8];
5886         u8         reserved_at_88[0x18];
5887
5888         u8         reserved_at_a0[0x8];
5889         u8         table_id[0x18];
5890
5891         u8         reserved_at_c0[0x40];
5892
5893         u8         flow_index[0x20];
5894
5895         u8         reserved_at_120[0xe0];
5896 };
5897
5898 struct mlx5_ifc_dealloc_xrcd_out_bits {
5899         u8         status[0x8];
5900         u8         reserved_at_8[0x18];
5901
5902         u8         syndrome[0x20];
5903
5904         u8         reserved_at_40[0x40];
5905 };
5906
5907 struct mlx5_ifc_dealloc_xrcd_in_bits {
5908         u8         opcode[0x10];
5909         u8         reserved_at_10[0x10];
5910
5911         u8         reserved_at_20[0x10];
5912         u8         op_mod[0x10];
5913
5914         u8         reserved_at_40[0x8];
5915         u8         xrcd[0x18];
5916
5917         u8         reserved_at_60[0x20];
5918 };
5919
5920 struct mlx5_ifc_dealloc_uar_out_bits {
5921         u8         status[0x8];
5922         u8         reserved_at_8[0x18];
5923
5924         u8         syndrome[0x20];
5925
5926         u8         reserved_at_40[0x40];
5927 };
5928
5929 struct mlx5_ifc_dealloc_uar_in_bits {
5930         u8         opcode[0x10];
5931         u8         reserved_at_10[0x10];
5932
5933         u8         reserved_at_20[0x10];
5934         u8         op_mod[0x10];
5935
5936         u8         reserved_at_40[0x8];
5937         u8         uar[0x18];
5938
5939         u8         reserved_at_60[0x20];
5940 };
5941
5942 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5943         u8         status[0x8];
5944         u8         reserved_at_8[0x18];
5945
5946         u8         syndrome[0x20];
5947
5948         u8         reserved_at_40[0x40];
5949 };
5950
5951 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5952         u8         opcode[0x10];
5953         u8         reserved_at_10[0x10];
5954
5955         u8         reserved_at_20[0x10];
5956         u8         op_mod[0x10];
5957
5958         u8         reserved_at_40[0x8];
5959         u8         transport_domain[0x18];
5960
5961         u8         reserved_at_60[0x20];
5962 };
5963
5964 struct mlx5_ifc_dealloc_q_counter_out_bits {
5965         u8         status[0x8];
5966         u8         reserved_at_8[0x18];
5967
5968         u8         syndrome[0x20];
5969
5970         u8         reserved_at_40[0x40];
5971 };
5972
5973 struct mlx5_ifc_dealloc_q_counter_in_bits {
5974         u8         opcode[0x10];
5975         u8         reserved_at_10[0x10];
5976
5977         u8         reserved_at_20[0x10];
5978         u8         op_mod[0x10];
5979
5980         u8         reserved_at_40[0x18];
5981         u8         counter_set_id[0x8];
5982
5983         u8         reserved_at_60[0x20];
5984 };
5985
5986 struct mlx5_ifc_dealloc_pd_out_bits {
5987         u8         status[0x8];
5988         u8         reserved_at_8[0x18];
5989
5990         u8         syndrome[0x20];
5991
5992         u8         reserved_at_40[0x40];
5993 };
5994
5995 struct mlx5_ifc_dealloc_pd_in_bits {
5996         u8         opcode[0x10];
5997         u8         reserved_at_10[0x10];
5998
5999         u8         reserved_at_20[0x10];
6000         u8         op_mod[0x10];
6001
6002         u8         reserved_at_40[0x8];
6003         u8         pd[0x18];
6004
6005         u8         reserved_at_60[0x20];
6006 };
6007
6008 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6009         u8         status[0x8];
6010         u8         reserved_at_8[0x18];
6011
6012         u8         syndrome[0x20];
6013
6014         u8         reserved_at_40[0x40];
6015 };
6016
6017 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6018         u8         opcode[0x10];
6019         u8         reserved_at_10[0x10];
6020
6021         u8         reserved_at_20[0x10];
6022         u8         op_mod[0x10];
6023
6024         u8         reserved_at_40[0x10];
6025         u8         flow_counter_id[0x10];
6026
6027         u8         reserved_at_60[0x20];
6028 };
6029
6030 struct mlx5_ifc_create_xrq_out_bits {
6031         u8         status[0x8];
6032         u8         reserved_at_8[0x18];
6033
6034         u8         syndrome[0x20];
6035
6036         u8         reserved_at_40[0x8];
6037         u8         xrqn[0x18];
6038
6039         u8         reserved_at_60[0x20];
6040 };
6041
6042 struct mlx5_ifc_create_xrq_in_bits {
6043         u8         opcode[0x10];
6044         u8         reserved_at_10[0x10];
6045
6046         u8         reserved_at_20[0x10];
6047         u8         op_mod[0x10];
6048
6049         u8         reserved_at_40[0x40];
6050
6051         struct mlx5_ifc_xrqc_bits xrq_context;
6052 };
6053
6054 struct mlx5_ifc_create_xrc_srq_out_bits {
6055         u8         status[0x8];
6056         u8         reserved_at_8[0x18];
6057
6058         u8         syndrome[0x20];
6059
6060         u8         reserved_at_40[0x8];
6061         u8         xrc_srqn[0x18];
6062
6063         u8         reserved_at_60[0x20];
6064 };
6065
6066 struct mlx5_ifc_create_xrc_srq_in_bits {
6067         u8         opcode[0x10];
6068         u8         reserved_at_10[0x10];
6069
6070         u8         reserved_at_20[0x10];
6071         u8         op_mod[0x10];
6072
6073         u8         reserved_at_40[0x40];
6074
6075         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6076
6077         u8         reserved_at_280[0x600];
6078
6079         u8         pas[0][0x40];
6080 };
6081
6082 struct mlx5_ifc_create_tis_out_bits {
6083         u8         status[0x8];
6084         u8         reserved_at_8[0x18];
6085
6086         u8         syndrome[0x20];
6087
6088         u8         reserved_at_40[0x8];
6089         u8         tisn[0x18];
6090
6091         u8         reserved_at_60[0x20];
6092 };
6093
6094 struct mlx5_ifc_create_tis_in_bits {
6095         u8         opcode[0x10];
6096         u8         reserved_at_10[0x10];
6097
6098         u8         reserved_at_20[0x10];
6099         u8         op_mod[0x10];
6100
6101         u8         reserved_at_40[0xc0];
6102
6103         struct mlx5_ifc_tisc_bits ctx;
6104 };
6105
6106 struct mlx5_ifc_create_tir_out_bits {
6107         u8         status[0x8];
6108         u8         reserved_at_8[0x18];
6109
6110         u8         syndrome[0x20];
6111
6112         u8         reserved_at_40[0x8];
6113         u8         tirn[0x18];
6114
6115         u8         reserved_at_60[0x20];
6116 };
6117
6118 struct mlx5_ifc_create_tir_in_bits {
6119         u8         opcode[0x10];
6120         u8         reserved_at_10[0x10];
6121
6122         u8         reserved_at_20[0x10];
6123         u8         op_mod[0x10];
6124
6125         u8         reserved_at_40[0xc0];
6126
6127         struct mlx5_ifc_tirc_bits ctx;
6128 };
6129
6130 struct mlx5_ifc_create_srq_out_bits {
6131         u8         status[0x8];
6132         u8         reserved_at_8[0x18];
6133
6134         u8         syndrome[0x20];
6135
6136         u8         reserved_at_40[0x8];
6137         u8         srqn[0x18];
6138
6139         u8         reserved_at_60[0x20];
6140 };
6141
6142 struct mlx5_ifc_create_srq_in_bits {
6143         u8         opcode[0x10];
6144         u8         reserved_at_10[0x10];
6145
6146         u8         reserved_at_20[0x10];
6147         u8         op_mod[0x10];
6148
6149         u8         reserved_at_40[0x40];
6150
6151         struct mlx5_ifc_srqc_bits srq_context_entry;
6152
6153         u8         reserved_at_280[0x600];
6154
6155         u8         pas[0][0x40];
6156 };
6157
6158 struct mlx5_ifc_create_sq_out_bits {
6159         u8         status[0x8];
6160         u8         reserved_at_8[0x18];
6161
6162         u8         syndrome[0x20];
6163
6164         u8         reserved_at_40[0x8];
6165         u8         sqn[0x18];
6166
6167         u8         reserved_at_60[0x20];
6168 };
6169
6170 struct mlx5_ifc_create_sq_in_bits {
6171         u8         opcode[0x10];
6172         u8         reserved_at_10[0x10];
6173
6174         u8         reserved_at_20[0x10];
6175         u8         op_mod[0x10];
6176
6177         u8         reserved_at_40[0xc0];
6178
6179         struct mlx5_ifc_sqc_bits ctx;
6180 };
6181
6182 struct mlx5_ifc_create_scheduling_element_out_bits {
6183         u8         status[0x8];
6184         u8         reserved_at_8[0x18];
6185
6186         u8         syndrome[0x20];
6187
6188         u8         reserved_at_40[0x40];
6189
6190         u8         scheduling_element_id[0x20];
6191
6192         u8         reserved_at_a0[0x160];
6193 };
6194
6195 struct mlx5_ifc_create_scheduling_element_in_bits {
6196         u8         opcode[0x10];
6197         u8         reserved_at_10[0x10];
6198
6199         u8         reserved_at_20[0x10];
6200         u8         op_mod[0x10];
6201
6202         u8         scheduling_hierarchy[0x8];
6203         u8         reserved_at_48[0x18];
6204
6205         u8         reserved_at_60[0xa0];
6206
6207         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6208
6209         u8         reserved_at_300[0x100];
6210 };
6211
6212 struct mlx5_ifc_create_rqt_out_bits {
6213         u8         status[0x8];
6214         u8         reserved_at_8[0x18];
6215
6216         u8         syndrome[0x20];
6217
6218         u8         reserved_at_40[0x8];
6219         u8         rqtn[0x18];
6220
6221         u8         reserved_at_60[0x20];
6222 };
6223
6224 struct mlx5_ifc_create_rqt_in_bits {
6225         u8         opcode[0x10];
6226         u8         reserved_at_10[0x10];
6227
6228         u8         reserved_at_20[0x10];
6229         u8         op_mod[0x10];
6230
6231         u8         reserved_at_40[0xc0];
6232
6233         struct mlx5_ifc_rqtc_bits rqt_context;
6234 };
6235
6236 struct mlx5_ifc_create_rq_out_bits {
6237         u8         status[0x8];
6238         u8         reserved_at_8[0x18];
6239
6240         u8         syndrome[0x20];
6241
6242         u8         reserved_at_40[0x8];
6243         u8         rqn[0x18];
6244
6245         u8         reserved_at_60[0x20];
6246 };
6247
6248 struct mlx5_ifc_create_rq_in_bits {
6249         u8         opcode[0x10];
6250         u8         reserved_at_10[0x10];
6251
6252         u8         reserved_at_20[0x10];
6253         u8         op_mod[0x10];
6254
6255         u8         reserved_at_40[0xc0];
6256
6257         struct mlx5_ifc_rqc_bits ctx;
6258 };
6259
6260 struct mlx5_ifc_create_rmp_out_bits {
6261         u8         status[0x8];
6262         u8         reserved_at_8[0x18];
6263
6264         u8         syndrome[0x20];
6265
6266         u8         reserved_at_40[0x8];
6267         u8         rmpn[0x18];
6268
6269         u8         reserved_at_60[0x20];
6270 };
6271
6272 struct mlx5_ifc_create_rmp_in_bits {
6273         u8         opcode[0x10];
6274         u8         reserved_at_10[0x10];
6275
6276         u8         reserved_at_20[0x10];
6277         u8         op_mod[0x10];
6278
6279         u8         reserved_at_40[0xc0];
6280
6281         struct mlx5_ifc_rmpc_bits ctx;
6282 };
6283
6284 struct mlx5_ifc_create_qp_out_bits {
6285         u8         status[0x8];
6286         u8         reserved_at_8[0x18];
6287
6288         u8         syndrome[0x20];
6289
6290         u8         reserved_at_40[0x8];
6291         u8         qpn[0x18];
6292
6293         u8         reserved_at_60[0x20];
6294 };
6295
6296 struct mlx5_ifc_create_qp_in_bits {
6297         u8         opcode[0x10];
6298         u8         reserved_at_10[0x10];
6299
6300         u8         reserved_at_20[0x10];
6301         u8         op_mod[0x10];
6302
6303         u8         reserved_at_40[0x40];
6304
6305         u8         opt_param_mask[0x20];
6306
6307         u8         reserved_at_a0[0x20];
6308
6309         struct mlx5_ifc_qpc_bits qpc;
6310
6311         u8         reserved_at_800[0x80];
6312
6313         u8         pas[0][0x40];
6314 };
6315
6316 struct mlx5_ifc_create_psv_out_bits {
6317         u8         status[0x8];
6318         u8         reserved_at_8[0x18];
6319
6320         u8         syndrome[0x20];
6321
6322         u8         reserved_at_40[0x40];
6323
6324         u8         reserved_at_80[0x8];
6325         u8         psv0_index[0x18];
6326
6327         u8         reserved_at_a0[0x8];
6328         u8         psv1_index[0x18];
6329
6330         u8         reserved_at_c0[0x8];
6331         u8         psv2_index[0x18];
6332
6333         u8         reserved_at_e0[0x8];
6334         u8         psv3_index[0x18];
6335 };
6336
6337 struct mlx5_ifc_create_psv_in_bits {
6338         u8         opcode[0x10];
6339         u8         reserved_at_10[0x10];
6340
6341         u8         reserved_at_20[0x10];
6342         u8         op_mod[0x10];
6343
6344         u8         num_psv[0x4];
6345         u8         reserved_at_44[0x4];
6346         u8         pd[0x18];
6347
6348         u8         reserved_at_60[0x20];
6349 };
6350
6351 struct mlx5_ifc_create_mkey_out_bits {
6352         u8         status[0x8];
6353         u8         reserved_at_8[0x18];
6354
6355         u8         syndrome[0x20];
6356
6357         u8         reserved_at_40[0x8];
6358         u8         mkey_index[0x18];
6359
6360         u8         reserved_at_60[0x20];
6361 };
6362
6363 struct mlx5_ifc_create_mkey_in_bits {
6364         u8         opcode[0x10];
6365         u8         reserved_at_10[0x10];
6366
6367         u8         reserved_at_20[0x10];
6368         u8         op_mod[0x10];
6369
6370         u8         reserved_at_40[0x20];
6371
6372         u8         pg_access[0x1];
6373         u8         reserved_at_61[0x1f];
6374
6375         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6376
6377         u8         reserved_at_280[0x80];
6378
6379         u8         translations_octword_actual_size[0x20];
6380
6381         u8         reserved_at_320[0x560];
6382
6383         u8         klm_pas_mtt[0][0x20];
6384 };
6385
6386 struct mlx5_ifc_create_flow_table_out_bits {
6387         u8         status[0x8];
6388         u8         reserved_at_8[0x18];
6389
6390         u8         syndrome[0x20];
6391
6392         u8         reserved_at_40[0x8];
6393         u8         table_id[0x18];
6394
6395         u8         reserved_at_60[0x20];
6396 };
6397
6398 struct mlx5_ifc_create_flow_table_in_bits {
6399         u8         opcode[0x10];
6400         u8         reserved_at_10[0x10];
6401
6402         u8         reserved_at_20[0x10];
6403         u8         op_mod[0x10];
6404
6405         u8         other_vport[0x1];
6406         u8         reserved_at_41[0xf];
6407         u8         vport_number[0x10];
6408
6409         u8         reserved_at_60[0x20];
6410
6411         u8         table_type[0x8];
6412         u8         reserved_at_88[0x18];
6413
6414         u8         reserved_at_a0[0x20];
6415
6416         u8         encap_en[0x1];
6417         u8         decap_en[0x1];
6418         u8         reserved_at_c2[0x2];
6419         u8         table_miss_mode[0x4];
6420         u8         level[0x8];
6421         u8         reserved_at_d0[0x8];
6422         u8         log_size[0x8];
6423
6424         u8         reserved_at_e0[0x8];
6425         u8         table_miss_id[0x18];
6426
6427         u8         reserved_at_100[0x8];
6428         u8         lag_master_next_table_id[0x18];
6429
6430         u8         reserved_at_120[0x80];
6431 };
6432
6433 struct mlx5_ifc_create_flow_group_out_bits {
6434         u8         status[0x8];
6435         u8         reserved_at_8[0x18];
6436
6437         u8         syndrome[0x20];
6438
6439         u8         reserved_at_40[0x8];
6440         u8         group_id[0x18];
6441
6442         u8         reserved_at_60[0x20];
6443 };
6444
6445 enum {
6446         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6447         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6448         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6449 };
6450
6451 struct mlx5_ifc_create_flow_group_in_bits {
6452         u8         opcode[0x10];
6453         u8         reserved_at_10[0x10];
6454
6455         u8         reserved_at_20[0x10];
6456         u8         op_mod[0x10];
6457
6458         u8         other_vport[0x1];
6459         u8         reserved_at_41[0xf];
6460         u8         vport_number[0x10];
6461
6462         u8         reserved_at_60[0x20];
6463
6464         u8         table_type[0x8];
6465         u8         reserved_at_88[0x18];
6466
6467         u8         reserved_at_a0[0x8];
6468         u8         table_id[0x18];
6469
6470         u8         reserved_at_c0[0x20];
6471
6472         u8         start_flow_index[0x20];
6473
6474         u8         reserved_at_100[0x20];
6475
6476         u8         end_flow_index[0x20];
6477
6478         u8         reserved_at_140[0xa0];
6479
6480         u8         reserved_at_1e0[0x18];
6481         u8         match_criteria_enable[0x8];
6482
6483         struct mlx5_ifc_fte_match_param_bits match_criteria;
6484
6485         u8         reserved_at_1200[0xe00];
6486 };
6487
6488 struct mlx5_ifc_create_eq_out_bits {
6489         u8         status[0x8];
6490         u8         reserved_at_8[0x18];
6491
6492         u8         syndrome[0x20];
6493
6494         u8         reserved_at_40[0x18];
6495         u8         eq_number[0x8];
6496
6497         u8         reserved_at_60[0x20];
6498 };
6499
6500 struct mlx5_ifc_create_eq_in_bits {
6501         u8         opcode[0x10];
6502         u8         reserved_at_10[0x10];
6503
6504         u8         reserved_at_20[0x10];
6505         u8         op_mod[0x10];
6506
6507         u8         reserved_at_40[0x40];
6508
6509         struct mlx5_ifc_eqc_bits eq_context_entry;
6510
6511         u8         reserved_at_280[0x40];
6512
6513         u8         event_bitmask[0x40];
6514
6515         u8         reserved_at_300[0x580];
6516
6517         u8         pas[0][0x40];
6518 };
6519
6520 struct mlx5_ifc_create_dct_out_bits {
6521         u8         status[0x8];
6522         u8         reserved_at_8[0x18];
6523
6524         u8         syndrome[0x20];
6525
6526         u8         reserved_at_40[0x8];
6527         u8         dctn[0x18];
6528
6529         u8         reserved_at_60[0x20];
6530 };
6531
6532 struct mlx5_ifc_create_dct_in_bits {
6533         u8         opcode[0x10];
6534         u8         reserved_at_10[0x10];
6535
6536         u8         reserved_at_20[0x10];
6537         u8         op_mod[0x10];
6538
6539         u8         reserved_at_40[0x40];
6540
6541         struct mlx5_ifc_dctc_bits dct_context_entry;
6542
6543         u8         reserved_at_280[0x180];
6544 };
6545
6546 struct mlx5_ifc_create_cq_out_bits {
6547         u8         status[0x8];
6548         u8         reserved_at_8[0x18];
6549
6550         u8         syndrome[0x20];
6551
6552         u8         reserved_at_40[0x8];
6553         u8         cqn[0x18];
6554
6555         u8         reserved_at_60[0x20];
6556 };
6557
6558 struct mlx5_ifc_create_cq_in_bits {
6559         u8         opcode[0x10];
6560         u8         reserved_at_10[0x10];
6561
6562         u8         reserved_at_20[0x10];
6563         u8         op_mod[0x10];
6564
6565         u8         reserved_at_40[0x40];
6566
6567         struct mlx5_ifc_cqc_bits cq_context;
6568
6569         u8         reserved_at_280[0x600];
6570
6571         u8         pas[0][0x40];
6572 };
6573
6574 struct mlx5_ifc_config_int_moderation_out_bits {
6575         u8         status[0x8];
6576         u8         reserved_at_8[0x18];
6577
6578         u8         syndrome[0x20];
6579
6580         u8         reserved_at_40[0x4];
6581         u8         min_delay[0xc];
6582         u8         int_vector[0x10];
6583
6584         u8         reserved_at_60[0x20];
6585 };
6586
6587 enum {
6588         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
6589         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
6590 };
6591
6592 struct mlx5_ifc_config_int_moderation_in_bits {
6593         u8         opcode[0x10];
6594         u8         reserved_at_10[0x10];
6595
6596         u8         reserved_at_20[0x10];
6597         u8         op_mod[0x10];
6598
6599         u8         reserved_at_40[0x4];
6600         u8         min_delay[0xc];
6601         u8         int_vector[0x10];
6602
6603         u8         reserved_at_60[0x20];
6604 };
6605
6606 struct mlx5_ifc_attach_to_mcg_out_bits {
6607         u8         status[0x8];
6608         u8         reserved_at_8[0x18];
6609
6610         u8         syndrome[0x20];
6611
6612         u8         reserved_at_40[0x40];
6613 };
6614
6615 struct mlx5_ifc_attach_to_mcg_in_bits {
6616         u8         opcode[0x10];
6617         u8         reserved_at_10[0x10];
6618
6619         u8         reserved_at_20[0x10];
6620         u8         op_mod[0x10];
6621
6622         u8         reserved_at_40[0x8];
6623         u8         qpn[0x18];
6624
6625         u8         reserved_at_60[0x20];
6626
6627         u8         multicast_gid[16][0x8];
6628 };
6629
6630 struct mlx5_ifc_arm_xrq_out_bits {
6631         u8         status[0x8];
6632         u8         reserved_at_8[0x18];
6633
6634         u8         syndrome[0x20];
6635
6636         u8         reserved_at_40[0x40];
6637 };
6638
6639 struct mlx5_ifc_arm_xrq_in_bits {
6640         u8         opcode[0x10];
6641         u8         reserved_at_10[0x10];
6642
6643         u8         reserved_at_20[0x10];
6644         u8         op_mod[0x10];
6645
6646         u8         reserved_at_40[0x8];
6647         u8         xrqn[0x18];
6648
6649         u8         reserved_at_60[0x10];
6650         u8         lwm[0x10];
6651 };
6652
6653 struct mlx5_ifc_arm_xrc_srq_out_bits {
6654         u8         status[0x8];
6655         u8         reserved_at_8[0x18];
6656
6657         u8         syndrome[0x20];
6658
6659         u8         reserved_at_40[0x40];
6660 };
6661
6662 enum {
6663         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
6664 };
6665
6666 struct mlx5_ifc_arm_xrc_srq_in_bits {
6667         u8         opcode[0x10];
6668         u8         reserved_at_10[0x10];
6669
6670         u8         reserved_at_20[0x10];
6671         u8         op_mod[0x10];
6672
6673         u8         reserved_at_40[0x8];
6674         u8         xrc_srqn[0x18];
6675
6676         u8         reserved_at_60[0x10];
6677         u8         lwm[0x10];
6678 };
6679
6680 struct mlx5_ifc_arm_rq_out_bits {
6681         u8         status[0x8];
6682         u8         reserved_at_8[0x18];
6683
6684         u8         syndrome[0x20];
6685
6686         u8         reserved_at_40[0x40];
6687 };
6688
6689 enum {
6690         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6691         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6692 };
6693
6694 struct mlx5_ifc_arm_rq_in_bits {
6695         u8         opcode[0x10];
6696         u8         reserved_at_10[0x10];
6697
6698         u8         reserved_at_20[0x10];
6699         u8         op_mod[0x10];
6700
6701         u8         reserved_at_40[0x8];
6702         u8         srq_number[0x18];
6703
6704         u8         reserved_at_60[0x10];
6705         u8         lwm[0x10];
6706 };
6707
6708 struct mlx5_ifc_arm_dct_out_bits {
6709         u8         status[0x8];
6710         u8         reserved_at_8[0x18];
6711
6712         u8         syndrome[0x20];
6713
6714         u8         reserved_at_40[0x40];
6715 };
6716
6717 struct mlx5_ifc_arm_dct_in_bits {
6718         u8         opcode[0x10];
6719         u8         reserved_at_10[0x10];
6720
6721         u8         reserved_at_20[0x10];
6722         u8         op_mod[0x10];
6723
6724         u8         reserved_at_40[0x8];
6725         u8         dct_number[0x18];
6726
6727         u8         reserved_at_60[0x20];
6728 };
6729
6730 struct mlx5_ifc_alloc_xrcd_out_bits {
6731         u8         status[0x8];
6732         u8         reserved_at_8[0x18];
6733
6734         u8         syndrome[0x20];
6735
6736         u8         reserved_at_40[0x8];
6737         u8         xrcd[0x18];
6738
6739         u8         reserved_at_60[0x20];
6740 };
6741
6742 struct mlx5_ifc_alloc_xrcd_in_bits {
6743         u8         opcode[0x10];
6744         u8         reserved_at_10[0x10];
6745
6746         u8         reserved_at_20[0x10];
6747         u8         op_mod[0x10];
6748
6749         u8         reserved_at_40[0x40];
6750 };
6751
6752 struct mlx5_ifc_alloc_uar_out_bits {
6753         u8         status[0x8];
6754         u8         reserved_at_8[0x18];
6755
6756         u8         syndrome[0x20];
6757
6758         u8         reserved_at_40[0x8];
6759         u8         uar[0x18];
6760
6761         u8         reserved_at_60[0x20];
6762 };
6763
6764 struct mlx5_ifc_alloc_uar_in_bits {
6765         u8         opcode[0x10];
6766         u8         reserved_at_10[0x10];
6767
6768         u8         reserved_at_20[0x10];
6769         u8         op_mod[0x10];
6770
6771         u8         reserved_at_40[0x40];
6772 };
6773
6774 struct mlx5_ifc_alloc_transport_domain_out_bits {
6775         u8         status[0x8];
6776         u8         reserved_at_8[0x18];
6777
6778         u8         syndrome[0x20];
6779
6780         u8         reserved_at_40[0x8];
6781         u8         transport_domain[0x18];
6782
6783         u8         reserved_at_60[0x20];
6784 };
6785
6786 struct mlx5_ifc_alloc_transport_domain_in_bits {
6787         u8         opcode[0x10];
6788         u8         reserved_at_10[0x10];
6789
6790         u8         reserved_at_20[0x10];
6791         u8         op_mod[0x10];
6792
6793         u8         reserved_at_40[0x40];
6794 };
6795
6796 struct mlx5_ifc_alloc_q_counter_out_bits {
6797         u8         status[0x8];
6798         u8         reserved_at_8[0x18];
6799
6800         u8         syndrome[0x20];
6801
6802         u8         reserved_at_40[0x18];
6803         u8         counter_set_id[0x8];
6804
6805         u8         reserved_at_60[0x20];
6806 };
6807
6808 struct mlx5_ifc_alloc_q_counter_in_bits {
6809         u8         opcode[0x10];
6810         u8         reserved_at_10[0x10];
6811
6812         u8         reserved_at_20[0x10];
6813         u8         op_mod[0x10];
6814
6815         u8         reserved_at_40[0x40];
6816 };
6817
6818 struct mlx5_ifc_alloc_pd_out_bits {
6819         u8         status[0x8];
6820         u8         reserved_at_8[0x18];
6821
6822         u8         syndrome[0x20];
6823
6824         u8         reserved_at_40[0x8];
6825         u8         pd[0x18];
6826
6827         u8         reserved_at_60[0x20];
6828 };
6829
6830 struct mlx5_ifc_alloc_pd_in_bits {
6831         u8         opcode[0x10];
6832         u8         reserved_at_10[0x10];
6833
6834         u8         reserved_at_20[0x10];
6835         u8         op_mod[0x10];
6836
6837         u8         reserved_at_40[0x40];
6838 };
6839
6840 struct mlx5_ifc_alloc_flow_counter_out_bits {
6841         u8         status[0x8];
6842         u8         reserved_at_8[0x18];
6843
6844         u8         syndrome[0x20];
6845
6846         u8         reserved_at_40[0x10];
6847         u8         flow_counter_id[0x10];
6848
6849         u8         reserved_at_60[0x20];
6850 };
6851
6852 struct mlx5_ifc_alloc_flow_counter_in_bits {
6853         u8         opcode[0x10];
6854         u8         reserved_at_10[0x10];
6855
6856         u8         reserved_at_20[0x10];
6857         u8         op_mod[0x10];
6858
6859         u8         reserved_at_40[0x40];
6860 };
6861
6862 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6863         u8         status[0x8];
6864         u8         reserved_at_8[0x18];
6865
6866         u8         syndrome[0x20];
6867
6868         u8         reserved_at_40[0x40];
6869 };
6870
6871 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6872         u8         opcode[0x10];
6873         u8         reserved_at_10[0x10];
6874
6875         u8         reserved_at_20[0x10];
6876         u8         op_mod[0x10];
6877
6878         u8         reserved_at_40[0x20];
6879
6880         u8         reserved_at_60[0x10];
6881         u8         vxlan_udp_port[0x10];
6882 };
6883
6884 struct mlx5_ifc_set_rate_limit_out_bits {
6885         u8         status[0x8];
6886         u8         reserved_at_8[0x18];
6887
6888         u8         syndrome[0x20];
6889
6890         u8         reserved_at_40[0x40];
6891 };
6892
6893 struct mlx5_ifc_set_rate_limit_in_bits {
6894         u8         opcode[0x10];
6895         u8         reserved_at_10[0x10];
6896
6897         u8         reserved_at_20[0x10];
6898         u8         op_mod[0x10];
6899
6900         u8         reserved_at_40[0x10];
6901         u8         rate_limit_index[0x10];
6902
6903         u8         reserved_at_60[0x20];
6904
6905         u8         rate_limit[0x20];
6906 };
6907
6908 struct mlx5_ifc_access_register_out_bits {
6909         u8         status[0x8];
6910         u8         reserved_at_8[0x18];
6911
6912         u8         syndrome[0x20];
6913
6914         u8         reserved_at_40[0x40];
6915
6916         u8         register_data[0][0x20];
6917 };
6918
6919 enum {
6920         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
6921         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
6922 };
6923
6924 struct mlx5_ifc_access_register_in_bits {
6925         u8         opcode[0x10];
6926         u8         reserved_at_10[0x10];
6927
6928         u8         reserved_at_20[0x10];
6929         u8         op_mod[0x10];
6930
6931         u8         reserved_at_40[0x10];
6932         u8         register_id[0x10];
6933
6934         u8         argument[0x20];
6935
6936         u8         register_data[0][0x20];
6937 };
6938
6939 struct mlx5_ifc_sltp_reg_bits {
6940         u8         status[0x4];
6941         u8         version[0x4];
6942         u8         local_port[0x8];
6943         u8         pnat[0x2];
6944         u8         reserved_at_12[0x2];
6945         u8         lane[0x4];
6946         u8         reserved_at_18[0x8];
6947
6948         u8         reserved_at_20[0x20];
6949
6950         u8         reserved_at_40[0x7];
6951         u8         polarity[0x1];
6952         u8         ob_tap0[0x8];
6953         u8         ob_tap1[0x8];
6954         u8         ob_tap2[0x8];
6955
6956         u8         reserved_at_60[0xc];
6957         u8         ob_preemp_mode[0x4];
6958         u8         ob_reg[0x8];
6959         u8         ob_bias[0x8];
6960
6961         u8         reserved_at_80[0x20];
6962 };
6963
6964 struct mlx5_ifc_slrg_reg_bits {
6965         u8         status[0x4];
6966         u8         version[0x4];
6967         u8         local_port[0x8];
6968         u8         pnat[0x2];
6969         u8         reserved_at_12[0x2];
6970         u8         lane[0x4];
6971         u8         reserved_at_18[0x8];
6972
6973         u8         time_to_link_up[0x10];
6974         u8         reserved_at_30[0xc];
6975         u8         grade_lane_speed[0x4];
6976
6977         u8         grade_version[0x8];
6978         u8         grade[0x18];
6979
6980         u8         reserved_at_60[0x4];
6981         u8         height_grade_type[0x4];
6982         u8         height_grade[0x18];
6983
6984         u8         height_dz[0x10];
6985         u8         height_dv[0x10];
6986
6987         u8         reserved_at_a0[0x10];
6988         u8         height_sigma[0x10];
6989
6990         u8         reserved_at_c0[0x20];
6991
6992         u8         reserved_at_e0[0x4];
6993         u8         phase_grade_type[0x4];
6994         u8         phase_grade[0x18];
6995
6996         u8         reserved_at_100[0x8];
6997         u8         phase_eo_pos[0x8];
6998         u8         reserved_at_110[0x8];
6999         u8         phase_eo_neg[0x8];
7000
7001         u8         ffe_set_tested[0x10];
7002         u8         test_errors_per_lane[0x10];
7003 };
7004
7005 struct mlx5_ifc_pvlc_reg_bits {
7006         u8         reserved_at_0[0x8];
7007         u8         local_port[0x8];
7008         u8         reserved_at_10[0x10];
7009
7010         u8         reserved_at_20[0x1c];
7011         u8         vl_hw_cap[0x4];
7012
7013         u8         reserved_at_40[0x1c];
7014         u8         vl_admin[0x4];
7015
7016         u8         reserved_at_60[0x1c];
7017         u8         vl_operational[0x4];
7018 };
7019
7020 struct mlx5_ifc_pude_reg_bits {
7021         u8         swid[0x8];
7022         u8         local_port[0x8];
7023         u8         reserved_at_10[0x4];
7024         u8         admin_status[0x4];
7025         u8         reserved_at_18[0x4];
7026         u8         oper_status[0x4];
7027
7028         u8         reserved_at_20[0x60];
7029 };
7030
7031 struct mlx5_ifc_ptys_reg_bits {
7032         u8         reserved_at_0[0x1];
7033         u8         an_disable_admin[0x1];
7034         u8         an_disable_cap[0x1];
7035         u8         reserved_at_3[0x5];
7036         u8         local_port[0x8];
7037         u8         reserved_at_10[0xd];
7038         u8         proto_mask[0x3];
7039
7040         u8         an_status[0x4];
7041         u8         reserved_at_24[0x3c];
7042
7043         u8         eth_proto_capability[0x20];
7044
7045         u8         ib_link_width_capability[0x10];
7046         u8         ib_proto_capability[0x10];
7047
7048         u8         reserved_at_a0[0x20];
7049
7050         u8         eth_proto_admin[0x20];
7051
7052         u8         ib_link_width_admin[0x10];
7053         u8         ib_proto_admin[0x10];
7054
7055         u8         reserved_at_100[0x20];
7056
7057         u8         eth_proto_oper[0x20];
7058
7059         u8         ib_link_width_oper[0x10];
7060         u8         ib_proto_oper[0x10];
7061
7062         u8         reserved_at_160[0x20];
7063
7064         u8         eth_proto_lp_advertise[0x20];
7065
7066         u8         reserved_at_1a0[0x60];
7067 };
7068
7069 struct mlx5_ifc_mlcr_reg_bits {
7070         u8         reserved_at_0[0x8];
7071         u8         local_port[0x8];
7072         u8         reserved_at_10[0x20];
7073
7074         u8         beacon_duration[0x10];
7075         u8         reserved_at_40[0x10];
7076
7077         u8         beacon_remain[0x10];
7078 };
7079
7080 struct mlx5_ifc_ptas_reg_bits {
7081         u8         reserved_at_0[0x20];
7082
7083         u8         algorithm_options[0x10];
7084         u8         reserved_at_30[0x4];
7085         u8         repetitions_mode[0x4];
7086         u8         num_of_repetitions[0x8];
7087
7088         u8         grade_version[0x8];
7089         u8         height_grade_type[0x4];
7090         u8         phase_grade_type[0x4];
7091         u8         height_grade_weight[0x8];
7092         u8         phase_grade_weight[0x8];
7093
7094         u8         gisim_measure_bits[0x10];
7095         u8         adaptive_tap_measure_bits[0x10];
7096
7097         u8         ber_bath_high_error_threshold[0x10];
7098         u8         ber_bath_mid_error_threshold[0x10];
7099
7100         u8         ber_bath_low_error_threshold[0x10];
7101         u8         one_ratio_high_threshold[0x10];
7102
7103         u8         one_ratio_high_mid_threshold[0x10];
7104         u8         one_ratio_low_mid_threshold[0x10];
7105
7106         u8         one_ratio_low_threshold[0x10];
7107         u8         ndeo_error_threshold[0x10];
7108
7109         u8         mixer_offset_step_size[0x10];
7110         u8         reserved_at_110[0x8];
7111         u8         mix90_phase_for_voltage_bath[0x8];
7112
7113         u8         mixer_offset_start[0x10];
7114         u8         mixer_offset_end[0x10];
7115
7116         u8         reserved_at_140[0x15];
7117         u8         ber_test_time[0xb];
7118 };
7119
7120 struct mlx5_ifc_pspa_reg_bits {
7121         u8         swid[0x8];
7122         u8         local_port[0x8];
7123         u8         sub_port[0x8];
7124         u8         reserved_at_18[0x8];
7125
7126         u8         reserved_at_20[0x20];
7127 };
7128
7129 struct mlx5_ifc_pqdr_reg_bits {
7130         u8         reserved_at_0[0x8];
7131         u8         local_port[0x8];
7132         u8         reserved_at_10[0x5];
7133         u8         prio[0x3];
7134         u8         reserved_at_18[0x6];
7135         u8         mode[0x2];
7136
7137         u8         reserved_at_20[0x20];
7138
7139         u8         reserved_at_40[0x10];
7140         u8         min_threshold[0x10];
7141
7142         u8         reserved_at_60[0x10];
7143         u8         max_threshold[0x10];
7144
7145         u8         reserved_at_80[0x10];
7146         u8         mark_probability_denominator[0x10];
7147
7148         u8         reserved_at_a0[0x60];
7149 };
7150
7151 struct mlx5_ifc_ppsc_reg_bits {
7152         u8         reserved_at_0[0x8];
7153         u8         local_port[0x8];
7154         u8         reserved_at_10[0x10];
7155
7156         u8         reserved_at_20[0x60];
7157
7158         u8         reserved_at_80[0x1c];
7159         u8         wrps_admin[0x4];
7160
7161         u8         reserved_at_a0[0x1c];
7162         u8         wrps_status[0x4];
7163
7164         u8         reserved_at_c0[0x8];
7165         u8         up_threshold[0x8];
7166         u8         reserved_at_d0[0x8];
7167         u8         down_threshold[0x8];
7168
7169         u8         reserved_at_e0[0x20];
7170
7171         u8         reserved_at_100[0x1c];
7172         u8         srps_admin[0x4];
7173
7174         u8         reserved_at_120[0x1c];
7175         u8         srps_status[0x4];
7176
7177         u8         reserved_at_140[0x40];
7178 };
7179
7180 struct mlx5_ifc_pplr_reg_bits {
7181         u8         reserved_at_0[0x8];
7182         u8         local_port[0x8];
7183         u8         reserved_at_10[0x10];
7184
7185         u8         reserved_at_20[0x8];
7186         u8         lb_cap[0x8];
7187         u8         reserved_at_30[0x8];
7188         u8         lb_en[0x8];
7189 };
7190
7191 struct mlx5_ifc_pplm_reg_bits {
7192         u8         reserved_at_0[0x8];
7193         u8         local_port[0x8];
7194         u8         reserved_at_10[0x10];
7195
7196         u8         reserved_at_20[0x20];
7197
7198         u8         port_profile_mode[0x8];
7199         u8         static_port_profile[0x8];
7200         u8         active_port_profile[0x8];
7201         u8         reserved_at_58[0x8];
7202
7203         u8         retransmission_active[0x8];
7204         u8         fec_mode_active[0x18];
7205
7206         u8         reserved_at_80[0x20];
7207 };
7208
7209 struct mlx5_ifc_ppcnt_reg_bits {
7210         u8         swid[0x8];
7211         u8         local_port[0x8];
7212         u8         pnat[0x2];
7213         u8         reserved_at_12[0x8];
7214         u8         grp[0x6];
7215
7216         u8         clr[0x1];
7217         u8         reserved_at_21[0x1c];
7218         u8         prio_tc[0x3];
7219
7220         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7221 };
7222
7223 struct mlx5_ifc_ppad_reg_bits {
7224         u8         reserved_at_0[0x3];
7225         u8         single_mac[0x1];
7226         u8         reserved_at_4[0x4];
7227         u8         local_port[0x8];
7228         u8         mac_47_32[0x10];
7229
7230         u8         mac_31_0[0x20];
7231
7232         u8         reserved_at_40[0x40];
7233 };
7234
7235 struct mlx5_ifc_pmtu_reg_bits {
7236         u8         reserved_at_0[0x8];
7237         u8         local_port[0x8];
7238         u8         reserved_at_10[0x10];
7239
7240         u8         max_mtu[0x10];
7241         u8         reserved_at_30[0x10];
7242
7243         u8         admin_mtu[0x10];
7244         u8         reserved_at_50[0x10];
7245
7246         u8         oper_mtu[0x10];
7247         u8         reserved_at_70[0x10];
7248 };
7249
7250 struct mlx5_ifc_pmpr_reg_bits {
7251         u8         reserved_at_0[0x8];
7252         u8         module[0x8];
7253         u8         reserved_at_10[0x10];
7254
7255         u8         reserved_at_20[0x18];
7256         u8         attenuation_5g[0x8];
7257
7258         u8         reserved_at_40[0x18];
7259         u8         attenuation_7g[0x8];
7260
7261         u8         reserved_at_60[0x18];
7262         u8         attenuation_12g[0x8];
7263 };
7264
7265 struct mlx5_ifc_pmpe_reg_bits {
7266         u8         reserved_at_0[0x8];
7267         u8         module[0x8];
7268         u8         reserved_at_10[0xc];
7269         u8         module_status[0x4];
7270
7271         u8         reserved_at_20[0x60];
7272 };
7273
7274 struct mlx5_ifc_pmpc_reg_bits {
7275         u8         module_state_updated[32][0x8];
7276 };
7277
7278 struct mlx5_ifc_pmlpn_reg_bits {
7279         u8         reserved_at_0[0x4];
7280         u8         mlpn_status[0x4];
7281         u8         local_port[0x8];
7282         u8         reserved_at_10[0x10];
7283
7284         u8         e[0x1];
7285         u8         reserved_at_21[0x1f];
7286 };
7287
7288 struct mlx5_ifc_pmlp_reg_bits {
7289         u8         rxtx[0x1];
7290         u8         reserved_at_1[0x7];
7291         u8         local_port[0x8];
7292         u8         reserved_at_10[0x8];
7293         u8         width[0x8];
7294
7295         u8         lane0_module_mapping[0x20];
7296
7297         u8         lane1_module_mapping[0x20];
7298
7299         u8         lane2_module_mapping[0x20];
7300
7301         u8         lane3_module_mapping[0x20];
7302
7303         u8         reserved_at_a0[0x160];
7304 };
7305
7306 struct mlx5_ifc_pmaos_reg_bits {
7307         u8         reserved_at_0[0x8];
7308         u8         module[0x8];
7309         u8         reserved_at_10[0x4];
7310         u8         admin_status[0x4];
7311         u8         reserved_at_18[0x4];
7312         u8         oper_status[0x4];
7313
7314         u8         ase[0x1];
7315         u8         ee[0x1];
7316         u8         reserved_at_22[0x1c];
7317         u8         e[0x2];
7318
7319         u8         reserved_at_40[0x40];
7320 };
7321
7322 struct mlx5_ifc_plpc_reg_bits {
7323         u8         reserved_at_0[0x4];
7324         u8         profile_id[0xc];
7325         u8         reserved_at_10[0x4];
7326         u8         proto_mask[0x4];
7327         u8         reserved_at_18[0x8];
7328
7329         u8         reserved_at_20[0x10];
7330         u8         lane_speed[0x10];
7331
7332         u8         reserved_at_40[0x17];
7333         u8         lpbf[0x1];
7334         u8         fec_mode_policy[0x8];
7335
7336         u8         retransmission_capability[0x8];
7337         u8         fec_mode_capability[0x18];
7338
7339         u8         retransmission_support_admin[0x8];
7340         u8         fec_mode_support_admin[0x18];
7341
7342         u8         retransmission_request_admin[0x8];
7343         u8         fec_mode_request_admin[0x18];
7344
7345         u8         reserved_at_c0[0x80];
7346 };
7347
7348 struct mlx5_ifc_plib_reg_bits {
7349         u8         reserved_at_0[0x8];
7350         u8         local_port[0x8];
7351         u8         reserved_at_10[0x8];
7352         u8         ib_port[0x8];
7353
7354         u8         reserved_at_20[0x60];
7355 };
7356
7357 struct mlx5_ifc_plbf_reg_bits {
7358         u8         reserved_at_0[0x8];
7359         u8         local_port[0x8];
7360         u8         reserved_at_10[0xd];
7361         u8         lbf_mode[0x3];
7362
7363         u8         reserved_at_20[0x20];
7364 };
7365
7366 struct mlx5_ifc_pipg_reg_bits {
7367         u8         reserved_at_0[0x8];
7368         u8         local_port[0x8];
7369         u8         reserved_at_10[0x10];
7370
7371         u8         dic[0x1];
7372         u8         reserved_at_21[0x19];
7373         u8         ipg[0x4];
7374         u8         reserved_at_3e[0x2];
7375 };
7376
7377 struct mlx5_ifc_pifr_reg_bits {
7378         u8         reserved_at_0[0x8];
7379         u8         local_port[0x8];
7380         u8         reserved_at_10[0x10];
7381
7382         u8         reserved_at_20[0xe0];
7383
7384         u8         port_filter[8][0x20];
7385
7386         u8         port_filter_update_en[8][0x20];
7387 };
7388
7389 struct mlx5_ifc_pfcc_reg_bits {
7390         u8         reserved_at_0[0x8];
7391         u8         local_port[0x8];
7392         u8         reserved_at_10[0x10];
7393
7394         u8         ppan[0x4];
7395         u8         reserved_at_24[0x4];
7396         u8         prio_mask_tx[0x8];
7397         u8         reserved_at_30[0x8];
7398         u8         prio_mask_rx[0x8];
7399
7400         u8         pptx[0x1];
7401         u8         aptx[0x1];
7402         u8         reserved_at_42[0x6];
7403         u8         pfctx[0x8];
7404         u8         reserved_at_50[0x10];
7405
7406         u8         pprx[0x1];
7407         u8         aprx[0x1];
7408         u8         reserved_at_62[0x6];
7409         u8         pfcrx[0x8];
7410         u8         reserved_at_70[0x10];
7411
7412         u8         reserved_at_80[0x80];
7413 };
7414
7415 struct mlx5_ifc_pelc_reg_bits {
7416         u8         op[0x4];
7417         u8         reserved_at_4[0x4];
7418         u8         local_port[0x8];
7419         u8         reserved_at_10[0x10];
7420
7421         u8         op_admin[0x8];
7422         u8         op_capability[0x8];
7423         u8         op_request[0x8];
7424         u8         op_active[0x8];
7425
7426         u8         admin[0x40];
7427
7428         u8         capability[0x40];
7429
7430         u8         request[0x40];
7431
7432         u8         active[0x40];
7433
7434         u8         reserved_at_140[0x80];
7435 };
7436
7437 struct mlx5_ifc_peir_reg_bits {
7438         u8         reserved_at_0[0x8];
7439         u8         local_port[0x8];
7440         u8         reserved_at_10[0x10];
7441
7442         u8         reserved_at_20[0xc];
7443         u8         error_count[0x4];
7444         u8         reserved_at_30[0x10];
7445
7446         u8         reserved_at_40[0xc];
7447         u8         lane[0x4];
7448         u8         reserved_at_50[0x8];
7449         u8         error_type[0x8];
7450 };
7451
7452 struct mlx5_ifc_pcap_reg_bits {
7453         u8         reserved_at_0[0x8];
7454         u8         local_port[0x8];
7455         u8         reserved_at_10[0x10];
7456
7457         u8         port_capability_mask[4][0x20];
7458 };
7459
7460 struct mlx5_ifc_paos_reg_bits {
7461         u8         swid[0x8];
7462         u8         local_port[0x8];
7463         u8         reserved_at_10[0x4];
7464         u8         admin_status[0x4];
7465         u8         reserved_at_18[0x4];
7466         u8         oper_status[0x4];
7467
7468         u8         ase[0x1];
7469         u8         ee[0x1];
7470         u8         reserved_at_22[0x1c];
7471         u8         e[0x2];
7472
7473         u8         reserved_at_40[0x40];
7474 };
7475
7476 struct mlx5_ifc_pamp_reg_bits {
7477         u8         reserved_at_0[0x8];
7478         u8         opamp_group[0x8];
7479         u8         reserved_at_10[0xc];
7480         u8         opamp_group_type[0x4];
7481
7482         u8         start_index[0x10];
7483         u8         reserved_at_30[0x4];
7484         u8         num_of_indices[0xc];
7485
7486         u8         index_data[18][0x10];
7487 };
7488
7489 struct mlx5_ifc_pcmr_reg_bits {
7490         u8         reserved_at_0[0x8];
7491         u8         local_port[0x8];
7492         u8         reserved_at_10[0x2e];
7493         u8         fcs_cap[0x1];
7494         u8         reserved_at_3f[0x1f];
7495         u8         fcs_chk[0x1];
7496         u8         reserved_at_5f[0x1];
7497 };
7498
7499 struct mlx5_ifc_lane_2_module_mapping_bits {
7500         u8         reserved_at_0[0x6];
7501         u8         rx_lane[0x2];
7502         u8         reserved_at_8[0x6];
7503         u8         tx_lane[0x2];
7504         u8         reserved_at_10[0x8];
7505         u8         module[0x8];
7506 };
7507
7508 struct mlx5_ifc_bufferx_reg_bits {
7509         u8         reserved_at_0[0x6];
7510         u8         lossy[0x1];
7511         u8         epsb[0x1];
7512         u8         reserved_at_8[0xc];
7513         u8         size[0xc];
7514
7515         u8         xoff_threshold[0x10];
7516         u8         xon_threshold[0x10];
7517 };
7518
7519 struct mlx5_ifc_set_node_in_bits {
7520         u8         node_description[64][0x8];
7521 };
7522
7523 struct mlx5_ifc_register_power_settings_bits {
7524         u8         reserved_at_0[0x18];
7525         u8         power_settings_level[0x8];
7526
7527         u8         reserved_at_20[0x60];
7528 };
7529
7530 struct mlx5_ifc_register_host_endianness_bits {
7531         u8         he[0x1];
7532         u8         reserved_at_1[0x1f];
7533
7534         u8         reserved_at_20[0x60];
7535 };
7536
7537 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7538         u8         reserved_at_0[0x20];
7539
7540         u8         mkey[0x20];
7541
7542         u8         addressh_63_32[0x20];
7543
7544         u8         addressl_31_0[0x20];
7545 };
7546
7547 struct mlx5_ifc_ud_adrs_vector_bits {
7548         u8         dc_key[0x40];
7549
7550         u8         ext[0x1];
7551         u8         reserved_at_41[0x7];
7552         u8         destination_qp_dct[0x18];
7553
7554         u8         static_rate[0x4];
7555         u8         sl_eth_prio[0x4];
7556         u8         fl[0x1];
7557         u8         mlid[0x7];
7558         u8         rlid_udp_sport[0x10];
7559
7560         u8         reserved_at_80[0x20];
7561
7562         u8         rmac_47_16[0x20];
7563
7564         u8         rmac_15_0[0x10];
7565         u8         tclass[0x8];
7566         u8         hop_limit[0x8];
7567
7568         u8         reserved_at_e0[0x1];
7569         u8         grh[0x1];
7570         u8         reserved_at_e2[0x2];
7571         u8         src_addr_index[0x8];
7572         u8         flow_label[0x14];
7573
7574         u8         rgid_rip[16][0x8];
7575 };
7576
7577 struct mlx5_ifc_pages_req_event_bits {
7578         u8         reserved_at_0[0x10];
7579         u8         function_id[0x10];
7580
7581         u8         num_pages[0x20];
7582
7583         u8         reserved_at_40[0xa0];
7584 };
7585
7586 struct mlx5_ifc_eqe_bits {
7587         u8         reserved_at_0[0x8];
7588         u8         event_type[0x8];
7589         u8         reserved_at_10[0x8];
7590         u8         event_sub_type[0x8];
7591
7592         u8         reserved_at_20[0xe0];
7593
7594         union mlx5_ifc_event_auto_bits event_data;
7595
7596         u8         reserved_at_1e0[0x10];
7597         u8         signature[0x8];
7598         u8         reserved_at_1f8[0x7];
7599         u8         owner[0x1];
7600 };
7601
7602 enum {
7603         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
7604 };
7605
7606 struct mlx5_ifc_cmd_queue_entry_bits {
7607         u8         type[0x8];
7608         u8         reserved_at_8[0x18];
7609
7610         u8         input_length[0x20];
7611
7612         u8         input_mailbox_pointer_63_32[0x20];
7613
7614         u8         input_mailbox_pointer_31_9[0x17];
7615         u8         reserved_at_77[0x9];
7616
7617         u8         command_input_inline_data[16][0x8];
7618
7619         u8         command_output_inline_data[16][0x8];
7620
7621         u8         output_mailbox_pointer_63_32[0x20];
7622
7623         u8         output_mailbox_pointer_31_9[0x17];
7624         u8         reserved_at_1b7[0x9];
7625
7626         u8         output_length[0x20];
7627
7628         u8         token[0x8];
7629         u8         signature[0x8];
7630         u8         reserved_at_1f0[0x8];
7631         u8         status[0x7];
7632         u8         ownership[0x1];
7633 };
7634
7635 struct mlx5_ifc_cmd_out_bits {
7636         u8         status[0x8];
7637         u8         reserved_at_8[0x18];
7638
7639         u8         syndrome[0x20];
7640
7641         u8         command_output[0x20];
7642 };
7643
7644 struct mlx5_ifc_cmd_in_bits {
7645         u8         opcode[0x10];
7646         u8         reserved_at_10[0x10];
7647
7648         u8         reserved_at_20[0x10];
7649         u8         op_mod[0x10];
7650
7651         u8         command[0][0x20];
7652 };
7653
7654 struct mlx5_ifc_cmd_if_box_bits {
7655         u8         mailbox_data[512][0x8];
7656
7657         u8         reserved_at_1000[0x180];
7658
7659         u8         next_pointer_63_32[0x20];
7660
7661         u8         next_pointer_31_10[0x16];
7662         u8         reserved_at_11b6[0xa];
7663
7664         u8         block_number[0x20];
7665
7666         u8         reserved_at_11e0[0x8];
7667         u8         token[0x8];
7668         u8         ctrl_signature[0x8];
7669         u8         signature[0x8];
7670 };
7671
7672 struct mlx5_ifc_mtt_bits {
7673         u8         ptag_63_32[0x20];
7674
7675         u8         ptag_31_8[0x18];
7676         u8         reserved_at_38[0x6];
7677         u8         wr_en[0x1];
7678         u8         rd_en[0x1];
7679 };
7680
7681 struct mlx5_ifc_query_wol_rol_out_bits {
7682         u8         status[0x8];
7683         u8         reserved_at_8[0x18];
7684
7685         u8         syndrome[0x20];
7686
7687         u8         reserved_at_40[0x10];
7688         u8         rol_mode[0x8];
7689         u8         wol_mode[0x8];
7690
7691         u8         reserved_at_60[0x20];
7692 };
7693
7694 struct mlx5_ifc_query_wol_rol_in_bits {
7695         u8         opcode[0x10];
7696         u8         reserved_at_10[0x10];
7697
7698         u8         reserved_at_20[0x10];
7699         u8         op_mod[0x10];
7700
7701         u8         reserved_at_40[0x40];
7702 };
7703
7704 struct mlx5_ifc_set_wol_rol_out_bits {
7705         u8         status[0x8];
7706         u8         reserved_at_8[0x18];
7707
7708         u8         syndrome[0x20];
7709
7710         u8         reserved_at_40[0x40];
7711 };
7712
7713 struct mlx5_ifc_set_wol_rol_in_bits {
7714         u8         opcode[0x10];
7715         u8         reserved_at_10[0x10];
7716
7717         u8         reserved_at_20[0x10];
7718         u8         op_mod[0x10];
7719
7720         u8         rol_mode_valid[0x1];
7721         u8         wol_mode_valid[0x1];
7722         u8         reserved_at_42[0xe];
7723         u8         rol_mode[0x8];
7724         u8         wol_mode[0x8];
7725
7726         u8         reserved_at_60[0x20];
7727 };
7728
7729 enum {
7730         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
7731         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
7732         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
7733 };
7734
7735 enum {
7736         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
7737         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
7738         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
7739 };
7740
7741 enum {
7742         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
7743         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
7744         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
7745         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
7746         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
7747         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
7748         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
7749         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
7750         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
7751         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
7752         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
7753 };
7754
7755 struct mlx5_ifc_initial_seg_bits {
7756         u8         fw_rev_minor[0x10];
7757         u8         fw_rev_major[0x10];
7758
7759         u8         cmd_interface_rev[0x10];
7760         u8         fw_rev_subminor[0x10];
7761
7762         u8         reserved_at_40[0x40];
7763
7764         u8         cmdq_phy_addr_63_32[0x20];
7765
7766         u8         cmdq_phy_addr_31_12[0x14];
7767         u8         reserved_at_b4[0x2];
7768         u8         nic_interface[0x2];
7769         u8         log_cmdq_size[0x4];
7770         u8         log_cmdq_stride[0x4];
7771
7772         u8         command_doorbell_vector[0x20];
7773
7774         u8         reserved_at_e0[0xf00];
7775
7776         u8         initializing[0x1];
7777         u8         reserved_at_fe1[0x4];
7778         u8         nic_interface_supported[0x3];
7779         u8         reserved_at_fe8[0x18];
7780
7781         struct mlx5_ifc_health_buffer_bits health_buffer;
7782
7783         u8         no_dram_nic_offset[0x20];
7784
7785         u8         reserved_at_1220[0x6e40];
7786
7787         u8         reserved_at_8060[0x1f];
7788         u8         clear_int[0x1];
7789
7790         u8         health_syndrome[0x8];
7791         u8         health_counter[0x18];
7792
7793         u8         reserved_at_80a0[0x17fc0];
7794 };
7795
7796 union mlx5_ifc_ports_control_registers_document_bits {
7797         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7798         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7799         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7800         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7801         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7802         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7803         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7804         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7805         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7806         struct mlx5_ifc_pamp_reg_bits pamp_reg;
7807         struct mlx5_ifc_paos_reg_bits paos_reg;
7808         struct mlx5_ifc_pcap_reg_bits pcap_reg;
7809         struct mlx5_ifc_peir_reg_bits peir_reg;
7810         struct mlx5_ifc_pelc_reg_bits pelc_reg;
7811         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
7812         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
7813         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7814         struct mlx5_ifc_pifr_reg_bits pifr_reg;
7815         struct mlx5_ifc_pipg_reg_bits pipg_reg;
7816         struct mlx5_ifc_plbf_reg_bits plbf_reg;
7817         struct mlx5_ifc_plib_reg_bits plib_reg;
7818         struct mlx5_ifc_plpc_reg_bits plpc_reg;
7819         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7820         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7821         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7822         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7823         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7824         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7825         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7826         struct mlx5_ifc_ppad_reg_bits ppad_reg;
7827         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7828         struct mlx5_ifc_pplm_reg_bits pplm_reg;
7829         struct mlx5_ifc_pplr_reg_bits pplr_reg;
7830         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7831         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7832         struct mlx5_ifc_pspa_reg_bits pspa_reg;
7833         struct mlx5_ifc_ptas_reg_bits ptas_reg;
7834         struct mlx5_ifc_ptys_reg_bits ptys_reg;
7835         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
7836         struct mlx5_ifc_pude_reg_bits pude_reg;
7837         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7838         struct mlx5_ifc_slrg_reg_bits slrg_reg;
7839         struct mlx5_ifc_sltp_reg_bits sltp_reg;
7840         u8         reserved_at_0[0x60e0];
7841 };
7842
7843 union mlx5_ifc_debug_enhancements_document_bits {
7844         struct mlx5_ifc_health_buffer_bits health_buffer;
7845         u8         reserved_at_0[0x200];
7846 };
7847
7848 union mlx5_ifc_uplink_pci_interface_document_bits {
7849         struct mlx5_ifc_initial_seg_bits initial_seg;
7850         u8         reserved_at_0[0x20060];
7851 };
7852
7853 struct mlx5_ifc_set_flow_table_root_out_bits {
7854         u8         status[0x8];
7855         u8         reserved_at_8[0x18];
7856
7857         u8         syndrome[0x20];
7858
7859         u8         reserved_at_40[0x40];
7860 };
7861
7862 struct mlx5_ifc_set_flow_table_root_in_bits {
7863         u8         opcode[0x10];
7864         u8         reserved_at_10[0x10];
7865
7866         u8         reserved_at_20[0x10];
7867         u8         op_mod[0x10];
7868
7869         u8         other_vport[0x1];
7870         u8         reserved_at_41[0xf];
7871         u8         vport_number[0x10];
7872
7873         u8         reserved_at_60[0x20];
7874
7875         u8         table_type[0x8];
7876         u8         reserved_at_88[0x18];
7877
7878         u8         reserved_at_a0[0x8];
7879         u8         table_id[0x18];
7880
7881         u8         reserved_at_c0[0x140];
7882 };
7883
7884 enum {
7885         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
7886         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
7887 };
7888
7889 struct mlx5_ifc_modify_flow_table_out_bits {
7890         u8         status[0x8];
7891         u8         reserved_at_8[0x18];
7892
7893         u8         syndrome[0x20];
7894
7895         u8         reserved_at_40[0x40];
7896 };
7897
7898 struct mlx5_ifc_modify_flow_table_in_bits {
7899         u8         opcode[0x10];
7900         u8         reserved_at_10[0x10];
7901
7902         u8         reserved_at_20[0x10];
7903         u8         op_mod[0x10];
7904
7905         u8         other_vport[0x1];
7906         u8         reserved_at_41[0xf];
7907         u8         vport_number[0x10];
7908
7909         u8         reserved_at_60[0x10];
7910         u8         modify_field_select[0x10];
7911
7912         u8         table_type[0x8];
7913         u8         reserved_at_88[0x18];
7914
7915         u8         reserved_at_a0[0x8];
7916         u8         table_id[0x18];
7917
7918         u8         reserved_at_c0[0x4];
7919         u8         table_miss_mode[0x4];
7920         u8         reserved_at_c8[0x18];
7921
7922         u8         reserved_at_e0[0x8];
7923         u8         table_miss_id[0x18];
7924
7925         u8         reserved_at_100[0x8];
7926         u8         lag_master_next_table_id[0x18];
7927
7928         u8         reserved_at_120[0x80];
7929 };
7930
7931 struct mlx5_ifc_ets_tcn_config_reg_bits {
7932         u8         g[0x1];
7933         u8         b[0x1];
7934         u8         r[0x1];
7935         u8         reserved_at_3[0x9];
7936         u8         group[0x4];
7937         u8         reserved_at_10[0x9];
7938         u8         bw_allocation[0x7];
7939
7940         u8         reserved_at_20[0xc];
7941         u8         max_bw_units[0x4];
7942         u8         reserved_at_30[0x8];
7943         u8         max_bw_value[0x8];
7944 };
7945
7946 struct mlx5_ifc_ets_global_config_reg_bits {
7947         u8         reserved_at_0[0x2];
7948         u8         r[0x1];
7949         u8         reserved_at_3[0x1d];
7950
7951         u8         reserved_at_20[0xc];
7952         u8         max_bw_units[0x4];
7953         u8         reserved_at_30[0x8];
7954         u8         max_bw_value[0x8];
7955 };
7956
7957 struct mlx5_ifc_qetc_reg_bits {
7958         u8                                         reserved_at_0[0x8];
7959         u8                                         port_number[0x8];
7960         u8                                         reserved_at_10[0x30];
7961
7962         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
7963         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7964 };
7965
7966 struct mlx5_ifc_qtct_reg_bits {
7967         u8         reserved_at_0[0x8];
7968         u8         port_number[0x8];
7969         u8         reserved_at_10[0xd];
7970         u8         prio[0x3];
7971
7972         u8         reserved_at_20[0x1d];
7973         u8         tclass[0x3];
7974 };
7975
7976 struct mlx5_ifc_mcia_reg_bits {
7977         u8         l[0x1];
7978         u8         reserved_at_1[0x7];
7979         u8         module[0x8];
7980         u8         reserved_at_10[0x8];
7981         u8         status[0x8];
7982
7983         u8         i2c_device_address[0x8];
7984         u8         page_number[0x8];
7985         u8         device_address[0x10];
7986
7987         u8         reserved_at_40[0x10];
7988         u8         size[0x10];
7989
7990         u8         reserved_at_60[0x20];
7991
7992         u8         dword_0[0x20];
7993         u8         dword_1[0x20];
7994         u8         dword_2[0x20];
7995         u8         dword_3[0x20];
7996         u8         dword_4[0x20];
7997         u8         dword_5[0x20];
7998         u8         dword_6[0x20];
7999         u8         dword_7[0x20];
8000         u8         dword_8[0x20];
8001         u8         dword_9[0x20];
8002         u8         dword_10[0x20];
8003         u8         dword_11[0x20];
8004 };
8005
8006 struct mlx5_ifc_dcbx_param_bits {
8007         u8         dcbx_cee_cap[0x1];
8008         u8         dcbx_ieee_cap[0x1];
8009         u8         dcbx_standby_cap[0x1];
8010         u8         reserved_at_0[0x5];
8011         u8         port_number[0x8];
8012         u8         reserved_at_10[0xa];
8013         u8         max_application_table_size[6];
8014         u8         reserved_at_20[0x15];
8015         u8         version_oper[0x3];
8016         u8         reserved_at_38[5];
8017         u8         version_admin[0x3];
8018         u8         willing_admin[0x1];
8019         u8         reserved_at_41[0x3];
8020         u8         pfc_cap_oper[0x4];
8021         u8         reserved_at_48[0x4];
8022         u8         pfc_cap_admin[0x4];
8023         u8         reserved_at_50[0x4];
8024         u8         num_of_tc_oper[0x4];
8025         u8         reserved_at_58[0x4];
8026         u8         num_of_tc_admin[0x4];
8027         u8         remote_willing[0x1];
8028         u8         reserved_at_61[3];
8029         u8         remote_pfc_cap[4];
8030         u8         reserved_at_68[0x14];
8031         u8         remote_num_of_tc[0x4];
8032         u8         reserved_at_80[0x18];
8033         u8         error[0x8];
8034         u8         reserved_at_a0[0x160];
8035 };
8036
8037 struct mlx5_ifc_lagc_bits {
8038         u8         reserved_at_0[0x1d];
8039         u8         lag_state[0x3];
8040
8041         u8         reserved_at_20[0x14];
8042         u8         tx_remap_affinity_2[0x4];
8043         u8         reserved_at_38[0x4];
8044         u8         tx_remap_affinity_1[0x4];
8045 };
8046
8047 struct mlx5_ifc_create_lag_out_bits {
8048         u8         status[0x8];
8049         u8         reserved_at_8[0x18];
8050
8051         u8         syndrome[0x20];
8052
8053         u8         reserved_at_40[0x40];
8054 };
8055
8056 struct mlx5_ifc_create_lag_in_bits {
8057         u8         opcode[0x10];
8058         u8         reserved_at_10[0x10];
8059
8060         u8         reserved_at_20[0x10];
8061         u8         op_mod[0x10];
8062
8063         struct mlx5_ifc_lagc_bits ctx;
8064 };
8065
8066 struct mlx5_ifc_modify_lag_out_bits {
8067         u8         status[0x8];
8068         u8         reserved_at_8[0x18];
8069
8070         u8         syndrome[0x20];
8071
8072         u8         reserved_at_40[0x40];
8073 };
8074
8075 struct mlx5_ifc_modify_lag_in_bits {
8076         u8         opcode[0x10];
8077         u8         reserved_at_10[0x10];
8078
8079         u8         reserved_at_20[0x10];
8080         u8         op_mod[0x10];
8081
8082         u8         reserved_at_40[0x20];
8083         u8         field_select[0x20];
8084
8085         struct mlx5_ifc_lagc_bits ctx;
8086 };
8087
8088 struct mlx5_ifc_query_lag_out_bits {
8089         u8         status[0x8];
8090         u8         reserved_at_8[0x18];
8091
8092         u8         syndrome[0x20];
8093
8094         u8         reserved_at_40[0x40];
8095
8096         struct mlx5_ifc_lagc_bits ctx;
8097 };
8098
8099 struct mlx5_ifc_query_lag_in_bits {
8100         u8         opcode[0x10];
8101         u8         reserved_at_10[0x10];
8102
8103         u8         reserved_at_20[0x10];
8104         u8         op_mod[0x10];
8105
8106         u8         reserved_at_40[0x40];
8107 };
8108
8109 struct mlx5_ifc_destroy_lag_out_bits {
8110         u8         status[0x8];
8111         u8         reserved_at_8[0x18];
8112
8113         u8         syndrome[0x20];
8114
8115         u8         reserved_at_40[0x40];
8116 };
8117
8118 struct mlx5_ifc_destroy_lag_in_bits {
8119         u8         opcode[0x10];
8120         u8         reserved_at_10[0x10];
8121
8122         u8         reserved_at_20[0x10];
8123         u8         op_mod[0x10];
8124
8125         u8         reserved_at_40[0x40];
8126 };
8127
8128 struct mlx5_ifc_create_vport_lag_out_bits {
8129         u8         status[0x8];
8130         u8         reserved_at_8[0x18];
8131
8132         u8         syndrome[0x20];
8133
8134         u8         reserved_at_40[0x40];
8135 };
8136
8137 struct mlx5_ifc_create_vport_lag_in_bits {
8138         u8         opcode[0x10];
8139         u8         reserved_at_10[0x10];
8140
8141         u8         reserved_at_20[0x10];
8142         u8         op_mod[0x10];
8143
8144         u8         reserved_at_40[0x40];
8145 };
8146
8147 struct mlx5_ifc_destroy_vport_lag_out_bits {
8148         u8         status[0x8];
8149         u8         reserved_at_8[0x18];
8150
8151         u8         syndrome[0x20];
8152
8153         u8         reserved_at_40[0x40];
8154 };
8155
8156 struct mlx5_ifc_destroy_vport_lag_in_bits {
8157         u8         opcode[0x10];
8158         u8         reserved_at_10[0x10];
8159
8160         u8         reserved_at_20[0x10];
8161         u8         op_mod[0x10];
8162
8163         u8         reserved_at_40[0x40];
8164 };
8165
8166 #endif /* MLX5_IFC_H */