include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  71 };
  72
  73 enum {
  74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  75         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  76 };
  77
  78 enum {
  79         MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4),
  80         MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5),
  81 };
  82
  83 enum {
  84         MLX5_OBJ_TYPE_UCTX = 0x0004,
  85 };
  86
  87 enum {
  88         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  89         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  90         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  91         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  92         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  93         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  94         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  95         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  96         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  97         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  98         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  99         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 100         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 101         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 102         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 103         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 104         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 105         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 106         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 107         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 108         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 109         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 110         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 111         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 112         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 113         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 114         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 115         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 116         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 117         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 118         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 119         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 120         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 121         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 122         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 123         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 124         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 125         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 126         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 127         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 128         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 129         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 130         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 131         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 132         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 133         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 134         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 135         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 136         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 137         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 138         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 139         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 140         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 141         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 142         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 143         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 144         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 145         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 146         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 147         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 148         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 149         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 150         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 151         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 152         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 153         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 154         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 155         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 156         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 157         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 158         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 159         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 160         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 161         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 162         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 163         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 164         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 165         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 166         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 167         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 168         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 169         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 170         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 171         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 172         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 173         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 174         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 175         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 176         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 177         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 178         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 179         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 180         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 181         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 182         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 183         MLX5_CMD_OP_NOP                           = 0x80d,
 184         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 185         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 186         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 187         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 188         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 189         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 190         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 191         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 192         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 193         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 194         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 195         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 196         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 197         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 198         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 199         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 200         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 201         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 202         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 203         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 204         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 205         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 206         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 207         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 208         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 209         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 210         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 211         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 212         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 213         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 214         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 215         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 216         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 217         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 218         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 219         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 220         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 221         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 222         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 223         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 224         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 225         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 226         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 227         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 228         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 229         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 230         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 231         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 232         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 233         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 234         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 235         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 236         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 237         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 238         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 239         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 240         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 241         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 242         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 243         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 244         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 245         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 246         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 247         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 248         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 249         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 250         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 251         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 252         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 253         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 254         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 255         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 256         MLX5_CMD_OP_MAX
 257 };
 258
 259 struct mlx5_ifc_flow_table_fields_supported_bits {
 260         u8         outer_dmac[0x1];
 261         u8         outer_smac[0x1];
 262         u8         outer_ether_type[0x1];
 263         u8         outer_ip_version[0x1];
 264         u8         outer_first_prio[0x1];
 265         u8         outer_first_cfi[0x1];
 266         u8         outer_first_vid[0x1];
 267         u8         outer_ipv4_ttl[0x1];
 268         u8         outer_second_prio[0x1];
 269         u8         outer_second_cfi[0x1];
 270         u8         outer_second_vid[0x1];
 271         u8         reserved_at_b[0x1];
 272         u8         outer_sip[0x1];
 273         u8         outer_dip[0x1];
 274         u8         outer_frag[0x1];
 275         u8         outer_ip_protocol[0x1];
 276         u8         outer_ip_ecn[0x1];
 277         u8         outer_ip_dscp[0x1];
 278         u8         outer_udp_sport[0x1];
 279         u8         outer_udp_dport[0x1];
 280         u8         outer_tcp_sport[0x1];
 281         u8         outer_tcp_dport[0x1];
 282         u8         outer_tcp_flags[0x1];
 283         u8         outer_gre_protocol[0x1];
 284         u8         outer_gre_key[0x1];
 285         u8         outer_vxlan_vni[0x1];
 286         u8         reserved_at_1a[0x5];
 287         u8         source_eswitch_port[0x1];
 288
 289         u8         inner_dmac[0x1];
 290         u8         inner_smac[0x1];
 291         u8         inner_ether_type[0x1];
 292         u8         inner_ip_version[0x1];
 293         u8         inner_first_prio[0x1];
 294         u8         inner_first_cfi[0x1];
 295         u8         inner_first_vid[0x1];
 296         u8         reserved_at_27[0x1];
 297         u8         inner_second_prio[0x1];
 298         u8         inner_second_cfi[0x1];
 299         u8         inner_second_vid[0x1];
 300         u8         reserved_at_2b[0x1];
 301         u8         inner_sip[0x1];
 302         u8         inner_dip[0x1];
 303         u8         inner_frag[0x1];
 304         u8         inner_ip_protocol[0x1];
 305         u8         inner_ip_ecn[0x1];
 306         u8         inner_ip_dscp[0x1];
 307         u8         inner_udp_sport[0x1];
 308         u8         inner_udp_dport[0x1];
 309         u8         inner_tcp_sport[0x1];
 310         u8         inner_tcp_dport[0x1];
 311         u8         inner_tcp_flags[0x1];
 312         u8         reserved_at_37[0x9];
 313
 314         u8         reserved_at_40[0x5];
 315         u8         outer_first_mpls_over_udp[0x4];
 316         u8         outer_first_mpls_over_gre[0x4];
 317         u8         inner_first_mpls[0x4];
 318         u8         outer_first_mpls[0x4];
 319         u8         reserved_at_55[0x2];
 320         u8         outer_esp_spi[0x1];
 321         u8         reserved_at_58[0x2];
 322         u8         bth_dst_qp[0x1];
 323
 324         u8         reserved_at_5b[0x25];
 325 };
 326
 327 struct mlx5_ifc_flow_table_prop_layout_bits {
 328         u8         ft_support[0x1];
 329         u8         reserved_at_1[0x1];
 330         u8         flow_counter[0x1];
 331         u8         flow_modify_en[0x1];
 332         u8         modify_root[0x1];
 333         u8         identified_miss_table_mode[0x1];
 334         u8         flow_table_modify[0x1];
 335         u8         encap[0x1];
 336         u8         decap[0x1];
 337         u8         reserved_at_9[0x1];
 338         u8         pop_vlan[0x1];
 339         u8         push_vlan[0x1];
 340         u8         reserved_at_c[0x14];
 341
 342         u8         reserved_at_20[0x2];
 343         u8         log_max_ft_size[0x6];
 344         u8         log_max_modify_header_context[0x8];
 345         u8         max_modify_header_actions[0x8];
 346         u8         max_ft_level[0x8];
 347
 348         u8         reserved_at_40[0x20];
 349
 350         u8         reserved_at_60[0x18];
 351         u8         log_max_ft_num[0x8];
 352
 353         u8         reserved_at_80[0x18];
 354         u8         log_max_destination[0x8];
 355
 356         u8         log_max_flow_counter[0x8];
 357         u8         reserved_at_a8[0x10];
 358         u8         log_max_flow[0x8];
 359
 360         u8         reserved_at_c0[0x40];
 361
 362         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 363
 364         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 365 };
 366
 367 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 368         u8         send[0x1];
 369         u8         receive[0x1];
 370         u8         write[0x1];
 371         u8         read[0x1];
 372         u8         atomic[0x1];
 373         u8         srq_receive[0x1];
 374         u8         reserved_at_6[0x1a];
 375 };
 376
 377 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 378         u8         smac_47_16[0x20];
 379
 380         u8         smac_15_0[0x10];
 381         u8         ethertype[0x10];
 382
 383         u8         dmac_47_16[0x20];
 384
 385         u8         dmac_15_0[0x10];
 386         u8         first_prio[0x3];
 387         u8         first_cfi[0x1];
 388         u8         first_vid[0xc];
 389
 390         u8         ip_protocol[0x8];
 391         u8         ip_dscp[0x6];
 392         u8         ip_ecn[0x2];
 393         u8         cvlan_tag[0x1];
 394         u8         svlan_tag[0x1];
 395         u8         frag[0x1];
 396         u8         ip_version[0x4];
 397         u8         tcp_flags[0x9];
 398
 399         u8         tcp_sport[0x10];
 400         u8         tcp_dport[0x10];
 401
 402         u8         reserved_at_c0[0x18];
 403         u8         ttl_hoplimit[0x8];
 404
 405         u8         udp_sport[0x10];
 406         u8         udp_dport[0x10];
 407
 408         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 409
 410         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 411 };
 412
 413 struct mlx5_ifc_fte_match_set_misc_bits {
 414         u8         reserved_at_0[0x8];
 415         u8         source_sqn[0x18];
 416
 417         u8         source_eswitch_owner_vhca_id[0x10];
 418         u8         source_port[0x10];
 419
 420         u8         outer_second_prio[0x3];
 421         u8         outer_second_cfi[0x1];
 422         u8         outer_second_vid[0xc];
 423         u8         inner_second_prio[0x3];
 424         u8         inner_second_cfi[0x1];
 425         u8         inner_second_vid[0xc];
 426
 427         u8         outer_second_cvlan_tag[0x1];
 428         u8         inner_second_cvlan_tag[0x1];
 429         u8         outer_second_svlan_tag[0x1];
 430         u8         inner_second_svlan_tag[0x1];
 431         u8         reserved_at_64[0xc];
 432         u8         gre_protocol[0x10];
 433
 434         u8         gre_key_h[0x18];
 435         u8         gre_key_l[0x8];
 436
 437         u8         vxlan_vni[0x18];
 438         u8         reserved_at_b8[0x8];
 439
 440         u8         reserved_at_c0[0x20];
 441
 442         u8         reserved_at_e0[0xc];
 443         u8         outer_ipv6_flow_label[0x14];
 444
 445         u8         reserved_at_100[0xc];
 446         u8         inner_ipv6_flow_label[0x14];
 447
 448         u8         reserved_at_120[0x28];
 449         u8         bth_dst_qp[0x18];
 450         u8         reserved_at_160[0x20];
 451         u8         outer_esp_spi[0x20];
 452         u8         reserved_at_1a0[0x60];
 453 };
 454
 455 struct mlx5_ifc_fte_match_mpls_bits {
 456         u8         mpls_label[0x14];
 457         u8         mpls_exp[0x3];
 458         u8         mpls_s_bos[0x1];
 459         u8         mpls_ttl[0x8];
 460 };
 461
 462 struct mlx5_ifc_fte_match_set_misc2_bits {
 463         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 464
 465         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 466
 467         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 468
 469         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 470
 471         u8         reserved_at_80[0x100];
 472
 473         u8         metadata_reg_a[0x20];
 474
 475         u8         reserved_at_1a0[0x60];
 476 };
 477
 478 struct mlx5_ifc_cmd_pas_bits {
 479         u8         pa_h[0x20];
 480
 481         u8         pa_l[0x14];
 482         u8         reserved_at_34[0xc];
 483 };
 484
 485 struct mlx5_ifc_uint64_bits {
 486         u8         hi[0x20];
 487
 488         u8         lo[0x20];
 489 };
 490
 491 enum {
 492         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 493         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 494         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 495         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 496         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 497         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 498         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 499         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 500         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 501         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 502 };
 503
 504 struct mlx5_ifc_ads_bits {
 505         u8         fl[0x1];
 506         u8         free_ar[0x1];
 507         u8         reserved_at_2[0xe];
 508         u8         pkey_index[0x10];
 509
 510         u8         reserved_at_20[0x8];
 511         u8         grh[0x1];
 512         u8         mlid[0x7];
 513         u8         rlid[0x10];
 514
 515         u8         ack_timeout[0x5];
 516         u8         reserved_at_45[0x3];
 517         u8         src_addr_index[0x8];
 518         u8         reserved_at_50[0x4];
 519         u8         stat_rate[0x4];
 520         u8         hop_limit[0x8];
 521
 522         u8         reserved_at_60[0x4];
 523         u8         tclass[0x8];
 524         u8         flow_label[0x14];
 525
 526         u8         rgid_rip[16][0x8];
 527
 528         u8         reserved_at_100[0x4];
 529         u8         f_dscp[0x1];
 530         u8         f_ecn[0x1];
 531         u8         reserved_at_106[0x1];
 532         u8         f_eth_prio[0x1];
 533         u8         ecn[0x2];
 534         u8         dscp[0x6];
 535         u8         udp_sport[0x10];
 536
 537         u8         dei_cfi[0x1];
 538         u8         eth_prio[0x3];
 539         u8         sl[0x4];
 540         u8         vhca_port_num[0x8];
 541         u8         rmac_47_32[0x10];
 542
 543         u8         rmac_31_0[0x20];
 544 };
 545
 546 struct mlx5_ifc_flow_table_nic_cap_bits {
 547         u8         nic_rx_multi_path_tirs[0x1];
 548         u8         nic_rx_multi_path_tirs_fts[0x1];
 549         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 550         u8         reserved_at_3[0x1fd];
 551
 552         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 553
 554         u8         reserved_at_400[0x200];
 555
 556         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 557
 558         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 559
 560         u8         reserved_at_a00[0x200];
 561
 562         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 563
 564         u8         reserved_at_e00[0x7200];
 565 };
 566
 567 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 568         u8      reserved_at_0[0x1c];
 569         u8      fdb_multi_path_to_table[0x1];
 570         u8      reserved_at_1d[0x1e3];
 571
 572         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 573
 574         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 575
 576         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 577
 578         u8      reserved_at_800[0x7800];
 579 };
 580
 581 struct mlx5_ifc_e_switch_cap_bits {
 582         u8         vport_svlan_strip[0x1];
 583         u8         vport_cvlan_strip[0x1];
 584         u8         vport_svlan_insert[0x1];
 585         u8         vport_cvlan_insert_if_not_exist[0x1];
 586         u8         vport_cvlan_insert_overwrite[0x1];
 587         u8         reserved_at_5[0x18];
 588         u8         merged_eswitch[0x1];
 589         u8         nic_vport_node_guid_modify[0x1];
 590         u8         nic_vport_port_guid_modify[0x1];
 591
 592         u8         vxlan_encap_decap[0x1];
 593         u8         nvgre_encap_decap[0x1];
 594         u8         reserved_at_22[0x9];
 595         u8         log_max_encap_headers[0x5];
 596         u8         reserved_2b[0x6];
 597         u8         max_encap_header_size[0xa];
 598
 599         u8         reserved_40[0x7c0];
 600
 601 };
 602
 603 struct mlx5_ifc_qos_cap_bits {
 604         u8         packet_pacing[0x1];
 605         u8         esw_scheduling[0x1];
 606         u8         esw_bw_share[0x1];
 607         u8         esw_rate_limit[0x1];
 608         u8         reserved_at_4[0x1];
 609         u8         packet_pacing_burst_bound[0x1];
 610         u8         packet_pacing_typical_size[0x1];
 611         u8         reserved_at_7[0x19];
 612
 613         u8         reserved_at_20[0x20];
 614
 615         u8         packet_pacing_max_rate[0x20];
 616
 617         u8         packet_pacing_min_rate[0x20];
 618
 619         u8         reserved_at_80[0x10];
 620         u8         packet_pacing_rate_table_size[0x10];
 621
 622         u8         esw_element_type[0x10];
 623         u8         esw_tsar_type[0x10];
 624
 625         u8         reserved_at_c0[0x10];
 626         u8         max_qos_para_vport[0x10];
 627
 628         u8         max_tsar_bw_share[0x20];
 629
 630         u8         reserved_at_100[0x700];
 631 };
 632
 633 struct mlx5_ifc_debug_cap_bits {
 634         u8         reserved_at_0[0x20];
 635
 636         u8         reserved_at_20[0x2];
 637         u8         stall_detect[0x1];
 638         u8         reserved_at_23[0x1d];
 639
 640         u8         reserved_at_40[0x7c0];
 641 };
 642
 643 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 644         u8         csum_cap[0x1];
 645         u8         vlan_cap[0x1];
 646         u8         lro_cap[0x1];
 647         u8         lro_psh_flag[0x1];
 648         u8         lro_time_stamp[0x1];
 649         u8         reserved_at_5[0x2];
 650         u8         wqe_vlan_insert[0x1];
 651         u8         self_lb_en_modifiable[0x1];
 652         u8         reserved_at_9[0x2];
 653         u8         max_lso_cap[0x5];
 654         u8         multi_pkt_send_wqe[0x2];
 655         u8         wqe_inline_mode[0x2];
 656         u8         rss_ind_tbl_cap[0x4];
 657         u8         reg_umr_sq[0x1];
 658         u8         scatter_fcs[0x1];
 659         u8         enhanced_multi_pkt_send_wqe[0x1];
 660         u8         tunnel_lso_const_out_ip_id[0x1];
 661         u8         reserved_at_1c[0x2];
 662         u8         tunnel_stateless_gre[0x1];
 663         u8         tunnel_stateless_vxlan[0x1];
 664
 665         u8         swp[0x1];
 666         u8         swp_csum[0x1];
 667         u8         swp_lso[0x1];
 668         u8         reserved_at_23[0x1b];
 669         u8         max_geneve_opt_len[0x1];
 670         u8         tunnel_stateless_geneve_rx[0x1];
 671
 672         u8         reserved_at_40[0x10];
 673         u8         lro_min_mss_size[0x10];
 674
 675         u8         reserved_at_60[0x120];
 676
 677         u8         lro_timer_supported_periods[4][0x20];
 678
 679         u8         reserved_at_200[0x600];
 680 };
 681
 682 struct mlx5_ifc_roce_cap_bits {
 683         u8         roce_apm[0x1];
 684         u8         reserved_at_1[0x1f];
 685
 686         u8         reserved_at_20[0x60];
 687
 688         u8         reserved_at_80[0xc];
 689         u8         l3_type[0x4];
 690         u8         reserved_at_90[0x8];
 691         u8         roce_version[0x8];
 692
 693         u8         reserved_at_a0[0x10];
 694         u8         r_roce_dest_udp_port[0x10];
 695
 696         u8         r_roce_max_src_udp_port[0x10];
 697         u8         r_roce_min_src_udp_port[0x10];
 698
 699         u8         reserved_at_e0[0x10];
 700         u8         roce_address_table_size[0x10];
 701
 702         u8         reserved_at_100[0x700];
 703 };
 704
 705 struct mlx5_ifc_device_mem_cap_bits {
 706         u8         memic[0x1];
 707         u8         reserved_at_1[0x1f];
 708
 709         u8         reserved_at_20[0xb];
 710         u8         log_min_memic_alloc_size[0x5];
 711         u8         reserved_at_30[0x8];
 712         u8         log_max_memic_addr_alignment[0x8];
 713
 714         u8         memic_bar_start_addr[0x40];
 715
 716         u8         memic_bar_size[0x20];
 717
 718         u8         max_memic_size[0x20];
 719
 720         u8         reserved_at_c0[0x740];
 721 };
 722
 723 enum {
 724         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 725         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 726         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 727         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 728         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 729         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 730         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 731         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 732         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 733 };
 734
 735 enum {
 736         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 737         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 738         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 739         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 740         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 741         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 742         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 743         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 744         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 745 };
 746
 747 struct mlx5_ifc_atomic_caps_bits {
 748         u8         reserved_at_0[0x40];
 749
 750         u8         atomic_req_8B_endianness_mode[0x2];
 751         u8         reserved_at_42[0x4];
 752         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 753
 754         u8         reserved_at_47[0x19];
 755
 756         u8         reserved_at_60[0x20];
 757
 758         u8         reserved_at_80[0x10];
 759         u8         atomic_operations[0x10];
 760
 761         u8         reserved_at_a0[0x10];
 762         u8         atomic_size_qp[0x10];
 763
 764         u8         reserved_at_c0[0x10];
 765         u8         atomic_size_dc[0x10];
 766
 767         u8         reserved_at_e0[0x720];
 768 };
 769
 770 struct mlx5_ifc_odp_cap_bits {
 771         u8         reserved_at_0[0x40];
 772
 773         u8         sig[0x1];
 774         u8         reserved_at_41[0x1f];
 775
 776         u8         reserved_at_60[0x20];
 777
 778         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 779
 780         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 781
 782         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 783
 784         u8         reserved_at_e0[0x720];
 785 };
 786
 787 struct mlx5_ifc_calc_op {
 788         u8        reserved_at_0[0x10];
 789         u8        reserved_at_10[0x9];
 790         u8        op_swap_endianness[0x1];
 791         u8        op_min[0x1];
 792         u8        op_xor[0x1];
 793         u8        op_or[0x1];
 794         u8        op_and[0x1];
 795         u8        op_max[0x1];
 796         u8        op_add[0x1];
 797 };
 798
 799 struct mlx5_ifc_vector_calc_cap_bits {
 800         u8         calc_matrix[0x1];
 801         u8         reserved_at_1[0x1f];
 802         u8         reserved_at_20[0x8];
 803         u8         max_vec_count[0x8];
 804         u8         reserved_at_30[0xd];
 805         u8         max_chunk_size[0x3];
 806         struct mlx5_ifc_calc_op calc0;
 807         struct mlx5_ifc_calc_op calc1;
 808         struct mlx5_ifc_calc_op calc2;
 809         struct mlx5_ifc_calc_op calc3;
 810
 811         u8         reserved_at_e0[0x720];
 812 };
 813
 814 enum {
 815         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 816         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 817         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 818         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
 819 };
 820
 821 enum {
 822         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 823         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 824 };
 825
 826 enum {
 827         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 828         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 829         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 830         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 831         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 832 };
 833
 834 enum {
 835         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 836         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 837         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 838         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 839         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 840         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 841 };
 842
 843 enum {
 844         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 845         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 846 };
 847
 848 enum {
 849         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 850         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 851         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 852 };
 853
 854 enum {
 855         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 856         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 857 };
 858
 859 enum {
 860         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
 861         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
 862         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
 863 };
 864
 865 struct mlx5_ifc_cmd_hca_cap_bits {
 866         u8         reserved_at_0[0x30];
 867         u8         vhca_id[0x10];
 868
 869         u8         reserved_at_40[0x40];
 870
 871         u8         log_max_srq_sz[0x8];
 872         u8         log_max_qp_sz[0x8];
 873         u8         reserved_at_90[0xb];
 874         u8         log_max_qp[0x5];
 875
 876         u8         reserved_at_a0[0xb];
 877         u8         log_max_srq[0x5];
 878         u8         reserved_at_b0[0x10];
 879
 880         u8         reserved_at_c0[0x8];
 881         u8         log_max_cq_sz[0x8];
 882         u8         reserved_at_d0[0xb];
 883         u8         log_max_cq[0x5];
 884
 885         u8         log_max_eq_sz[0x8];
 886         u8         reserved_at_e8[0x2];
 887         u8         log_max_mkey[0x6];
 888         u8         reserved_at_f0[0x8];
 889         u8         dump_fill_mkey[0x1];
 890         u8         reserved_at_f9[0x3];
 891         u8         log_max_eq[0x4];
 892
 893         u8         max_indirection[0x8];
 894         u8         fixed_buffer_size[0x1];
 895         u8         log_max_mrw_sz[0x7];
 896         u8         force_teardown[0x1];
 897         u8         reserved_at_111[0x1];
 898         u8         log_max_bsf_list_size[0x6];
 899         u8         umr_extended_translation_offset[0x1];
 900         u8         null_mkey[0x1];
 901         u8         log_max_klm_list_size[0x6];
 902
 903         u8         reserved_at_120[0xa];
 904         u8         log_max_ra_req_dc[0x6];
 905         u8         reserved_at_130[0xa];
 906         u8         log_max_ra_res_dc[0x6];
 907
 908         u8         reserved_at_140[0xa];
 909         u8         log_max_ra_req_qp[0x6];
 910         u8         reserved_at_150[0xa];
 911         u8         log_max_ra_res_qp[0x6];
 912
 913         u8         end_pad[0x1];
 914         u8         cc_query_allowed[0x1];
 915         u8         cc_modify_allowed[0x1];
 916         u8         start_pad[0x1];
 917         u8         cache_line_128byte[0x1];
 918         u8         reserved_at_165[0xa];
 919         u8         qcam_reg[0x1];
 920         u8         gid_table_size[0x10];
 921
 922         u8         out_of_seq_cnt[0x1];
 923         u8         vport_counters[0x1];
 924         u8         retransmission_q_counters[0x1];
 925         u8         debug[0x1];
 926         u8         modify_rq_counter_set_id[0x1];
 927         u8         rq_delay_drop[0x1];
 928         u8         max_qp_cnt[0xa];
 929         u8         pkey_table_size[0x10];
 930
 931         u8         vport_group_manager[0x1];
 932         u8         vhca_group_manager[0x1];
 933         u8         ib_virt[0x1];
 934         u8         eth_virt[0x1];
 935         u8         vnic_env_queue_counters[0x1];
 936         u8         ets[0x1];
 937         u8         nic_flow_table[0x1];
 938         u8         eswitch_flow_table[0x1];
 939         u8         device_memory[0x1];
 940         u8         mcam_reg[0x1];
 941         u8         pcam_reg[0x1];
 942         u8         local_ca_ack_delay[0x5];
 943         u8         port_module_event[0x1];
 944         u8         enhanced_error_q_counters[0x1];
 945         u8         ports_check[0x1];
 946         u8         reserved_at_1b3[0x1];
 947         u8         disable_link_up[0x1];
 948         u8         beacon_led[0x1];
 949         u8         port_type[0x2];
 950         u8         num_ports[0x8];
 951
 952         u8         reserved_at_1c0[0x1];
 953         u8         pps[0x1];
 954         u8         pps_modify[0x1];
 955         u8         log_max_msg[0x5];
 956         u8         reserved_at_1c8[0x4];
 957         u8         max_tc[0x4];
 958         u8         temp_warn_event[0x1];
 959         u8         dcbx[0x1];
 960         u8         general_notification_event[0x1];
 961         u8         reserved_at_1d3[0x2];
 962         u8         fpga[0x1];
 963         u8         rol_s[0x1];
 964         u8         rol_g[0x1];
 965         u8         reserved_at_1d8[0x1];
 966         u8         wol_s[0x1];
 967         u8         wol_g[0x1];
 968         u8         wol_a[0x1];
 969         u8         wol_b[0x1];
 970         u8         wol_m[0x1];
 971         u8         wol_u[0x1];
 972         u8         wol_p[0x1];
 973
 974         u8         stat_rate_support[0x10];
 975         u8         reserved_at_1f0[0xc];
 976         u8         cqe_version[0x4];
 977
 978         u8         compact_address_vector[0x1];
 979         u8         striding_rq[0x1];
 980         u8         reserved_at_202[0x1];
 981         u8         ipoib_enhanced_offloads[0x1];
 982         u8         ipoib_basic_offloads[0x1];
 983         u8         reserved_at_205[0x1];
 984         u8         repeated_block_disabled[0x1];
 985         u8         umr_modify_entity_size_disabled[0x1];
 986         u8         umr_modify_atomic_disabled[0x1];
 987         u8         umr_indirect_mkey_disabled[0x1];
 988         u8         umr_fence[0x2];
 989         u8         reserved_at_20c[0x3];
 990         u8         drain_sigerr[0x1];
 991         u8         cmdif_checksum[0x2];
 992         u8         sigerr_cqe[0x1];
 993         u8         reserved_at_213[0x1];
 994         u8         wq_signature[0x1];
 995         u8         sctr_data_cqe[0x1];
 996         u8         reserved_at_216[0x1];
 997         u8         sho[0x1];
 998         u8         tph[0x1];
 999         u8         rf[0x1];
1000         u8         dct[0x1];
1001         u8         qos[0x1];
1002         u8         eth_net_offloads[0x1];
1003         u8         roce[0x1];
1004         u8         atomic[0x1];
1005         u8         reserved_at_21f[0x1];
1006
1007         u8         cq_oi[0x1];
1008         u8         cq_resize[0x1];
1009         u8         cq_moderation[0x1];
1010         u8         reserved_at_223[0x3];
1011         u8         cq_eq_remap[0x1];
1012         u8         pg[0x1];
1013         u8         block_lb_mc[0x1];
1014         u8         reserved_at_229[0x1];
1015         u8         scqe_break_moderation[0x1];
1016         u8         cq_period_start_from_cqe[0x1];
1017         u8         cd[0x1];
1018         u8         reserved_at_22d[0x1];
1019         u8         apm[0x1];
1020         u8         vector_calc[0x1];
1021         u8         umr_ptr_rlky[0x1];
1022         u8         imaicl[0x1];
1023         u8         reserved_at_232[0x4];
1024         u8         qkv[0x1];
1025         u8         pkv[0x1];
1026         u8         set_deth_sqpn[0x1];
1027         u8         reserved_at_239[0x3];
1028         u8         xrc[0x1];
1029         u8         ud[0x1];
1030         u8         uc[0x1];
1031         u8         rc[0x1];
1032
1033         u8         uar_4k[0x1];
1034         u8         reserved_at_241[0x9];
1035         u8         uar_sz[0x6];
1036         u8         reserved_at_250[0x8];
1037         u8         log_pg_sz[0x8];
1038
1039         u8         bf[0x1];
1040         u8         driver_version[0x1];
1041         u8         pad_tx_eth_packet[0x1];
1042         u8         reserved_at_263[0x8];
1043         u8         log_bf_reg_size[0x5];
1044
1045         u8         reserved_at_270[0xb];
1046         u8         lag_master[0x1];
1047         u8         num_lag_ports[0x4];
1048
1049         u8         reserved_at_280[0x10];
1050         u8         max_wqe_sz_sq[0x10];
1051
1052         u8         reserved_at_2a0[0x10];
1053         u8         max_wqe_sz_rq[0x10];
1054
1055         u8         max_flow_counter_31_16[0x10];
1056         u8         max_wqe_sz_sq_dc[0x10];
1057
1058         u8         reserved_at_2e0[0x7];
1059         u8         max_qp_mcg[0x19];
1060
1061         u8         reserved_at_300[0x18];
1062         u8         log_max_mcg[0x8];
1063
1064         u8         reserved_at_320[0x3];
1065         u8         log_max_transport_domain[0x5];
1066         u8         reserved_at_328[0x3];
1067         u8         log_max_pd[0x5];
1068         u8         reserved_at_330[0xb];
1069         u8         log_max_xrcd[0x5];
1070
1071         u8         nic_receive_steering_discard[0x1];
1072         u8         receive_discard_vport_down[0x1];
1073         u8         transmit_discard_vport_down[0x1];
1074         u8         reserved_at_343[0x5];
1075         u8         log_max_flow_counter_bulk[0x8];
1076         u8         max_flow_counter_15_0[0x10];
1077
1078
1079         u8         reserved_at_360[0x3];
1080         u8         log_max_rq[0x5];
1081         u8         reserved_at_368[0x3];
1082         u8         log_max_sq[0x5];
1083         u8         reserved_at_370[0x3];
1084         u8         log_max_tir[0x5];
1085         u8         reserved_at_378[0x3];
1086         u8         log_max_tis[0x5];
1087
1088         u8         basic_cyclic_rcv_wqe[0x1];
1089         u8         reserved_at_381[0x2];
1090         u8         log_max_rmp[0x5];
1091         u8         reserved_at_388[0x3];
1092         u8         log_max_rqt[0x5];
1093         u8         reserved_at_390[0x3];
1094         u8         log_max_rqt_size[0x5];
1095         u8         reserved_at_398[0x3];
1096         u8         log_max_tis_per_sq[0x5];
1097
1098         u8         ext_stride_num_range[0x1];
1099         u8         reserved_at_3a1[0x2];
1100         u8         log_max_stride_sz_rq[0x5];
1101         u8         reserved_at_3a8[0x3];
1102         u8         log_min_stride_sz_rq[0x5];
1103         u8         reserved_at_3b0[0x3];
1104         u8         log_max_stride_sz_sq[0x5];
1105         u8         reserved_at_3b8[0x3];
1106         u8         log_min_stride_sz_sq[0x5];
1107
1108         u8         hairpin[0x1];
1109         u8         reserved_at_3c1[0x2];
1110         u8         log_max_hairpin_queues[0x5];
1111         u8         reserved_at_3c8[0x3];
1112         u8         log_max_hairpin_wq_data_sz[0x5];
1113         u8         reserved_at_3d0[0x3];
1114         u8         log_max_hairpin_num_packets[0x5];
1115         u8         reserved_at_3d8[0x3];
1116         u8         log_max_wq_sz[0x5];
1117
1118         u8         nic_vport_change_event[0x1];
1119         u8         disable_local_lb_uc[0x1];
1120         u8         disable_local_lb_mc[0x1];
1121         u8         log_min_hairpin_wq_data_sz[0x5];
1122         u8         reserved_at_3e8[0x3];
1123         u8         log_max_vlan_list[0x5];
1124         u8         reserved_at_3f0[0x3];
1125         u8         log_max_current_mc_list[0x5];
1126         u8         reserved_at_3f8[0x3];
1127         u8         log_max_current_uc_list[0x5];
1128
1129         u8         general_obj_types[0x40];
1130
1131         u8         reserved_at_440[0x40];
1132
1133         u8         reserved_at_480[0x3];
1134         u8         log_max_l2_table[0x5];
1135         u8         reserved_at_488[0x8];
1136         u8         log_uar_page_sz[0x10];
1137
1138         u8         reserved_at_4a0[0x20];
1139         u8         device_frequency_mhz[0x20];
1140         u8         device_frequency_khz[0x20];
1141
1142         u8         reserved_at_500[0x20];
1143         u8         num_of_uars_per_page[0x20];
1144
1145         u8         flex_parser_protocols[0x20];
1146         u8         reserved_at_560[0x20];
1147
1148         u8         reserved_at_580[0x3c];
1149         u8         mini_cqe_resp_stride_index[0x1];
1150         u8         cqe_128_always[0x1];
1151         u8         cqe_compression_128[0x1];
1152         u8         cqe_compression[0x1];
1153
1154         u8         cqe_compression_timeout[0x10];
1155         u8         cqe_compression_max_num[0x10];
1156
1157         u8         reserved_at_5e0[0x10];
1158         u8         tag_matching[0x1];
1159         u8         rndv_offload_rc[0x1];
1160         u8         rndv_offload_dc[0x1];
1161         u8         log_tag_matching_list_sz[0x5];
1162         u8         reserved_at_5f8[0x3];
1163         u8         log_max_xrq[0x5];
1164
1165         u8         affiliate_nic_vport_criteria[0x8];
1166         u8         native_port_num[0x8];
1167         u8         num_vhca_ports[0x8];
1168         u8         reserved_at_618[0x6];
1169         u8         sw_owner_id[0x1];
1170         u8         reserved_at_61f[0x1e1];
1171 };
1172
1173 enum mlx5_flow_destination_type {
1174         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1175         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1176         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1177
1178         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1179         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1180 };
1181
1182 struct mlx5_ifc_dest_format_struct_bits {
1183         u8         destination_type[0x8];
1184         u8         destination_id[0x18];
1185         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1186         u8         reserved_at_21[0xf];
1187         u8         destination_eswitch_owner_vhca_id[0x10];
1188 };
1189
1190 struct mlx5_ifc_flow_counter_list_bits {
1191         u8         flow_counter_id[0x20];
1192
1193         u8         reserved_at_20[0x20];
1194 };
1195
1196 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1197         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1198         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1199         u8         reserved_at_0[0x40];
1200 };
1201
1202 struct mlx5_ifc_fte_match_param_bits {
1203         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1204
1205         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1206
1207         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1208
1209         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1210
1211         u8         reserved_at_800[0x800];
1212 };
1213
1214 enum {
1215         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1216         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1217         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1218         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1219         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1220 };
1221
1222 struct mlx5_ifc_rx_hash_field_select_bits {
1223         u8         l3_prot_type[0x1];
1224         u8         l4_prot_type[0x1];
1225         u8         selected_fields[0x1e];
1226 };
1227
1228 enum {
1229         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1230         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1231 };
1232
1233 enum {
1234         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1235         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1236 };
1237
1238 struct mlx5_ifc_wq_bits {
1239         u8         wq_type[0x4];
1240         u8         wq_signature[0x1];
1241         u8         end_padding_mode[0x2];
1242         u8         cd_slave[0x1];
1243         u8         reserved_at_8[0x18];
1244
1245         u8         hds_skip_first_sge[0x1];
1246         u8         log2_hds_buf_size[0x3];
1247         u8         reserved_at_24[0x7];
1248         u8         page_offset[0x5];
1249         u8         lwm[0x10];
1250
1251         u8         reserved_at_40[0x8];
1252         u8         pd[0x18];
1253
1254         u8         reserved_at_60[0x8];
1255         u8         uar_page[0x18];
1256
1257         u8         dbr_addr[0x40];
1258
1259         u8         hw_counter[0x20];
1260
1261         u8         sw_counter[0x20];
1262
1263         u8         reserved_at_100[0xc];
1264         u8         log_wq_stride[0x4];
1265         u8         reserved_at_110[0x3];
1266         u8         log_wq_pg_sz[0x5];
1267         u8         reserved_at_118[0x3];
1268         u8         log_wq_sz[0x5];
1269
1270         u8         reserved_at_120[0x3];
1271         u8         log_hairpin_num_packets[0x5];
1272         u8         reserved_at_128[0x3];
1273         u8         log_hairpin_data_sz[0x5];
1274
1275         u8         reserved_at_130[0x4];
1276         u8         log_wqe_num_of_strides[0x4];
1277         u8         two_byte_shift_en[0x1];
1278         u8         reserved_at_139[0x4];
1279         u8         log_wqe_stride_size[0x3];
1280
1281         u8         reserved_at_140[0x4c0];
1282
1283         struct mlx5_ifc_cmd_pas_bits pas[0];
1284 };
1285
1286 struct mlx5_ifc_rq_num_bits {
1287         u8         reserved_at_0[0x8];
1288         u8         rq_num[0x18];
1289 };
1290
1291 struct mlx5_ifc_mac_address_layout_bits {
1292         u8         reserved_at_0[0x10];
1293         u8         mac_addr_47_32[0x10];
1294
1295         u8         mac_addr_31_0[0x20];
1296 };
1297
1298 struct mlx5_ifc_vlan_layout_bits {
1299         u8         reserved_at_0[0x14];
1300         u8         vlan[0x0c];
1301
1302         u8         reserved_at_20[0x20];
1303 };
1304
1305 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1306         u8         reserved_at_0[0xa0];
1307
1308         u8         min_time_between_cnps[0x20];
1309
1310         u8         reserved_at_c0[0x12];
1311         u8         cnp_dscp[0x6];
1312         u8         reserved_at_d8[0x4];
1313         u8         cnp_prio_mode[0x1];
1314         u8         cnp_802p_prio[0x3];
1315
1316         u8         reserved_at_e0[0x720];
1317 };
1318
1319 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1320         u8         reserved_at_0[0x60];
1321
1322         u8         reserved_at_60[0x4];
1323         u8         clamp_tgt_rate[0x1];
1324         u8         reserved_at_65[0x3];
1325         u8         clamp_tgt_rate_after_time_inc[0x1];
1326         u8         reserved_at_69[0x17];
1327
1328         u8         reserved_at_80[0x20];
1329
1330         u8         rpg_time_reset[0x20];
1331
1332         u8         rpg_byte_reset[0x20];
1333
1334         u8         rpg_threshold[0x20];
1335
1336         u8         rpg_max_rate[0x20];
1337
1338         u8         rpg_ai_rate[0x20];
1339
1340         u8         rpg_hai_rate[0x20];
1341
1342         u8         rpg_gd[0x20];
1343
1344         u8         rpg_min_dec_fac[0x20];
1345
1346         u8         rpg_min_rate[0x20];
1347
1348         u8         reserved_at_1c0[0xe0];
1349
1350         u8         rate_to_set_on_first_cnp[0x20];
1351
1352         u8         dce_tcp_g[0x20];
1353
1354         u8         dce_tcp_rtt[0x20];
1355
1356         u8         rate_reduce_monitor_period[0x20];
1357
1358         u8         reserved_at_320[0x20];
1359
1360         u8         initial_alpha_value[0x20];
1361
1362         u8         reserved_at_360[0x4a0];
1363 };
1364
1365 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1366         u8         reserved_at_0[0x80];
1367
1368         u8         rppp_max_rps[0x20];
1369
1370         u8         rpg_time_reset[0x20];
1371
1372         u8         rpg_byte_reset[0x20];
1373
1374         u8         rpg_threshold[0x20];
1375
1376         u8         rpg_max_rate[0x20];
1377
1378         u8         rpg_ai_rate[0x20];
1379
1380         u8         rpg_hai_rate[0x20];
1381
1382         u8         rpg_gd[0x20];
1383
1384         u8         rpg_min_dec_fac[0x20];
1385
1386         u8         rpg_min_rate[0x20];
1387
1388         u8         reserved_at_1c0[0x640];
1389 };
1390
1391 enum {
1392         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1393         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1394         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1395 };
1396
1397 struct mlx5_ifc_resize_field_select_bits {
1398         u8         resize_field_select[0x20];
1399 };
1400
1401 enum {
1402         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1403         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1404         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1405         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1406 };
1407
1408 struct mlx5_ifc_modify_field_select_bits {
1409         u8         modify_field_select[0x20];
1410 };
1411
1412 struct mlx5_ifc_field_select_r_roce_np_bits {
1413         u8         field_select_r_roce_np[0x20];
1414 };
1415
1416 struct mlx5_ifc_field_select_r_roce_rp_bits {
1417         u8         field_select_r_roce_rp[0x20];
1418 };
1419
1420 enum {
1421         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1422         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1423         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1424         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1425         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1426         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1427         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1428         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1429         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1430         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1431 };
1432
1433 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1434         u8         field_select_8021qaurp[0x20];
1435 };
1436
1437 struct mlx5_ifc_phys_layer_cntrs_bits {
1438         u8         time_since_last_clear_high[0x20];
1439
1440         u8         time_since_last_clear_low[0x20];
1441
1442         u8         symbol_errors_high[0x20];
1443
1444         u8         symbol_errors_low[0x20];
1445
1446         u8         sync_headers_errors_high[0x20];
1447
1448         u8         sync_headers_errors_low[0x20];
1449
1450         u8         edpl_bip_errors_lane0_high[0x20];
1451
1452         u8         edpl_bip_errors_lane0_low[0x20];
1453
1454         u8         edpl_bip_errors_lane1_high[0x20];
1455
1456         u8         edpl_bip_errors_lane1_low[0x20];
1457
1458         u8         edpl_bip_errors_lane2_high[0x20];
1459
1460         u8         edpl_bip_errors_lane2_low[0x20];
1461
1462         u8         edpl_bip_errors_lane3_high[0x20];
1463
1464         u8         edpl_bip_errors_lane3_low[0x20];
1465
1466         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1467
1468         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1469
1470         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1471
1472         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1473
1474         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1475
1476         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1477
1478         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1479
1480         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1481
1482         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1483
1484         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1485
1486         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1487
1488         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1489
1490         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1491
1492         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1493
1494         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1495
1496         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1497
1498         u8         rs_fec_corrected_blocks_high[0x20];
1499
1500         u8         rs_fec_corrected_blocks_low[0x20];
1501
1502         u8         rs_fec_uncorrectable_blocks_high[0x20];
1503
1504         u8         rs_fec_uncorrectable_blocks_low[0x20];
1505
1506         u8         rs_fec_no_errors_blocks_high[0x20];
1507
1508         u8         rs_fec_no_errors_blocks_low[0x20];
1509
1510         u8         rs_fec_single_error_blocks_high[0x20];
1511
1512         u8         rs_fec_single_error_blocks_low[0x20];
1513
1514         u8         rs_fec_corrected_symbols_total_high[0x20];
1515
1516         u8         rs_fec_corrected_symbols_total_low[0x20];
1517
1518         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1519
1520         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1521
1522         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1523
1524         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1525
1526         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1527
1528         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1529
1530         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1531
1532         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1533
1534         u8         link_down_events[0x20];
1535
1536         u8         successful_recovery_events[0x20];
1537
1538         u8         reserved_at_640[0x180];
1539 };
1540
1541 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1542         u8         time_since_last_clear_high[0x20];
1543
1544         u8         time_since_last_clear_low[0x20];
1545
1546         u8         phy_received_bits_high[0x20];
1547
1548         u8         phy_received_bits_low[0x20];
1549
1550         u8         phy_symbol_errors_high[0x20];
1551
1552         u8         phy_symbol_errors_low[0x20];
1553
1554         u8         phy_corrected_bits_high[0x20];
1555
1556         u8         phy_corrected_bits_low[0x20];
1557
1558         u8         phy_corrected_bits_lane0_high[0x20];
1559
1560         u8         phy_corrected_bits_lane0_low[0x20];
1561
1562         u8         phy_corrected_bits_lane1_high[0x20];
1563
1564         u8         phy_corrected_bits_lane1_low[0x20];
1565
1566         u8         phy_corrected_bits_lane2_high[0x20];
1567
1568         u8         phy_corrected_bits_lane2_low[0x20];
1569
1570         u8         phy_corrected_bits_lane3_high[0x20];
1571
1572         u8         phy_corrected_bits_lane3_low[0x20];
1573
1574         u8         reserved_at_200[0x5c0];
1575 };
1576
1577 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1578         u8         symbol_error_counter[0x10];
1579
1580         u8         link_error_recovery_counter[0x8];
1581
1582         u8         link_downed_counter[0x8];
1583
1584         u8         port_rcv_errors[0x10];
1585
1586         u8         port_rcv_remote_physical_errors[0x10];
1587
1588         u8         port_rcv_switch_relay_errors[0x10];
1589
1590         u8         port_xmit_discards[0x10];
1591
1592         u8         port_xmit_constraint_errors[0x8];
1593
1594         u8         port_rcv_constraint_errors[0x8];
1595
1596         u8         reserved_at_70[0x8];
1597
1598         u8         link_overrun_errors[0x8];
1599
1600         u8         reserved_at_80[0x10];
1601
1602         u8         vl_15_dropped[0x10];
1603
1604         u8         reserved_at_a0[0x80];
1605
1606         u8         port_xmit_wait[0x20];
1607 };
1608
1609 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1610         u8         transmit_queue_high[0x20];
1611
1612         u8         transmit_queue_low[0x20];
1613
1614         u8         reserved_at_40[0x780];
1615 };
1616
1617 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1618         u8         rx_octets_high[0x20];
1619
1620         u8         rx_octets_low[0x20];
1621
1622         u8         reserved_at_40[0xc0];
1623
1624         u8         rx_frames_high[0x20];
1625
1626         u8         rx_frames_low[0x20];
1627
1628         u8         tx_octets_high[0x20];
1629
1630         u8         tx_octets_low[0x20];
1631
1632         u8         reserved_at_180[0xc0];
1633
1634         u8         tx_frames_high[0x20];
1635
1636         u8         tx_frames_low[0x20];
1637
1638         u8         rx_pause_high[0x20];
1639
1640         u8         rx_pause_low[0x20];
1641
1642         u8         rx_pause_duration_high[0x20];
1643
1644         u8         rx_pause_duration_low[0x20];
1645
1646         u8         tx_pause_high[0x20];
1647
1648         u8         tx_pause_low[0x20];
1649
1650         u8         tx_pause_duration_high[0x20];
1651
1652         u8         tx_pause_duration_low[0x20];
1653
1654         u8         rx_pause_transition_high[0x20];
1655
1656         u8         rx_pause_transition_low[0x20];
1657
1658         u8         reserved_at_3c0[0x40];
1659
1660         u8         device_stall_minor_watermark_cnt_high[0x20];
1661
1662         u8         device_stall_minor_watermark_cnt_low[0x20];
1663
1664         u8         device_stall_critical_watermark_cnt_high[0x20];
1665
1666         u8         device_stall_critical_watermark_cnt_low[0x20];
1667
1668         u8         reserved_at_480[0x340];
1669 };
1670
1671 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1672         u8         port_transmit_wait_high[0x20];
1673
1674         u8         port_transmit_wait_low[0x20];
1675
1676         u8         reserved_at_40[0x100];
1677
1678         u8         rx_buffer_almost_full_high[0x20];
1679
1680         u8         rx_buffer_almost_full_low[0x20];
1681
1682         u8         rx_buffer_full_high[0x20];
1683
1684         u8         rx_buffer_full_low[0x20];
1685
1686         u8         rx_icrc_encapsulated_high[0x20];
1687
1688         u8         rx_icrc_encapsulated_low[0x20];
1689
1690         u8         reserved_at_200[0x5c0];
1691 };
1692
1693 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1694         u8         dot3stats_alignment_errors_high[0x20];
1695
1696         u8         dot3stats_alignment_errors_low[0x20];
1697
1698         u8         dot3stats_fcs_errors_high[0x20];
1699
1700         u8         dot3stats_fcs_errors_low[0x20];
1701
1702         u8         dot3stats_single_collision_frames_high[0x20];
1703
1704         u8         dot3stats_single_collision_frames_low[0x20];
1705
1706         u8         dot3stats_multiple_collision_frames_high[0x20];
1707
1708         u8         dot3stats_multiple_collision_frames_low[0x20];
1709
1710         u8         dot3stats_sqe_test_errors_high[0x20];
1711
1712         u8         dot3stats_sqe_test_errors_low[0x20];
1713
1714         u8         dot3stats_deferred_transmissions_high[0x20];
1715
1716         u8         dot3stats_deferred_transmissions_low[0x20];
1717
1718         u8         dot3stats_late_collisions_high[0x20];
1719
1720         u8         dot3stats_late_collisions_low[0x20];
1721
1722         u8         dot3stats_excessive_collisions_high[0x20];
1723
1724         u8         dot3stats_excessive_collisions_low[0x20];
1725
1726         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1727
1728         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1729
1730         u8         dot3stats_carrier_sense_errors_high[0x20];
1731
1732         u8         dot3stats_carrier_sense_errors_low[0x20];
1733
1734         u8         dot3stats_frame_too_longs_high[0x20];
1735
1736         u8         dot3stats_frame_too_longs_low[0x20];
1737
1738         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1739
1740         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1741
1742         u8         dot3stats_symbol_errors_high[0x20];
1743
1744         u8         dot3stats_symbol_errors_low[0x20];
1745
1746         u8         dot3control_in_unknown_opcodes_high[0x20];
1747
1748         u8         dot3control_in_unknown_opcodes_low[0x20];
1749
1750         u8         dot3in_pause_frames_high[0x20];
1751
1752         u8         dot3in_pause_frames_low[0x20];
1753
1754         u8         dot3out_pause_frames_high[0x20];
1755
1756         u8         dot3out_pause_frames_low[0x20];
1757
1758         u8         reserved_at_400[0x3c0];
1759 };
1760
1761 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1762         u8         ether_stats_drop_events_high[0x20];
1763
1764         u8         ether_stats_drop_events_low[0x20];
1765
1766         u8         ether_stats_octets_high[0x20];
1767
1768         u8         ether_stats_octets_low[0x20];
1769
1770         u8         ether_stats_pkts_high[0x20];
1771
1772         u8         ether_stats_pkts_low[0x20];
1773
1774         u8         ether_stats_broadcast_pkts_high[0x20];
1775
1776         u8         ether_stats_broadcast_pkts_low[0x20];
1777
1778         u8         ether_stats_multicast_pkts_high[0x20];
1779
1780         u8         ether_stats_multicast_pkts_low[0x20];
1781
1782         u8         ether_stats_crc_align_errors_high[0x20];
1783
1784         u8         ether_stats_crc_align_errors_low[0x20];
1785
1786         u8         ether_stats_undersize_pkts_high[0x20];
1787
1788         u8         ether_stats_undersize_pkts_low[0x20];
1789
1790         u8         ether_stats_oversize_pkts_high[0x20];
1791
1792         u8         ether_stats_oversize_pkts_low[0x20];
1793
1794         u8         ether_stats_fragments_high[0x20];
1795
1796         u8         ether_stats_fragments_low[0x20];
1797
1798         u8         ether_stats_jabbers_high[0x20];
1799
1800         u8         ether_stats_jabbers_low[0x20];
1801
1802         u8         ether_stats_collisions_high[0x20];
1803
1804         u8         ether_stats_collisions_low[0x20];
1805
1806         u8         ether_stats_pkts64octets_high[0x20];
1807
1808         u8         ether_stats_pkts64octets_low[0x20];
1809
1810         u8         ether_stats_pkts65to127octets_high[0x20];
1811
1812         u8         ether_stats_pkts65to127octets_low[0x20];
1813
1814         u8         ether_stats_pkts128to255octets_high[0x20];
1815
1816         u8         ether_stats_pkts128to255octets_low[0x20];
1817
1818         u8         ether_stats_pkts256to511octets_high[0x20];
1819
1820         u8         ether_stats_pkts256to511octets_low[0x20];
1821
1822         u8         ether_stats_pkts512to1023octets_high[0x20];
1823
1824         u8         ether_stats_pkts512to1023octets_low[0x20];
1825
1826         u8         ether_stats_pkts1024to1518octets_high[0x20];
1827
1828         u8         ether_stats_pkts1024to1518octets_low[0x20];
1829
1830         u8         ether_stats_pkts1519to2047octets_high[0x20];
1831
1832         u8         ether_stats_pkts1519to2047octets_low[0x20];
1833
1834         u8         ether_stats_pkts2048to4095octets_high[0x20];
1835
1836         u8         ether_stats_pkts2048to4095octets_low[0x20];
1837
1838         u8         ether_stats_pkts4096to8191octets_high[0x20];
1839
1840         u8         ether_stats_pkts4096to8191octets_low[0x20];
1841
1842         u8         ether_stats_pkts8192to10239octets_high[0x20];
1843
1844         u8         ether_stats_pkts8192to10239octets_low[0x20];
1845
1846         u8         reserved_at_540[0x280];
1847 };
1848
1849 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1850         u8         if_in_octets_high[0x20];
1851
1852         u8         if_in_octets_low[0x20];
1853
1854         u8         if_in_ucast_pkts_high[0x20];
1855
1856         u8         if_in_ucast_pkts_low[0x20];
1857
1858         u8         if_in_discards_high[0x20];
1859
1860         u8         if_in_discards_low[0x20];
1861
1862         u8         if_in_errors_high[0x20];
1863
1864         u8         if_in_errors_low[0x20];
1865
1866         u8         if_in_unknown_protos_high[0x20];
1867
1868         u8         if_in_unknown_protos_low[0x20];
1869
1870         u8         if_out_octets_high[0x20];
1871
1872         u8         if_out_octets_low[0x20];
1873
1874         u8         if_out_ucast_pkts_high[0x20];
1875
1876         u8         if_out_ucast_pkts_low[0x20];
1877
1878         u8         if_out_discards_high[0x20];
1879
1880         u8         if_out_discards_low[0x20];
1881
1882         u8         if_out_errors_high[0x20];
1883
1884         u8         if_out_errors_low[0x20];
1885
1886         u8         if_in_multicast_pkts_high[0x20];
1887
1888         u8         if_in_multicast_pkts_low[0x20];
1889
1890         u8         if_in_broadcast_pkts_high[0x20];
1891
1892         u8         if_in_broadcast_pkts_low[0x20];
1893
1894         u8         if_out_multicast_pkts_high[0x20];
1895
1896         u8         if_out_multicast_pkts_low[0x20];
1897
1898         u8         if_out_broadcast_pkts_high[0x20];
1899
1900         u8         if_out_broadcast_pkts_low[0x20];
1901
1902         u8         reserved_at_340[0x480];
1903 };
1904
1905 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1906         u8         a_frames_transmitted_ok_high[0x20];
1907
1908         u8         a_frames_transmitted_ok_low[0x20];
1909
1910         u8         a_frames_received_ok_high[0x20];
1911
1912         u8         a_frames_received_ok_low[0x20];
1913
1914         u8         a_frame_check_sequence_errors_high[0x20];
1915
1916         u8         a_frame_check_sequence_errors_low[0x20];
1917
1918         u8         a_alignment_errors_high[0x20];
1919
1920         u8         a_alignment_errors_low[0x20];
1921
1922         u8         a_octets_transmitted_ok_high[0x20];
1923
1924         u8         a_octets_transmitted_ok_low[0x20];
1925
1926         u8         a_octets_received_ok_high[0x20];
1927
1928         u8         a_octets_received_ok_low[0x20];
1929
1930         u8         a_multicast_frames_xmitted_ok_high[0x20];
1931
1932         u8         a_multicast_frames_xmitted_ok_low[0x20];
1933
1934         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1935
1936         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1937
1938         u8         a_multicast_frames_received_ok_high[0x20];
1939
1940         u8         a_multicast_frames_received_ok_low[0x20];
1941
1942         u8         a_broadcast_frames_received_ok_high[0x20];
1943
1944         u8         a_broadcast_frames_received_ok_low[0x20];
1945
1946         u8         a_in_range_length_errors_high[0x20];
1947
1948         u8         a_in_range_length_errors_low[0x20];
1949
1950         u8         a_out_of_range_length_field_high[0x20];
1951
1952         u8         a_out_of_range_length_field_low[0x20];
1953
1954         u8         a_frame_too_long_errors_high[0x20];
1955
1956         u8         a_frame_too_long_errors_low[0x20];
1957
1958         u8         a_symbol_error_during_carrier_high[0x20];
1959
1960         u8         a_symbol_error_during_carrier_low[0x20];
1961
1962         u8         a_mac_control_frames_transmitted_high[0x20];
1963
1964         u8         a_mac_control_frames_transmitted_low[0x20];
1965
1966         u8         a_mac_control_frames_received_high[0x20];
1967
1968         u8         a_mac_control_frames_received_low[0x20];
1969
1970         u8         a_unsupported_opcodes_received_high[0x20];
1971
1972         u8         a_unsupported_opcodes_received_low[0x20];
1973
1974         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1975
1976         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1977
1978         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1979
1980         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1981
1982         u8         reserved_at_4c0[0x300];
1983 };
1984
1985 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1986         u8         life_time_counter_high[0x20];
1987
1988         u8         life_time_counter_low[0x20];
1989
1990         u8         rx_errors[0x20];
1991
1992         u8         tx_errors[0x20];
1993
1994         u8         l0_to_recovery_eieos[0x20];
1995
1996         u8         l0_to_recovery_ts[0x20];
1997
1998         u8         l0_to_recovery_framing[0x20];
1999
2000         u8         l0_to_recovery_retrain[0x20];
2001
2002         u8         crc_error_dllp[0x20];
2003
2004         u8         crc_error_tlp[0x20];
2005
2006         u8         tx_overflow_buffer_pkt_high[0x20];
2007
2008         u8         tx_overflow_buffer_pkt_low[0x20];
2009
2010         u8         outbound_stalled_reads[0x20];
2011
2012         u8         outbound_stalled_writes[0x20];
2013
2014         u8         outbound_stalled_reads_events[0x20];
2015
2016         u8         outbound_stalled_writes_events[0x20];
2017
2018         u8         reserved_at_200[0x5c0];
2019 };
2020
2021 struct mlx5_ifc_cmd_inter_comp_event_bits {
2022         u8         command_completion_vector[0x20];
2023
2024         u8         reserved_at_20[0xc0];
2025 };
2026
2027 struct mlx5_ifc_stall_vl_event_bits {
2028         u8         reserved_at_0[0x18];
2029         u8         port_num[0x1];
2030         u8         reserved_at_19[0x3];
2031         u8         vl[0x4];
2032
2033         u8         reserved_at_20[0xa0];
2034 };
2035
2036 struct mlx5_ifc_db_bf_congestion_event_bits {
2037         u8         event_subtype[0x8];
2038         u8         reserved_at_8[0x8];
2039         u8         congestion_level[0x8];
2040         u8         reserved_at_18[0x8];
2041
2042         u8         reserved_at_20[0xa0];
2043 };
2044
2045 struct mlx5_ifc_gpio_event_bits {
2046         u8         reserved_at_0[0x60];
2047
2048         u8         gpio_event_hi[0x20];
2049
2050         u8         gpio_event_lo[0x20];
2051
2052         u8         reserved_at_a0[0x40];
2053 };
2054
2055 struct mlx5_ifc_port_state_change_event_bits {
2056         u8         reserved_at_0[0x40];
2057
2058         u8         port_num[0x4];
2059         u8         reserved_at_44[0x1c];
2060
2061         u8         reserved_at_60[0x80];
2062 };
2063
2064 struct mlx5_ifc_dropped_packet_logged_bits {
2065         u8         reserved_at_0[0xe0];
2066 };
2067
2068 enum {
2069         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2070         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2071 };
2072
2073 struct mlx5_ifc_cq_error_bits {
2074         u8         reserved_at_0[0x8];
2075         u8         cqn[0x18];
2076
2077         u8         reserved_at_20[0x20];
2078
2079         u8         reserved_at_40[0x18];
2080         u8         syndrome[0x8];
2081
2082         u8         reserved_at_60[0x80];
2083 };
2084
2085 struct mlx5_ifc_rdma_page_fault_event_bits {
2086         u8         bytes_committed[0x20];
2087
2088         u8         r_key[0x20];
2089
2090         u8         reserved_at_40[0x10];
2091         u8         packet_len[0x10];
2092
2093         u8         rdma_op_len[0x20];
2094
2095         u8         rdma_va[0x40];
2096
2097         u8         reserved_at_c0[0x5];
2098         u8         rdma[0x1];
2099         u8         write[0x1];
2100         u8         requestor[0x1];
2101         u8         qp_number[0x18];
2102 };
2103
2104 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2105         u8         bytes_committed[0x20];
2106
2107         u8         reserved_at_20[0x10];
2108         u8         wqe_index[0x10];
2109
2110         u8         reserved_at_40[0x10];
2111         u8         len[0x10];
2112
2113         u8         reserved_at_60[0x60];
2114
2115         u8         reserved_at_c0[0x5];
2116         u8         rdma[0x1];
2117         u8         write_read[0x1];
2118         u8         requestor[0x1];
2119         u8         qpn[0x18];
2120 };
2121
2122 struct mlx5_ifc_qp_events_bits {
2123         u8         reserved_at_0[0xa0];
2124
2125         u8         type[0x8];
2126         u8         reserved_at_a8[0x18];
2127
2128         u8         reserved_at_c0[0x8];
2129         u8         qpn_rqn_sqn[0x18];
2130 };
2131
2132 struct mlx5_ifc_dct_events_bits {
2133         u8         reserved_at_0[0xc0];
2134
2135         u8         reserved_at_c0[0x8];
2136         u8         dct_number[0x18];
2137 };
2138
2139 struct mlx5_ifc_comp_event_bits {
2140         u8         reserved_at_0[0xc0];
2141
2142         u8         reserved_at_c0[0x8];
2143         u8         cq_number[0x18];
2144 };
2145
2146 enum {
2147         MLX5_QPC_STATE_RST        = 0x0,
2148         MLX5_QPC_STATE_INIT       = 0x1,
2149         MLX5_QPC_STATE_RTR        = 0x2,
2150         MLX5_QPC_STATE_RTS        = 0x3,
2151         MLX5_QPC_STATE_SQER       = 0x4,
2152         MLX5_QPC_STATE_ERR        = 0x6,
2153         MLX5_QPC_STATE_SQD        = 0x7,
2154         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2155 };
2156
2157 enum {
2158         MLX5_QPC_ST_RC            = 0x0,
2159         MLX5_QPC_ST_UC            = 0x1,
2160         MLX5_QPC_ST_UD            = 0x2,
2161         MLX5_QPC_ST_XRC           = 0x3,
2162         MLX5_QPC_ST_DCI           = 0x5,
2163         MLX5_QPC_ST_QP0           = 0x7,
2164         MLX5_QPC_ST_QP1           = 0x8,
2165         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2166         MLX5_QPC_ST_REG_UMR       = 0xc,
2167 };
2168
2169 enum {
2170         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2171         MLX5_QPC_PM_STATE_REARM     = 0x1,
2172         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2173         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2174 };
2175
2176 enum {
2177         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2178 };
2179
2180 enum {
2181         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2182         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2183 };
2184
2185 enum {
2186         MLX5_QPC_MTU_256_BYTES        = 0x1,
2187         MLX5_QPC_MTU_512_BYTES        = 0x2,
2188         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2189         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2190         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2191         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2192 };
2193
2194 enum {
2195         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2196         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2197         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2198         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2199         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2200         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2201         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2202         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2203 };
2204
2205 enum {
2206         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2207         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2208         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2209 };
2210
2211 enum {
2212         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2213         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2214         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2215 };
2216
2217 struct mlx5_ifc_qpc_bits {
2218         u8         state[0x4];
2219         u8         lag_tx_port_affinity[0x4];
2220         u8         st[0x8];
2221         u8         reserved_at_10[0x3];
2222         u8         pm_state[0x2];
2223         u8         reserved_at_15[0x3];
2224         u8         offload_type[0x4];
2225         u8         end_padding_mode[0x2];
2226         u8         reserved_at_1e[0x2];
2227
2228         u8         wq_signature[0x1];
2229         u8         block_lb_mc[0x1];
2230         u8         atomic_like_write_en[0x1];
2231         u8         latency_sensitive[0x1];
2232         u8         reserved_at_24[0x1];
2233         u8         drain_sigerr[0x1];
2234         u8         reserved_at_26[0x2];
2235         u8         pd[0x18];
2236
2237         u8         mtu[0x3];
2238         u8         log_msg_max[0x5];
2239         u8         reserved_at_48[0x1];
2240         u8         log_rq_size[0x4];
2241         u8         log_rq_stride[0x3];
2242         u8         no_sq[0x1];
2243         u8         log_sq_size[0x4];
2244         u8         reserved_at_55[0x6];
2245         u8         rlky[0x1];
2246         u8         ulp_stateless_offload_mode[0x4];
2247
2248         u8         counter_set_id[0x8];
2249         u8         uar_page[0x18];
2250
2251         u8         reserved_at_80[0x8];
2252         u8         user_index[0x18];
2253
2254         u8         reserved_at_a0[0x3];
2255         u8         log_page_size[0x5];
2256         u8         remote_qpn[0x18];
2257
2258         struct mlx5_ifc_ads_bits primary_address_path;
2259
2260         struct mlx5_ifc_ads_bits secondary_address_path;
2261
2262         u8         log_ack_req_freq[0x4];
2263         u8         reserved_at_384[0x4];
2264         u8         log_sra_max[0x3];
2265         u8         reserved_at_38b[0x2];
2266         u8         retry_count[0x3];
2267         u8         rnr_retry[0x3];
2268         u8         reserved_at_393[0x1];
2269         u8         fre[0x1];
2270         u8         cur_rnr_retry[0x3];
2271         u8         cur_retry_count[0x3];
2272         u8         reserved_at_39b[0x5];
2273
2274         u8         reserved_at_3a0[0x20];
2275
2276         u8         reserved_at_3c0[0x8];
2277         u8         next_send_psn[0x18];
2278
2279         u8         reserved_at_3e0[0x8];
2280         u8         cqn_snd[0x18];
2281
2282         u8         reserved_at_400[0x8];
2283         u8         deth_sqpn[0x18];
2284
2285         u8         reserved_at_420[0x20];
2286
2287         u8         reserved_at_440[0x8];
2288         u8         last_acked_psn[0x18];
2289
2290         u8         reserved_at_460[0x8];
2291         u8         ssn[0x18];
2292
2293         u8         reserved_at_480[0x8];
2294         u8         log_rra_max[0x3];
2295         u8         reserved_at_48b[0x1];
2296         u8         atomic_mode[0x4];
2297         u8         rre[0x1];
2298         u8         rwe[0x1];
2299         u8         rae[0x1];
2300         u8         reserved_at_493[0x1];
2301         u8         page_offset[0x6];
2302         u8         reserved_at_49a[0x3];
2303         u8         cd_slave_receive[0x1];
2304         u8         cd_slave_send[0x1];
2305         u8         cd_master[0x1];
2306
2307         u8         reserved_at_4a0[0x3];
2308         u8         min_rnr_nak[0x5];
2309         u8         next_rcv_psn[0x18];
2310
2311         u8         reserved_at_4c0[0x8];
2312         u8         xrcd[0x18];
2313
2314         u8         reserved_at_4e0[0x8];
2315         u8         cqn_rcv[0x18];
2316
2317         u8         dbr_addr[0x40];
2318
2319         u8         q_key[0x20];
2320
2321         u8         reserved_at_560[0x5];
2322         u8         rq_type[0x3];
2323         u8         srqn_rmpn_xrqn[0x18];
2324
2325         u8         reserved_at_580[0x8];
2326         u8         rmsn[0x18];
2327
2328         u8         hw_sq_wqebb_counter[0x10];
2329         u8         sw_sq_wqebb_counter[0x10];
2330
2331         u8         hw_rq_counter[0x20];
2332
2333         u8         sw_rq_counter[0x20];
2334
2335         u8         reserved_at_600[0x20];
2336
2337         u8         reserved_at_620[0xf];
2338         u8         cgs[0x1];
2339         u8         cs_req[0x8];
2340         u8         cs_res[0x8];
2341
2342         u8         dc_access_key[0x40];
2343
2344         u8         reserved_at_680[0xc0];
2345 };
2346
2347 struct mlx5_ifc_roce_addr_layout_bits {
2348         u8         source_l3_address[16][0x8];
2349
2350         u8         reserved_at_80[0x3];
2351         u8         vlan_valid[0x1];
2352         u8         vlan_id[0xc];
2353         u8         source_mac_47_32[0x10];
2354
2355         u8         source_mac_31_0[0x20];
2356
2357         u8         reserved_at_c0[0x14];
2358         u8         roce_l3_type[0x4];
2359         u8         roce_version[0x8];
2360
2361         u8         reserved_at_e0[0x20];
2362 };
2363
2364 union mlx5_ifc_hca_cap_union_bits {
2365         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2366         struct mlx5_ifc_odp_cap_bits odp_cap;
2367         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2368         struct mlx5_ifc_roce_cap_bits roce_cap;
2369         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2370         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2371         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2372         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2373         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2374         struct mlx5_ifc_qos_cap_bits qos_cap;
2375         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2376         u8         reserved_at_0[0x8000];
2377 };
2378
2379 enum {
2380         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2381         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2382         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2383         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2384         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2385         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2386         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2387         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2388         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2389 };
2390
2391 struct mlx5_ifc_vlan_bits {
2392         u8         ethtype[0x10];
2393         u8         prio[0x3];
2394         u8         cfi[0x1];
2395         u8         vid[0xc];
2396 };
2397
2398 struct mlx5_ifc_flow_context_bits {
2399         struct mlx5_ifc_vlan_bits push_vlan;
2400
2401         u8         group_id[0x20];
2402
2403         u8         reserved_at_40[0x8];
2404         u8         flow_tag[0x18];
2405
2406         u8         reserved_at_60[0x10];
2407         u8         action[0x10];
2408
2409         u8         reserved_at_80[0x8];
2410         u8         destination_list_size[0x18];
2411
2412         u8         reserved_at_a0[0x8];
2413         u8         flow_counter_list_size[0x18];
2414
2415         u8         encap_id[0x20];
2416
2417         u8         modify_header_id[0x20];
2418
2419         u8         reserved_at_100[0x100];
2420
2421         struct mlx5_ifc_fte_match_param_bits match_value;
2422
2423         u8         reserved_at_1200[0x600];
2424
2425         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2426 };
2427
2428 enum {
2429         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2430         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2431 };
2432
2433 struct mlx5_ifc_xrc_srqc_bits {
2434         u8         state[0x4];
2435         u8         log_xrc_srq_size[0x4];
2436         u8         reserved_at_8[0x18];
2437
2438         u8         wq_signature[0x1];
2439         u8         cont_srq[0x1];
2440         u8         reserved_at_22[0x1];
2441         u8         rlky[0x1];
2442         u8         basic_cyclic_rcv_wqe[0x1];
2443         u8         log_rq_stride[0x3];
2444         u8         xrcd[0x18];
2445
2446         u8         page_offset[0x6];
2447         u8         reserved_at_46[0x2];
2448         u8         cqn[0x18];
2449
2450         u8         reserved_at_60[0x20];
2451
2452         u8         user_index_equal_xrc_srqn[0x1];
2453         u8         reserved_at_81[0x1];
2454         u8         log_page_size[0x6];
2455         u8         user_index[0x18];
2456
2457         u8         reserved_at_a0[0x20];
2458
2459         u8         reserved_at_c0[0x8];
2460         u8         pd[0x18];
2461
2462         u8         lwm[0x10];
2463         u8         wqe_cnt[0x10];
2464
2465         u8         reserved_at_100[0x40];
2466
2467         u8         db_record_addr_h[0x20];
2468
2469         u8         db_record_addr_l[0x1e];
2470         u8         reserved_at_17e[0x2];
2471
2472         u8         reserved_at_180[0x80];
2473 };
2474
2475 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2476         u8         counter_error_queues[0x20];
2477
2478         u8         total_error_queues[0x20];
2479
2480         u8         send_queue_priority_update_flow[0x20];
2481
2482         u8         reserved_at_60[0x20];
2483
2484         u8         nic_receive_steering_discard[0x40];
2485
2486         u8         receive_discard_vport_down[0x40];
2487
2488         u8         transmit_discard_vport_down[0x40];
2489
2490         u8         reserved_at_140[0xec0];
2491 };
2492
2493 struct mlx5_ifc_traffic_counter_bits {
2494         u8         packets[0x40];
2495
2496         u8         octets[0x40];
2497 };
2498
2499 struct mlx5_ifc_tisc_bits {
2500         u8         strict_lag_tx_port_affinity[0x1];
2501         u8         reserved_at_1[0x3];
2502         u8         lag_tx_port_affinity[0x04];
2503
2504         u8         reserved_at_8[0x4];
2505         u8         prio[0x4];
2506         u8         reserved_at_10[0x10];
2507
2508         u8         reserved_at_20[0x100];
2509
2510         u8         reserved_at_120[0x8];
2511         u8         transport_domain[0x18];
2512
2513         u8         reserved_at_140[0x8];
2514         u8         underlay_qpn[0x18];
2515         u8         reserved_at_160[0x3a0];
2516 };
2517
2518 enum {
2519         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2520         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2521 };
2522
2523 enum {
2524         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2525         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2526 };
2527
2528 enum {
2529         MLX5_RX_HASH_FN_NONE           = 0x0,
2530         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2531         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2532 };
2533
2534 enum {
2535         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2536         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2537 };
2538
2539 struct mlx5_ifc_tirc_bits {
2540         u8         reserved_at_0[0x20];
2541
2542         u8         disp_type[0x4];
2543         u8         reserved_at_24[0x1c];
2544
2545         u8         reserved_at_40[0x40];
2546
2547         u8         reserved_at_80[0x4];
2548         u8         lro_timeout_period_usecs[0x10];
2549         u8         lro_enable_mask[0x4];
2550         u8         lro_max_ip_payload_size[0x8];
2551
2552         u8         reserved_at_a0[0x40];
2553
2554         u8         reserved_at_e0[0x8];
2555         u8         inline_rqn[0x18];
2556
2557         u8         rx_hash_symmetric[0x1];
2558         u8         reserved_at_101[0x1];
2559         u8         tunneled_offload_en[0x1];
2560         u8         reserved_at_103[0x5];
2561         u8         indirect_table[0x18];
2562
2563         u8         rx_hash_fn[0x4];
2564         u8         reserved_at_124[0x2];
2565         u8         self_lb_block[0x2];
2566         u8         transport_domain[0x18];
2567
2568         u8         rx_hash_toeplitz_key[10][0x20];
2569
2570         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2571
2572         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2573
2574         u8         reserved_at_2c0[0x4c0];
2575 };
2576
2577 enum {
2578         MLX5_SRQC_STATE_GOOD   = 0x0,
2579         MLX5_SRQC_STATE_ERROR  = 0x1,
2580 };
2581
2582 struct mlx5_ifc_srqc_bits {
2583         u8         state[0x4];
2584         u8         log_srq_size[0x4];
2585         u8         reserved_at_8[0x18];
2586
2587         u8         wq_signature[0x1];
2588         u8         cont_srq[0x1];
2589         u8         reserved_at_22[0x1];
2590         u8         rlky[0x1];
2591         u8         reserved_at_24[0x1];
2592         u8         log_rq_stride[0x3];
2593         u8         xrcd[0x18];
2594
2595         u8         page_offset[0x6];
2596         u8         reserved_at_46[0x2];
2597         u8         cqn[0x18];
2598
2599         u8         reserved_at_60[0x20];
2600
2601         u8         reserved_at_80[0x2];
2602         u8         log_page_size[0x6];
2603         u8         reserved_at_88[0x18];
2604
2605         u8         reserved_at_a0[0x20];
2606
2607         u8         reserved_at_c0[0x8];
2608         u8         pd[0x18];
2609
2610         u8         lwm[0x10];
2611         u8         wqe_cnt[0x10];
2612
2613         u8         reserved_at_100[0x40];
2614
2615         u8         dbr_addr[0x40];
2616
2617         u8         reserved_at_180[0x80];
2618 };
2619
2620 enum {
2621         MLX5_SQC_STATE_RST  = 0x0,
2622         MLX5_SQC_STATE_RDY  = 0x1,
2623         MLX5_SQC_STATE_ERR  = 0x3,
2624 };
2625
2626 struct mlx5_ifc_sqc_bits {
2627         u8         rlky[0x1];
2628         u8         cd_master[0x1];
2629         u8         fre[0x1];
2630         u8         flush_in_error_en[0x1];
2631         u8         allow_multi_pkt_send_wqe[0x1];
2632         u8         min_wqe_inline_mode[0x3];
2633         u8         state[0x4];
2634         u8         reg_umr[0x1];
2635         u8         allow_swp[0x1];
2636         u8         hairpin[0x1];
2637         u8         reserved_at_f[0x11];
2638
2639         u8         reserved_at_20[0x8];
2640         u8         user_index[0x18];
2641
2642         u8         reserved_at_40[0x8];
2643         u8         cqn[0x18];
2644
2645         u8         reserved_at_60[0x8];
2646         u8         hairpin_peer_rq[0x18];
2647
2648         u8         reserved_at_80[0x10];
2649         u8         hairpin_peer_vhca[0x10];
2650
2651         u8         reserved_at_a0[0x50];
2652
2653         u8         packet_pacing_rate_limit_index[0x10];
2654         u8         tis_lst_sz[0x10];
2655         u8         reserved_at_110[0x10];
2656
2657         u8         reserved_at_120[0x40];
2658
2659         u8         reserved_at_160[0x8];
2660         u8         tis_num_0[0x18];
2661
2662         struct mlx5_ifc_wq_bits wq;
2663 };
2664
2665 enum {
2666         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2667         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2668         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2669         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2670 };
2671
2672 struct mlx5_ifc_scheduling_context_bits {
2673         u8         element_type[0x8];
2674         u8         reserved_at_8[0x18];
2675
2676         u8         element_attributes[0x20];
2677
2678         u8         parent_element_id[0x20];
2679
2680         u8         reserved_at_60[0x40];
2681
2682         u8         bw_share[0x20];
2683
2684         u8         max_average_bw[0x20];
2685
2686         u8         reserved_at_e0[0x120];
2687 };
2688
2689 struct mlx5_ifc_rqtc_bits {
2690         u8         reserved_at_0[0xa0];
2691
2692         u8         reserved_at_a0[0x10];
2693         u8         rqt_max_size[0x10];
2694
2695         u8         reserved_at_c0[0x10];
2696         u8         rqt_actual_size[0x10];
2697
2698         u8         reserved_at_e0[0x6a0];
2699
2700         struct mlx5_ifc_rq_num_bits rq_num[0];
2701 };
2702
2703 enum {
2704         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2705         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2706 };
2707
2708 enum {
2709         MLX5_RQC_STATE_RST  = 0x0,
2710         MLX5_RQC_STATE_RDY  = 0x1,
2711         MLX5_RQC_STATE_ERR  = 0x3,
2712 };
2713
2714 struct mlx5_ifc_rqc_bits {
2715         u8         rlky[0x1];
2716         u8         delay_drop_en[0x1];
2717         u8         scatter_fcs[0x1];
2718         u8         vsd[0x1];
2719         u8         mem_rq_type[0x4];
2720         u8         state[0x4];
2721         u8         reserved_at_c[0x1];
2722         u8         flush_in_error_en[0x1];
2723         u8         hairpin[0x1];
2724         u8         reserved_at_f[0x11];
2725
2726         u8         reserved_at_20[0x8];
2727         u8         user_index[0x18];
2728
2729         u8         reserved_at_40[0x8];
2730         u8         cqn[0x18];
2731
2732         u8         counter_set_id[0x8];
2733         u8         reserved_at_68[0x18];
2734
2735         u8         reserved_at_80[0x8];
2736         u8         rmpn[0x18];
2737
2738         u8         reserved_at_a0[0x8];
2739         u8         hairpin_peer_sq[0x18];
2740
2741         u8         reserved_at_c0[0x10];
2742         u8         hairpin_peer_vhca[0x10];
2743
2744         u8         reserved_at_e0[0xa0];
2745
2746         struct mlx5_ifc_wq_bits wq;
2747 };
2748
2749 enum {
2750         MLX5_RMPC_STATE_RDY  = 0x1,
2751         MLX5_RMPC_STATE_ERR  = 0x3,
2752 };
2753
2754 struct mlx5_ifc_rmpc_bits {
2755         u8         reserved_at_0[0x8];
2756         u8         state[0x4];
2757         u8         reserved_at_c[0x14];
2758
2759         u8         basic_cyclic_rcv_wqe[0x1];
2760         u8         reserved_at_21[0x1f];
2761
2762         u8         reserved_at_40[0x140];
2763
2764         struct mlx5_ifc_wq_bits wq;
2765 };
2766
2767 struct mlx5_ifc_nic_vport_context_bits {
2768         u8         reserved_at_0[0x5];
2769         u8         min_wqe_inline_mode[0x3];
2770         u8         reserved_at_8[0x15];
2771         u8         disable_mc_local_lb[0x1];
2772         u8         disable_uc_local_lb[0x1];
2773         u8         roce_en[0x1];
2774
2775         u8         arm_change_event[0x1];
2776         u8         reserved_at_21[0x1a];
2777         u8         event_on_mtu[0x1];
2778         u8         event_on_promisc_change[0x1];
2779         u8         event_on_vlan_change[0x1];
2780         u8         event_on_mc_address_change[0x1];
2781         u8         event_on_uc_address_change[0x1];
2782
2783         u8         reserved_at_40[0xc];
2784
2785         u8         affiliation_criteria[0x4];
2786         u8         affiliated_vhca_id[0x10];
2787
2788         u8         reserved_at_60[0xd0];
2789
2790         u8         mtu[0x10];
2791
2792         u8         system_image_guid[0x40];
2793         u8         port_guid[0x40];
2794         u8         node_guid[0x40];
2795
2796         u8         reserved_at_200[0x140];
2797         u8         qkey_violation_counter[0x10];
2798         u8         reserved_at_350[0x430];
2799
2800         u8         promisc_uc[0x1];
2801         u8         promisc_mc[0x1];
2802         u8         promisc_all[0x1];
2803         u8         reserved_at_783[0x2];
2804         u8         allowed_list_type[0x3];
2805         u8         reserved_at_788[0xc];
2806         u8         allowed_list_size[0xc];
2807
2808         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2809
2810         u8         reserved_at_7e0[0x20];
2811
2812         u8         current_uc_mac_address[0][0x40];
2813 };
2814
2815 enum {
2816         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2817         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2818         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2819         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2820         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2821 };
2822
2823 struct mlx5_ifc_mkc_bits {
2824         u8         reserved_at_0[0x1];
2825         u8         free[0x1];
2826         u8         reserved_at_2[0x1];
2827         u8         access_mode_4_2[0x3];
2828         u8         reserved_at_6[0x7];
2829         u8         relaxed_ordering_write[0x1];
2830         u8         reserved_at_e[0x1];
2831         u8         small_fence_on_rdma_read_response[0x1];
2832         u8         umr_en[0x1];
2833         u8         a[0x1];
2834         u8         rw[0x1];
2835         u8         rr[0x1];
2836         u8         lw[0x1];
2837         u8         lr[0x1];
2838         u8         access_mode_1_0[0x2];
2839         u8         reserved_at_18[0x8];
2840
2841         u8         qpn[0x18];
2842         u8         mkey_7_0[0x8];
2843
2844         u8         reserved_at_40[0x20];
2845
2846         u8         length64[0x1];
2847         u8         bsf_en[0x1];
2848         u8         sync_umr[0x1];
2849         u8         reserved_at_63[0x2];
2850         u8         expected_sigerr_count[0x1];
2851         u8         reserved_at_66[0x1];
2852         u8         en_rinval[0x1];
2853         u8         pd[0x18];
2854
2855         u8         start_addr[0x40];
2856
2857         u8         len[0x40];
2858
2859         u8         bsf_octword_size[0x20];
2860
2861         u8         reserved_at_120[0x80];
2862
2863         u8         translations_octword_size[0x20];
2864
2865         u8         reserved_at_1c0[0x1b];
2866         u8         log_page_size[0x5];
2867
2868         u8         reserved_at_1e0[0x20];
2869 };
2870
2871 struct mlx5_ifc_pkey_bits {
2872         u8         reserved_at_0[0x10];
2873         u8         pkey[0x10];
2874 };
2875
2876 struct mlx5_ifc_array128_auto_bits {
2877         u8         array128_auto[16][0x8];
2878 };
2879
2880 struct mlx5_ifc_hca_vport_context_bits {
2881         u8         field_select[0x20];
2882
2883         u8         reserved_at_20[0xe0];
2884
2885         u8         sm_virt_aware[0x1];
2886         u8         has_smi[0x1];
2887         u8         has_raw[0x1];
2888         u8         grh_required[0x1];
2889         u8         reserved_at_104[0xc];
2890         u8         port_physical_state[0x4];
2891         u8         vport_state_policy[0x4];
2892         u8         port_state[0x4];
2893         u8         vport_state[0x4];
2894
2895         u8         reserved_at_120[0x20];
2896
2897         u8         system_image_guid[0x40];
2898
2899         u8         port_guid[0x40];
2900
2901         u8         node_guid[0x40];
2902
2903         u8         cap_mask1[0x20];
2904
2905         u8         cap_mask1_field_select[0x20];
2906
2907         u8         cap_mask2[0x20];
2908
2909         u8         cap_mask2_field_select[0x20];
2910
2911         u8         reserved_at_280[0x80];
2912
2913         u8         lid[0x10];
2914         u8         reserved_at_310[0x4];
2915         u8         init_type_reply[0x4];
2916         u8         lmc[0x3];
2917         u8         subnet_timeout[0x5];
2918
2919         u8         sm_lid[0x10];
2920         u8         sm_sl[0x4];
2921         u8         reserved_at_334[0xc];
2922
2923         u8         qkey_violation_counter[0x10];
2924         u8         pkey_violation_counter[0x10];
2925
2926         u8         reserved_at_360[0xca0];
2927 };
2928
2929 struct mlx5_ifc_esw_vport_context_bits {
2930         u8         reserved_at_0[0x3];
2931         u8         vport_svlan_strip[0x1];
2932         u8         vport_cvlan_strip[0x1];
2933         u8         vport_svlan_insert[0x1];
2934         u8         vport_cvlan_insert[0x2];
2935         u8         reserved_at_8[0x18];
2936
2937         u8         reserved_at_20[0x20];
2938
2939         u8         svlan_cfi[0x1];
2940         u8         svlan_pcp[0x3];
2941         u8         svlan_id[0xc];
2942         u8         cvlan_cfi[0x1];
2943         u8         cvlan_pcp[0x3];
2944         u8         cvlan_id[0xc];
2945
2946         u8         reserved_at_60[0x7a0];
2947 };
2948
2949 enum {
2950         MLX5_EQC_STATUS_OK                = 0x0,
2951         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2952 };
2953
2954 enum {
2955         MLX5_EQC_ST_ARMED  = 0x9,
2956         MLX5_EQC_ST_FIRED  = 0xa,
2957 };
2958
2959 struct mlx5_ifc_eqc_bits {
2960         u8         status[0x4];
2961         u8         reserved_at_4[0x9];
2962         u8         ec[0x1];
2963         u8         oi[0x1];
2964         u8         reserved_at_f[0x5];
2965         u8         st[0x4];
2966         u8         reserved_at_18[0x8];
2967
2968         u8         reserved_at_20[0x20];
2969
2970         u8         reserved_at_40[0x14];
2971         u8         page_offset[0x6];
2972         u8         reserved_at_5a[0x6];
2973
2974         u8         reserved_at_60[0x3];
2975         u8         log_eq_size[0x5];
2976         u8         uar_page[0x18];
2977
2978         u8         reserved_at_80[0x20];
2979
2980         u8         reserved_at_a0[0x18];
2981         u8         intr[0x8];
2982
2983         u8         reserved_at_c0[0x3];
2984         u8         log_page_size[0x5];
2985         u8         reserved_at_c8[0x18];
2986
2987         u8         reserved_at_e0[0x60];
2988
2989         u8         reserved_at_140[0x8];
2990         u8         consumer_counter[0x18];
2991
2992         u8         reserved_at_160[0x8];
2993         u8         producer_counter[0x18];
2994
2995         u8         reserved_at_180[0x80];
2996 };
2997
2998 enum {
2999         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3000         MLX5_DCTC_STATE_DRAINING  = 0x1,
3001         MLX5_DCTC_STATE_DRAINED   = 0x2,
3002 };
3003
3004 enum {
3005         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3006         MLX5_DCTC_CS_RES_NA         = 0x1,
3007         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3008 };
3009
3010 enum {
3011         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3012         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3013         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3014         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3015         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3016 };
3017
3018 struct mlx5_ifc_dctc_bits {
3019         u8         reserved_at_0[0x4];
3020         u8         state[0x4];
3021         u8         reserved_at_8[0x18];
3022
3023         u8         reserved_at_20[0x8];
3024         u8         user_index[0x18];
3025
3026         u8         reserved_at_40[0x8];
3027         u8         cqn[0x18];
3028
3029         u8         counter_set_id[0x8];
3030         u8         atomic_mode[0x4];
3031         u8         rre[0x1];
3032         u8         rwe[0x1];
3033         u8         rae[0x1];
3034         u8         atomic_like_write_en[0x1];
3035         u8         latency_sensitive[0x1];
3036         u8         rlky[0x1];
3037         u8         free_ar[0x1];
3038         u8         reserved_at_73[0xd];
3039
3040         u8         reserved_at_80[0x8];
3041         u8         cs_res[0x8];
3042         u8         reserved_at_90[0x3];
3043         u8         min_rnr_nak[0x5];
3044         u8         reserved_at_98[0x8];
3045
3046         u8         reserved_at_a0[0x8];
3047         u8         srqn_xrqn[0x18];
3048
3049         u8         reserved_at_c0[0x8];
3050         u8         pd[0x18];
3051
3052         u8         tclass[0x8];
3053         u8         reserved_at_e8[0x4];
3054         u8         flow_label[0x14];
3055
3056         u8         dc_access_key[0x40];
3057
3058         u8         reserved_at_140[0x5];
3059         u8         mtu[0x3];
3060         u8         port[0x8];
3061         u8         pkey_index[0x10];
3062
3063         u8         reserved_at_160[0x8];
3064         u8         my_addr_index[0x8];
3065         u8         reserved_at_170[0x8];
3066         u8         hop_limit[0x8];
3067
3068         u8         dc_access_key_violation_count[0x20];
3069
3070         u8         reserved_at_1a0[0x14];
3071         u8         dei_cfi[0x1];
3072         u8         eth_prio[0x3];
3073         u8         ecn[0x2];
3074         u8         dscp[0x6];
3075
3076         u8         reserved_at_1c0[0x40];
3077 };
3078
3079 enum {
3080         MLX5_CQC_STATUS_OK             = 0x0,
3081         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3082         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3083 };
3084
3085 enum {
3086         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3087         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3088 };
3089
3090 enum {
3091         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3092         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3093         MLX5_CQC_ST_FIRED                                 = 0xa,
3094 };
3095
3096 enum {
3097         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3098         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3099         MLX5_CQ_PERIOD_NUM_MODES
3100 };
3101
3102 struct mlx5_ifc_cqc_bits {
3103         u8         status[0x4];
3104         u8         reserved_at_4[0x4];
3105         u8         cqe_sz[0x3];
3106         u8         cc[0x1];
3107         u8         reserved_at_c[0x1];
3108         u8         scqe_break_moderation_en[0x1];
3109         u8         oi[0x1];
3110         u8         cq_period_mode[0x2];
3111         u8         cqe_comp_en[0x1];
3112         u8         mini_cqe_res_format[0x2];
3113         u8         st[0x4];
3114         u8         reserved_at_18[0x8];
3115
3116         u8         reserved_at_20[0x20];
3117
3118         u8         reserved_at_40[0x14];
3119         u8         page_offset[0x6];
3120         u8         reserved_at_5a[0x6];
3121
3122         u8         reserved_at_60[0x3];
3123         u8         log_cq_size[0x5];
3124         u8         uar_page[0x18];
3125
3126         u8         reserved_at_80[0x4];
3127         u8         cq_period[0xc];
3128         u8         cq_max_count[0x10];
3129
3130         u8         reserved_at_a0[0x18];
3131         u8         c_eqn[0x8];
3132
3133         u8         reserved_at_c0[0x3];
3134         u8         log_page_size[0x5];
3135         u8         reserved_at_c8[0x18];
3136
3137         u8         reserved_at_e0[0x20];
3138
3139         u8         reserved_at_100[0x8];
3140         u8         last_notified_index[0x18];
3141
3142         u8         reserved_at_120[0x8];
3143         u8         last_solicit_index[0x18];
3144
3145         u8         reserved_at_140[0x8];
3146         u8         consumer_counter[0x18];
3147
3148         u8         reserved_at_160[0x8];
3149         u8         producer_counter[0x18];
3150
3151         u8         reserved_at_180[0x40];
3152
3153         u8         dbr_addr[0x40];
3154 };
3155
3156 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3157         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3158         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3159         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3160         u8         reserved_at_0[0x800];
3161 };
3162
3163 struct mlx5_ifc_query_adapter_param_block_bits {
3164         u8         reserved_at_0[0xc0];
3165
3166         u8         reserved_at_c0[0x8];
3167         u8         ieee_vendor_id[0x18];
3168
3169         u8         reserved_at_e0[0x10];
3170         u8         vsd_vendor_id[0x10];
3171
3172         u8         vsd[208][0x8];
3173
3174         u8         vsd_contd_psid[16][0x8];
3175 };
3176
3177 enum {
3178         MLX5_XRQC_STATE_GOOD   = 0x0,
3179         MLX5_XRQC_STATE_ERROR  = 0x1,
3180 };
3181
3182 enum {
3183         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3184         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3185 };
3186
3187 enum {
3188         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3189 };
3190
3191 struct mlx5_ifc_tag_matching_topology_context_bits {
3192         u8         log_matching_list_sz[0x4];
3193         u8         reserved_at_4[0xc];
3194         u8         append_next_index[0x10];
3195
3196         u8         sw_phase_cnt[0x10];
3197         u8         hw_phase_cnt[0x10];
3198
3199         u8         reserved_at_40[0x40];
3200 };
3201
3202 struct mlx5_ifc_xrqc_bits {
3203         u8         state[0x4];
3204         u8         rlkey[0x1];
3205         u8         reserved_at_5[0xf];
3206         u8         topology[0x4];
3207         u8         reserved_at_18[0x4];
3208         u8         offload[0x4];
3209
3210         u8         reserved_at_20[0x8];
3211         u8         user_index[0x18];
3212
3213         u8         reserved_at_40[0x8];
3214         u8         cqn[0x18];
3215
3216         u8         reserved_at_60[0xa0];
3217
3218         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3219
3220         u8         reserved_at_180[0x280];
3221
3222         struct mlx5_ifc_wq_bits wq;
3223 };
3224
3225 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3226         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3227         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3228         u8         reserved_at_0[0x20];
3229 };
3230
3231 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3232         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3233         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3234         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3235         u8         reserved_at_0[0x20];
3236 };
3237
3238 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3239         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3240         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3241         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3242         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3243         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3244         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3245         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3246         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3247         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3248         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3249         u8         reserved_at_0[0x7c0];
3250 };
3251
3252 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3253         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3254         u8         reserved_at_0[0x7c0];
3255 };
3256
3257 union mlx5_ifc_event_auto_bits {
3258         struct mlx5_ifc_comp_event_bits comp_event;
3259         struct mlx5_ifc_dct_events_bits dct_events;
3260         struct mlx5_ifc_qp_events_bits qp_events;
3261         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3262         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3263         struct mlx5_ifc_cq_error_bits cq_error;
3264         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3265         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3266         struct mlx5_ifc_gpio_event_bits gpio_event;
3267         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3268         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3269         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3270         u8         reserved_at_0[0xe0];
3271 };
3272
3273 struct mlx5_ifc_health_buffer_bits {
3274         u8         reserved_at_0[0x100];
3275
3276         u8         assert_existptr[0x20];
3277
3278         u8         assert_callra[0x20];
3279
3280         u8         reserved_at_140[0x40];
3281
3282         u8         fw_version[0x20];
3283
3284         u8         hw_id[0x20];
3285
3286         u8         reserved_at_1c0[0x20];
3287
3288         u8         irisc_index[0x8];
3289         u8         synd[0x8];
3290         u8         ext_synd[0x10];
3291 };
3292
3293 struct mlx5_ifc_register_loopback_control_bits {
3294         u8         no_lb[0x1];
3295         u8         reserved_at_1[0x7];
3296         u8         port[0x8];
3297         u8         reserved_at_10[0x10];
3298
3299         u8         reserved_at_20[0x60];
3300 };
3301
3302 struct mlx5_ifc_vport_tc_element_bits {
3303         u8         traffic_class[0x4];
3304         u8         reserved_at_4[0xc];
3305         u8         vport_number[0x10];
3306 };
3307
3308 struct mlx5_ifc_vport_element_bits {
3309         u8         reserved_at_0[0x10];
3310         u8         vport_number[0x10];
3311 };
3312
3313 enum {
3314         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3315         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3316         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3317 };
3318
3319 struct mlx5_ifc_tsar_element_bits {
3320         u8         reserved_at_0[0x8];
3321         u8         tsar_type[0x8];
3322         u8         reserved_at_10[0x10];
3323 };
3324
3325 enum {
3326         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3327         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3328 };
3329
3330 struct mlx5_ifc_teardown_hca_out_bits {
3331         u8         status[0x8];
3332         u8         reserved_at_8[0x18];
3333
3334         u8         syndrome[0x20];
3335
3336         u8         reserved_at_40[0x3f];
3337
3338         u8         force_state[0x1];
3339 };
3340
3341 enum {
3342         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3343         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3344 };
3345
3346 struct mlx5_ifc_teardown_hca_in_bits {
3347         u8         opcode[0x10];
3348         u8         reserved_at_10[0x10];
3349
3350         u8         reserved_at_20[0x10];
3351         u8         op_mod[0x10];
3352
3353         u8         reserved_at_40[0x10];
3354         u8         profile[0x10];
3355
3356         u8         reserved_at_60[0x20];
3357 };
3358
3359 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3360         u8         status[0x8];
3361         u8         reserved_at_8[0x18];
3362
3363         u8         syndrome[0x20];
3364
3365         u8         reserved_at_40[0x40];
3366 };
3367
3368 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3369         u8         opcode[0x10];
3370         u8         reserved_at_10[0x10];
3371
3372         u8         reserved_at_20[0x10];
3373         u8         op_mod[0x10];
3374
3375         u8         reserved_at_40[0x8];
3376         u8         qpn[0x18];
3377
3378         u8         reserved_at_60[0x20];
3379
3380         u8         opt_param_mask[0x20];
3381
3382         u8         reserved_at_a0[0x20];
3383
3384         struct mlx5_ifc_qpc_bits qpc;
3385
3386         u8         reserved_at_800[0x80];
3387 };
3388
3389 struct mlx5_ifc_sqd2rts_qp_out_bits {
3390         u8         status[0x8];
3391         u8         reserved_at_8[0x18];
3392
3393         u8         syndrome[0x20];
3394
3395         u8         reserved_at_40[0x40];
3396 };
3397
3398 struct mlx5_ifc_sqd2rts_qp_in_bits {
3399         u8         opcode[0x10];
3400         u8         reserved_at_10[0x10];
3401
3402         u8         reserved_at_20[0x10];
3403         u8         op_mod[0x10];
3404
3405         u8         reserved_at_40[0x8];
3406         u8         qpn[0x18];
3407
3408         u8         reserved_at_60[0x20];
3409
3410         u8         opt_param_mask[0x20];
3411
3412         u8         reserved_at_a0[0x20];
3413
3414         struct mlx5_ifc_qpc_bits qpc;
3415
3416         u8         reserved_at_800[0x80];
3417 };
3418
3419 struct mlx5_ifc_set_roce_address_out_bits {
3420         u8         status[0x8];
3421         u8         reserved_at_8[0x18];
3422
3423         u8         syndrome[0x20];
3424
3425         u8         reserved_at_40[0x40];
3426 };
3427
3428 struct mlx5_ifc_set_roce_address_in_bits {
3429         u8         opcode[0x10];
3430         u8         reserved_at_10[0x10];
3431
3432         u8         reserved_at_20[0x10];
3433         u8         op_mod[0x10];
3434
3435         u8         roce_address_index[0x10];
3436         u8         reserved_at_50[0xc];
3437         u8         vhca_port_num[0x4];
3438
3439         u8         reserved_at_60[0x20];
3440
3441         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3442 };
3443
3444 struct mlx5_ifc_set_mad_demux_out_bits {
3445         u8         status[0x8];
3446         u8         reserved_at_8[0x18];
3447
3448         u8         syndrome[0x20];
3449
3450         u8         reserved_at_40[0x40];
3451 };
3452
3453 enum {
3454         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3455         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3456 };
3457
3458 struct mlx5_ifc_set_mad_demux_in_bits {
3459         u8         opcode[0x10];
3460         u8         reserved_at_10[0x10];
3461
3462         u8         reserved_at_20[0x10];
3463         u8         op_mod[0x10];
3464
3465         u8         reserved_at_40[0x20];
3466
3467         u8         reserved_at_60[0x6];
3468         u8         demux_mode[0x2];
3469         u8         reserved_at_68[0x18];
3470 };
3471
3472 struct mlx5_ifc_set_l2_table_entry_out_bits {
3473         u8         status[0x8];
3474         u8         reserved_at_8[0x18];
3475
3476         u8         syndrome[0x20];
3477
3478         u8         reserved_at_40[0x40];
3479 };
3480
3481 struct mlx5_ifc_set_l2_table_entry_in_bits {
3482         u8         opcode[0x10];
3483         u8         reserved_at_10[0x10];
3484
3485         u8         reserved_at_20[0x10];
3486         u8         op_mod[0x10];
3487
3488         u8         reserved_at_40[0x60];
3489
3490         u8         reserved_at_a0[0x8];
3491         u8         table_index[0x18];
3492
3493         u8         reserved_at_c0[0x20];
3494
3495         u8         reserved_at_e0[0x13];
3496         u8         vlan_valid[0x1];
3497         u8         vlan[0xc];
3498
3499         struct mlx5_ifc_mac_address_layout_bits mac_address;
3500
3501         u8         reserved_at_140[0xc0];
3502 };
3503
3504 struct mlx5_ifc_set_issi_out_bits {
3505         u8         status[0x8];
3506         u8         reserved_at_8[0x18];
3507
3508         u8         syndrome[0x20];
3509
3510         u8         reserved_at_40[0x40];
3511 };
3512
3513 struct mlx5_ifc_set_issi_in_bits {
3514         u8         opcode[0x10];
3515         u8         reserved_at_10[0x10];
3516
3517         u8         reserved_at_20[0x10];
3518         u8         op_mod[0x10];
3519
3520         u8         reserved_at_40[0x10];
3521         u8         current_issi[0x10];
3522
3523         u8         reserved_at_60[0x20];
3524 };
3525
3526 struct mlx5_ifc_set_hca_cap_out_bits {
3527         u8         status[0x8];
3528         u8         reserved_at_8[0x18];
3529
3530         u8         syndrome[0x20];
3531
3532         u8         reserved_at_40[0x40];
3533 };
3534
3535 struct mlx5_ifc_set_hca_cap_in_bits {
3536         u8         opcode[0x10];
3537         u8         reserved_at_10[0x10];
3538
3539         u8         reserved_at_20[0x10];
3540         u8         op_mod[0x10];
3541
3542         u8         reserved_at_40[0x40];
3543
3544         union mlx5_ifc_hca_cap_union_bits capability;
3545 };
3546
3547 enum {
3548         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3549         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3550         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3551         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3552 };
3553
3554 struct mlx5_ifc_set_fte_out_bits {
3555         u8         status[0x8];
3556         u8         reserved_at_8[0x18];
3557
3558         u8         syndrome[0x20];
3559
3560         u8         reserved_at_40[0x40];
3561 };
3562
3563 struct mlx5_ifc_set_fte_in_bits {
3564         u8         opcode[0x10];
3565         u8         reserved_at_10[0x10];
3566
3567         u8         reserved_at_20[0x10];
3568         u8         op_mod[0x10];
3569
3570         u8         other_vport[0x1];
3571         u8         reserved_at_41[0xf];
3572         u8         vport_number[0x10];
3573
3574         u8         reserved_at_60[0x20];
3575
3576         u8         table_type[0x8];
3577         u8         reserved_at_88[0x18];
3578
3579         u8         reserved_at_a0[0x8];
3580         u8         table_id[0x18];
3581
3582         u8         reserved_at_c0[0x18];
3583         u8         modify_enable_mask[0x8];
3584
3585         u8         reserved_at_e0[0x20];
3586
3587         u8         flow_index[0x20];
3588
3589         u8         reserved_at_120[0xe0];
3590
3591         struct mlx5_ifc_flow_context_bits flow_context;
3592 };
3593
3594 struct mlx5_ifc_rts2rts_qp_out_bits {
3595         u8         status[0x8];
3596         u8         reserved_at_8[0x18];
3597
3598         u8         syndrome[0x20];
3599
3600         u8         reserved_at_40[0x40];
3601 };
3602
3603 struct mlx5_ifc_rts2rts_qp_in_bits {
3604         u8         opcode[0x10];
3605         u8         reserved_at_10[0x10];
3606
3607         u8         reserved_at_20[0x10];
3608         u8         op_mod[0x10];
3609
3610         u8         reserved_at_40[0x8];
3611         u8         qpn[0x18];
3612
3613         u8         reserved_at_60[0x20];
3614
3615         u8         opt_param_mask[0x20];
3616
3617         u8         reserved_at_a0[0x20];
3618
3619         struct mlx5_ifc_qpc_bits qpc;
3620
3621         u8         reserved_at_800[0x80];
3622 };
3623
3624 struct mlx5_ifc_rtr2rts_qp_out_bits {
3625         u8         status[0x8];
3626         u8         reserved_at_8[0x18];
3627
3628         u8         syndrome[0x20];
3629
3630         u8         reserved_at_40[0x40];
3631 };
3632
3633 struct mlx5_ifc_rtr2rts_qp_in_bits {
3634         u8         opcode[0x10];
3635         u8         reserved_at_10[0x10];
3636
3637         u8         reserved_at_20[0x10];
3638         u8         op_mod[0x10];
3639
3640         u8         reserved_at_40[0x8];
3641         u8         qpn[0x18];
3642
3643         u8         reserved_at_60[0x20];
3644
3645         u8         opt_param_mask[0x20];
3646
3647         u8         reserved_at_a0[0x20];
3648
3649         struct mlx5_ifc_qpc_bits qpc;
3650
3651         u8         reserved_at_800[0x80];
3652 };
3653
3654 struct mlx5_ifc_rst2init_qp_out_bits {
3655         u8         status[0x8];
3656         u8         reserved_at_8[0x18];
3657
3658         u8         syndrome[0x20];
3659
3660         u8         reserved_at_40[0x40];
3661 };
3662
3663 struct mlx5_ifc_rst2init_qp_in_bits {
3664         u8         opcode[0x10];
3665         u8         reserved_at_10[0x10];
3666
3667         u8         reserved_at_20[0x10];
3668         u8         op_mod[0x10];
3669
3670         u8         reserved_at_40[0x8];
3671         u8         qpn[0x18];
3672
3673         u8         reserved_at_60[0x20];
3674
3675         u8         opt_param_mask[0x20];
3676
3677         u8         reserved_at_a0[0x20];
3678
3679         struct mlx5_ifc_qpc_bits qpc;
3680
3681         u8         reserved_at_800[0x80];
3682 };
3683
3684 struct mlx5_ifc_query_xrq_out_bits {
3685         u8         status[0x8];
3686         u8         reserved_at_8[0x18];
3687
3688         u8         syndrome[0x20];
3689
3690         u8         reserved_at_40[0x40];
3691
3692         struct mlx5_ifc_xrqc_bits xrq_context;
3693 };
3694
3695 struct mlx5_ifc_query_xrq_in_bits {
3696         u8         opcode[0x10];
3697         u8         reserved_at_10[0x10];
3698
3699         u8         reserved_at_20[0x10];
3700         u8         op_mod[0x10];
3701
3702         u8         reserved_at_40[0x8];
3703         u8         xrqn[0x18];
3704
3705         u8         reserved_at_60[0x20];
3706 };
3707
3708 struct mlx5_ifc_query_xrc_srq_out_bits {
3709         u8         status[0x8];
3710         u8         reserved_at_8[0x18];
3711
3712         u8         syndrome[0x20];
3713
3714         u8         reserved_at_40[0x40];
3715
3716         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3717
3718         u8         reserved_at_280[0x600];
3719
3720         u8         pas[0][0x40];
3721 };
3722
3723 struct mlx5_ifc_query_xrc_srq_in_bits {
3724         u8         opcode[0x10];
3725         u8         reserved_at_10[0x10];
3726
3727         u8         reserved_at_20[0x10];
3728         u8         op_mod[0x10];
3729
3730         u8         reserved_at_40[0x8];
3731         u8         xrc_srqn[0x18];
3732
3733         u8         reserved_at_60[0x20];
3734 };
3735
3736 enum {
3737         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3738         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3739 };
3740
3741 struct mlx5_ifc_query_vport_state_out_bits {
3742         u8         status[0x8];
3743         u8         reserved_at_8[0x18];
3744
3745         u8         syndrome[0x20];
3746
3747         u8         reserved_at_40[0x20];
3748
3749         u8         reserved_at_60[0x18];
3750         u8         admin_state[0x4];
3751         u8         state[0x4];
3752 };
3753
3754 enum {
3755         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3756         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3757 };
3758
3759 struct mlx5_ifc_query_vport_state_in_bits {
3760         u8         opcode[0x10];
3761         u8         reserved_at_10[0x10];
3762
3763         u8         reserved_at_20[0x10];
3764         u8         op_mod[0x10];
3765
3766         u8         other_vport[0x1];
3767         u8         reserved_at_41[0xf];
3768         u8         vport_number[0x10];
3769
3770         u8         reserved_at_60[0x20];
3771 };
3772
3773 struct mlx5_ifc_query_vnic_env_out_bits {
3774         u8         status[0x8];
3775         u8         reserved_at_8[0x18];
3776
3777         u8         syndrome[0x20];
3778
3779         u8         reserved_at_40[0x40];
3780
3781         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3782 };
3783
3784 enum {
3785         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
3786 };
3787
3788 struct mlx5_ifc_query_vnic_env_in_bits {
3789         u8         opcode[0x10];
3790         u8         reserved_at_10[0x10];
3791
3792         u8         reserved_at_20[0x10];
3793         u8         op_mod[0x10];
3794
3795         u8         other_vport[0x1];
3796         u8         reserved_at_41[0xf];
3797         u8         vport_number[0x10];
3798
3799         u8         reserved_at_60[0x20];
3800 };
3801
3802 struct mlx5_ifc_query_vport_counter_out_bits {
3803         u8         status[0x8];
3804         u8         reserved_at_8[0x18];
3805
3806         u8         syndrome[0x20];
3807
3808         u8         reserved_at_40[0x40];
3809
3810         struct mlx5_ifc_traffic_counter_bits received_errors;
3811
3812         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3813
3814         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3815
3816         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3817
3818         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3819
3820         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3821
3822         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3823
3824         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3825
3826         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3827
3828         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3829
3830         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3831
3832         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3833
3834         u8         reserved_at_680[0xa00];
3835 };
3836
3837 enum {
3838         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3839 };
3840
3841 struct mlx5_ifc_query_vport_counter_in_bits {
3842         u8         opcode[0x10];
3843         u8         reserved_at_10[0x10];
3844
3845         u8         reserved_at_20[0x10];
3846         u8         op_mod[0x10];
3847
3848         u8         other_vport[0x1];
3849         u8         reserved_at_41[0xb];
3850         u8         port_num[0x4];
3851         u8         vport_number[0x10];
3852
3853         u8         reserved_at_60[0x60];
3854
3855         u8         clear[0x1];
3856         u8         reserved_at_c1[0x1f];
3857
3858         u8         reserved_at_e0[0x20];
3859 };
3860
3861 struct mlx5_ifc_query_tis_out_bits {
3862         u8         status[0x8];
3863         u8         reserved_at_8[0x18];
3864
3865         u8         syndrome[0x20];
3866
3867         u8         reserved_at_40[0x40];
3868
3869         struct mlx5_ifc_tisc_bits tis_context;
3870 };
3871
3872 struct mlx5_ifc_query_tis_in_bits {
3873         u8         opcode[0x10];
3874         u8         reserved_at_10[0x10];
3875
3876         u8         reserved_at_20[0x10];
3877         u8         op_mod[0x10];
3878
3879         u8         reserved_at_40[0x8];
3880         u8         tisn[0x18];
3881
3882         u8         reserved_at_60[0x20];
3883 };
3884
3885 struct mlx5_ifc_query_tir_out_bits {
3886         u8         status[0x8];
3887         u8         reserved_at_8[0x18];
3888
3889         u8         syndrome[0x20];
3890
3891         u8         reserved_at_40[0xc0];
3892
3893         struct mlx5_ifc_tirc_bits tir_context;
3894 };
3895
3896 struct mlx5_ifc_query_tir_in_bits {
3897         u8         opcode[0x10];
3898         u8         reserved_at_10[0x10];
3899
3900         u8         reserved_at_20[0x10];
3901         u8         op_mod[0x10];
3902
3903         u8         reserved_at_40[0x8];
3904         u8         tirn[0x18];
3905
3906         u8         reserved_at_60[0x20];
3907 };
3908
3909 struct mlx5_ifc_query_srq_out_bits {
3910         u8         status[0x8];
3911         u8         reserved_at_8[0x18];
3912
3913         u8         syndrome[0x20];
3914
3915         u8         reserved_at_40[0x40];
3916
3917         struct mlx5_ifc_srqc_bits srq_context_entry;
3918
3919         u8         reserved_at_280[0x600];
3920
3921         u8         pas[0][0x40];
3922 };
3923
3924 struct mlx5_ifc_query_srq_in_bits {
3925         u8         opcode[0x10];
3926         u8         reserved_at_10[0x10];
3927
3928         u8         reserved_at_20[0x10];
3929         u8         op_mod[0x10];
3930
3931         u8         reserved_at_40[0x8];
3932         u8         srqn[0x18];
3933
3934         u8         reserved_at_60[0x20];
3935 };
3936
3937 struct mlx5_ifc_query_sq_out_bits {
3938         u8         status[0x8];
3939         u8         reserved_at_8[0x18];
3940
3941         u8         syndrome[0x20];
3942
3943         u8         reserved_at_40[0xc0];
3944
3945         struct mlx5_ifc_sqc_bits sq_context;
3946 };
3947
3948 struct mlx5_ifc_query_sq_in_bits {
3949         u8         opcode[0x10];
3950         u8         reserved_at_10[0x10];
3951
3952         u8         reserved_at_20[0x10];
3953         u8         op_mod[0x10];
3954
3955         u8         reserved_at_40[0x8];
3956         u8         sqn[0x18];
3957
3958         u8         reserved_at_60[0x20];
3959 };
3960
3961 struct mlx5_ifc_query_special_contexts_out_bits {
3962         u8         status[0x8];
3963         u8         reserved_at_8[0x18];
3964
3965         u8         syndrome[0x20];
3966
3967         u8         dump_fill_mkey[0x20];
3968
3969         u8         resd_lkey[0x20];
3970
3971         u8         null_mkey[0x20];
3972
3973         u8         reserved_at_a0[0x60];
3974 };
3975
3976 struct mlx5_ifc_query_special_contexts_in_bits {
3977         u8         opcode[0x10];
3978         u8         reserved_at_10[0x10];
3979
3980         u8         reserved_at_20[0x10];
3981         u8         op_mod[0x10];
3982
3983         u8         reserved_at_40[0x40];
3984 };
3985
3986 struct mlx5_ifc_query_scheduling_element_out_bits {
3987         u8         opcode[0x10];
3988         u8         reserved_at_10[0x10];
3989
3990         u8         reserved_at_20[0x10];
3991         u8         op_mod[0x10];
3992
3993         u8         reserved_at_40[0xc0];
3994
3995         struct mlx5_ifc_scheduling_context_bits scheduling_context;
3996
3997         u8         reserved_at_300[0x100];
3998 };
3999
4000 enum {
4001         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4002 };
4003
4004 struct mlx5_ifc_query_scheduling_element_in_bits {
4005         u8         opcode[0x10];
4006         u8         reserved_at_10[0x10];
4007
4008         u8         reserved_at_20[0x10];
4009         u8         op_mod[0x10];
4010
4011         u8         scheduling_hierarchy[0x8];
4012         u8         reserved_at_48[0x18];
4013
4014         u8         scheduling_element_id[0x20];
4015
4016         u8         reserved_at_80[0x180];
4017 };
4018
4019 struct mlx5_ifc_query_rqt_out_bits {
4020         u8         status[0x8];
4021         u8         reserved_at_8[0x18];
4022
4023         u8         syndrome[0x20];
4024
4025         u8         reserved_at_40[0xc0];
4026
4027         struct mlx5_ifc_rqtc_bits rqt_context;
4028 };
4029
4030 struct mlx5_ifc_query_rqt_in_bits {
4031         u8         opcode[0x10];
4032         u8         reserved_at_10[0x10];
4033
4034         u8         reserved_at_20[0x10];
4035         u8         op_mod[0x10];
4036
4037         u8         reserved_at_40[0x8];
4038         u8         rqtn[0x18];
4039
4040         u8         reserved_at_60[0x20];
4041 };
4042
4043 struct mlx5_ifc_query_rq_out_bits {
4044         u8         status[0x8];
4045         u8         reserved_at_8[0x18];
4046
4047         u8         syndrome[0x20];
4048
4049         u8         reserved_at_40[0xc0];
4050
4051         struct mlx5_ifc_rqc_bits rq_context;
4052 };
4053
4054 struct mlx5_ifc_query_rq_in_bits {
4055         u8         opcode[0x10];
4056         u8         reserved_at_10[0x10];
4057
4058         u8         reserved_at_20[0x10];
4059         u8         op_mod[0x10];
4060
4061         u8         reserved_at_40[0x8];
4062         u8         rqn[0x18];
4063
4064         u8         reserved_at_60[0x20];
4065 };
4066
4067 struct mlx5_ifc_query_roce_address_out_bits {
4068         u8         status[0x8];
4069         u8         reserved_at_8[0x18];
4070
4071         u8         syndrome[0x20];
4072
4073         u8         reserved_at_40[0x40];
4074
4075         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4076 };
4077
4078 struct mlx5_ifc_query_roce_address_in_bits {
4079         u8         opcode[0x10];
4080         u8         reserved_at_10[0x10];
4081
4082         u8         reserved_at_20[0x10];
4083         u8         op_mod[0x10];
4084
4085         u8         roce_address_index[0x10];
4086         u8         reserved_at_50[0xc];
4087         u8         vhca_port_num[0x4];
4088
4089         u8         reserved_at_60[0x20];
4090 };
4091
4092 struct mlx5_ifc_query_rmp_out_bits {
4093         u8         status[0x8];
4094         u8         reserved_at_8[0x18];
4095
4096         u8         syndrome[0x20];
4097
4098         u8         reserved_at_40[0xc0];
4099
4100         struct mlx5_ifc_rmpc_bits rmp_context;
4101 };
4102
4103 struct mlx5_ifc_query_rmp_in_bits {
4104         u8         opcode[0x10];
4105         u8         reserved_at_10[0x10];
4106
4107         u8         reserved_at_20[0x10];
4108         u8         op_mod[0x10];
4109
4110         u8         reserved_at_40[0x8];
4111         u8         rmpn[0x18];
4112
4113         u8         reserved_at_60[0x20];
4114 };
4115
4116 struct mlx5_ifc_query_qp_out_bits {
4117         u8         status[0x8];
4118         u8         reserved_at_8[0x18];
4119
4120         u8         syndrome[0x20];
4121
4122         u8         reserved_at_40[0x40];
4123
4124         u8         opt_param_mask[0x20];
4125
4126         u8         reserved_at_a0[0x20];
4127
4128         struct mlx5_ifc_qpc_bits qpc;
4129
4130         u8         reserved_at_800[0x80];
4131
4132         u8         pas[0][0x40];
4133 };
4134
4135 struct mlx5_ifc_query_qp_in_bits {
4136         u8         opcode[0x10];
4137         u8         reserved_at_10[0x10];
4138
4139         u8         reserved_at_20[0x10];
4140         u8         op_mod[0x10];
4141
4142         u8         reserved_at_40[0x8];
4143         u8         qpn[0x18];
4144
4145         u8         reserved_at_60[0x20];
4146 };
4147
4148 struct mlx5_ifc_query_q_counter_out_bits {
4149         u8         status[0x8];
4150         u8         reserved_at_8[0x18];
4151
4152         u8         syndrome[0x20];
4153
4154         u8         reserved_at_40[0x40];
4155
4156         u8         rx_write_requests[0x20];
4157
4158         u8         reserved_at_a0[0x20];
4159
4160         u8         rx_read_requests[0x20];
4161
4162         u8         reserved_at_e0[0x20];
4163
4164         u8         rx_atomic_requests[0x20];
4165
4166         u8         reserved_at_120[0x20];
4167
4168         u8         rx_dct_connect[0x20];
4169
4170         u8         reserved_at_160[0x20];
4171
4172         u8         out_of_buffer[0x20];
4173
4174         u8         reserved_at_1a0[0x20];
4175
4176         u8         out_of_sequence[0x20];
4177
4178         u8         reserved_at_1e0[0x20];
4179
4180         u8         duplicate_request[0x20];
4181
4182         u8         reserved_at_220[0x20];
4183
4184         u8         rnr_nak_retry_err[0x20];
4185
4186         u8         reserved_at_260[0x20];
4187
4188         u8         packet_seq_err[0x20];
4189
4190         u8         reserved_at_2a0[0x20];
4191
4192         u8         implied_nak_seq_err[0x20];
4193
4194         u8         reserved_at_2e0[0x20];
4195
4196         u8         local_ack_timeout_err[0x20];
4197
4198         u8         reserved_at_320[0xa0];
4199
4200         u8         resp_local_length_error[0x20];
4201
4202         u8         req_local_length_error[0x20];
4203
4204         u8         resp_local_qp_error[0x20];
4205
4206         u8         local_operation_error[0x20];
4207
4208         u8         resp_local_protection[0x20];
4209
4210         u8         req_local_protection[0x20];
4211
4212         u8         resp_cqe_error[0x20];
4213
4214         u8         req_cqe_error[0x20];
4215
4216         u8         req_mw_binding[0x20];
4217
4218         u8         req_bad_response[0x20];
4219
4220         u8         req_remote_invalid_request[0x20];
4221
4222         u8         resp_remote_invalid_request[0x20];
4223
4224         u8         req_remote_access_errors[0x20];
4225
4226         u8         resp_remote_access_errors[0x20];
4227
4228         u8         req_remote_operation_errors[0x20];
4229
4230         u8         req_transport_retries_exceeded[0x20];
4231
4232         u8         cq_overflow[0x20];
4233
4234         u8         resp_cqe_flush_error[0x20];
4235
4236         u8         req_cqe_flush_error[0x20];
4237
4238         u8         reserved_at_620[0x1e0];
4239 };
4240
4241 struct mlx5_ifc_query_q_counter_in_bits {
4242         u8         opcode[0x10];
4243         u8         reserved_at_10[0x10];
4244
4245         u8         reserved_at_20[0x10];
4246         u8         op_mod[0x10];
4247
4248         u8         reserved_at_40[0x80];
4249
4250         u8         clear[0x1];
4251         u8         reserved_at_c1[0x1f];
4252
4253         u8         reserved_at_e0[0x18];
4254         u8         counter_set_id[0x8];
4255 };
4256
4257 struct mlx5_ifc_query_pages_out_bits {
4258         u8         status[0x8];
4259         u8         reserved_at_8[0x18];
4260
4261         u8         syndrome[0x20];
4262
4263         u8         reserved_at_40[0x10];
4264         u8         function_id[0x10];
4265
4266         u8         num_pages[0x20];
4267 };
4268
4269 enum {
4270         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4271         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4272         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4273 };
4274
4275 struct mlx5_ifc_query_pages_in_bits {
4276         u8         opcode[0x10];
4277         u8         reserved_at_10[0x10];
4278
4279         u8         reserved_at_20[0x10];
4280         u8         op_mod[0x10];
4281
4282         u8         reserved_at_40[0x10];
4283         u8         function_id[0x10];
4284
4285         u8         reserved_at_60[0x20];
4286 };
4287
4288 struct mlx5_ifc_query_nic_vport_context_out_bits {
4289         u8         status[0x8];
4290         u8         reserved_at_8[0x18];
4291
4292         u8         syndrome[0x20];
4293
4294         u8         reserved_at_40[0x40];
4295
4296         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4297 };
4298
4299 struct mlx5_ifc_query_nic_vport_context_in_bits {
4300         u8         opcode[0x10];
4301         u8         reserved_at_10[0x10];
4302
4303         u8         reserved_at_20[0x10];
4304         u8         op_mod[0x10];
4305
4306         u8         other_vport[0x1];
4307         u8         reserved_at_41[0xf];
4308         u8         vport_number[0x10];
4309
4310         u8         reserved_at_60[0x5];
4311         u8         allowed_list_type[0x3];
4312         u8         reserved_at_68[0x18];
4313 };
4314
4315 struct mlx5_ifc_query_mkey_out_bits {
4316         u8         status[0x8];
4317         u8         reserved_at_8[0x18];
4318
4319         u8         syndrome[0x20];
4320
4321         u8         reserved_at_40[0x40];
4322
4323         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4324
4325         u8         reserved_at_280[0x600];
4326
4327         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4328
4329         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4330 };
4331
4332 struct mlx5_ifc_query_mkey_in_bits {
4333         u8         opcode[0x10];
4334         u8         reserved_at_10[0x10];
4335
4336         u8         reserved_at_20[0x10];
4337         u8         op_mod[0x10];
4338
4339         u8         reserved_at_40[0x8];
4340         u8         mkey_index[0x18];
4341
4342         u8         pg_access[0x1];
4343         u8         reserved_at_61[0x1f];
4344 };
4345
4346 struct mlx5_ifc_query_mad_demux_out_bits {
4347         u8         status[0x8];
4348         u8         reserved_at_8[0x18];
4349
4350         u8         syndrome[0x20];
4351
4352         u8         reserved_at_40[0x40];
4353
4354         u8         mad_dumux_parameters_block[0x20];
4355 };
4356
4357 struct mlx5_ifc_query_mad_demux_in_bits {
4358         u8         opcode[0x10];
4359         u8         reserved_at_10[0x10];
4360
4361         u8         reserved_at_20[0x10];
4362         u8         op_mod[0x10];
4363
4364         u8         reserved_at_40[0x40];
4365 };
4366
4367 struct mlx5_ifc_query_l2_table_entry_out_bits {
4368         u8         status[0x8];
4369         u8         reserved_at_8[0x18];
4370
4371         u8         syndrome[0x20];
4372
4373         u8         reserved_at_40[0xa0];
4374
4375         u8         reserved_at_e0[0x13];
4376         u8         vlan_valid[0x1];
4377         u8         vlan[0xc];
4378
4379         struct mlx5_ifc_mac_address_layout_bits mac_address;
4380
4381         u8         reserved_at_140[0xc0];
4382 };
4383
4384 struct mlx5_ifc_query_l2_table_entry_in_bits {
4385         u8         opcode[0x10];
4386         u8         reserved_at_10[0x10];
4387
4388         u8         reserved_at_20[0x10];
4389         u8         op_mod[0x10];
4390
4391         u8         reserved_at_40[0x60];
4392
4393         u8         reserved_at_a0[0x8];
4394         u8         table_index[0x18];
4395
4396         u8         reserved_at_c0[0x140];
4397 };
4398
4399 struct mlx5_ifc_query_issi_out_bits {
4400         u8         status[0x8];
4401         u8         reserved_at_8[0x18];
4402
4403         u8         syndrome[0x20];
4404
4405         u8         reserved_at_40[0x10];
4406         u8         current_issi[0x10];
4407
4408         u8         reserved_at_60[0xa0];
4409
4410         u8         reserved_at_100[76][0x8];
4411         u8         supported_issi_dw0[0x20];
4412 };
4413
4414 struct mlx5_ifc_query_issi_in_bits {
4415         u8         opcode[0x10];
4416         u8         reserved_at_10[0x10];
4417
4418         u8         reserved_at_20[0x10];
4419         u8         op_mod[0x10];
4420
4421         u8         reserved_at_40[0x40];
4422 };
4423
4424 struct mlx5_ifc_set_driver_version_out_bits {
4425         u8         status[0x8];
4426         u8         reserved_0[0x18];
4427
4428         u8         syndrome[0x20];
4429         u8         reserved_1[0x40];
4430 };
4431
4432 struct mlx5_ifc_set_driver_version_in_bits {
4433         u8         opcode[0x10];
4434         u8         reserved_0[0x10];
4435
4436         u8         reserved_1[0x10];
4437         u8         op_mod[0x10];
4438
4439         u8         reserved_2[0x40];
4440         u8         driver_version[64][0x8];
4441 };
4442
4443 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4444         u8         status[0x8];
4445         u8         reserved_at_8[0x18];
4446
4447         u8         syndrome[0x20];
4448
4449         u8         reserved_at_40[0x40];
4450
4451         struct mlx5_ifc_pkey_bits pkey[0];
4452 };
4453
4454 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4455         u8         opcode[0x10];
4456         u8         reserved_at_10[0x10];
4457
4458         u8         reserved_at_20[0x10];
4459         u8         op_mod[0x10];
4460
4461         u8         other_vport[0x1];
4462         u8         reserved_at_41[0xb];
4463         u8         port_num[0x4];
4464         u8         vport_number[0x10];
4465
4466         u8         reserved_at_60[0x10];
4467         u8         pkey_index[0x10];
4468 };
4469
4470 enum {
4471         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4472         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4473         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4474 };
4475
4476 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4477         u8         status[0x8];
4478         u8         reserved_at_8[0x18];
4479
4480         u8         syndrome[0x20];
4481
4482         u8         reserved_at_40[0x20];
4483
4484         u8         gids_num[0x10];
4485         u8         reserved_at_70[0x10];
4486
4487         struct mlx5_ifc_array128_auto_bits gid[0];
4488 };
4489
4490 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4491         u8         opcode[0x10];
4492         u8         reserved_at_10[0x10];
4493
4494         u8         reserved_at_20[0x10];
4495         u8         op_mod[0x10];
4496
4497         u8         other_vport[0x1];
4498         u8         reserved_at_41[0xb];
4499         u8         port_num[0x4];
4500         u8         vport_number[0x10];
4501
4502         u8         reserved_at_60[0x10];
4503         u8         gid_index[0x10];
4504 };
4505
4506 struct mlx5_ifc_query_hca_vport_context_out_bits {
4507         u8         status[0x8];
4508         u8         reserved_at_8[0x18];
4509
4510         u8         syndrome[0x20];
4511
4512         u8         reserved_at_40[0x40];
4513
4514         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4515 };
4516
4517 struct mlx5_ifc_query_hca_vport_context_in_bits {
4518         u8         opcode[0x10];
4519         u8         reserved_at_10[0x10];
4520
4521         u8         reserved_at_20[0x10];
4522         u8         op_mod[0x10];
4523
4524         u8         other_vport[0x1];
4525         u8         reserved_at_41[0xb];
4526         u8         port_num[0x4];
4527         u8         vport_number[0x10];
4528
4529         u8         reserved_at_60[0x20];
4530 };
4531
4532 struct mlx5_ifc_query_hca_cap_out_bits {
4533         u8         status[0x8];
4534         u8         reserved_at_8[0x18];
4535
4536         u8         syndrome[0x20];
4537
4538         u8         reserved_at_40[0x40];
4539
4540         union mlx5_ifc_hca_cap_union_bits capability;
4541 };
4542
4543 struct mlx5_ifc_query_hca_cap_in_bits {
4544         u8         opcode[0x10];
4545         u8         reserved_at_10[0x10];
4546
4547         u8         reserved_at_20[0x10];
4548         u8         op_mod[0x10];
4549
4550         u8         reserved_at_40[0x40];
4551 };
4552
4553 struct mlx5_ifc_query_flow_table_out_bits {
4554         u8         status[0x8];
4555         u8         reserved_at_8[0x18];
4556
4557         u8         syndrome[0x20];
4558
4559         u8         reserved_at_40[0x80];
4560
4561         u8         reserved_at_c0[0x8];
4562         u8         level[0x8];
4563         u8         reserved_at_d0[0x8];
4564         u8         log_size[0x8];
4565
4566         u8         reserved_at_e0[0x120];
4567 };
4568
4569 struct mlx5_ifc_query_flow_table_in_bits {
4570         u8         opcode[0x10];
4571         u8         reserved_at_10[0x10];
4572
4573         u8         reserved_at_20[0x10];
4574         u8         op_mod[0x10];
4575
4576         u8         reserved_at_40[0x40];
4577
4578         u8         table_type[0x8];
4579         u8         reserved_at_88[0x18];
4580
4581         u8         reserved_at_a0[0x8];
4582         u8         table_id[0x18];
4583
4584         u8         reserved_at_c0[0x140];
4585 };
4586
4587 struct mlx5_ifc_query_fte_out_bits {
4588         u8         status[0x8];
4589         u8         reserved_at_8[0x18];
4590
4591         u8         syndrome[0x20];
4592
4593         u8         reserved_at_40[0x1c0];
4594
4595         struct mlx5_ifc_flow_context_bits flow_context;
4596 };
4597
4598 struct mlx5_ifc_query_fte_in_bits {
4599         u8         opcode[0x10];
4600         u8         reserved_at_10[0x10];
4601
4602         u8         reserved_at_20[0x10];
4603         u8         op_mod[0x10];
4604
4605         u8         reserved_at_40[0x40];
4606
4607         u8         table_type[0x8];
4608         u8         reserved_at_88[0x18];
4609
4610         u8         reserved_at_a0[0x8];
4611         u8         table_id[0x18];
4612
4613         u8         reserved_at_c0[0x40];
4614
4615         u8         flow_index[0x20];
4616
4617         u8         reserved_at_120[0xe0];
4618 };
4619
4620 enum {
4621         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4622         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4623         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4624         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0X3,
4625 };
4626
4627 struct mlx5_ifc_query_flow_group_out_bits {
4628         u8         status[0x8];
4629         u8         reserved_at_8[0x18];
4630
4631         u8         syndrome[0x20];
4632
4633         u8         reserved_at_40[0xa0];
4634
4635         u8         start_flow_index[0x20];
4636
4637         u8         reserved_at_100[0x20];
4638
4639         u8         end_flow_index[0x20];
4640
4641         u8         reserved_at_140[0xa0];
4642
4643         u8         reserved_at_1e0[0x18];
4644         u8         match_criteria_enable[0x8];
4645
4646         struct mlx5_ifc_fte_match_param_bits match_criteria;
4647
4648         u8         reserved_at_1200[0xe00];
4649 };
4650
4651 struct mlx5_ifc_query_flow_group_in_bits {
4652         u8         opcode[0x10];
4653         u8         reserved_at_10[0x10];
4654
4655         u8         reserved_at_20[0x10];
4656         u8         op_mod[0x10];
4657
4658         u8         reserved_at_40[0x40];
4659
4660         u8         table_type[0x8];
4661         u8         reserved_at_88[0x18];
4662
4663         u8         reserved_at_a0[0x8];
4664         u8         table_id[0x18];
4665
4666         u8         group_id[0x20];
4667
4668         u8         reserved_at_e0[0x120];
4669 };
4670
4671 struct mlx5_ifc_query_flow_counter_out_bits {
4672         u8         status[0x8];
4673         u8         reserved_at_8[0x18];
4674
4675         u8         syndrome[0x20];
4676
4677         u8         reserved_at_40[0x40];
4678
4679         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4680 };
4681
4682 struct mlx5_ifc_query_flow_counter_in_bits {
4683         u8         opcode[0x10];
4684         u8         reserved_at_10[0x10];
4685
4686         u8         reserved_at_20[0x10];
4687         u8         op_mod[0x10];
4688
4689         u8         reserved_at_40[0x80];
4690
4691         u8         clear[0x1];
4692         u8         reserved_at_c1[0xf];
4693         u8         num_of_counters[0x10];
4694
4695         u8         flow_counter_id[0x20];
4696 };
4697
4698 struct mlx5_ifc_query_esw_vport_context_out_bits {
4699         u8         status[0x8];
4700         u8         reserved_at_8[0x18];
4701
4702         u8         syndrome[0x20];
4703
4704         u8         reserved_at_40[0x40];
4705
4706         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4707 };
4708
4709 struct mlx5_ifc_query_esw_vport_context_in_bits {
4710         u8         opcode[0x10];
4711         u8         reserved_at_10[0x10];
4712
4713         u8         reserved_at_20[0x10];
4714         u8         op_mod[0x10];
4715
4716         u8         other_vport[0x1];
4717         u8         reserved_at_41[0xf];
4718         u8         vport_number[0x10];
4719
4720         u8         reserved_at_60[0x20];
4721 };
4722
4723 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4724         u8         status[0x8];
4725         u8         reserved_at_8[0x18];
4726
4727         u8         syndrome[0x20];
4728
4729         u8         reserved_at_40[0x40];
4730 };
4731
4732 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4733         u8         reserved_at_0[0x1c];
4734         u8         vport_cvlan_insert[0x1];
4735         u8         vport_svlan_insert[0x1];
4736         u8         vport_cvlan_strip[0x1];
4737         u8         vport_svlan_strip[0x1];
4738 };
4739
4740 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4741         u8         opcode[0x10];
4742         u8         reserved_at_10[0x10];
4743
4744         u8         reserved_at_20[0x10];
4745         u8         op_mod[0x10];
4746
4747         u8         other_vport[0x1];
4748         u8         reserved_at_41[0xf];
4749         u8         vport_number[0x10];
4750
4751         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4752
4753         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4754 };
4755
4756 struct mlx5_ifc_query_eq_out_bits {
4757         u8         status[0x8];
4758         u8         reserved_at_8[0x18];
4759
4760         u8         syndrome[0x20];
4761
4762         u8         reserved_at_40[0x40];
4763
4764         struct mlx5_ifc_eqc_bits eq_context_entry;
4765
4766         u8         reserved_at_280[0x40];
4767
4768         u8         event_bitmask[0x40];
4769
4770         u8         reserved_at_300[0x580];
4771
4772         u8         pas[0][0x40];
4773 };
4774
4775 struct mlx5_ifc_query_eq_in_bits {
4776         u8         opcode[0x10];
4777         u8         reserved_at_10[0x10];
4778
4779         u8         reserved_at_20[0x10];
4780         u8         op_mod[0x10];
4781
4782         u8         reserved_at_40[0x18];
4783         u8         eq_number[0x8];
4784
4785         u8         reserved_at_60[0x20];
4786 };
4787
4788 struct mlx5_ifc_encap_header_in_bits {
4789         u8         reserved_at_0[0x5];
4790         u8         header_type[0x3];
4791         u8         reserved_at_8[0xe];
4792         u8         encap_header_size[0xa];
4793
4794         u8         reserved_at_20[0x10];
4795         u8         encap_header[2][0x8];
4796
4797         u8         more_encap_header[0][0x8];
4798 };
4799
4800 struct mlx5_ifc_query_encap_header_out_bits {
4801         u8         status[0x8];
4802         u8         reserved_at_8[0x18];
4803
4804         u8         syndrome[0x20];
4805
4806         u8         reserved_at_40[0xa0];
4807
4808         struct mlx5_ifc_encap_header_in_bits encap_header[0];
4809 };
4810
4811 struct mlx5_ifc_query_encap_header_in_bits {
4812         u8         opcode[0x10];
4813         u8         reserved_at_10[0x10];
4814
4815         u8         reserved_at_20[0x10];
4816         u8         op_mod[0x10];
4817
4818         u8         encap_id[0x20];
4819
4820         u8         reserved_at_60[0xa0];
4821 };
4822
4823 struct mlx5_ifc_alloc_encap_header_out_bits {
4824         u8         status[0x8];
4825         u8         reserved_at_8[0x18];
4826
4827         u8         syndrome[0x20];
4828
4829         u8         encap_id[0x20];
4830
4831         u8         reserved_at_60[0x20];
4832 };
4833
4834 struct mlx5_ifc_alloc_encap_header_in_bits {
4835         u8         opcode[0x10];
4836         u8         reserved_at_10[0x10];
4837
4838         u8         reserved_at_20[0x10];
4839         u8         op_mod[0x10];
4840
4841         u8         reserved_at_40[0xa0];
4842
4843         struct mlx5_ifc_encap_header_in_bits encap_header;
4844 };
4845
4846 struct mlx5_ifc_dealloc_encap_header_out_bits {
4847         u8         status[0x8];
4848         u8         reserved_at_8[0x18];
4849
4850         u8         syndrome[0x20];
4851
4852         u8         reserved_at_40[0x40];
4853 };
4854
4855 struct mlx5_ifc_dealloc_encap_header_in_bits {
4856         u8         opcode[0x10];
4857         u8         reserved_at_10[0x10];
4858
4859         u8         reserved_20[0x10];
4860         u8         op_mod[0x10];
4861
4862         u8         encap_id[0x20];
4863
4864         u8         reserved_60[0x20];
4865 };
4866
4867 struct mlx5_ifc_set_action_in_bits {
4868         u8         action_type[0x4];
4869         u8         field[0xc];
4870         u8         reserved_at_10[0x3];
4871         u8         offset[0x5];
4872         u8         reserved_at_18[0x3];
4873         u8         length[0x5];
4874
4875         u8         data[0x20];
4876 };
4877
4878 struct mlx5_ifc_add_action_in_bits {
4879         u8         action_type[0x4];
4880         u8         field[0xc];
4881         u8         reserved_at_10[0x10];
4882
4883         u8         data[0x20];
4884 };
4885
4886 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4887         struct mlx5_ifc_set_action_in_bits set_action_in;
4888         struct mlx5_ifc_add_action_in_bits add_action_in;
4889         u8         reserved_at_0[0x40];
4890 };
4891
4892 enum {
4893         MLX5_ACTION_TYPE_SET   = 0x1,
4894         MLX5_ACTION_TYPE_ADD   = 0x2,
4895 };
4896
4897 enum {
4898         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
4899         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
4900         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
4901         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
4902         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
4903         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
4904         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
4905         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
4906         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
4907         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
4908         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
4909         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
4910         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
4911         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
4912         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
4913         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
4914         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
4915         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
4916         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
4917         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
4918         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
4919         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
4920         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4921 };
4922
4923 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4924         u8         status[0x8];
4925         u8         reserved_at_8[0x18];
4926
4927         u8         syndrome[0x20];
4928
4929         u8         modify_header_id[0x20];
4930
4931         u8         reserved_at_60[0x20];
4932 };
4933
4934 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4935         u8         opcode[0x10];
4936         u8         reserved_at_10[0x10];
4937
4938         u8         reserved_at_20[0x10];
4939         u8         op_mod[0x10];
4940
4941         u8         reserved_at_40[0x20];
4942
4943         u8         table_type[0x8];
4944         u8         reserved_at_68[0x10];
4945         u8         num_of_actions[0x8];
4946
4947         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4948 };
4949
4950 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4951         u8         status[0x8];
4952         u8         reserved_at_8[0x18];
4953
4954         u8         syndrome[0x20];
4955
4956         u8         reserved_at_40[0x40];
4957 };
4958
4959 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4960         u8         opcode[0x10];
4961         u8         reserved_at_10[0x10];
4962
4963         u8         reserved_at_20[0x10];
4964         u8         op_mod[0x10];
4965
4966         u8         modify_header_id[0x20];
4967
4968         u8         reserved_at_60[0x20];
4969 };
4970
4971 struct mlx5_ifc_query_dct_out_bits {
4972         u8         status[0x8];
4973         u8         reserved_at_8[0x18];
4974
4975         u8         syndrome[0x20];
4976
4977         u8         reserved_at_40[0x40];
4978
4979         struct mlx5_ifc_dctc_bits dct_context_entry;
4980
4981         u8         reserved_at_280[0x180];
4982 };
4983
4984 struct mlx5_ifc_query_dct_in_bits {
4985         u8         opcode[0x10];
4986         u8         reserved_at_10[0x10];
4987
4988         u8         reserved_at_20[0x10];
4989         u8         op_mod[0x10];
4990
4991         u8         reserved_at_40[0x8];
4992         u8         dctn[0x18];
4993
4994         u8         reserved_at_60[0x20];
4995 };
4996
4997 struct mlx5_ifc_query_cq_out_bits {
4998         u8         status[0x8];
4999         u8         reserved_at_8[0x18];
5000
5001         u8         syndrome[0x20];
5002
5003         u8         reserved_at_40[0x40];
5004
5005         struct mlx5_ifc_cqc_bits cq_context;
5006
5007         u8         reserved_at_280[0x600];
5008
5009         u8         pas[0][0x40];
5010 };
5011
5012 struct mlx5_ifc_query_cq_in_bits {
5013         u8         opcode[0x10];
5014         u8         reserved_at_10[0x10];
5015
5016         u8         reserved_at_20[0x10];
5017         u8         op_mod[0x10];
5018
5019         u8         reserved_at_40[0x8];
5020         u8         cqn[0x18];
5021
5022         u8         reserved_at_60[0x20];
5023 };
5024
5025 struct mlx5_ifc_query_cong_status_out_bits {
5026         u8         status[0x8];
5027         u8         reserved_at_8[0x18];
5028
5029         u8         syndrome[0x20];
5030
5031         u8         reserved_at_40[0x20];
5032
5033         u8         enable[0x1];
5034         u8         tag_enable[0x1];
5035         u8         reserved_at_62[0x1e];
5036 };
5037
5038 struct mlx5_ifc_query_cong_status_in_bits {
5039         u8         opcode[0x10];
5040         u8         reserved_at_10[0x10];
5041
5042         u8         reserved_at_20[0x10];
5043         u8         op_mod[0x10];
5044
5045         u8         reserved_at_40[0x18];
5046         u8         priority[0x4];
5047         u8         cong_protocol[0x4];
5048
5049         u8         reserved_at_60[0x20];
5050 };
5051
5052 struct mlx5_ifc_query_cong_statistics_out_bits {
5053         u8         status[0x8];
5054         u8         reserved_at_8[0x18];
5055
5056         u8         syndrome[0x20];
5057
5058         u8         reserved_at_40[0x40];
5059
5060         u8         rp_cur_flows[0x20];
5061
5062         u8         sum_flows[0x20];
5063
5064         u8         rp_cnp_ignored_high[0x20];
5065
5066         u8         rp_cnp_ignored_low[0x20];
5067
5068         u8         rp_cnp_handled_high[0x20];
5069
5070         u8         rp_cnp_handled_low[0x20];
5071
5072         u8         reserved_at_140[0x100];
5073
5074         u8         time_stamp_high[0x20];
5075
5076         u8         time_stamp_low[0x20];
5077
5078         u8         accumulators_period[0x20];
5079
5080         u8         np_ecn_marked_roce_packets_high[0x20];
5081
5082         u8         np_ecn_marked_roce_packets_low[0x20];
5083
5084         u8         np_cnp_sent_high[0x20];
5085
5086         u8         np_cnp_sent_low[0x20];
5087
5088         u8         reserved_at_320[0x560];
5089 };
5090
5091 struct mlx5_ifc_query_cong_statistics_in_bits {
5092         u8         opcode[0x10];
5093         u8         reserved_at_10[0x10];
5094
5095         u8         reserved_at_20[0x10];
5096         u8         op_mod[0x10];
5097
5098         u8         clear[0x1];
5099         u8         reserved_at_41[0x1f];
5100
5101         u8         reserved_at_60[0x20];
5102 };
5103
5104 struct mlx5_ifc_query_cong_params_out_bits {
5105         u8         status[0x8];
5106         u8         reserved_at_8[0x18];
5107
5108         u8         syndrome[0x20];
5109
5110         u8         reserved_at_40[0x40];
5111
5112         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5113 };
5114
5115 struct mlx5_ifc_query_cong_params_in_bits {
5116         u8         opcode[0x10];
5117         u8         reserved_at_10[0x10];
5118
5119         u8         reserved_at_20[0x10];
5120         u8         op_mod[0x10];
5121
5122         u8         reserved_at_40[0x1c];
5123         u8         cong_protocol[0x4];
5124
5125         u8         reserved_at_60[0x20];
5126 };
5127
5128 struct mlx5_ifc_query_adapter_out_bits {
5129         u8         status[0x8];
5130         u8         reserved_at_8[0x18];
5131
5132         u8         syndrome[0x20];
5133
5134         u8         reserved_at_40[0x40];
5135
5136         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5137 };
5138
5139 struct mlx5_ifc_query_adapter_in_bits {
5140         u8         opcode[0x10];
5141         u8         reserved_at_10[0x10];
5142
5143         u8         reserved_at_20[0x10];
5144         u8         op_mod[0x10];
5145
5146         u8         reserved_at_40[0x40];
5147 };
5148
5149 struct mlx5_ifc_qp_2rst_out_bits {
5150         u8         status[0x8];
5151         u8         reserved_at_8[0x18];
5152
5153         u8         syndrome[0x20];
5154
5155         u8         reserved_at_40[0x40];
5156 };
5157
5158 struct mlx5_ifc_qp_2rst_in_bits {
5159         u8         opcode[0x10];
5160         u8         reserved_at_10[0x10];
5161
5162         u8         reserved_at_20[0x10];
5163         u8         op_mod[0x10];
5164
5165         u8         reserved_at_40[0x8];
5166         u8         qpn[0x18];
5167
5168         u8         reserved_at_60[0x20];
5169 };
5170
5171 struct mlx5_ifc_qp_2err_out_bits {
5172         u8         status[0x8];
5173         u8         reserved_at_8[0x18];
5174
5175         u8         syndrome[0x20];
5176
5177         u8         reserved_at_40[0x40];
5178 };
5179
5180 struct mlx5_ifc_qp_2err_in_bits {
5181         u8         opcode[0x10];
5182         u8         reserved_at_10[0x10];
5183
5184         u8         reserved_at_20[0x10];
5185         u8         op_mod[0x10];
5186
5187         u8         reserved_at_40[0x8];
5188         u8         qpn[0x18];
5189
5190         u8         reserved_at_60[0x20];
5191 };
5192
5193 struct mlx5_ifc_page_fault_resume_out_bits {
5194         u8         status[0x8];
5195         u8         reserved_at_8[0x18];
5196
5197         u8         syndrome[0x20];
5198
5199         u8         reserved_at_40[0x40];
5200 };
5201
5202 struct mlx5_ifc_page_fault_resume_in_bits {
5203         u8         opcode[0x10];
5204         u8         reserved_at_10[0x10];
5205
5206         u8         reserved_at_20[0x10];
5207         u8         op_mod[0x10];
5208
5209         u8         error[0x1];
5210         u8         reserved_at_41[0x4];
5211         u8         page_fault_type[0x3];
5212         u8         wq_number[0x18];
5213
5214         u8         reserved_at_60[0x8];
5215         u8         token[0x18];
5216 };
5217
5218 struct mlx5_ifc_nop_out_bits {
5219         u8         status[0x8];
5220         u8         reserved_at_8[0x18];
5221
5222         u8         syndrome[0x20];
5223
5224         u8         reserved_at_40[0x40];
5225 };
5226
5227 struct mlx5_ifc_nop_in_bits {
5228         u8         opcode[0x10];
5229         u8         reserved_at_10[0x10];
5230
5231         u8         reserved_at_20[0x10];
5232         u8         op_mod[0x10];
5233
5234         u8         reserved_at_40[0x40];
5235 };
5236
5237 struct mlx5_ifc_modify_vport_state_out_bits {
5238         u8         status[0x8];
5239         u8         reserved_at_8[0x18];
5240
5241         u8         syndrome[0x20];
5242
5243         u8         reserved_at_40[0x40];
5244 };
5245
5246 struct mlx5_ifc_modify_vport_state_in_bits {
5247         u8         opcode[0x10];
5248         u8         reserved_at_10[0x10];
5249
5250         u8         reserved_at_20[0x10];
5251         u8         op_mod[0x10];
5252
5253         u8         other_vport[0x1];
5254         u8         reserved_at_41[0xf];
5255         u8         vport_number[0x10];
5256
5257         u8         reserved_at_60[0x18];
5258         u8         admin_state[0x4];
5259         u8         reserved_at_7c[0x4];
5260 };
5261
5262 struct mlx5_ifc_modify_tis_out_bits {
5263         u8         status[0x8];
5264         u8         reserved_at_8[0x18];
5265
5266         u8         syndrome[0x20];
5267
5268         u8         reserved_at_40[0x40];
5269 };
5270
5271 struct mlx5_ifc_modify_tis_bitmask_bits {
5272         u8         reserved_at_0[0x20];
5273
5274         u8         reserved_at_20[0x1d];
5275         u8         lag_tx_port_affinity[0x1];
5276         u8         strict_lag_tx_port_affinity[0x1];
5277         u8         prio[0x1];
5278 };
5279
5280 struct mlx5_ifc_modify_tis_in_bits {
5281         u8         opcode[0x10];
5282         u8         reserved_at_10[0x10];
5283
5284         u8         reserved_at_20[0x10];
5285         u8         op_mod[0x10];
5286
5287         u8         reserved_at_40[0x8];
5288         u8         tisn[0x18];
5289
5290         u8         reserved_at_60[0x20];
5291
5292         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5293
5294         u8         reserved_at_c0[0x40];
5295
5296         struct mlx5_ifc_tisc_bits ctx;
5297 };
5298
5299 struct mlx5_ifc_modify_tir_bitmask_bits {
5300         u8         reserved_at_0[0x20];
5301
5302         u8         reserved_at_20[0x1b];
5303         u8         self_lb_en[0x1];
5304         u8         reserved_at_3c[0x1];
5305         u8         hash[0x1];
5306         u8         reserved_at_3e[0x1];
5307         u8         lro[0x1];
5308 };
5309
5310 struct mlx5_ifc_modify_tir_out_bits {
5311         u8         status[0x8];
5312         u8         reserved_at_8[0x18];
5313
5314         u8         syndrome[0x20];
5315
5316         u8         reserved_at_40[0x40];
5317 };
5318
5319 struct mlx5_ifc_modify_tir_in_bits {
5320         u8         opcode[0x10];
5321         u8         reserved_at_10[0x10];
5322
5323         u8         reserved_at_20[0x10];
5324         u8         op_mod[0x10];
5325
5326         u8         reserved_at_40[0x8];
5327         u8         tirn[0x18];
5328
5329         u8         reserved_at_60[0x20];
5330
5331         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5332
5333         u8         reserved_at_c0[0x40];
5334
5335         struct mlx5_ifc_tirc_bits ctx;
5336 };
5337
5338 struct mlx5_ifc_modify_sq_out_bits {
5339         u8         status[0x8];
5340         u8         reserved_at_8[0x18];
5341
5342         u8         syndrome[0x20];
5343
5344         u8         reserved_at_40[0x40];
5345 };
5346
5347 struct mlx5_ifc_modify_sq_in_bits {
5348         u8         opcode[0x10];
5349         u8         reserved_at_10[0x10];
5350
5351         u8         reserved_at_20[0x10];
5352         u8         op_mod[0x10];
5353
5354         u8         sq_state[0x4];
5355         u8         reserved_at_44[0x4];
5356         u8         sqn[0x18];
5357
5358         u8         reserved_at_60[0x20];
5359
5360         u8         modify_bitmask[0x40];
5361
5362         u8         reserved_at_c0[0x40];
5363
5364         struct mlx5_ifc_sqc_bits ctx;
5365 };
5366
5367 struct mlx5_ifc_modify_scheduling_element_out_bits {
5368         u8         status[0x8];
5369         u8         reserved_at_8[0x18];
5370
5371         u8         syndrome[0x20];
5372
5373         u8         reserved_at_40[0x1c0];
5374 };
5375
5376 enum {
5377         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5378         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5379 };
5380
5381 struct mlx5_ifc_modify_scheduling_element_in_bits {
5382         u8         opcode[0x10];
5383         u8         reserved_at_10[0x10];
5384
5385         u8         reserved_at_20[0x10];
5386         u8         op_mod[0x10];
5387
5388         u8         scheduling_hierarchy[0x8];
5389         u8         reserved_at_48[0x18];
5390
5391         u8         scheduling_element_id[0x20];
5392
5393         u8         reserved_at_80[0x20];
5394
5395         u8         modify_bitmask[0x20];
5396
5397         u8         reserved_at_c0[0x40];
5398
5399         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5400
5401         u8         reserved_at_300[0x100];
5402 };
5403
5404 struct mlx5_ifc_modify_rqt_out_bits {
5405         u8         status[0x8];
5406         u8         reserved_at_8[0x18];
5407
5408         u8         syndrome[0x20];
5409
5410         u8         reserved_at_40[0x40];
5411 };
5412
5413 struct mlx5_ifc_rqt_bitmask_bits {
5414         u8         reserved_at_0[0x20];
5415
5416         u8         reserved_at_20[0x1f];
5417         u8         rqn_list[0x1];
5418 };
5419
5420 struct mlx5_ifc_modify_rqt_in_bits {
5421         u8         opcode[0x10];
5422         u8         reserved_at_10[0x10];
5423
5424         u8         reserved_at_20[0x10];
5425         u8         op_mod[0x10];
5426
5427         u8         reserved_at_40[0x8];
5428         u8         rqtn[0x18];
5429
5430         u8         reserved_at_60[0x20];
5431
5432         struct mlx5_ifc_rqt_bitmask_bits bitmask;
5433
5434         u8         reserved_at_c0[0x40];
5435
5436         struct mlx5_ifc_rqtc_bits ctx;
5437 };
5438
5439 struct mlx5_ifc_modify_rq_out_bits {
5440         u8         status[0x8];
5441         u8         reserved_at_8[0x18];
5442
5443         u8         syndrome[0x20];
5444
5445         u8         reserved_at_40[0x40];
5446 };
5447
5448 enum {
5449         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5450         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5451         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5452 };
5453
5454 struct mlx5_ifc_modify_rq_in_bits {
5455         u8         opcode[0x10];
5456         u8         reserved_at_10[0x10];
5457
5458         u8         reserved_at_20[0x10];
5459         u8         op_mod[0x10];
5460
5461         u8         rq_state[0x4];
5462         u8         reserved_at_44[0x4];
5463         u8         rqn[0x18];
5464
5465         u8         reserved_at_60[0x20];
5466
5467         u8         modify_bitmask[0x40];
5468
5469         u8         reserved_at_c0[0x40];
5470
5471         struct mlx5_ifc_rqc_bits ctx;
5472 };
5473
5474 struct mlx5_ifc_modify_rmp_out_bits {
5475         u8         status[0x8];
5476         u8         reserved_at_8[0x18];
5477
5478         u8         syndrome[0x20];
5479
5480         u8         reserved_at_40[0x40];
5481 };
5482
5483 struct mlx5_ifc_rmp_bitmask_bits {
5484         u8         reserved_at_0[0x20];
5485
5486         u8         reserved_at_20[0x1f];
5487         u8         lwm[0x1];
5488 };
5489
5490 struct mlx5_ifc_modify_rmp_in_bits {
5491         u8         opcode[0x10];
5492         u8         reserved_at_10[0x10];
5493
5494         u8         reserved_at_20[0x10];
5495         u8         op_mod[0x10];
5496
5497         u8         rmp_state[0x4];
5498         u8         reserved_at_44[0x4];
5499         u8         rmpn[0x18];
5500
5501         u8         reserved_at_60[0x20];
5502
5503         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5504
5505         u8         reserved_at_c0[0x40];
5506
5507         struct mlx5_ifc_rmpc_bits ctx;
5508 };
5509
5510 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5511         u8         status[0x8];
5512         u8         reserved_at_8[0x18];
5513
5514         u8         syndrome[0x20];
5515
5516         u8         reserved_at_40[0x40];
5517 };
5518
5519 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5520         u8         reserved_at_0[0x12];
5521         u8         affiliation[0x1];
5522         u8         reserved_at_e[0x1];
5523         u8         disable_uc_local_lb[0x1];
5524         u8         disable_mc_local_lb[0x1];
5525         u8         node_guid[0x1];
5526         u8         port_guid[0x1];
5527         u8         min_inline[0x1];
5528         u8         mtu[0x1];
5529         u8         change_event[0x1];
5530         u8         promisc[0x1];
5531         u8         permanent_address[0x1];
5532         u8         addresses_list[0x1];
5533         u8         roce_en[0x1];
5534         u8         reserved_at_1f[0x1];
5535 };
5536
5537 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5538         u8         opcode[0x10];
5539         u8         reserved_at_10[0x10];
5540
5541         u8         reserved_at_20[0x10];
5542         u8         op_mod[0x10];
5543
5544         u8         other_vport[0x1];
5545         u8         reserved_at_41[0xf];
5546         u8         vport_number[0x10];
5547
5548         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5549
5550         u8         reserved_at_80[0x780];
5551
5552         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5553 };
5554
5555 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5556         u8         status[0x8];
5557         u8         reserved_at_8[0x18];
5558
5559         u8         syndrome[0x20];
5560
5561         u8         reserved_at_40[0x40];
5562 };
5563
5564 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5565         u8         opcode[0x10];
5566         u8         reserved_at_10[0x10];
5567
5568         u8         reserved_at_20[0x10];
5569         u8         op_mod[0x10];
5570
5571         u8         other_vport[0x1];
5572         u8         reserved_at_41[0xb];
5573         u8         port_num[0x4];
5574         u8         vport_number[0x10];
5575
5576         u8         reserved_at_60[0x20];
5577
5578         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5579 };
5580
5581 struct mlx5_ifc_modify_cq_out_bits {
5582         u8         status[0x8];
5583         u8         reserved_at_8[0x18];
5584
5585         u8         syndrome[0x20];
5586
5587         u8         reserved_at_40[0x40];
5588 };
5589
5590 enum {
5591         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5592         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5593 };
5594
5595 struct mlx5_ifc_modify_cq_in_bits {
5596         u8         opcode[0x10];
5597         u8         reserved_at_10[0x10];
5598
5599         u8         reserved_at_20[0x10];
5600         u8         op_mod[0x10];
5601
5602         u8         reserved_at_40[0x8];
5603         u8         cqn[0x18];
5604
5605         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5606
5607         struct mlx5_ifc_cqc_bits cq_context;
5608
5609         u8         reserved_at_280[0x600];
5610
5611         u8         pas[0][0x40];
5612 };
5613
5614 struct mlx5_ifc_modify_cong_status_out_bits {
5615         u8         status[0x8];
5616         u8         reserved_at_8[0x18];
5617
5618         u8         syndrome[0x20];
5619
5620         u8         reserved_at_40[0x40];
5621 };
5622
5623 struct mlx5_ifc_modify_cong_status_in_bits {
5624         u8         opcode[0x10];
5625         u8         reserved_at_10[0x10];
5626
5627         u8         reserved_at_20[0x10];
5628         u8         op_mod[0x10];
5629
5630         u8         reserved_at_40[0x18];
5631         u8         priority[0x4];
5632         u8         cong_protocol[0x4];
5633
5634         u8         enable[0x1];
5635         u8         tag_enable[0x1];
5636         u8         reserved_at_62[0x1e];
5637 };
5638
5639 struct mlx5_ifc_modify_cong_params_out_bits {
5640         u8         status[0x8];
5641         u8         reserved_at_8[0x18];
5642
5643         u8         syndrome[0x20];
5644
5645         u8         reserved_at_40[0x40];
5646 };
5647
5648 struct mlx5_ifc_modify_cong_params_in_bits {
5649         u8         opcode[0x10];
5650         u8         reserved_at_10[0x10];
5651
5652         u8         reserved_at_20[0x10];
5653         u8         op_mod[0x10];
5654
5655         u8         reserved_at_40[0x1c];
5656         u8         cong_protocol[0x4];
5657
5658         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5659
5660         u8         reserved_at_80[0x80];
5661
5662         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5663 };
5664
5665 struct mlx5_ifc_manage_pages_out_bits {
5666         u8         status[0x8];
5667         u8         reserved_at_8[0x18];
5668
5669         u8         syndrome[0x20];
5670
5671         u8         output_num_entries[0x20];
5672
5673         u8         reserved_at_60[0x20];
5674
5675         u8         pas[0][0x40];
5676 };
5677
5678 enum {
5679         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5680         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5681         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5682 };
5683
5684 struct mlx5_ifc_manage_pages_in_bits {
5685         u8         opcode[0x10];
5686         u8         reserved_at_10[0x10];
5687
5688         u8         reserved_at_20[0x10];
5689         u8         op_mod[0x10];
5690
5691         u8         reserved_at_40[0x10];
5692         u8         function_id[0x10];
5693
5694         u8         input_num_entries[0x20];
5695
5696         u8         pas[0][0x40];
5697 };
5698
5699 struct mlx5_ifc_mad_ifc_out_bits {
5700         u8         status[0x8];
5701         u8         reserved_at_8[0x18];
5702
5703         u8         syndrome[0x20];
5704
5705         u8         reserved_at_40[0x40];
5706
5707         u8         response_mad_packet[256][0x8];
5708 };
5709
5710 struct mlx5_ifc_mad_ifc_in_bits {
5711         u8         opcode[0x10];
5712         u8         reserved_at_10[0x10];
5713
5714         u8         reserved_at_20[0x10];
5715         u8         op_mod[0x10];
5716
5717         u8         remote_lid[0x10];
5718         u8         reserved_at_50[0x8];
5719         u8         port[0x8];
5720
5721         u8         reserved_at_60[0x20];
5722
5723         u8         mad[256][0x8];
5724 };
5725
5726 struct mlx5_ifc_init_hca_out_bits {
5727         u8         status[0x8];
5728         u8         reserved_at_8[0x18];
5729
5730         u8         syndrome[0x20];
5731
5732         u8         reserved_at_40[0x40];
5733 };
5734
5735 struct mlx5_ifc_init_hca_in_bits {
5736         u8         opcode[0x10];
5737         u8         reserved_at_10[0x10];
5738
5739         u8         reserved_at_20[0x10];
5740         u8         op_mod[0x10];
5741
5742         u8         reserved_at_40[0x40];
5743         u8         sw_owner_id[4][0x20];
5744 };
5745
5746 struct mlx5_ifc_init2rtr_qp_out_bits {
5747         u8         status[0x8];
5748         u8         reserved_at_8[0x18];
5749
5750         u8         syndrome[0x20];
5751
5752         u8         reserved_at_40[0x40];
5753 };
5754
5755 struct mlx5_ifc_init2rtr_qp_in_bits {
5756         u8         opcode[0x10];
5757         u8         reserved_at_10[0x10];
5758
5759         u8         reserved_at_20[0x10];
5760         u8         op_mod[0x10];
5761
5762         u8         reserved_at_40[0x8];
5763         u8         qpn[0x18];
5764
5765         u8         reserved_at_60[0x20];
5766
5767         u8         opt_param_mask[0x20];
5768
5769         u8         reserved_at_a0[0x20];
5770
5771         struct mlx5_ifc_qpc_bits qpc;
5772
5773         u8         reserved_at_800[0x80];
5774 };
5775
5776 struct mlx5_ifc_init2init_qp_out_bits {
5777         u8         status[0x8];
5778         u8         reserved_at_8[0x18];
5779
5780         u8         syndrome[0x20];
5781
5782         u8         reserved_at_40[0x40];
5783 };
5784
5785 struct mlx5_ifc_init2init_qp_in_bits {
5786         u8         opcode[0x10];
5787         u8         reserved_at_10[0x10];
5788
5789         u8         reserved_at_20[0x10];
5790         u8         op_mod[0x10];
5791
5792         u8         reserved_at_40[0x8];
5793         u8         qpn[0x18];
5794
5795         u8         reserved_at_60[0x20];
5796
5797         u8         opt_param_mask[0x20];
5798
5799         u8         reserved_at_a0[0x20];
5800
5801         struct mlx5_ifc_qpc_bits qpc;
5802
5803         u8         reserved_at_800[0x80];
5804 };
5805
5806 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5807         u8         status[0x8];
5808         u8         reserved_at_8[0x18];
5809
5810         u8         syndrome[0x20];
5811
5812         u8         reserved_at_40[0x40];
5813
5814         u8         packet_headers_log[128][0x8];
5815
5816         u8         packet_syndrome[64][0x8];
5817 };
5818
5819 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5820         u8         opcode[0x10];
5821         u8         reserved_at_10[0x10];
5822
5823         u8         reserved_at_20[0x10];
5824         u8         op_mod[0x10];
5825
5826         u8         reserved_at_40[0x40];
5827 };
5828
5829 struct mlx5_ifc_gen_eqe_in_bits {
5830         u8         opcode[0x10];
5831         u8         reserved_at_10[0x10];
5832
5833         u8         reserved_at_20[0x10];
5834         u8         op_mod[0x10];
5835
5836         u8         reserved_at_40[0x18];
5837         u8         eq_number[0x8];
5838
5839         u8         reserved_at_60[0x20];
5840
5841         u8         eqe[64][0x8];
5842 };
5843
5844 struct mlx5_ifc_gen_eq_out_bits {
5845         u8         status[0x8];
5846         u8         reserved_at_8[0x18];
5847
5848         u8         syndrome[0x20];
5849
5850         u8         reserved_at_40[0x40];
5851 };
5852
5853 struct mlx5_ifc_enable_hca_out_bits {
5854         u8         status[0x8];
5855         u8         reserved_at_8[0x18];
5856
5857         u8         syndrome[0x20];
5858
5859         u8         reserved_at_40[0x20];
5860 };
5861
5862 struct mlx5_ifc_enable_hca_in_bits {
5863         u8         opcode[0x10];
5864         u8         reserved_at_10[0x10];
5865
5866         u8         reserved_at_20[0x10];
5867         u8         op_mod[0x10];
5868
5869         u8         reserved_at_40[0x10];
5870         u8         function_id[0x10];
5871
5872         u8         reserved_at_60[0x20];
5873 };
5874
5875 struct mlx5_ifc_drain_dct_out_bits {
5876         u8         status[0x8];
5877         u8         reserved_at_8[0x18];
5878
5879         u8         syndrome[0x20];
5880
5881         u8         reserved_at_40[0x40];
5882 };
5883
5884 struct mlx5_ifc_drain_dct_in_bits {
5885         u8         opcode[0x10];
5886         u8         reserved_at_10[0x10];
5887
5888         u8         reserved_at_20[0x10];
5889         u8         op_mod[0x10];
5890
5891         u8         reserved_at_40[0x8];
5892         u8         dctn[0x18];
5893
5894         u8         reserved_at_60[0x20];
5895 };
5896
5897 struct mlx5_ifc_disable_hca_out_bits {
5898         u8         status[0x8];
5899         u8         reserved_at_8[0x18];
5900
5901         u8         syndrome[0x20];
5902
5903         u8         reserved_at_40[0x20];
5904 };
5905
5906 struct mlx5_ifc_disable_hca_in_bits {
5907         u8         opcode[0x10];
5908         u8         reserved_at_10[0x10];
5909
5910         u8         reserved_at_20[0x10];
5911         u8         op_mod[0x10];
5912
5913         u8         reserved_at_40[0x10];
5914         u8         function_id[0x10];
5915
5916         u8         reserved_at_60[0x20];
5917 };
5918
5919 struct mlx5_ifc_detach_from_mcg_out_bits {
5920         u8         status[0x8];
5921         u8         reserved_at_8[0x18];
5922
5923         u8         syndrome[0x20];
5924
5925         u8         reserved_at_40[0x40];
5926 };
5927
5928 struct mlx5_ifc_detach_from_mcg_in_bits {
5929         u8         opcode[0x10];
5930         u8         reserved_at_10[0x10];
5931
5932         u8         reserved_at_20[0x10];
5933         u8         op_mod[0x10];
5934
5935         u8         reserved_at_40[0x8];
5936         u8         qpn[0x18];
5937
5938         u8         reserved_at_60[0x20];
5939
5940         u8         multicast_gid[16][0x8];
5941 };
5942
5943 struct mlx5_ifc_destroy_xrq_out_bits {
5944         u8         status[0x8];
5945         u8         reserved_at_8[0x18];
5946
5947         u8         syndrome[0x20];
5948
5949         u8         reserved_at_40[0x40];
5950 };
5951
5952 struct mlx5_ifc_destroy_xrq_in_bits {
5953         u8         opcode[0x10];
5954         u8         reserved_at_10[0x10];
5955
5956         u8         reserved_at_20[0x10];
5957         u8         op_mod[0x10];
5958
5959         u8         reserved_at_40[0x8];
5960         u8         xrqn[0x18];
5961
5962         u8         reserved_at_60[0x20];
5963 };
5964
5965 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5966         u8         status[0x8];
5967         u8         reserved_at_8[0x18];
5968
5969         u8         syndrome[0x20];
5970
5971         u8         reserved_at_40[0x40];
5972 };
5973
5974 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5975         u8         opcode[0x10];
5976         u8         reserved_at_10[0x10];
5977
5978         u8         reserved_at_20[0x10];
5979         u8         op_mod[0x10];
5980
5981         u8         reserved_at_40[0x8];
5982         u8         xrc_srqn[0x18];
5983
5984         u8         reserved_at_60[0x20];
5985 };
5986
5987 struct mlx5_ifc_destroy_tis_out_bits {
5988         u8         status[0x8];
5989         u8         reserved_at_8[0x18];
5990
5991         u8         syndrome[0x20];
5992
5993         u8         reserved_at_40[0x40];
5994 };
5995
5996 struct mlx5_ifc_destroy_tis_in_bits {
5997         u8         opcode[0x10];
5998         u8         reserved_at_10[0x10];
5999
6000         u8         reserved_at_20[0x10];
6001         u8         op_mod[0x10];
6002
6003         u8         reserved_at_40[0x8];
6004         u8         tisn[0x18];
6005
6006         u8         reserved_at_60[0x20];
6007 };
6008
6009 struct mlx5_ifc_destroy_tir_out_bits {
6010         u8         status[0x8];
6011         u8         reserved_at_8[0x18];
6012
6013         u8         syndrome[0x20];
6014
6015         u8         reserved_at_40[0x40];
6016 };
6017
6018 struct mlx5_ifc_destroy_tir_in_bits {
6019         u8         opcode[0x10];
6020         u8         reserved_at_10[0x10];
6021
6022         u8         reserved_at_20[0x10];
6023         u8         op_mod[0x10];
6024
6025         u8         reserved_at_40[0x8];
6026         u8         tirn[0x18];
6027
6028         u8         reserved_at_60[0x20];
6029 };
6030
6031 struct mlx5_ifc_destroy_srq_out_bits {
6032         u8         status[0x8];
6033         u8         reserved_at_8[0x18];
6034
6035         u8         syndrome[0x20];
6036
6037         u8         reserved_at_40[0x40];
6038 };
6039
6040 struct mlx5_ifc_destroy_srq_in_bits {
6041         u8         opcode[0x10];
6042         u8         reserved_at_10[0x10];
6043
6044         u8         reserved_at_20[0x10];
6045         u8         op_mod[0x10];
6046
6047         u8         reserved_at_40[0x8];
6048         u8         srqn[0x18];
6049
6050         u8         reserved_at_60[0x20];
6051 };
6052
6053 struct mlx5_ifc_destroy_sq_out_bits {
6054         u8         status[0x8];
6055         u8         reserved_at_8[0x18];
6056
6057         u8         syndrome[0x20];
6058
6059         u8         reserved_at_40[0x40];
6060 };
6061
6062 struct mlx5_ifc_destroy_sq_in_bits {
6063         u8         opcode[0x10];
6064         u8         reserved_at_10[0x10];
6065
6066         u8         reserved_at_20[0x10];
6067         u8         op_mod[0x10];
6068
6069         u8         reserved_at_40[0x8];
6070         u8         sqn[0x18];
6071
6072         u8         reserved_at_60[0x20];
6073 };
6074
6075 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6076         u8         status[0x8];
6077         u8         reserved_at_8[0x18];
6078
6079         u8         syndrome[0x20];
6080
6081         u8         reserved_at_40[0x1c0];
6082 };
6083
6084 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6085         u8         opcode[0x10];
6086         u8         reserved_at_10[0x10];
6087
6088         u8         reserved_at_20[0x10];
6089         u8         op_mod[0x10];
6090
6091         u8         scheduling_hierarchy[0x8];
6092         u8         reserved_at_48[0x18];
6093
6094         u8         scheduling_element_id[0x20];
6095
6096         u8         reserved_at_80[0x180];
6097 };
6098
6099 struct mlx5_ifc_destroy_rqt_out_bits {
6100         u8         status[0x8];
6101         u8         reserved_at_8[0x18];
6102
6103         u8         syndrome[0x20];
6104
6105         u8         reserved_at_40[0x40];
6106 };
6107
6108 struct mlx5_ifc_destroy_rqt_in_bits {
6109         u8         opcode[0x10];
6110         u8         reserved_at_10[0x10];
6111
6112         u8         reserved_at_20[0x10];
6113         u8         op_mod[0x10];
6114
6115         u8         reserved_at_40[0x8];
6116         u8         rqtn[0x18];
6117
6118         u8         reserved_at_60[0x20];
6119 };
6120
6121 struct mlx5_ifc_destroy_rq_out_bits {
6122         u8         status[0x8];
6123         u8         reserved_at_8[0x18];
6124
6125         u8         syndrome[0x20];
6126
6127         u8         reserved_at_40[0x40];
6128 };
6129
6130 struct mlx5_ifc_destroy_rq_in_bits {
6131         u8         opcode[0x10];
6132         u8         reserved_at_10[0x10];
6133
6134         u8         reserved_at_20[0x10];
6135         u8         op_mod[0x10];
6136
6137         u8         reserved_at_40[0x8];
6138         u8         rqn[0x18];
6139
6140         u8         reserved_at_60[0x20];
6141 };
6142
6143 struct mlx5_ifc_set_delay_drop_params_in_bits {
6144         u8         opcode[0x10];
6145         u8         reserved_at_10[0x10];
6146
6147         u8         reserved_at_20[0x10];
6148         u8         op_mod[0x10];
6149
6150         u8         reserved_at_40[0x20];
6151
6152         u8         reserved_at_60[0x10];
6153         u8         delay_drop_timeout[0x10];
6154 };
6155
6156 struct mlx5_ifc_set_delay_drop_params_out_bits {
6157         u8         status[0x8];
6158         u8         reserved_at_8[0x18];
6159
6160         u8         syndrome[0x20];
6161
6162         u8         reserved_at_40[0x40];
6163 };
6164
6165 struct mlx5_ifc_destroy_rmp_out_bits {
6166         u8         status[0x8];
6167         u8         reserved_at_8[0x18];
6168
6169         u8         syndrome[0x20];
6170
6171         u8         reserved_at_40[0x40];
6172 };
6173
6174 struct mlx5_ifc_destroy_rmp_in_bits {
6175         u8         opcode[0x10];
6176         u8         reserved_at_10[0x10];
6177
6178         u8         reserved_at_20[0x10];
6179         u8         op_mod[0x10];
6180
6181         u8         reserved_at_40[0x8];
6182         u8         rmpn[0x18];
6183
6184         u8         reserved_at_60[0x20];
6185 };
6186
6187 struct mlx5_ifc_destroy_qp_out_bits {
6188         u8         status[0x8];
6189         u8         reserved_at_8[0x18];
6190
6191         u8         syndrome[0x20];
6192
6193         u8         reserved_at_40[0x40];
6194 };
6195
6196 struct mlx5_ifc_destroy_qp_in_bits {
6197         u8         opcode[0x10];
6198         u8         reserved_at_10[0x10];
6199
6200         u8         reserved_at_20[0x10];
6201         u8         op_mod[0x10];
6202
6203         u8         reserved_at_40[0x8];
6204         u8         qpn[0x18];
6205
6206         u8         reserved_at_60[0x20];
6207 };
6208
6209 struct mlx5_ifc_destroy_psv_out_bits {
6210         u8         status[0x8];
6211         u8         reserved_at_8[0x18];
6212
6213         u8         syndrome[0x20];
6214
6215         u8         reserved_at_40[0x40];
6216 };
6217
6218 struct mlx5_ifc_destroy_psv_in_bits {
6219         u8         opcode[0x10];
6220         u8         reserved_at_10[0x10];
6221
6222         u8         reserved_at_20[0x10];
6223         u8         op_mod[0x10];
6224
6225         u8         reserved_at_40[0x8];
6226         u8         psvn[0x18];
6227
6228         u8         reserved_at_60[0x20];
6229 };
6230
6231 struct mlx5_ifc_destroy_mkey_out_bits {
6232         u8         status[0x8];
6233         u8         reserved_at_8[0x18];
6234
6235         u8         syndrome[0x20];
6236
6237         u8         reserved_at_40[0x40];
6238 };
6239
6240 struct mlx5_ifc_destroy_mkey_in_bits {
6241         u8         opcode[0x10];
6242         u8         reserved_at_10[0x10];
6243
6244         u8         reserved_at_20[0x10];
6245         u8         op_mod[0x10];
6246
6247         u8         reserved_at_40[0x8];
6248         u8         mkey_index[0x18];
6249
6250         u8         reserved_at_60[0x20];
6251 };
6252
6253 struct mlx5_ifc_destroy_flow_table_out_bits {
6254         u8         status[0x8];
6255         u8         reserved_at_8[0x18];
6256
6257         u8         syndrome[0x20];
6258
6259         u8         reserved_at_40[0x40];
6260 };
6261
6262 struct mlx5_ifc_destroy_flow_table_in_bits {
6263         u8         opcode[0x10];
6264         u8         reserved_at_10[0x10];
6265
6266         u8         reserved_at_20[0x10];
6267         u8         op_mod[0x10];
6268
6269         u8         other_vport[0x1];
6270         u8         reserved_at_41[0xf];
6271         u8         vport_number[0x10];
6272
6273         u8         reserved_at_60[0x20];
6274
6275         u8         table_type[0x8];
6276         u8         reserved_at_88[0x18];
6277
6278         u8         reserved_at_a0[0x8];
6279         u8         table_id[0x18];
6280
6281         u8         reserved_at_c0[0x140];
6282 };
6283
6284 struct mlx5_ifc_destroy_flow_group_out_bits {
6285         u8         status[0x8];
6286         u8         reserved_at_8[0x18];
6287
6288         u8         syndrome[0x20];
6289
6290         u8         reserved_at_40[0x40];
6291 };
6292
6293 struct mlx5_ifc_destroy_flow_group_in_bits {
6294         u8         opcode[0x10];
6295         u8         reserved_at_10[0x10];
6296
6297         u8         reserved_at_20[0x10];
6298         u8         op_mod[0x10];
6299
6300         u8         other_vport[0x1];
6301         u8         reserved_at_41[0xf];
6302         u8         vport_number[0x10];
6303
6304         u8         reserved_at_60[0x20];
6305
6306         u8         table_type[0x8];
6307         u8         reserved_at_88[0x18];
6308
6309         u8         reserved_at_a0[0x8];
6310         u8         table_id[0x18];
6311
6312         u8         group_id[0x20];
6313
6314         u8         reserved_at_e0[0x120];
6315 };
6316
6317 struct mlx5_ifc_destroy_eq_out_bits {
6318         u8         status[0x8];
6319         u8         reserved_at_8[0x18];
6320
6321         u8         syndrome[0x20];
6322
6323         u8         reserved_at_40[0x40];
6324 };
6325
6326 struct mlx5_ifc_destroy_eq_in_bits {
6327         u8         opcode[0x10];
6328         u8         reserved_at_10[0x10];
6329
6330         u8         reserved_at_20[0x10];
6331         u8         op_mod[0x10];
6332
6333         u8         reserved_at_40[0x18];
6334         u8         eq_number[0x8];
6335
6336         u8         reserved_at_60[0x20];
6337 };
6338
6339 struct mlx5_ifc_destroy_dct_out_bits {
6340         u8         status[0x8];
6341         u8         reserved_at_8[0x18];
6342
6343         u8         syndrome[0x20];
6344
6345         u8         reserved_at_40[0x40];
6346 };
6347
6348 struct mlx5_ifc_destroy_dct_in_bits {
6349         u8         opcode[0x10];
6350         u8         reserved_at_10[0x10];
6351
6352         u8         reserved_at_20[0x10];
6353         u8         op_mod[0x10];
6354
6355         u8         reserved_at_40[0x8];
6356         u8         dctn[0x18];
6357
6358         u8         reserved_at_60[0x20];
6359 };
6360
6361 struct mlx5_ifc_destroy_cq_out_bits {
6362         u8         status[0x8];
6363         u8         reserved_at_8[0x18];
6364
6365         u8         syndrome[0x20];
6366
6367         u8         reserved_at_40[0x40];
6368 };
6369
6370 struct mlx5_ifc_destroy_cq_in_bits {
6371         u8         opcode[0x10];
6372         u8         reserved_at_10[0x10];
6373
6374         u8         reserved_at_20[0x10];
6375         u8         op_mod[0x10];
6376
6377         u8         reserved_at_40[0x8];
6378         u8         cqn[0x18];
6379
6380         u8         reserved_at_60[0x20];
6381 };
6382
6383 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6384         u8         status[0x8];
6385         u8         reserved_at_8[0x18];
6386
6387         u8         syndrome[0x20];
6388
6389         u8         reserved_at_40[0x40];
6390 };
6391
6392 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6393         u8         opcode[0x10];
6394         u8         reserved_at_10[0x10];
6395
6396         u8         reserved_at_20[0x10];
6397         u8         op_mod[0x10];
6398
6399         u8         reserved_at_40[0x20];
6400
6401         u8         reserved_at_60[0x10];
6402         u8         vxlan_udp_port[0x10];
6403 };
6404
6405 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6406         u8         status[0x8];
6407         u8         reserved_at_8[0x18];
6408
6409         u8         syndrome[0x20];
6410
6411         u8         reserved_at_40[0x40];
6412 };
6413
6414 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6415         u8         opcode[0x10];
6416         u8         reserved_at_10[0x10];
6417
6418         u8         reserved_at_20[0x10];
6419         u8         op_mod[0x10];
6420
6421         u8         reserved_at_40[0x60];
6422
6423         u8         reserved_at_a0[0x8];
6424         u8         table_index[0x18];
6425
6426         u8         reserved_at_c0[0x140];
6427 };
6428
6429 struct mlx5_ifc_delete_fte_out_bits {
6430         u8         status[0x8];
6431         u8         reserved_at_8[0x18];
6432
6433         u8         syndrome[0x20];
6434
6435         u8         reserved_at_40[0x40];
6436 };
6437
6438 struct mlx5_ifc_delete_fte_in_bits {
6439         u8         opcode[0x10];
6440         u8         reserved_at_10[0x10];
6441
6442         u8         reserved_at_20[0x10];
6443         u8         op_mod[0x10];
6444
6445         u8         other_vport[0x1];
6446         u8         reserved_at_41[0xf];
6447         u8         vport_number[0x10];
6448
6449         u8         reserved_at_60[0x20];
6450
6451         u8         table_type[0x8];
6452         u8         reserved_at_88[0x18];
6453
6454         u8         reserved_at_a0[0x8];
6455         u8         table_id[0x18];
6456
6457         u8         reserved_at_c0[0x40];
6458
6459         u8         flow_index[0x20];
6460
6461         u8         reserved_at_120[0xe0];
6462 };
6463
6464 struct mlx5_ifc_dealloc_xrcd_out_bits {
6465         u8         status[0x8];
6466         u8         reserved_at_8[0x18];
6467
6468         u8         syndrome[0x20];
6469
6470         u8         reserved_at_40[0x40];
6471 };
6472
6473 struct mlx5_ifc_dealloc_xrcd_in_bits {
6474         u8         opcode[0x10];
6475         u8         reserved_at_10[0x10];
6476
6477         u8         reserved_at_20[0x10];
6478         u8         op_mod[0x10];
6479
6480         u8         reserved_at_40[0x8];
6481         u8         xrcd[0x18];
6482
6483         u8         reserved_at_60[0x20];
6484 };
6485
6486 struct mlx5_ifc_dealloc_uar_out_bits {
6487         u8         status[0x8];
6488         u8         reserved_at_8[0x18];
6489
6490         u8         syndrome[0x20];
6491
6492         u8         reserved_at_40[0x40];
6493 };
6494
6495 struct mlx5_ifc_dealloc_uar_in_bits {
6496         u8         opcode[0x10];
6497         u8         reserved_at_10[0x10];
6498
6499         u8         reserved_at_20[0x10];
6500         u8         op_mod[0x10];
6501
6502         u8         reserved_at_40[0x8];
6503         u8         uar[0x18];
6504
6505         u8         reserved_at_60[0x20];
6506 };
6507
6508 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6509         u8         status[0x8];
6510         u8         reserved_at_8[0x18];
6511
6512         u8         syndrome[0x20];
6513
6514         u8         reserved_at_40[0x40];
6515 };
6516
6517 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6518         u8         opcode[0x10];
6519         u8         reserved_at_10[0x10];
6520
6521         u8         reserved_at_20[0x10];
6522         u8         op_mod[0x10];
6523
6524         u8         reserved_at_40[0x8];
6525         u8         transport_domain[0x18];
6526
6527         u8         reserved_at_60[0x20];
6528 };
6529
6530 struct mlx5_ifc_dealloc_q_counter_out_bits {
6531         u8         status[0x8];
6532         u8         reserved_at_8[0x18];
6533
6534         u8         syndrome[0x20];
6535
6536         u8         reserved_at_40[0x40];
6537 };
6538
6539 struct mlx5_ifc_dealloc_q_counter_in_bits {
6540         u8         opcode[0x10];
6541         u8         reserved_at_10[0x10];
6542
6543         u8         reserved_at_20[0x10];
6544         u8         op_mod[0x10];
6545
6546         u8         reserved_at_40[0x18];
6547         u8         counter_set_id[0x8];
6548
6549         u8         reserved_at_60[0x20];
6550 };
6551
6552 struct mlx5_ifc_dealloc_pd_out_bits {
6553         u8         status[0x8];
6554         u8         reserved_at_8[0x18];
6555
6556         u8         syndrome[0x20];
6557
6558         u8         reserved_at_40[0x40];
6559 };
6560
6561 struct mlx5_ifc_dealloc_pd_in_bits {
6562         u8         opcode[0x10];
6563         u8         reserved_at_10[0x10];
6564
6565         u8         reserved_at_20[0x10];
6566         u8         op_mod[0x10];
6567
6568         u8         reserved_at_40[0x8];
6569         u8         pd[0x18];
6570
6571         u8         reserved_at_60[0x20];
6572 };
6573
6574 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6575         u8         status[0x8];
6576         u8         reserved_at_8[0x18];
6577
6578         u8         syndrome[0x20];
6579
6580         u8         reserved_at_40[0x40];
6581 };
6582
6583 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6584         u8         opcode[0x10];
6585         u8         reserved_at_10[0x10];
6586
6587         u8         reserved_at_20[0x10];
6588         u8         op_mod[0x10];
6589
6590         u8         flow_counter_id[0x20];
6591
6592         u8         reserved_at_60[0x20];
6593 };
6594
6595 struct mlx5_ifc_create_xrq_out_bits {
6596         u8         status[0x8];
6597         u8         reserved_at_8[0x18];
6598
6599         u8         syndrome[0x20];
6600
6601         u8         reserved_at_40[0x8];
6602         u8         xrqn[0x18];
6603
6604         u8         reserved_at_60[0x20];
6605 };
6606
6607 struct mlx5_ifc_create_xrq_in_bits {
6608         u8         opcode[0x10];
6609         u8         reserved_at_10[0x10];
6610
6611         u8         reserved_at_20[0x10];
6612         u8         op_mod[0x10];
6613
6614         u8         reserved_at_40[0x40];
6615
6616         struct mlx5_ifc_xrqc_bits xrq_context;
6617 };
6618
6619 struct mlx5_ifc_create_xrc_srq_out_bits {
6620         u8         status[0x8];
6621         u8         reserved_at_8[0x18];
6622
6623         u8         syndrome[0x20];
6624
6625         u8         reserved_at_40[0x8];
6626         u8         xrc_srqn[0x18];
6627
6628         u8         reserved_at_60[0x20];
6629 };
6630
6631 struct mlx5_ifc_create_xrc_srq_in_bits {
6632         u8         opcode[0x10];
6633         u8         reserved_at_10[0x10];
6634
6635         u8         reserved_at_20[0x10];
6636         u8         op_mod[0x10];
6637
6638         u8         reserved_at_40[0x40];
6639
6640         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6641
6642         u8         reserved_at_280[0x600];
6643
6644         u8         pas[0][0x40];
6645 };
6646
6647 struct mlx5_ifc_create_tis_out_bits {
6648         u8         status[0x8];
6649         u8         reserved_at_8[0x18];
6650
6651         u8         syndrome[0x20];
6652
6653         u8         reserved_at_40[0x8];
6654         u8         tisn[0x18];
6655
6656         u8         reserved_at_60[0x20];
6657 };
6658
6659 struct mlx5_ifc_create_tis_in_bits {
6660         u8         opcode[0x10];
6661         u8         reserved_at_10[0x10];
6662
6663         u8         reserved_at_20[0x10];
6664         u8         op_mod[0x10];
6665
6666         u8         reserved_at_40[0xc0];
6667
6668         struct mlx5_ifc_tisc_bits ctx;
6669 };
6670
6671 struct mlx5_ifc_create_tir_out_bits {
6672         u8         status[0x8];
6673         u8         reserved_at_8[0x18];
6674
6675         u8         syndrome[0x20];
6676
6677         u8         reserved_at_40[0x8];
6678         u8         tirn[0x18];
6679
6680         u8         reserved_at_60[0x20];
6681 };
6682
6683 struct mlx5_ifc_create_tir_in_bits {
6684         u8         opcode[0x10];
6685         u8         reserved_at_10[0x10];
6686
6687         u8         reserved_at_20[0x10];
6688         u8         op_mod[0x10];
6689
6690         u8         reserved_at_40[0xc0];
6691
6692         struct mlx5_ifc_tirc_bits ctx;
6693 };
6694
6695 struct mlx5_ifc_create_srq_out_bits {
6696         u8         status[0x8];
6697         u8         reserved_at_8[0x18];
6698
6699         u8         syndrome[0x20];
6700
6701         u8         reserved_at_40[0x8];
6702         u8         srqn[0x18];
6703
6704         u8         reserved_at_60[0x20];
6705 };
6706
6707 struct mlx5_ifc_create_srq_in_bits {
6708         u8         opcode[0x10];
6709         u8         reserved_at_10[0x10];
6710
6711         u8         reserved_at_20[0x10];
6712         u8         op_mod[0x10];
6713
6714         u8         reserved_at_40[0x40];
6715
6716         struct mlx5_ifc_srqc_bits srq_context_entry;
6717
6718         u8         reserved_at_280[0x600];
6719
6720         u8         pas[0][0x40];
6721 };
6722
6723 struct mlx5_ifc_create_sq_out_bits {
6724         u8         status[0x8];
6725         u8         reserved_at_8[0x18];
6726
6727         u8         syndrome[0x20];
6728
6729         u8         reserved_at_40[0x8];
6730         u8         sqn[0x18];
6731
6732         u8         reserved_at_60[0x20];
6733 };
6734
6735 struct mlx5_ifc_create_sq_in_bits {
6736         u8         opcode[0x10];
6737         u8         reserved_at_10[0x10];
6738
6739         u8         reserved_at_20[0x10];
6740         u8         op_mod[0x10];
6741
6742         u8         reserved_at_40[0xc0];
6743
6744         struct mlx5_ifc_sqc_bits ctx;
6745 };
6746
6747 struct mlx5_ifc_create_scheduling_element_out_bits {
6748         u8         status[0x8];
6749         u8         reserved_at_8[0x18];
6750
6751         u8         syndrome[0x20];
6752
6753         u8         reserved_at_40[0x40];
6754
6755         u8         scheduling_element_id[0x20];
6756
6757         u8         reserved_at_a0[0x160];
6758 };
6759
6760 struct mlx5_ifc_create_scheduling_element_in_bits {
6761         u8         opcode[0x10];
6762         u8         reserved_at_10[0x10];
6763
6764         u8         reserved_at_20[0x10];
6765         u8         op_mod[0x10];
6766
6767         u8         scheduling_hierarchy[0x8];
6768         u8         reserved_at_48[0x18];
6769
6770         u8         reserved_at_60[0xa0];
6771
6772         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6773
6774         u8         reserved_at_300[0x100];
6775 };
6776
6777 struct mlx5_ifc_create_rqt_out_bits {
6778         u8         status[0x8];
6779         u8         reserved_at_8[0x18];
6780
6781         u8         syndrome[0x20];
6782
6783         u8         reserved_at_40[0x8];
6784         u8         rqtn[0x18];
6785
6786         u8         reserved_at_60[0x20];
6787 };
6788
6789 struct mlx5_ifc_create_rqt_in_bits {
6790         u8         opcode[0x10];
6791         u8         reserved_at_10[0x10];
6792
6793         u8         reserved_at_20[0x10];
6794         u8         op_mod[0x10];
6795
6796         u8         reserved_at_40[0xc0];
6797
6798         struct mlx5_ifc_rqtc_bits rqt_context;
6799 };
6800
6801 struct mlx5_ifc_create_rq_out_bits {
6802         u8         status[0x8];
6803         u8         reserved_at_8[0x18];
6804
6805         u8         syndrome[0x20];
6806
6807         u8         reserved_at_40[0x8];
6808         u8         rqn[0x18];
6809
6810         u8         reserved_at_60[0x20];
6811 };
6812
6813 struct mlx5_ifc_create_rq_in_bits {
6814         u8         opcode[0x10];
6815         u8         reserved_at_10[0x10];
6816
6817         u8         reserved_at_20[0x10];
6818         u8         op_mod[0x10];
6819
6820         u8         reserved_at_40[0xc0];
6821
6822         struct mlx5_ifc_rqc_bits ctx;
6823 };
6824
6825 struct mlx5_ifc_create_rmp_out_bits {
6826         u8         status[0x8];
6827         u8         reserved_at_8[0x18];
6828
6829         u8         syndrome[0x20];
6830
6831         u8         reserved_at_40[0x8];
6832         u8         rmpn[0x18];
6833
6834         u8         reserved_at_60[0x20];
6835 };
6836
6837 struct mlx5_ifc_create_rmp_in_bits {
6838         u8         opcode[0x10];
6839         u8         reserved_at_10[0x10];
6840
6841         u8         reserved_at_20[0x10];
6842         u8         op_mod[0x10];
6843
6844         u8         reserved_at_40[0xc0];
6845
6846         struct mlx5_ifc_rmpc_bits ctx;
6847 };
6848
6849 struct mlx5_ifc_create_qp_out_bits {
6850         u8         status[0x8];
6851         u8         reserved_at_8[0x18];
6852
6853         u8         syndrome[0x20];
6854
6855         u8         reserved_at_40[0x8];
6856         u8         qpn[0x18];
6857
6858         u8         reserved_at_60[0x20];
6859 };
6860
6861 struct mlx5_ifc_create_qp_in_bits {
6862         u8         opcode[0x10];
6863         u8         reserved_at_10[0x10];
6864
6865         u8         reserved_at_20[0x10];
6866         u8         op_mod[0x10];
6867
6868         u8         reserved_at_40[0x40];
6869
6870         u8         opt_param_mask[0x20];
6871
6872         u8         reserved_at_a0[0x20];
6873
6874         struct mlx5_ifc_qpc_bits qpc;
6875
6876         u8         reserved_at_800[0x80];
6877
6878         u8         pas[0][0x40];
6879 };
6880
6881 struct mlx5_ifc_create_psv_out_bits {
6882         u8         status[0x8];
6883         u8         reserved_at_8[0x18];
6884
6885         u8         syndrome[0x20];
6886
6887         u8         reserved_at_40[0x40];
6888
6889         u8         reserved_at_80[0x8];
6890         u8         psv0_index[0x18];
6891
6892         u8         reserved_at_a0[0x8];
6893         u8         psv1_index[0x18];
6894
6895         u8         reserved_at_c0[0x8];
6896         u8         psv2_index[0x18];
6897
6898         u8         reserved_at_e0[0x8];
6899         u8         psv3_index[0x18];
6900 };
6901
6902 struct mlx5_ifc_create_psv_in_bits {
6903         u8         opcode[0x10];
6904         u8         reserved_at_10[0x10];
6905
6906         u8         reserved_at_20[0x10];
6907         u8         op_mod[0x10];
6908
6909         u8         num_psv[0x4];
6910         u8         reserved_at_44[0x4];
6911         u8         pd[0x18];
6912
6913         u8         reserved_at_60[0x20];
6914 };
6915
6916 struct mlx5_ifc_create_mkey_out_bits {
6917         u8         status[0x8];
6918         u8         reserved_at_8[0x18];
6919
6920         u8         syndrome[0x20];
6921
6922         u8         reserved_at_40[0x8];
6923         u8         mkey_index[0x18];
6924
6925         u8         reserved_at_60[0x20];
6926 };
6927
6928 struct mlx5_ifc_create_mkey_in_bits {
6929         u8         opcode[0x10];
6930         u8         reserved_at_10[0x10];
6931
6932         u8         reserved_at_20[0x10];
6933         u8         op_mod[0x10];
6934
6935         u8         reserved_at_40[0x20];
6936
6937         u8         pg_access[0x1];
6938         u8         reserved_at_61[0x1f];
6939
6940         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6941
6942         u8         reserved_at_280[0x80];
6943
6944         u8         translations_octword_actual_size[0x20];
6945
6946         u8         reserved_at_320[0x560];
6947
6948         u8         klm_pas_mtt[0][0x20];
6949 };
6950
6951 struct mlx5_ifc_create_flow_table_out_bits {
6952         u8         status[0x8];
6953         u8         reserved_at_8[0x18];
6954
6955         u8         syndrome[0x20];
6956
6957         u8         reserved_at_40[0x8];
6958         u8         table_id[0x18];
6959
6960         u8         reserved_at_60[0x20];
6961 };
6962
6963 struct mlx5_ifc_flow_table_context_bits {
6964         u8         encap_en[0x1];
6965         u8         decap_en[0x1];
6966         u8         reserved_at_2[0x2];
6967         u8         table_miss_action[0x4];
6968         u8         level[0x8];
6969         u8         reserved_at_10[0x8];
6970         u8         log_size[0x8];
6971
6972         u8         reserved_at_20[0x8];
6973         u8         table_miss_id[0x18];
6974
6975         u8         reserved_at_40[0x8];
6976         u8         lag_master_next_table_id[0x18];
6977
6978         u8         reserved_at_60[0xe0];
6979 };
6980
6981 struct mlx5_ifc_create_flow_table_in_bits {
6982         u8         opcode[0x10];
6983         u8         reserved_at_10[0x10];
6984
6985         u8         reserved_at_20[0x10];
6986         u8         op_mod[0x10];
6987
6988         u8         other_vport[0x1];
6989         u8         reserved_at_41[0xf];
6990         u8         vport_number[0x10];
6991
6992         u8         reserved_at_60[0x20];
6993
6994         u8         table_type[0x8];
6995         u8         reserved_at_88[0x18];
6996
6997         u8         reserved_at_a0[0x20];
6998
6999         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7000 };
7001
7002 struct mlx5_ifc_create_flow_group_out_bits {
7003         u8         status[0x8];
7004         u8         reserved_at_8[0x18];
7005
7006         u8         syndrome[0x20];
7007
7008         u8         reserved_at_40[0x8];
7009         u8         group_id[0x18];
7010
7011         u8         reserved_at_60[0x20];
7012 };
7013
7014 enum {
7015         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
7016         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
7017         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
7018         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7019 };
7020
7021 struct mlx5_ifc_create_flow_group_in_bits {
7022         u8         opcode[0x10];
7023         u8         reserved_at_10[0x10];
7024
7025         u8         reserved_at_20[0x10];
7026         u8         op_mod[0x10];
7027
7028         u8         other_vport[0x1];
7029         u8         reserved_at_41[0xf];
7030         u8         vport_number[0x10];
7031
7032         u8         reserved_at_60[0x20];
7033
7034         u8         table_type[0x8];
7035         u8         reserved_at_88[0x18];
7036
7037         u8         reserved_at_a0[0x8];
7038         u8         table_id[0x18];
7039
7040         u8         source_eswitch_owner_vhca_id_valid[0x1];
7041
7042         u8         reserved_at_c1[0x1f];
7043
7044         u8         start_flow_index[0x20];
7045
7046         u8         reserved_at_100[0x20];
7047
7048         u8         end_flow_index[0x20];
7049
7050         u8         reserved_at_140[0xa0];
7051
7052         u8         reserved_at_1e0[0x18];
7053         u8         match_criteria_enable[0x8];
7054
7055         struct mlx5_ifc_fte_match_param_bits match_criteria;
7056
7057         u8         reserved_at_1200[0xe00];
7058 };
7059
7060 struct mlx5_ifc_create_eq_out_bits {
7061         u8         status[0x8];
7062         u8         reserved_at_8[0x18];
7063
7064         u8         syndrome[0x20];
7065
7066         u8         reserved_at_40[0x18];
7067         u8         eq_number[0x8];
7068
7069         u8         reserved_at_60[0x20];
7070 };
7071
7072 struct mlx5_ifc_create_eq_in_bits {
7073         u8         opcode[0x10];
7074         u8         reserved_at_10[0x10];
7075
7076         u8         reserved_at_20[0x10];
7077         u8         op_mod[0x10];
7078
7079         u8         reserved_at_40[0x40];
7080
7081         struct mlx5_ifc_eqc_bits eq_context_entry;
7082
7083         u8         reserved_at_280[0x40];
7084
7085         u8         event_bitmask[0x40];
7086
7087         u8         reserved_at_300[0x580];
7088
7089         u8         pas[0][0x40];
7090 };
7091
7092 struct mlx5_ifc_create_dct_out_bits {
7093         u8         status[0x8];
7094         u8         reserved_at_8[0x18];
7095
7096         u8         syndrome[0x20];
7097
7098         u8         reserved_at_40[0x8];
7099         u8         dctn[0x18];
7100
7101         u8         reserved_at_60[0x20];
7102 };
7103
7104 struct mlx5_ifc_create_dct_in_bits {
7105         u8         opcode[0x10];
7106         u8         reserved_at_10[0x10];
7107
7108         u8         reserved_at_20[0x10];
7109         u8         op_mod[0x10];
7110
7111         u8         reserved_at_40[0x40];
7112
7113         struct mlx5_ifc_dctc_bits dct_context_entry;
7114
7115         u8         reserved_at_280[0x180];
7116 };
7117
7118 struct mlx5_ifc_create_cq_out_bits {
7119         u8         status[0x8];
7120         u8         reserved_at_8[0x18];
7121
7122         u8         syndrome[0x20];
7123
7124         u8         reserved_at_40[0x8];
7125         u8         cqn[0x18];
7126
7127         u8         reserved_at_60[0x20];
7128 };
7129
7130 struct mlx5_ifc_create_cq_in_bits {
7131         u8         opcode[0x10];
7132         u8         reserved_at_10[0x10];
7133
7134         u8         reserved_at_20[0x10];
7135         u8         op_mod[0x10];
7136
7137         u8         reserved_at_40[0x40];
7138
7139         struct mlx5_ifc_cqc_bits cq_context;
7140
7141         u8         reserved_at_280[0x600];
7142
7143         u8         pas[0][0x40];
7144 };
7145
7146 struct mlx5_ifc_config_int_moderation_out_bits {
7147         u8         status[0x8];
7148         u8         reserved_at_8[0x18];
7149
7150         u8         syndrome[0x20];
7151
7152         u8         reserved_at_40[0x4];
7153         u8         min_delay[0xc];
7154         u8         int_vector[0x10];
7155
7156         u8         reserved_at_60[0x20];
7157 };
7158
7159 enum {
7160         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7161         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7162 };
7163
7164 struct mlx5_ifc_config_int_moderation_in_bits {
7165         u8         opcode[0x10];
7166         u8         reserved_at_10[0x10];
7167
7168         u8         reserved_at_20[0x10];
7169         u8         op_mod[0x10];
7170
7171         u8         reserved_at_40[0x4];
7172         u8         min_delay[0xc];
7173         u8         int_vector[0x10];
7174
7175         u8         reserved_at_60[0x20];
7176 };
7177
7178 struct mlx5_ifc_attach_to_mcg_out_bits {
7179         u8         status[0x8];
7180         u8         reserved_at_8[0x18];
7181
7182         u8         syndrome[0x20];
7183
7184         u8         reserved_at_40[0x40];
7185 };
7186
7187 struct mlx5_ifc_attach_to_mcg_in_bits {
7188         u8         opcode[0x10];
7189         u8         reserved_at_10[0x10];
7190
7191         u8         reserved_at_20[0x10];
7192         u8         op_mod[0x10];
7193
7194         u8         reserved_at_40[0x8];
7195         u8         qpn[0x18];
7196
7197         u8         reserved_at_60[0x20];
7198
7199         u8         multicast_gid[16][0x8];
7200 };
7201
7202 struct mlx5_ifc_arm_xrq_out_bits {
7203         u8         status[0x8];
7204         u8         reserved_at_8[0x18];
7205
7206         u8         syndrome[0x20];
7207
7208         u8         reserved_at_40[0x40];
7209 };
7210
7211 struct mlx5_ifc_arm_xrq_in_bits {
7212         u8         opcode[0x10];
7213         u8         reserved_at_10[0x10];
7214
7215         u8         reserved_at_20[0x10];
7216         u8         op_mod[0x10];
7217
7218         u8         reserved_at_40[0x8];
7219         u8         xrqn[0x18];
7220
7221         u8         reserved_at_60[0x10];
7222         u8         lwm[0x10];
7223 };
7224
7225 struct mlx5_ifc_arm_xrc_srq_out_bits {
7226         u8         status[0x8];
7227         u8         reserved_at_8[0x18];
7228
7229         u8         syndrome[0x20];
7230
7231         u8         reserved_at_40[0x40];
7232 };
7233
7234 enum {
7235         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7236 };
7237
7238 struct mlx5_ifc_arm_xrc_srq_in_bits {
7239         u8         opcode[0x10];
7240         u8         reserved_at_10[0x10];
7241
7242         u8         reserved_at_20[0x10];
7243         u8         op_mod[0x10];
7244
7245         u8         reserved_at_40[0x8];
7246         u8         xrc_srqn[0x18];
7247
7248         u8         reserved_at_60[0x10];
7249         u8         lwm[0x10];
7250 };
7251
7252 struct mlx5_ifc_arm_rq_out_bits {
7253         u8         status[0x8];
7254         u8         reserved_at_8[0x18];
7255
7256         u8         syndrome[0x20];
7257
7258         u8         reserved_at_40[0x40];
7259 };
7260
7261 enum {
7262         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7263         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7264 };
7265
7266 struct mlx5_ifc_arm_rq_in_bits {
7267         u8         opcode[0x10];
7268         u8         reserved_at_10[0x10];
7269
7270         u8         reserved_at_20[0x10];
7271         u8         op_mod[0x10];
7272
7273         u8         reserved_at_40[0x8];
7274         u8         srq_number[0x18];
7275
7276         u8         reserved_at_60[0x10];
7277         u8         lwm[0x10];
7278 };
7279
7280 struct mlx5_ifc_arm_dct_out_bits {
7281         u8         status[0x8];
7282         u8         reserved_at_8[0x18];
7283
7284         u8         syndrome[0x20];
7285
7286         u8         reserved_at_40[0x40];
7287 };
7288
7289 struct mlx5_ifc_arm_dct_in_bits {
7290         u8         opcode[0x10];
7291         u8         reserved_at_10[0x10];
7292
7293         u8         reserved_at_20[0x10];
7294         u8         op_mod[0x10];
7295
7296         u8         reserved_at_40[0x8];
7297         u8         dct_number[0x18];
7298
7299         u8         reserved_at_60[0x20];
7300 };
7301
7302 struct mlx5_ifc_alloc_xrcd_out_bits {
7303         u8         status[0x8];
7304         u8         reserved_at_8[0x18];
7305
7306         u8         syndrome[0x20];
7307
7308         u8         reserved_at_40[0x8];
7309         u8         xrcd[0x18];
7310
7311         u8         reserved_at_60[0x20];
7312 };
7313
7314 struct mlx5_ifc_alloc_xrcd_in_bits {
7315         u8         opcode[0x10];
7316         u8         reserved_at_10[0x10];
7317
7318         u8         reserved_at_20[0x10];
7319         u8         op_mod[0x10];
7320
7321         u8         reserved_at_40[0x40];
7322 };
7323
7324 struct mlx5_ifc_alloc_uar_out_bits {
7325         u8         status[0x8];
7326         u8         reserved_at_8[0x18];
7327
7328         u8         syndrome[0x20];
7329
7330         u8         reserved_at_40[0x8];
7331         u8         uar[0x18];
7332
7333         u8         reserved_at_60[0x20];
7334 };
7335
7336 struct mlx5_ifc_alloc_uar_in_bits {
7337         u8         opcode[0x10];
7338         u8         reserved_at_10[0x10];
7339
7340         u8         reserved_at_20[0x10];
7341         u8         op_mod[0x10];
7342
7343         u8         reserved_at_40[0x40];
7344 };
7345
7346 struct mlx5_ifc_alloc_transport_domain_out_bits {
7347         u8         status[0x8];
7348         u8         reserved_at_8[0x18];
7349
7350         u8         syndrome[0x20];
7351
7352         u8         reserved_at_40[0x8];
7353         u8         transport_domain[0x18];
7354
7355         u8         reserved_at_60[0x20];
7356 };
7357
7358 struct mlx5_ifc_alloc_transport_domain_in_bits {
7359         u8         opcode[0x10];
7360         u8         reserved_at_10[0x10];
7361
7362         u8         reserved_at_20[0x10];
7363         u8         op_mod[0x10];
7364
7365         u8         reserved_at_40[0x40];
7366 };
7367
7368 struct mlx5_ifc_alloc_q_counter_out_bits {
7369         u8         status[0x8];
7370         u8         reserved_at_8[0x18];
7371
7372         u8         syndrome[0x20];
7373
7374         u8         reserved_at_40[0x18];
7375         u8         counter_set_id[0x8];
7376
7377         u8         reserved_at_60[0x20];
7378 };
7379
7380 struct mlx5_ifc_alloc_q_counter_in_bits {
7381         u8         opcode[0x10];
7382         u8         reserved_at_10[0x10];
7383
7384         u8         reserved_at_20[0x10];
7385         u8         op_mod[0x10];
7386
7387         u8         reserved_at_40[0x40];
7388 };
7389
7390 struct mlx5_ifc_alloc_pd_out_bits {
7391         u8         status[0x8];
7392         u8         reserved_at_8[0x18];
7393
7394         u8         syndrome[0x20];
7395
7396         u8         reserved_at_40[0x8];
7397         u8         pd[0x18];
7398
7399         u8         reserved_at_60[0x20];
7400 };
7401
7402 struct mlx5_ifc_alloc_pd_in_bits {
7403         u8         opcode[0x10];
7404         u8         reserved_at_10[0x10];
7405
7406         u8         reserved_at_20[0x10];
7407         u8         op_mod[0x10];
7408
7409         u8         reserved_at_40[0x40];
7410 };
7411
7412 struct mlx5_ifc_alloc_flow_counter_out_bits {
7413         u8         status[0x8];
7414         u8         reserved_at_8[0x18];
7415
7416         u8         syndrome[0x20];
7417
7418         u8         flow_counter_id[0x20];
7419
7420         u8         reserved_at_60[0x20];
7421 };
7422
7423 struct mlx5_ifc_alloc_flow_counter_in_bits {
7424         u8         opcode[0x10];
7425         u8         reserved_at_10[0x10];
7426
7427         u8         reserved_at_20[0x10];
7428         u8         op_mod[0x10];
7429
7430         u8         reserved_at_40[0x40];
7431 };
7432
7433 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7434         u8         status[0x8];
7435         u8         reserved_at_8[0x18];
7436
7437         u8         syndrome[0x20];
7438
7439         u8         reserved_at_40[0x40];
7440 };
7441
7442 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7443         u8         opcode[0x10];
7444         u8         reserved_at_10[0x10];
7445
7446         u8         reserved_at_20[0x10];
7447         u8         op_mod[0x10];
7448
7449         u8         reserved_at_40[0x20];
7450
7451         u8         reserved_at_60[0x10];
7452         u8         vxlan_udp_port[0x10];
7453 };
7454
7455 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7456         u8         status[0x8];
7457         u8         reserved_at_8[0x18];
7458
7459         u8         syndrome[0x20];
7460
7461         u8         reserved_at_40[0x40];
7462 };
7463
7464 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7465         u8         opcode[0x10];
7466         u8         reserved_at_10[0x10];
7467
7468         u8         reserved_at_20[0x10];
7469         u8         op_mod[0x10];
7470
7471         u8         reserved_at_40[0x10];
7472         u8         rate_limit_index[0x10];
7473
7474         u8         reserved_at_60[0x20];
7475
7476         u8         rate_limit[0x20];
7477
7478         u8         burst_upper_bound[0x20];
7479
7480         u8         reserved_at_c0[0x10];
7481         u8         typical_packet_size[0x10];
7482
7483         u8         reserved_at_e0[0x120];
7484 };
7485
7486 struct mlx5_ifc_access_register_out_bits {
7487         u8         status[0x8];
7488         u8         reserved_at_8[0x18];
7489
7490         u8         syndrome[0x20];
7491
7492         u8         reserved_at_40[0x40];
7493
7494         u8         register_data[0][0x20];
7495 };
7496
7497 enum {
7498         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7499         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7500 };
7501
7502 struct mlx5_ifc_access_register_in_bits {
7503         u8         opcode[0x10];
7504         u8         reserved_at_10[0x10];
7505
7506         u8         reserved_at_20[0x10];
7507         u8         op_mod[0x10];
7508
7509         u8         reserved_at_40[0x10];
7510         u8         register_id[0x10];
7511
7512         u8         argument[0x20];
7513
7514         u8         register_data[0][0x20];
7515 };
7516
7517 struct mlx5_ifc_sltp_reg_bits {
7518         u8         status[0x4];
7519         u8         version[0x4];
7520         u8         local_port[0x8];
7521         u8         pnat[0x2];
7522         u8         reserved_at_12[0x2];
7523         u8         lane[0x4];
7524         u8         reserved_at_18[0x8];
7525
7526         u8         reserved_at_20[0x20];
7527
7528         u8         reserved_at_40[0x7];
7529         u8         polarity[0x1];
7530         u8         ob_tap0[0x8];
7531         u8         ob_tap1[0x8];
7532         u8         ob_tap2[0x8];
7533
7534         u8         reserved_at_60[0xc];
7535         u8         ob_preemp_mode[0x4];
7536         u8         ob_reg[0x8];
7537         u8         ob_bias[0x8];
7538
7539         u8         reserved_at_80[0x20];
7540 };
7541
7542 struct mlx5_ifc_slrg_reg_bits {
7543         u8         status[0x4];
7544         u8         version[0x4];
7545         u8         local_port[0x8];
7546         u8         pnat[0x2];
7547         u8         reserved_at_12[0x2];
7548         u8         lane[0x4];
7549         u8         reserved_at_18[0x8];
7550
7551         u8         time_to_link_up[0x10];
7552         u8         reserved_at_30[0xc];
7553         u8         grade_lane_speed[0x4];
7554
7555         u8         grade_version[0x8];
7556         u8         grade[0x18];
7557
7558         u8         reserved_at_60[0x4];
7559         u8         height_grade_type[0x4];
7560         u8         height_grade[0x18];
7561
7562         u8         height_dz[0x10];
7563         u8         height_dv[0x10];
7564
7565         u8         reserved_at_a0[0x10];
7566         u8         height_sigma[0x10];
7567
7568         u8         reserved_at_c0[0x20];
7569
7570         u8         reserved_at_e0[0x4];
7571         u8         phase_grade_type[0x4];
7572         u8         phase_grade[0x18];
7573
7574         u8         reserved_at_100[0x8];
7575         u8         phase_eo_pos[0x8];
7576         u8         reserved_at_110[0x8];
7577         u8         phase_eo_neg[0x8];
7578
7579         u8         ffe_set_tested[0x10];
7580         u8         test_errors_per_lane[0x10];
7581 };
7582
7583 struct mlx5_ifc_pvlc_reg_bits {
7584         u8         reserved_at_0[0x8];
7585         u8         local_port[0x8];
7586         u8         reserved_at_10[0x10];
7587
7588         u8         reserved_at_20[0x1c];
7589         u8         vl_hw_cap[0x4];
7590
7591         u8         reserved_at_40[0x1c];
7592         u8         vl_admin[0x4];
7593
7594         u8         reserved_at_60[0x1c];
7595         u8         vl_operational[0x4];
7596 };
7597
7598 struct mlx5_ifc_pude_reg_bits {
7599         u8         swid[0x8];
7600         u8         local_port[0x8];
7601         u8         reserved_at_10[0x4];
7602         u8         admin_status[0x4];
7603         u8         reserved_at_18[0x4];
7604         u8         oper_status[0x4];
7605
7606         u8         reserved_at_20[0x60];
7607 };
7608
7609 struct mlx5_ifc_ptys_reg_bits {
7610         u8         reserved_at_0[0x1];
7611         u8         an_disable_admin[0x1];
7612         u8         an_disable_cap[0x1];
7613         u8         reserved_at_3[0x5];
7614         u8         local_port[0x8];
7615         u8         reserved_at_10[0xd];
7616         u8         proto_mask[0x3];
7617
7618         u8         an_status[0x4];
7619         u8         reserved_at_24[0x3c];
7620
7621         u8         eth_proto_capability[0x20];
7622
7623         u8         ib_link_width_capability[0x10];
7624         u8         ib_proto_capability[0x10];
7625
7626         u8         reserved_at_a0[0x20];
7627
7628         u8         eth_proto_admin[0x20];
7629
7630         u8         ib_link_width_admin[0x10];
7631         u8         ib_proto_admin[0x10];
7632
7633         u8         reserved_at_100[0x20];
7634
7635         u8         eth_proto_oper[0x20];
7636
7637         u8         ib_link_width_oper[0x10];
7638         u8         ib_proto_oper[0x10];
7639
7640         u8         reserved_at_160[0x1c];
7641         u8         connector_type[0x4];
7642
7643         u8         eth_proto_lp_advertise[0x20];
7644
7645         u8         reserved_at_1a0[0x60];
7646 };
7647
7648 struct mlx5_ifc_mlcr_reg_bits {
7649         u8         reserved_at_0[0x8];
7650         u8         local_port[0x8];
7651         u8         reserved_at_10[0x20];
7652
7653         u8         beacon_duration[0x10];
7654         u8         reserved_at_40[0x10];
7655
7656         u8         beacon_remain[0x10];
7657 };
7658
7659 struct mlx5_ifc_ptas_reg_bits {
7660         u8         reserved_at_0[0x20];
7661
7662         u8         algorithm_options[0x10];
7663         u8         reserved_at_30[0x4];
7664         u8         repetitions_mode[0x4];
7665         u8         num_of_repetitions[0x8];
7666
7667         u8         grade_version[0x8];
7668         u8         height_grade_type[0x4];
7669         u8         phase_grade_type[0x4];
7670         u8         height_grade_weight[0x8];
7671         u8         phase_grade_weight[0x8];
7672
7673         u8         gisim_measure_bits[0x10];
7674         u8         adaptive_tap_measure_bits[0x10];
7675
7676         u8         ber_bath_high_error_threshold[0x10];
7677         u8         ber_bath_mid_error_threshold[0x10];
7678
7679         u8         ber_bath_low_error_threshold[0x10];
7680         u8         one_ratio_high_threshold[0x10];
7681
7682         u8         one_ratio_high_mid_threshold[0x10];
7683         u8         one_ratio_low_mid_threshold[0x10];
7684
7685         u8         one_ratio_low_threshold[0x10];
7686         u8         ndeo_error_threshold[0x10];
7687
7688         u8         mixer_offset_step_size[0x10];
7689         u8         reserved_at_110[0x8];
7690         u8         mix90_phase_for_voltage_bath[0x8];
7691
7692         u8         mixer_offset_start[0x10];
7693         u8         mixer_offset_end[0x10];
7694
7695         u8         reserved_at_140[0x15];
7696         u8         ber_test_time[0xb];
7697 };
7698
7699 struct mlx5_ifc_pspa_reg_bits {
7700         u8         swid[0x8];
7701         u8         local_port[0x8];
7702         u8         sub_port[0x8];
7703         u8         reserved_at_18[0x8];
7704
7705         u8         reserved_at_20[0x20];
7706 };
7707
7708 struct mlx5_ifc_pqdr_reg_bits {
7709         u8         reserved_at_0[0x8];
7710         u8         local_port[0x8];
7711         u8         reserved_at_10[0x5];
7712         u8         prio[0x3];
7713         u8         reserved_at_18[0x6];
7714         u8         mode[0x2];
7715
7716         u8         reserved_at_20[0x20];
7717
7718         u8         reserved_at_40[0x10];
7719         u8         min_threshold[0x10];
7720
7721         u8         reserved_at_60[0x10];
7722         u8         max_threshold[0x10];
7723
7724         u8         reserved_at_80[0x10];
7725         u8         mark_probability_denominator[0x10];
7726
7727         u8         reserved_at_a0[0x60];
7728 };
7729
7730 struct mlx5_ifc_ppsc_reg_bits {
7731         u8         reserved_at_0[0x8];
7732         u8         local_port[0x8];
7733         u8         reserved_at_10[0x10];
7734
7735         u8         reserved_at_20[0x60];
7736
7737         u8         reserved_at_80[0x1c];
7738         u8         wrps_admin[0x4];
7739
7740         u8         reserved_at_a0[0x1c];
7741         u8         wrps_status[0x4];
7742
7743         u8         reserved_at_c0[0x8];
7744         u8         up_threshold[0x8];
7745         u8         reserved_at_d0[0x8];
7746         u8         down_threshold[0x8];
7747
7748         u8         reserved_at_e0[0x20];
7749
7750         u8         reserved_at_100[0x1c];
7751         u8         srps_admin[0x4];
7752
7753         u8         reserved_at_120[0x1c];
7754         u8         srps_status[0x4];
7755
7756         u8         reserved_at_140[0x40];
7757 };
7758
7759 struct mlx5_ifc_pplr_reg_bits {
7760         u8         reserved_at_0[0x8];
7761         u8         local_port[0x8];
7762         u8         reserved_at_10[0x10];
7763
7764         u8         reserved_at_20[0x8];
7765         u8         lb_cap[0x8];
7766         u8         reserved_at_30[0x8];
7767         u8         lb_en[0x8];
7768 };
7769
7770 struct mlx5_ifc_pplm_reg_bits {
7771         u8         reserved_at_0[0x8];
7772         u8         local_port[0x8];
7773         u8         reserved_at_10[0x10];
7774
7775         u8         reserved_at_20[0x20];
7776
7777         u8         port_profile_mode[0x8];
7778         u8         static_port_profile[0x8];
7779         u8         active_port_profile[0x8];
7780         u8         reserved_at_58[0x8];
7781
7782         u8         retransmission_active[0x8];
7783         u8         fec_mode_active[0x18];
7784
7785         u8         reserved_at_80[0x20];
7786 };
7787
7788 struct mlx5_ifc_ppcnt_reg_bits {
7789         u8         swid[0x8];
7790         u8         local_port[0x8];
7791         u8         pnat[0x2];
7792         u8         reserved_at_12[0x8];
7793         u8         grp[0x6];
7794
7795         u8         clr[0x1];
7796         u8         reserved_at_21[0x1c];
7797         u8         prio_tc[0x3];
7798
7799         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7800 };
7801
7802 struct mlx5_ifc_mpcnt_reg_bits {
7803         u8         reserved_at_0[0x8];
7804         u8         pcie_index[0x8];
7805         u8         reserved_at_10[0xa];
7806         u8         grp[0x6];
7807
7808         u8         clr[0x1];
7809         u8         reserved_at_21[0x1f];
7810
7811         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7812 };
7813
7814 struct mlx5_ifc_ppad_reg_bits {
7815         u8         reserved_at_0[0x3];
7816         u8         single_mac[0x1];
7817         u8         reserved_at_4[0x4];
7818         u8         local_port[0x8];
7819         u8         mac_47_32[0x10];
7820
7821         u8         mac_31_0[0x20];
7822
7823         u8         reserved_at_40[0x40];
7824 };
7825
7826 struct mlx5_ifc_pmtu_reg_bits {
7827         u8         reserved_at_0[0x8];
7828         u8         local_port[0x8];
7829         u8         reserved_at_10[0x10];
7830
7831         u8         max_mtu[0x10];
7832         u8         reserved_at_30[0x10];
7833
7834         u8         admin_mtu[0x10];
7835         u8         reserved_at_50[0x10];
7836
7837         u8         oper_mtu[0x10];
7838         u8         reserved_at_70[0x10];
7839 };
7840
7841 struct mlx5_ifc_pmpr_reg_bits {
7842         u8         reserved_at_0[0x8];
7843         u8         module[0x8];
7844         u8         reserved_at_10[0x10];
7845
7846         u8         reserved_at_20[0x18];
7847         u8         attenuation_5g[0x8];
7848
7849         u8         reserved_at_40[0x18];
7850         u8         attenuation_7g[0x8];
7851
7852         u8         reserved_at_60[0x18];
7853         u8         attenuation_12g[0x8];
7854 };
7855
7856 struct mlx5_ifc_pmpe_reg_bits {
7857         u8         reserved_at_0[0x8];
7858         u8         module[0x8];
7859         u8         reserved_at_10[0xc];
7860         u8         module_status[0x4];
7861
7862         u8         reserved_at_20[0x60];
7863 };
7864
7865 struct mlx5_ifc_pmpc_reg_bits {
7866         u8         module_state_updated[32][0x8];
7867 };
7868
7869 struct mlx5_ifc_pmlpn_reg_bits {
7870         u8         reserved_at_0[0x4];
7871         u8         mlpn_status[0x4];
7872         u8         local_port[0x8];
7873         u8         reserved_at_10[0x10];
7874
7875         u8         e[0x1];
7876         u8         reserved_at_21[0x1f];
7877 };
7878
7879 struct mlx5_ifc_pmlp_reg_bits {
7880         u8         rxtx[0x1];
7881         u8         reserved_at_1[0x7];
7882         u8         local_port[0x8];
7883         u8         reserved_at_10[0x8];
7884         u8         width[0x8];
7885
7886         u8         lane0_module_mapping[0x20];
7887
7888         u8         lane1_module_mapping[0x20];
7889
7890         u8         lane2_module_mapping[0x20];
7891
7892         u8         lane3_module_mapping[0x20];
7893
7894         u8         reserved_at_a0[0x160];
7895 };
7896
7897 struct mlx5_ifc_pmaos_reg_bits {
7898         u8         reserved_at_0[0x8];
7899         u8         module[0x8];
7900         u8         reserved_at_10[0x4];
7901         u8         admin_status[0x4];
7902         u8         reserved_at_18[0x4];
7903         u8         oper_status[0x4];
7904
7905         u8         ase[0x1];
7906         u8         ee[0x1];
7907         u8         reserved_at_22[0x1c];
7908         u8         e[0x2];
7909
7910         u8         reserved_at_40[0x40];
7911 };
7912
7913 struct mlx5_ifc_plpc_reg_bits {
7914         u8         reserved_at_0[0x4];
7915         u8         profile_id[0xc];
7916         u8         reserved_at_10[0x4];
7917         u8         proto_mask[0x4];
7918         u8         reserved_at_18[0x8];
7919
7920         u8         reserved_at_20[0x10];
7921         u8         lane_speed[0x10];
7922
7923         u8         reserved_at_40[0x17];
7924         u8         lpbf[0x1];
7925         u8         fec_mode_policy[0x8];
7926
7927         u8         retransmission_capability[0x8];
7928         u8         fec_mode_capability[0x18];
7929
7930         u8         retransmission_support_admin[0x8];
7931         u8         fec_mode_support_admin[0x18];
7932
7933         u8         retransmission_request_admin[0x8];
7934         u8         fec_mode_request_admin[0x18];
7935
7936         u8         reserved_at_c0[0x80];
7937 };
7938
7939 struct mlx5_ifc_plib_reg_bits {
7940         u8         reserved_at_0[0x8];
7941         u8         local_port[0x8];
7942         u8         reserved_at_10[0x8];
7943         u8         ib_port[0x8];
7944
7945         u8         reserved_at_20[0x60];
7946 };
7947
7948 struct mlx5_ifc_plbf_reg_bits {
7949         u8         reserved_at_0[0x8];
7950         u8         local_port[0x8];
7951         u8         reserved_at_10[0xd];
7952         u8         lbf_mode[0x3];
7953
7954         u8         reserved_at_20[0x20];
7955 };
7956
7957 struct mlx5_ifc_pipg_reg_bits {
7958         u8         reserved_at_0[0x8];
7959         u8         local_port[0x8];
7960         u8         reserved_at_10[0x10];
7961
7962         u8         dic[0x1];
7963         u8         reserved_at_21[0x19];
7964         u8         ipg[0x4];
7965         u8         reserved_at_3e[0x2];
7966 };
7967
7968 struct mlx5_ifc_pifr_reg_bits {
7969         u8         reserved_at_0[0x8];
7970         u8         local_port[0x8];
7971         u8         reserved_at_10[0x10];
7972
7973         u8         reserved_at_20[0xe0];
7974
7975         u8         port_filter[8][0x20];
7976
7977         u8         port_filter_update_en[8][0x20];
7978 };
7979
7980 struct mlx5_ifc_pfcc_reg_bits {
7981         u8         reserved_at_0[0x8];
7982         u8         local_port[0x8];
7983         u8         reserved_at_10[0xb];
7984         u8         ppan_mask_n[0x1];
7985         u8         minor_stall_mask[0x1];
7986         u8         critical_stall_mask[0x1];
7987         u8         reserved_at_1e[0x2];
7988
7989         u8         ppan[0x4];
7990         u8         reserved_at_24[0x4];
7991         u8         prio_mask_tx[0x8];
7992         u8         reserved_at_30[0x8];
7993         u8         prio_mask_rx[0x8];
7994
7995         u8         pptx[0x1];
7996         u8         aptx[0x1];
7997         u8         pptx_mask_n[0x1];
7998         u8         reserved_at_43[0x5];
7999         u8         pfctx[0x8];
8000         u8         reserved_at_50[0x10];
8001
8002         u8         pprx[0x1];
8003         u8         aprx[0x1];
8004         u8         pprx_mask_n[0x1];
8005         u8         reserved_at_63[0x5];
8006         u8         pfcrx[0x8];
8007         u8         reserved_at_70[0x10];
8008
8009         u8         device_stall_minor_watermark[0x10];
8010         u8         device_stall_critical_watermark[0x10];
8011
8012         u8         reserved_at_a0[0x60];
8013 };
8014
8015 struct mlx5_ifc_pelc_reg_bits {
8016         u8         op[0x4];
8017         u8         reserved_at_4[0x4];
8018         u8         local_port[0x8];
8019         u8         reserved_at_10[0x10];
8020
8021         u8         op_admin[0x8];
8022         u8         op_capability[0x8];
8023         u8         op_request[0x8];
8024         u8         op_active[0x8];
8025
8026         u8         admin[0x40];
8027
8028         u8         capability[0x40];
8029
8030         u8         request[0x40];
8031
8032         u8         active[0x40];
8033
8034         u8         reserved_at_140[0x80];
8035 };
8036
8037 struct mlx5_ifc_peir_reg_bits {
8038         u8         reserved_at_0[0x8];
8039         u8         local_port[0x8];
8040         u8         reserved_at_10[0x10];
8041
8042         u8         reserved_at_20[0xc];
8043         u8         error_count[0x4];
8044         u8         reserved_at_30[0x10];
8045
8046         u8         reserved_at_40[0xc];
8047         u8         lane[0x4];
8048         u8         reserved_at_50[0x8];
8049         u8         error_type[0x8];
8050 };
8051
8052 struct mlx5_ifc_pcam_enhanced_features_bits {
8053         u8         reserved_at_0[0x6d];
8054         u8         rx_icrc_encapsulated_counter[0x1];
8055         u8         reserved_at_6e[0x8];
8056         u8         pfcc_mask[0x1];
8057         u8         reserved_at_77[0x4];
8058         u8         rx_buffer_fullness_counters[0x1];
8059         u8         ptys_connector_type[0x1];
8060         u8         reserved_at_7d[0x1];
8061         u8         ppcnt_discard_group[0x1];
8062         u8         ppcnt_statistical_group[0x1];
8063 };
8064
8065 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8066         u8         port_access_reg_cap_mask_127_to_96[0x20];
8067         u8         port_access_reg_cap_mask_95_to_64[0x20];
8068         u8         port_access_reg_cap_mask_63_to_32[0x20];
8069
8070         u8         port_access_reg_cap_mask_31_to_13[0x13];
8071         u8         pbmc[0x1];
8072         u8         pptb[0x1];
8073         u8         port_access_reg_cap_mask_10_to_0[0xb];
8074 };
8075
8076 struct mlx5_ifc_pcam_reg_bits {
8077         u8         reserved_at_0[0x8];
8078         u8         feature_group[0x8];
8079         u8         reserved_at_10[0x8];
8080         u8         access_reg_group[0x8];
8081
8082         u8         reserved_at_20[0x20];
8083
8084         union {
8085                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8086                 u8         reserved_at_0[0x80];
8087         } port_access_reg_cap_mask;
8088
8089         u8         reserved_at_c0[0x80];
8090
8091         union {
8092                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8093                 u8         reserved_at_0[0x80];
8094         } feature_cap_mask;
8095
8096         u8         reserved_at_1c0[0xc0];
8097 };
8098
8099 struct mlx5_ifc_mcam_enhanced_features_bits {
8100         u8         reserved_at_0[0x7b];
8101         u8         pcie_outbound_stalled[0x1];
8102         u8         tx_overflow_buffer_pkt[0x1];
8103         u8         mtpps_enh_out_per_adj[0x1];
8104         u8         mtpps_fs[0x1];
8105         u8         pcie_performance_group[0x1];
8106 };
8107
8108 struct mlx5_ifc_mcam_access_reg_bits {
8109         u8         reserved_at_0[0x1c];
8110         u8         mcda[0x1];
8111         u8         mcc[0x1];
8112         u8         mcqi[0x1];
8113         u8         reserved_at_1f[0x1];
8114
8115         u8         regs_95_to_68[0x1c];
8116         u8         tracer_registers[0x4];
8117
8118         u8         regs_63_to_32[0x20];
8119         u8         regs_31_to_0[0x20];
8120 };
8121
8122 struct mlx5_ifc_mcam_reg_bits {
8123         u8         reserved_at_0[0x8];
8124         u8         feature_group[0x8];
8125         u8         reserved_at_10[0x8];
8126         u8         access_reg_group[0x8];
8127
8128         u8         reserved_at_20[0x20];
8129
8130         union {
8131                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8132                 u8         reserved_at_0[0x80];
8133         } mng_access_reg_cap_mask;
8134
8135         u8         reserved_at_c0[0x80];
8136
8137         union {
8138                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8139                 u8         reserved_at_0[0x80];
8140         } mng_feature_cap_mask;
8141
8142         u8         reserved_at_1c0[0x80];
8143 };
8144
8145 struct mlx5_ifc_qcam_access_reg_cap_mask {
8146         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8147         u8         qpdpm[0x1];
8148         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8149         u8         qdpm[0x1];
8150         u8         qpts[0x1];
8151         u8         qcap[0x1];
8152         u8         qcam_access_reg_cap_mask_0[0x1];
8153 };
8154
8155 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8156         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8157         u8         qpts_trust_both[0x1];
8158 };
8159
8160 struct mlx5_ifc_qcam_reg_bits {
8161         u8         reserved_at_0[0x8];
8162         u8         feature_group[0x8];
8163         u8         reserved_at_10[0x8];
8164         u8         access_reg_group[0x8];
8165         u8         reserved_at_20[0x20];
8166
8167         union {
8168                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8169                 u8  reserved_at_0[0x80];
8170         } qos_access_reg_cap_mask;
8171
8172         u8         reserved_at_c0[0x80];
8173
8174         union {
8175                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8176                 u8  reserved_at_0[0x80];
8177         } qos_feature_cap_mask;
8178
8179         u8         reserved_at_1c0[0x80];
8180 };
8181
8182 struct mlx5_ifc_pcap_reg_bits {
8183         u8         reserved_at_0[0x8];
8184         u8         local_port[0x8];
8185         u8         reserved_at_10[0x10];
8186
8187         u8         port_capability_mask[4][0x20];
8188 };
8189
8190 struct mlx5_ifc_paos_reg_bits {
8191         u8         swid[0x8];
8192         u8         local_port[0x8];
8193         u8         reserved_at_10[0x4];
8194         u8         admin_status[0x4];
8195         u8         reserved_at_18[0x4];
8196         u8         oper_status[0x4];
8197
8198         u8         ase[0x1];
8199         u8         ee[0x1];
8200         u8         reserved_at_22[0x1c];
8201         u8         e[0x2];
8202
8203         u8         reserved_at_40[0x40];
8204 };
8205
8206 struct mlx5_ifc_pamp_reg_bits {
8207         u8         reserved_at_0[0x8];
8208         u8         opamp_group[0x8];
8209         u8         reserved_at_10[0xc];
8210         u8         opamp_group_type[0x4];
8211
8212         u8         start_index[0x10];
8213         u8         reserved_at_30[0x4];
8214         u8         num_of_indices[0xc];
8215
8216         u8         index_data[18][0x10];
8217 };
8218
8219 struct mlx5_ifc_pcmr_reg_bits {
8220         u8         reserved_at_0[0x8];
8221         u8         local_port[0x8];
8222         u8         reserved_at_10[0x2e];
8223         u8         fcs_cap[0x1];
8224         u8         reserved_at_3f[0x1f];
8225         u8         fcs_chk[0x1];
8226         u8         reserved_at_5f[0x1];
8227 };
8228
8229 struct mlx5_ifc_lane_2_module_mapping_bits {
8230         u8         reserved_at_0[0x6];
8231         u8         rx_lane[0x2];
8232         u8         reserved_at_8[0x6];
8233         u8         tx_lane[0x2];
8234         u8         reserved_at_10[0x8];
8235         u8         module[0x8];
8236 };
8237
8238 struct mlx5_ifc_bufferx_reg_bits {
8239         u8         reserved_at_0[0x6];
8240         u8         lossy[0x1];
8241         u8         epsb[0x1];
8242         u8         reserved_at_8[0xc];
8243         u8         size[0xc];
8244
8245         u8         xoff_threshold[0x10];
8246         u8         xon_threshold[0x10];
8247 };
8248
8249 struct mlx5_ifc_set_node_in_bits {
8250         u8         node_description[64][0x8];
8251 };
8252
8253 struct mlx5_ifc_register_power_settings_bits {
8254         u8         reserved_at_0[0x18];
8255         u8         power_settings_level[0x8];
8256
8257         u8         reserved_at_20[0x60];
8258 };
8259
8260 struct mlx5_ifc_register_host_endianness_bits {
8261         u8         he[0x1];
8262         u8         reserved_at_1[0x1f];
8263
8264         u8         reserved_at_20[0x60];
8265 };
8266
8267 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8268         u8         reserved_at_0[0x20];
8269
8270         u8         mkey[0x20];
8271
8272         u8         addressh_63_32[0x20];
8273
8274         u8         addressl_31_0[0x20];
8275 };
8276
8277 struct mlx5_ifc_ud_adrs_vector_bits {
8278         u8         dc_key[0x40];
8279
8280         u8         ext[0x1];
8281         u8         reserved_at_41[0x7];
8282         u8         destination_qp_dct[0x18];
8283
8284         u8         static_rate[0x4];
8285         u8         sl_eth_prio[0x4];
8286         u8         fl[0x1];
8287         u8         mlid[0x7];
8288         u8         rlid_udp_sport[0x10];
8289
8290         u8         reserved_at_80[0x20];
8291
8292         u8         rmac_47_16[0x20];
8293
8294         u8         rmac_15_0[0x10];
8295         u8         tclass[0x8];
8296         u8         hop_limit[0x8];
8297
8298         u8         reserved_at_e0[0x1];
8299         u8         grh[0x1];
8300         u8         reserved_at_e2[0x2];
8301         u8         src_addr_index[0x8];
8302         u8         flow_label[0x14];
8303
8304         u8         rgid_rip[16][0x8];
8305 };
8306
8307 struct mlx5_ifc_pages_req_event_bits {
8308         u8         reserved_at_0[0x10];
8309         u8         function_id[0x10];
8310
8311         u8         num_pages[0x20];
8312
8313         u8         reserved_at_40[0xa0];
8314 };
8315
8316 struct mlx5_ifc_eqe_bits {
8317         u8         reserved_at_0[0x8];
8318         u8         event_type[0x8];
8319         u8         reserved_at_10[0x8];
8320         u8         event_sub_type[0x8];
8321
8322         u8         reserved_at_20[0xe0];
8323
8324         union mlx5_ifc_event_auto_bits event_data;
8325
8326         u8         reserved_at_1e0[0x10];
8327         u8         signature[0x8];
8328         u8         reserved_at_1f8[0x7];
8329         u8         owner[0x1];
8330 };
8331
8332 enum {
8333         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
8334 };
8335
8336 struct mlx5_ifc_cmd_queue_entry_bits {
8337         u8         type[0x8];
8338         u8         reserved_at_8[0x18];
8339
8340         u8         input_length[0x20];
8341
8342         u8         input_mailbox_pointer_63_32[0x20];
8343
8344         u8         input_mailbox_pointer_31_9[0x17];
8345         u8         reserved_at_77[0x9];
8346
8347         u8         command_input_inline_data[16][0x8];
8348
8349         u8         command_output_inline_data[16][0x8];
8350
8351         u8         output_mailbox_pointer_63_32[0x20];
8352
8353         u8         output_mailbox_pointer_31_9[0x17];
8354         u8         reserved_at_1b7[0x9];
8355
8356         u8         output_length[0x20];
8357
8358         u8         token[0x8];
8359         u8         signature[0x8];
8360         u8         reserved_at_1f0[0x8];
8361         u8         status[0x7];
8362         u8         ownership[0x1];
8363 };
8364
8365 struct mlx5_ifc_cmd_out_bits {
8366         u8         status[0x8];
8367         u8         reserved_at_8[0x18];
8368
8369         u8         syndrome[0x20];
8370
8371         u8         command_output[0x20];
8372 };
8373
8374 struct mlx5_ifc_cmd_in_bits {
8375         u8         opcode[0x10];
8376         u8         reserved_at_10[0x10];
8377
8378         u8         reserved_at_20[0x10];
8379         u8         op_mod[0x10];
8380
8381         u8         command[0][0x20];
8382 };
8383
8384 struct mlx5_ifc_cmd_if_box_bits {
8385         u8         mailbox_data[512][0x8];
8386
8387         u8         reserved_at_1000[0x180];
8388
8389         u8         next_pointer_63_32[0x20];
8390
8391         u8         next_pointer_31_10[0x16];
8392         u8         reserved_at_11b6[0xa];
8393
8394         u8         block_number[0x20];
8395
8396         u8         reserved_at_11e0[0x8];
8397         u8         token[0x8];
8398         u8         ctrl_signature[0x8];
8399         u8         signature[0x8];
8400 };
8401
8402 struct mlx5_ifc_mtt_bits {
8403         u8         ptag_63_32[0x20];
8404
8405         u8         ptag_31_8[0x18];
8406         u8         reserved_at_38[0x6];
8407         u8         wr_en[0x1];
8408         u8         rd_en[0x1];
8409 };
8410
8411 struct mlx5_ifc_query_wol_rol_out_bits {
8412         u8         status[0x8];
8413         u8         reserved_at_8[0x18];
8414
8415         u8         syndrome[0x20];
8416
8417         u8         reserved_at_40[0x10];
8418         u8         rol_mode[0x8];
8419         u8         wol_mode[0x8];
8420
8421         u8         reserved_at_60[0x20];
8422 };
8423
8424 struct mlx5_ifc_query_wol_rol_in_bits {
8425         u8         opcode[0x10];
8426         u8         reserved_at_10[0x10];
8427
8428         u8         reserved_at_20[0x10];
8429         u8         op_mod[0x10];
8430
8431         u8         reserved_at_40[0x40];
8432 };
8433
8434 struct mlx5_ifc_set_wol_rol_out_bits {
8435         u8         status[0x8];
8436         u8         reserved_at_8[0x18];
8437
8438         u8         syndrome[0x20];
8439
8440         u8         reserved_at_40[0x40];
8441 };
8442
8443 struct mlx5_ifc_set_wol_rol_in_bits {
8444         u8         opcode[0x10];
8445         u8         reserved_at_10[0x10];
8446
8447         u8         reserved_at_20[0x10];
8448         u8         op_mod[0x10];
8449
8450         u8         rol_mode_valid[0x1];
8451         u8         wol_mode_valid[0x1];
8452         u8         reserved_at_42[0xe];
8453         u8         rol_mode[0x8];
8454         u8         wol_mode[0x8];
8455
8456         u8         reserved_at_60[0x20];
8457 };
8458
8459 enum {
8460         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8461         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8462         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8463 };
8464
8465 enum {
8466         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8467         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8468         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8469 };
8470
8471 enum {
8472         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
8473         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
8474         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
8475         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
8476         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
8477         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
8478         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
8479         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
8480         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
8481         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
8482         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
8483 };
8484
8485 struct mlx5_ifc_initial_seg_bits {
8486         u8         fw_rev_minor[0x10];
8487         u8         fw_rev_major[0x10];
8488
8489         u8         cmd_interface_rev[0x10];
8490         u8         fw_rev_subminor[0x10];
8491
8492         u8         reserved_at_40[0x40];
8493
8494         u8         cmdq_phy_addr_63_32[0x20];
8495
8496         u8         cmdq_phy_addr_31_12[0x14];
8497         u8         reserved_at_b4[0x2];
8498         u8         nic_interface[0x2];
8499         u8         log_cmdq_size[0x4];
8500         u8         log_cmdq_stride[0x4];
8501
8502         u8         command_doorbell_vector[0x20];
8503
8504         u8         reserved_at_e0[0xf00];
8505
8506         u8         initializing[0x1];
8507         u8         reserved_at_fe1[0x4];
8508         u8         nic_interface_supported[0x3];
8509         u8         reserved_at_fe8[0x18];
8510
8511         struct mlx5_ifc_health_buffer_bits health_buffer;
8512
8513         u8         no_dram_nic_offset[0x20];
8514
8515         u8         reserved_at_1220[0x6e40];
8516
8517         u8         reserved_at_8060[0x1f];
8518         u8         clear_int[0x1];
8519
8520         u8         health_syndrome[0x8];
8521         u8         health_counter[0x18];
8522
8523         u8         reserved_at_80a0[0x17fc0];
8524 };
8525
8526 struct mlx5_ifc_mtpps_reg_bits {
8527         u8         reserved_at_0[0xc];
8528         u8         cap_number_of_pps_pins[0x4];
8529         u8         reserved_at_10[0x4];
8530         u8         cap_max_num_of_pps_in_pins[0x4];
8531         u8         reserved_at_18[0x4];
8532         u8         cap_max_num_of_pps_out_pins[0x4];
8533
8534         u8         reserved_at_20[0x24];
8535         u8         cap_pin_3_mode[0x4];
8536         u8         reserved_at_48[0x4];
8537         u8         cap_pin_2_mode[0x4];
8538         u8         reserved_at_50[0x4];
8539         u8         cap_pin_1_mode[0x4];
8540         u8         reserved_at_58[0x4];
8541         u8         cap_pin_0_mode[0x4];
8542
8543         u8         reserved_at_60[0x4];
8544         u8         cap_pin_7_mode[0x4];
8545         u8         reserved_at_68[0x4];
8546         u8         cap_pin_6_mode[0x4];
8547         u8         reserved_at_70[0x4];
8548         u8         cap_pin_5_mode[0x4];
8549         u8         reserved_at_78[0x4];
8550         u8         cap_pin_4_mode[0x4];
8551
8552         u8         field_select[0x20];
8553         u8         reserved_at_a0[0x60];
8554
8555         u8         enable[0x1];
8556         u8         reserved_at_101[0xb];
8557         u8         pattern[0x4];
8558         u8         reserved_at_110[0x4];
8559         u8         pin_mode[0x4];
8560         u8         pin[0x8];
8561
8562         u8         reserved_at_120[0x20];
8563
8564         u8         time_stamp[0x40];
8565
8566         u8         out_pulse_duration[0x10];
8567         u8         out_periodic_adjustment[0x10];
8568         u8         enhanced_out_periodic_adjustment[0x20];
8569
8570         u8         reserved_at_1c0[0x20];
8571 };
8572
8573 struct mlx5_ifc_mtppse_reg_bits {
8574         u8         reserved_at_0[0x18];
8575         u8         pin[0x8];
8576         u8         event_arm[0x1];
8577         u8         reserved_at_21[0x1b];
8578         u8         event_generation_mode[0x4];
8579         u8         reserved_at_40[0x40];
8580 };
8581
8582 struct mlx5_ifc_mcqi_cap_bits {
8583         u8         supported_info_bitmask[0x20];
8584
8585         u8         component_size[0x20];
8586
8587         u8         max_component_size[0x20];
8588
8589         u8         log_mcda_word_size[0x4];
8590         u8         reserved_at_64[0xc];
8591         u8         mcda_max_write_size[0x10];
8592
8593         u8         rd_en[0x1];
8594         u8         reserved_at_81[0x1];
8595         u8         match_chip_id[0x1];
8596         u8         match_psid[0x1];
8597         u8         check_user_timestamp[0x1];
8598         u8         match_base_guid_mac[0x1];
8599         u8         reserved_at_86[0x1a];
8600 };
8601
8602 struct mlx5_ifc_mcqi_reg_bits {
8603         u8         read_pending_component[0x1];
8604         u8         reserved_at_1[0xf];
8605         u8         component_index[0x10];
8606
8607         u8         reserved_at_20[0x20];
8608
8609         u8         reserved_at_40[0x1b];
8610         u8         info_type[0x5];
8611
8612         u8         info_size[0x20];
8613
8614         u8         offset[0x20];
8615
8616         u8         reserved_at_a0[0x10];
8617         u8         data_size[0x10];
8618
8619         u8         data[0][0x20];
8620 };
8621
8622 struct mlx5_ifc_mcc_reg_bits {
8623         u8         reserved_at_0[0x4];
8624         u8         time_elapsed_since_last_cmd[0xc];
8625         u8         reserved_at_10[0x8];
8626         u8         instruction[0x8];
8627
8628         u8         reserved_at_20[0x10];
8629         u8         component_index[0x10];
8630
8631         u8         reserved_at_40[0x8];
8632         u8         update_handle[0x18];
8633
8634         u8         handle_owner_type[0x4];
8635         u8         handle_owner_host_id[0x4];
8636         u8         reserved_at_68[0x1];
8637         u8         control_progress[0x7];
8638         u8         error_code[0x8];
8639         u8         reserved_at_78[0x4];
8640         u8         control_state[0x4];
8641
8642         u8         component_size[0x20];
8643
8644         u8         reserved_at_a0[0x60];
8645 };
8646
8647 struct mlx5_ifc_mcda_reg_bits {
8648         u8         reserved_at_0[0x8];
8649         u8         update_handle[0x18];
8650
8651         u8         offset[0x20];
8652
8653         u8         reserved_at_40[0x10];
8654         u8         size[0x10];
8655
8656         u8         reserved_at_60[0x20];
8657
8658         u8         data[0][0x20];
8659 };
8660
8661 union mlx5_ifc_ports_control_registers_document_bits {
8662         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8663         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8664         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8665         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8666         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8667         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8668         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8669         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8670         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8671         struct mlx5_ifc_pamp_reg_bits pamp_reg;
8672         struct mlx5_ifc_paos_reg_bits paos_reg;
8673         struct mlx5_ifc_pcap_reg_bits pcap_reg;
8674         struct mlx5_ifc_peir_reg_bits peir_reg;
8675         struct mlx5_ifc_pelc_reg_bits pelc_reg;
8676         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8677         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8678         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8679         struct mlx5_ifc_pifr_reg_bits pifr_reg;
8680         struct mlx5_ifc_pipg_reg_bits pipg_reg;
8681         struct mlx5_ifc_plbf_reg_bits plbf_reg;
8682         struct mlx5_ifc_plib_reg_bits plib_reg;
8683         struct mlx5_ifc_plpc_reg_bits plpc_reg;
8684         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8685         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8686         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8687         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8688         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8689         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8690         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8691         struct mlx5_ifc_ppad_reg_bits ppad_reg;
8692         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8693         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8694         struct mlx5_ifc_pplm_reg_bits pplm_reg;
8695         struct mlx5_ifc_pplr_reg_bits pplr_reg;
8696         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8697         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8698         struct mlx5_ifc_pspa_reg_bits pspa_reg;
8699         struct mlx5_ifc_ptas_reg_bits ptas_reg;
8700         struct mlx5_ifc_ptys_reg_bits ptys_reg;
8701         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8702         struct mlx5_ifc_pude_reg_bits pude_reg;
8703         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8704         struct mlx5_ifc_slrg_reg_bits slrg_reg;
8705         struct mlx5_ifc_sltp_reg_bits sltp_reg;
8706         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8707         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8708         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8709         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8710         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8711         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8712         struct mlx5_ifc_mcc_reg_bits mcc_reg;
8713         struct mlx5_ifc_mcda_reg_bits mcda_reg;
8714         u8         reserved_at_0[0x60e0];
8715 };
8716
8717 union mlx5_ifc_debug_enhancements_document_bits {
8718         struct mlx5_ifc_health_buffer_bits health_buffer;
8719         u8         reserved_at_0[0x200];
8720 };
8721
8722 union mlx5_ifc_uplink_pci_interface_document_bits {
8723         struct mlx5_ifc_initial_seg_bits initial_seg;
8724         u8         reserved_at_0[0x20060];
8725 };
8726
8727 struct mlx5_ifc_set_flow_table_root_out_bits {
8728         u8         status[0x8];
8729         u8         reserved_at_8[0x18];
8730
8731         u8         syndrome[0x20];
8732
8733         u8         reserved_at_40[0x40];
8734 };
8735
8736 struct mlx5_ifc_set_flow_table_root_in_bits {
8737         u8         opcode[0x10];
8738         u8         reserved_at_10[0x10];
8739
8740         u8         reserved_at_20[0x10];
8741         u8         op_mod[0x10];
8742
8743         u8         other_vport[0x1];
8744         u8         reserved_at_41[0xf];
8745         u8         vport_number[0x10];
8746
8747         u8         reserved_at_60[0x20];
8748
8749         u8         table_type[0x8];
8750         u8         reserved_at_88[0x18];
8751
8752         u8         reserved_at_a0[0x8];
8753         u8         table_id[0x18];
8754
8755         u8         reserved_at_c0[0x8];
8756         u8         underlay_qpn[0x18];
8757         u8         reserved_at_e0[0x120];
8758 };
8759
8760 enum {
8761         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
8762         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8763 };
8764
8765 struct mlx5_ifc_modify_flow_table_out_bits {
8766         u8         status[0x8];
8767         u8         reserved_at_8[0x18];
8768
8769         u8         syndrome[0x20];
8770
8771         u8         reserved_at_40[0x40];
8772 };
8773
8774 struct mlx5_ifc_modify_flow_table_in_bits {
8775         u8         opcode[0x10];
8776         u8         reserved_at_10[0x10];
8777
8778         u8         reserved_at_20[0x10];
8779         u8         op_mod[0x10];
8780
8781         u8         other_vport[0x1];
8782         u8         reserved_at_41[0xf];
8783         u8         vport_number[0x10];
8784
8785         u8         reserved_at_60[0x10];
8786         u8         modify_field_select[0x10];
8787
8788         u8         table_type[0x8];
8789         u8         reserved_at_88[0x18];
8790
8791         u8         reserved_at_a0[0x8];
8792         u8         table_id[0x18];
8793
8794         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8795 };
8796
8797 struct mlx5_ifc_ets_tcn_config_reg_bits {
8798         u8         g[0x1];
8799         u8         b[0x1];
8800         u8         r[0x1];
8801         u8         reserved_at_3[0x9];
8802         u8         group[0x4];
8803         u8         reserved_at_10[0x9];
8804         u8         bw_allocation[0x7];
8805
8806         u8         reserved_at_20[0xc];
8807         u8         max_bw_units[0x4];
8808         u8         reserved_at_30[0x8];
8809         u8         max_bw_value[0x8];
8810 };
8811
8812 struct mlx5_ifc_ets_global_config_reg_bits {
8813         u8         reserved_at_0[0x2];
8814         u8         r[0x1];
8815         u8         reserved_at_3[0x1d];
8816
8817         u8         reserved_at_20[0xc];
8818         u8         max_bw_units[0x4];
8819         u8         reserved_at_30[0x8];
8820         u8         max_bw_value[0x8];
8821 };
8822
8823 struct mlx5_ifc_qetc_reg_bits {
8824         u8                                         reserved_at_0[0x8];
8825         u8                                         port_number[0x8];
8826         u8                                         reserved_at_10[0x30];
8827
8828         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
8829         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8830 };
8831
8832 struct mlx5_ifc_qpdpm_dscp_reg_bits {
8833         u8         e[0x1];
8834         u8         reserved_at_01[0x0b];
8835         u8         prio[0x04];
8836 };
8837
8838 struct mlx5_ifc_qpdpm_reg_bits {
8839         u8                                     reserved_at_0[0x8];
8840         u8                                     local_port[0x8];
8841         u8                                     reserved_at_10[0x10];
8842         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
8843 };
8844
8845 struct mlx5_ifc_qpts_reg_bits {
8846         u8         reserved_at_0[0x8];
8847         u8         local_port[0x8];
8848         u8         reserved_at_10[0x2d];
8849         u8         trust_state[0x3];
8850 };
8851
8852 struct mlx5_ifc_pptb_reg_bits {
8853         u8         reserved_at_0[0x2];
8854         u8         mm[0x2];
8855         u8         reserved_at_4[0x4];
8856         u8         local_port[0x8];
8857         u8         reserved_at_10[0x6];
8858         u8         cm[0x1];
8859         u8         um[0x1];
8860         u8         pm[0x8];
8861
8862         u8         prio_x_buff[0x20];
8863
8864         u8         pm_msb[0x8];
8865         u8         reserved_at_48[0x10];
8866         u8         ctrl_buff[0x4];
8867         u8         untagged_buff[0x4];
8868 };
8869
8870 struct mlx5_ifc_pbmc_reg_bits {
8871         u8         reserved_at_0[0x8];
8872         u8         local_port[0x8];
8873         u8         reserved_at_10[0x10];
8874
8875         u8         xoff_timer_value[0x10];
8876         u8         xoff_refresh[0x10];
8877
8878         u8         reserved_at_40[0x9];
8879         u8         fullness_threshold[0x7];
8880         u8         port_buffer_size[0x10];
8881
8882         struct mlx5_ifc_bufferx_reg_bits buffer[10];
8883
8884         u8         reserved_at_2e0[0x40];
8885 };
8886
8887 struct mlx5_ifc_qtct_reg_bits {
8888         u8         reserved_at_0[0x8];
8889         u8         port_number[0x8];
8890         u8         reserved_at_10[0xd];
8891         u8         prio[0x3];
8892
8893         u8         reserved_at_20[0x1d];
8894         u8         tclass[0x3];
8895 };
8896
8897 struct mlx5_ifc_mcia_reg_bits {
8898         u8         l[0x1];
8899         u8         reserved_at_1[0x7];
8900         u8         module[0x8];
8901         u8         reserved_at_10[0x8];
8902         u8         status[0x8];
8903
8904         u8         i2c_device_address[0x8];
8905         u8         page_number[0x8];
8906         u8         device_address[0x10];
8907
8908         u8         reserved_at_40[0x10];
8909         u8         size[0x10];
8910
8911         u8         reserved_at_60[0x20];
8912
8913         u8         dword_0[0x20];
8914         u8         dword_1[0x20];
8915         u8         dword_2[0x20];
8916         u8         dword_3[0x20];
8917         u8         dword_4[0x20];
8918         u8         dword_5[0x20];
8919         u8         dword_6[0x20];
8920         u8         dword_7[0x20];
8921         u8         dword_8[0x20];
8922         u8         dword_9[0x20];
8923         u8         dword_10[0x20];
8924         u8         dword_11[0x20];
8925 };
8926
8927 struct mlx5_ifc_dcbx_param_bits {
8928         u8         dcbx_cee_cap[0x1];
8929         u8         dcbx_ieee_cap[0x1];
8930         u8         dcbx_standby_cap[0x1];
8931         u8         reserved_at_0[0x5];
8932         u8         port_number[0x8];
8933         u8         reserved_at_10[0xa];
8934         u8         max_application_table_size[6];
8935         u8         reserved_at_20[0x15];
8936         u8         version_oper[0x3];
8937         u8         reserved_at_38[5];
8938         u8         version_admin[0x3];
8939         u8         willing_admin[0x1];
8940         u8         reserved_at_41[0x3];
8941         u8         pfc_cap_oper[0x4];
8942         u8         reserved_at_48[0x4];
8943         u8         pfc_cap_admin[0x4];
8944         u8         reserved_at_50[0x4];
8945         u8         num_of_tc_oper[0x4];
8946         u8         reserved_at_58[0x4];
8947         u8         num_of_tc_admin[0x4];
8948         u8         remote_willing[0x1];
8949         u8         reserved_at_61[3];
8950         u8         remote_pfc_cap[4];
8951         u8         reserved_at_68[0x14];
8952         u8         remote_num_of_tc[0x4];
8953         u8         reserved_at_80[0x18];
8954         u8         error[0x8];
8955         u8         reserved_at_a0[0x160];
8956 };
8957
8958 struct mlx5_ifc_lagc_bits {
8959         u8         reserved_at_0[0x1d];
8960         u8         lag_state[0x3];
8961
8962         u8         reserved_at_20[0x14];
8963         u8         tx_remap_affinity_2[0x4];
8964         u8         reserved_at_38[0x4];
8965         u8         tx_remap_affinity_1[0x4];
8966 };
8967
8968 struct mlx5_ifc_create_lag_out_bits {
8969         u8         status[0x8];
8970         u8         reserved_at_8[0x18];
8971
8972         u8         syndrome[0x20];
8973
8974         u8         reserved_at_40[0x40];
8975 };
8976
8977 struct mlx5_ifc_create_lag_in_bits {
8978         u8         opcode[0x10];
8979         u8         reserved_at_10[0x10];
8980
8981         u8         reserved_at_20[0x10];
8982         u8         op_mod[0x10];
8983
8984         struct mlx5_ifc_lagc_bits ctx;
8985 };
8986
8987 struct mlx5_ifc_modify_lag_out_bits {
8988         u8         status[0x8];
8989         u8         reserved_at_8[0x18];
8990
8991         u8         syndrome[0x20];
8992
8993         u8         reserved_at_40[0x40];
8994 };
8995
8996 struct mlx5_ifc_modify_lag_in_bits {
8997         u8         opcode[0x10];
8998         u8         reserved_at_10[0x10];
8999
9000         u8         reserved_at_20[0x10];
9001         u8         op_mod[0x10];
9002
9003         u8         reserved_at_40[0x20];
9004         u8         field_select[0x20];
9005
9006         struct mlx5_ifc_lagc_bits ctx;
9007 };
9008
9009 struct mlx5_ifc_query_lag_out_bits {
9010         u8         status[0x8];
9011         u8         reserved_at_8[0x18];
9012
9013         u8         syndrome[0x20];
9014
9015         u8         reserved_at_40[0x40];
9016
9017         struct mlx5_ifc_lagc_bits ctx;
9018 };
9019
9020 struct mlx5_ifc_query_lag_in_bits {
9021         u8         opcode[0x10];
9022         u8         reserved_at_10[0x10];
9023
9024         u8         reserved_at_20[0x10];
9025         u8         op_mod[0x10];
9026
9027         u8         reserved_at_40[0x40];
9028 };
9029
9030 struct mlx5_ifc_destroy_lag_out_bits {
9031         u8         status[0x8];
9032         u8         reserved_at_8[0x18];
9033
9034         u8         syndrome[0x20];
9035
9036         u8         reserved_at_40[0x40];
9037 };
9038
9039 struct mlx5_ifc_destroy_lag_in_bits {
9040         u8         opcode[0x10];
9041         u8         reserved_at_10[0x10];
9042
9043         u8         reserved_at_20[0x10];
9044         u8         op_mod[0x10];
9045
9046         u8         reserved_at_40[0x40];
9047 };
9048
9049 struct mlx5_ifc_create_vport_lag_out_bits {
9050         u8         status[0x8];
9051         u8         reserved_at_8[0x18];
9052
9053         u8         syndrome[0x20];
9054
9055         u8         reserved_at_40[0x40];
9056 };
9057
9058 struct mlx5_ifc_create_vport_lag_in_bits {
9059         u8         opcode[0x10];
9060         u8         reserved_at_10[0x10];
9061
9062         u8         reserved_at_20[0x10];
9063         u8         op_mod[0x10];
9064
9065         u8         reserved_at_40[0x40];
9066 };
9067
9068 struct mlx5_ifc_destroy_vport_lag_out_bits {
9069         u8         status[0x8];
9070         u8         reserved_at_8[0x18];
9071
9072         u8         syndrome[0x20];
9073
9074         u8         reserved_at_40[0x40];
9075 };
9076
9077 struct mlx5_ifc_destroy_vport_lag_in_bits {
9078         u8         opcode[0x10];
9079         u8         reserved_at_10[0x10];
9080
9081         u8         reserved_at_20[0x10];
9082         u8         op_mod[0x10];
9083
9084         u8         reserved_at_40[0x40];
9085 };
9086
9087 struct mlx5_ifc_alloc_memic_in_bits {
9088         u8         opcode[0x10];
9089         u8         reserved_at_10[0x10];
9090
9091         u8         reserved_at_20[0x10];
9092         u8         op_mod[0x10];
9093
9094         u8         reserved_at_30[0x20];
9095
9096         u8         reserved_at_40[0x18];
9097         u8         log_memic_addr_alignment[0x8];
9098
9099         u8         range_start_addr[0x40];
9100
9101         u8         range_size[0x20];
9102
9103         u8         memic_size[0x20];
9104 };
9105
9106 struct mlx5_ifc_alloc_memic_out_bits {
9107         u8         status[0x8];
9108         u8         reserved_at_8[0x18];
9109
9110         u8         syndrome[0x20];
9111
9112         u8         memic_start_addr[0x40];
9113 };
9114
9115 struct mlx5_ifc_dealloc_memic_in_bits {
9116         u8         opcode[0x10];
9117         u8         reserved_at_10[0x10];
9118
9119         u8         reserved_at_20[0x10];
9120         u8         op_mod[0x10];
9121
9122         u8         reserved_at_40[0x40];
9123
9124         u8         memic_start_addr[0x40];
9125
9126         u8         memic_size[0x20];
9127
9128         u8         reserved_at_e0[0x20];
9129 };
9130
9131 struct mlx5_ifc_dealloc_memic_out_bits {
9132         u8         status[0x8];
9133         u8         reserved_at_8[0x18];
9134
9135         u8         syndrome[0x20];
9136
9137         u8         reserved_at_40[0x40];
9138 };
9139
9140 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9141         u8         opcode[0x10];
9142         u8         uid[0x10];
9143
9144         u8         reserved_at_20[0x10];
9145         u8         obj_type[0x10];
9146
9147         u8         obj_id[0x20];
9148
9149         u8         reserved_at_60[0x20];
9150 };
9151
9152 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9153         u8         status[0x8];
9154         u8         reserved_at_8[0x18];
9155
9156         u8         syndrome[0x20];
9157
9158         u8         obj_id[0x20];
9159
9160         u8         reserved_at_60[0x20];
9161 };
9162
9163 struct mlx5_ifc_umem_bits {
9164         u8         modify_field_select[0x40];
9165
9166         u8         reserved_at_40[0x5b];
9167         u8         log_page_size[0x5];
9168
9169         u8         page_offset[0x20];
9170
9171         u8         num_of_mtt[0x40];
9172
9173         struct mlx5_ifc_mtt_bits  mtt[0];
9174 };
9175
9176 struct mlx5_ifc_uctx_bits {
9177         u8         modify_field_select[0x40];
9178
9179         u8         reserved_at_40[0x1c0];
9180 };
9181
9182 struct mlx5_ifc_create_umem_in_bits {
9183         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
9184         struct mlx5_ifc_umem_bits                     umem;
9185 };
9186
9187 struct mlx5_ifc_create_uctx_in_bits {
9188         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
9189         struct mlx5_ifc_uctx_bits                     uctx;
9190 };
9191
9192 struct mlx5_ifc_mtrc_string_db_param_bits {
9193         u8         string_db_base_address[0x20];
9194
9195         u8         reserved_at_20[0x8];
9196         u8         string_db_size[0x18];
9197 };
9198
9199 struct mlx5_ifc_mtrc_cap_bits {
9200         u8         trace_owner[0x1];
9201         u8         trace_to_memory[0x1];
9202         u8         reserved_at_2[0x4];
9203         u8         trc_ver[0x2];
9204         u8         reserved_at_8[0x14];
9205         u8         num_string_db[0x4];
9206
9207         u8         first_string_trace[0x8];
9208         u8         num_string_trace[0x8];
9209         u8         reserved_at_30[0x28];
9210
9211         u8         log_max_trace_buffer_size[0x8];
9212
9213         u8         reserved_at_60[0x20];
9214
9215         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
9216
9217         u8         reserved_at_280[0x180];
9218 };
9219
9220 struct mlx5_ifc_mtrc_conf_bits {
9221         u8         reserved_at_0[0x1c];
9222         u8         trace_mode[0x4];
9223         u8         reserved_at_20[0x18];
9224         u8         log_trace_buffer_size[0x8];
9225         u8         trace_mkey[0x20];
9226         u8         reserved_at_60[0x3a0];
9227 };
9228
9229 struct mlx5_ifc_mtrc_stdb_bits {
9230         u8         string_db_index[0x4];
9231         u8         reserved_at_4[0x4];
9232         u8         read_size[0x18];
9233         u8         start_offset[0x20];
9234         u8         string_db_data[0];
9235 };
9236
9237 struct mlx5_ifc_mtrc_ctrl_bits {
9238         u8         trace_status[0x2];
9239         u8         reserved_at_2[0x2];
9240         u8         arm_event[0x1];
9241         u8         reserved_at_5[0xb];
9242         u8         modify_field_select[0x10];
9243         u8         reserved_at_20[0x2b];
9244         u8         current_timestamp52_32[0x15];
9245         u8         current_timestamp31_0[0x20];
9246         u8         reserved_at_80[0x180];
9247 };
9248
9249 #endif /* MLX5_IFC_H */