include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  68         MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
  69         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  70         MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
  71         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2       = 0x20,
  72         MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION       = 0x25,
  73 };
  74
  75 enum {
  76         MLX5_SHARED_RESOURCE_UID = 0xffff,
  77 };
  78
  79 enum {
  80         MLX5_OBJ_TYPE_SW_ICM = 0x0008,
  81 };
  82
  83 enum {
  84         MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
  85         MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
  86         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
  87         MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
  88 };
  89
  90 enum {
  91         MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
  92         MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
  93         MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
  94         MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
  95         MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
  96         MLX5_OBJ_TYPE_MKEY = 0xff01,
  97         MLX5_OBJ_TYPE_QP = 0xff02,
  98         MLX5_OBJ_TYPE_PSV = 0xff03,
  99         MLX5_OBJ_TYPE_RMP = 0xff04,
 100         MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
 101         MLX5_OBJ_TYPE_RQ = 0xff06,
 102         MLX5_OBJ_TYPE_SQ = 0xff07,
 103         MLX5_OBJ_TYPE_TIR = 0xff08,
 104         MLX5_OBJ_TYPE_TIS = 0xff09,
 105         MLX5_OBJ_TYPE_DCT = 0xff0a,
 106         MLX5_OBJ_TYPE_XRQ = 0xff0b,
 107         MLX5_OBJ_TYPE_RQT = 0xff0e,
 108         MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
 109         MLX5_OBJ_TYPE_CQ = 0xff10,
 110 };
 111
 112 enum {
 113         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
 114         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
 115         MLX5_CMD_OP_INIT_HCA                      = 0x102,
 116         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
 117         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
 118         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
 119         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
 120         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 121         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 122         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 123         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 124         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 125         MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
 126         MLX5_CMD_OP_ALLOC_SF                      = 0x113,
 127         MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
 128         MLX5_CMD_OP_SUSPEND_VHCA                  = 0x115,
 129         MLX5_CMD_OP_RESUME_VHCA                   = 0x116,
 130         MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE    = 0x117,
 131         MLX5_CMD_OP_SAVE_VHCA_STATE               = 0x118,
 132         MLX5_CMD_OP_LOAD_VHCA_STATE               = 0x119,
 133         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 134         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 135         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 136         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 137         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 138         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 139         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 140         MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
 141         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 142         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 143         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 144         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 145         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 146         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 147         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 148         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 149         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 150         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 151         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 152         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 153         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 154         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 155         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 156         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 157         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 158         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 159         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 160         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 161         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 162         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 163         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 164         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 165         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 166         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 167         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 168         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 169         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 170         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 171         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 172         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 173         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 174         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 175         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 176         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 177         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 178         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 179         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 180         MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
 181         MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
 182         MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
 183         MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
 184         MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
 185         MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
 186         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 187         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 188         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 189         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 190         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 191         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 192         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 193         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 194         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 195         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 196         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 197         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 198         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 199         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 200         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 201         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 202         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 203         MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
 204         MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
 205         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 206         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 207         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 208         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 209         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 210         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 211         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 212         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 213         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 214         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 215         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 216         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 217         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 218         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 219         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 220         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 221         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 222         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 223         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 224         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 225         MLX5_CMD_OP_NOP                           = 0x80d,
 226         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 227         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 228         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 229         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 230         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 231         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 232         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 233         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 234         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 235         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 236         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 237         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 238         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 239         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 240         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 241         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 242         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 243         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 244         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 245         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 246         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 247         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 248         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 249         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 250         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 251         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 252         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 253         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 254         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 255         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 256         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 257         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 258         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 259         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 260         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 261         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 262         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 263         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 264         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 265         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 266         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 267         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 268         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 269         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 270         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 271         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 272         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 273         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 274         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 275         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 276         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 277         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 278         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 279         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 280         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 281         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 282         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 283         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 284         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 285         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 286         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 287         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 288         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 289         MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
 290         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 291         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 292         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 293         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 294         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 295         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 296         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 297         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 298         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 299         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 300         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 301         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 302         MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
 303         MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
 304         MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
 305         MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
 306         MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
 307         MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
 308         MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
 309         MLX5_CMD_OP_MAX
 310 };
 311
 312 /* Valid range for general commands that don't work over an object */
 313 enum {
 314         MLX5_CMD_OP_GENERAL_START = 0xb00,
 315         MLX5_CMD_OP_GENERAL_END = 0xd00,
 316 };
 317
 318 struct mlx5_ifc_flow_table_fields_supported_bits {
 319         u8         outer_dmac[0x1];
 320         u8         outer_smac[0x1];
 321         u8         outer_ether_type[0x1];
 322         u8         outer_ip_version[0x1];
 323         u8         outer_first_prio[0x1];
 324         u8         outer_first_cfi[0x1];
 325         u8         outer_first_vid[0x1];
 326         u8         outer_ipv4_ttl[0x1];
 327         u8         outer_second_prio[0x1];
 328         u8         outer_second_cfi[0x1];
 329         u8         outer_second_vid[0x1];
 330         u8         reserved_at_b[0x1];
 331         u8         outer_sip[0x1];
 332         u8         outer_dip[0x1];
 333         u8         outer_frag[0x1];
 334         u8         outer_ip_protocol[0x1];
 335         u8         outer_ip_ecn[0x1];
 336         u8         outer_ip_dscp[0x1];
 337         u8         outer_udp_sport[0x1];
 338         u8         outer_udp_dport[0x1];
 339         u8         outer_tcp_sport[0x1];
 340         u8         outer_tcp_dport[0x1];
 341         u8         outer_tcp_flags[0x1];
 342         u8         outer_gre_protocol[0x1];
 343         u8         outer_gre_key[0x1];
 344         u8         outer_vxlan_vni[0x1];
 345         u8         outer_geneve_vni[0x1];
 346         u8         outer_geneve_oam[0x1];
 347         u8         outer_geneve_protocol_type[0x1];
 348         u8         outer_geneve_opt_len[0x1];
 349         u8         source_vhca_port[0x1];
 350         u8         source_eswitch_port[0x1];
 351
 352         u8         inner_dmac[0x1];
 353         u8         inner_smac[0x1];
 354         u8         inner_ether_type[0x1];
 355         u8         inner_ip_version[0x1];
 356         u8         inner_first_prio[0x1];
 357         u8         inner_first_cfi[0x1];
 358         u8         inner_first_vid[0x1];
 359         u8         reserved_at_27[0x1];
 360         u8         inner_second_prio[0x1];
 361         u8         inner_second_cfi[0x1];
 362         u8         inner_second_vid[0x1];
 363         u8         reserved_at_2b[0x1];
 364         u8         inner_sip[0x1];
 365         u8         inner_dip[0x1];
 366         u8         inner_frag[0x1];
 367         u8         inner_ip_protocol[0x1];
 368         u8         inner_ip_ecn[0x1];
 369         u8         inner_ip_dscp[0x1];
 370         u8         inner_udp_sport[0x1];
 371         u8         inner_udp_dport[0x1];
 372         u8         inner_tcp_sport[0x1];
 373         u8         inner_tcp_dport[0x1];
 374         u8         inner_tcp_flags[0x1];
 375         u8         reserved_at_37[0x9];
 376
 377         u8         geneve_tlv_option_0_data[0x1];
 378         u8         geneve_tlv_option_0_exist[0x1];
 379         u8         reserved_at_42[0x3];
 380         u8         outer_first_mpls_over_udp[0x4];
 381         u8         outer_first_mpls_over_gre[0x4];
 382         u8         inner_first_mpls[0x4];
 383         u8         outer_first_mpls[0x4];
 384         u8         reserved_at_55[0x2];
 385         u8         outer_esp_spi[0x1];
 386         u8         reserved_at_58[0x2];
 387         u8         bth_dst_qp[0x1];
 388         u8         reserved_at_5b[0x5];
 389
 390         u8         reserved_at_60[0x18];
 391         u8         metadata_reg_c_7[0x1];
 392         u8         metadata_reg_c_6[0x1];
 393         u8         metadata_reg_c_5[0x1];
 394         u8         metadata_reg_c_4[0x1];
 395         u8         metadata_reg_c_3[0x1];
 396         u8         metadata_reg_c_2[0x1];
 397         u8         metadata_reg_c_1[0x1];
 398         u8         metadata_reg_c_0[0x1];
 399 };
 400
 401 struct mlx5_ifc_flow_table_fields_supported_2_bits {
 402         u8         reserved_at_0[0xe];
 403         u8         bth_opcode[0x1];
 404         u8         reserved_at_f[0x11];
 405
 406         u8         reserved_at_20[0x60];
 407 };
 408
 409 struct mlx5_ifc_flow_table_prop_layout_bits {
 410         u8         ft_support[0x1];
 411         u8         reserved_at_1[0x1];
 412         u8         flow_counter[0x1];
 413         u8         flow_modify_en[0x1];
 414         u8         modify_root[0x1];
 415         u8         identified_miss_table_mode[0x1];
 416         u8         flow_table_modify[0x1];
 417         u8         reformat[0x1];
 418         u8         decap[0x1];
 419         u8         reserved_at_9[0x1];
 420         u8         pop_vlan[0x1];
 421         u8         push_vlan[0x1];
 422         u8         reserved_at_c[0x1];
 423         u8         pop_vlan_2[0x1];
 424         u8         push_vlan_2[0x1];
 425         u8         reformat_and_vlan_action[0x1];
 426         u8         reserved_at_10[0x1];
 427         u8         sw_owner[0x1];
 428         u8         reformat_l3_tunnel_to_l2[0x1];
 429         u8         reformat_l2_to_l3_tunnel[0x1];
 430         u8         reformat_and_modify_action[0x1];
 431         u8         ignore_flow_level[0x1];
 432         u8         reserved_at_16[0x1];
 433         u8         table_miss_action_domain[0x1];
 434         u8         termination_table[0x1];
 435         u8         reformat_and_fwd_to_table[0x1];
 436         u8         reserved_at_1a[0x2];
 437         u8         ipsec_encrypt[0x1];
 438         u8         ipsec_decrypt[0x1];
 439         u8         sw_owner_v2[0x1];
 440         u8         reserved_at_1f[0x1];
 441
 442         u8         termination_table_raw_traffic[0x1];
 443         u8         reserved_at_21[0x1];
 444         u8         log_max_ft_size[0x6];
 445         u8         log_max_modify_header_context[0x8];
 446         u8         max_modify_header_actions[0x8];
 447         u8         max_ft_level[0x8];
 448
 449         u8         reformat_add_esp_trasport[0x1];
 450         u8         reserved_at_41[0x2];
 451         u8         reformat_del_esp_trasport[0x1];
 452         u8         reserved_at_44[0x2];
 453         u8         execute_aso[0x1];
 454         u8         reserved_at_47[0x19];
 455
 456         u8         reserved_at_60[0x2];
 457         u8         reformat_insert[0x1];
 458         u8         reformat_remove[0x1];
 459         u8         macsec_encrypt[0x1];
 460         u8         macsec_decrypt[0x1];
 461         u8         reserved_at_66[0x2];
 462         u8         reformat_add_macsec[0x1];
 463         u8         reformat_remove_macsec[0x1];
 464         u8         reserved_at_6a[0xe];
 465         u8         log_max_ft_num[0x8];
 466
 467         u8         reserved_at_80[0x10];
 468         u8         log_max_flow_counter[0x8];
 469         u8         log_max_destination[0x8];
 470
 471         u8         reserved_at_a0[0x18];
 472         u8         log_max_flow[0x8];
 473
 474         u8         reserved_at_c0[0x40];
 475
 476         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 477
 478         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 479 };
 480
 481 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 482         u8         send[0x1];
 483         u8         receive[0x1];
 484         u8         write[0x1];
 485         u8         read[0x1];
 486         u8         atomic[0x1];
 487         u8         srq_receive[0x1];
 488         u8         reserved_at_6[0x1a];
 489 };
 490
 491 struct mlx5_ifc_ipv4_layout_bits {
 492         u8         reserved_at_0[0x60];
 493
 494         u8         ipv4[0x20];
 495 };
 496
 497 struct mlx5_ifc_ipv6_layout_bits {
 498         u8         ipv6[16][0x8];
 499 };
 500
 501 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 502         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 503         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 504         u8         reserved_at_0[0x80];
 505 };
 506
 507 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 508         u8         smac_47_16[0x20];
 509
 510         u8         smac_15_0[0x10];
 511         u8         ethertype[0x10];
 512
 513         u8         dmac_47_16[0x20];
 514
 515         u8         dmac_15_0[0x10];
 516         u8         first_prio[0x3];
 517         u8         first_cfi[0x1];
 518         u8         first_vid[0xc];
 519
 520         u8         ip_protocol[0x8];
 521         u8         ip_dscp[0x6];
 522         u8         ip_ecn[0x2];
 523         u8         cvlan_tag[0x1];
 524         u8         svlan_tag[0x1];
 525         u8         frag[0x1];
 526         u8         ip_version[0x4];
 527         u8         tcp_flags[0x9];
 528
 529         u8         tcp_sport[0x10];
 530         u8         tcp_dport[0x10];
 531
 532         u8         reserved_at_c0[0x10];
 533         u8         ipv4_ihl[0x4];
 534         u8         reserved_at_c4[0x4];
 535
 536         u8         ttl_hoplimit[0x8];
 537
 538         u8         udp_sport[0x10];
 539         u8         udp_dport[0x10];
 540
 541         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 542
 543         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 544 };
 545
 546 struct mlx5_ifc_nvgre_key_bits {
 547         u8 hi[0x18];
 548         u8 lo[0x8];
 549 };
 550
 551 union mlx5_ifc_gre_key_bits {
 552         struct mlx5_ifc_nvgre_key_bits nvgre;
 553         u8 key[0x20];
 554 };
 555
 556 struct mlx5_ifc_fte_match_set_misc_bits {
 557         u8         gre_c_present[0x1];
 558         u8         reserved_at_1[0x1];
 559         u8         gre_k_present[0x1];
 560         u8         gre_s_present[0x1];
 561         u8         source_vhca_port[0x4];
 562         u8         source_sqn[0x18];
 563
 564         u8         source_eswitch_owner_vhca_id[0x10];
 565         u8         source_port[0x10];
 566
 567         u8         outer_second_prio[0x3];
 568         u8         outer_second_cfi[0x1];
 569         u8         outer_second_vid[0xc];
 570         u8         inner_second_prio[0x3];
 571         u8         inner_second_cfi[0x1];
 572         u8         inner_second_vid[0xc];
 573
 574         u8         outer_second_cvlan_tag[0x1];
 575         u8         inner_second_cvlan_tag[0x1];
 576         u8         outer_second_svlan_tag[0x1];
 577         u8         inner_second_svlan_tag[0x1];
 578         u8         reserved_at_64[0xc];
 579         u8         gre_protocol[0x10];
 580
 581         union mlx5_ifc_gre_key_bits gre_key;
 582
 583         u8         vxlan_vni[0x18];
 584         u8         bth_opcode[0x8];
 585
 586         u8         geneve_vni[0x18];
 587         u8         reserved_at_d8[0x6];
 588         u8         geneve_tlv_option_0_exist[0x1];
 589         u8         geneve_oam[0x1];
 590
 591         u8         reserved_at_e0[0xc];
 592         u8         outer_ipv6_flow_label[0x14];
 593
 594         u8         reserved_at_100[0xc];
 595         u8         inner_ipv6_flow_label[0x14];
 596
 597         u8         reserved_at_120[0xa];
 598         u8         geneve_opt_len[0x6];
 599         u8         geneve_protocol_type[0x10];
 600
 601         u8         reserved_at_140[0x8];
 602         u8         bth_dst_qp[0x18];
 603         u8         reserved_at_160[0x20];
 604         u8         outer_esp_spi[0x20];
 605         u8         reserved_at_1a0[0x60];
 606 };
 607
 608 struct mlx5_ifc_fte_match_mpls_bits {
 609         u8         mpls_label[0x14];
 610         u8         mpls_exp[0x3];
 611         u8         mpls_s_bos[0x1];
 612         u8         mpls_ttl[0x8];
 613 };
 614
 615 struct mlx5_ifc_fte_match_set_misc2_bits {
 616         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 617
 618         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 619
 620         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 621
 622         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 623
 624         u8         metadata_reg_c_7[0x20];
 625
 626         u8         metadata_reg_c_6[0x20];
 627
 628         u8         metadata_reg_c_5[0x20];
 629
 630         u8         metadata_reg_c_4[0x20];
 631
 632         u8         metadata_reg_c_3[0x20];
 633
 634         u8         metadata_reg_c_2[0x20];
 635
 636         u8         metadata_reg_c_1[0x20];
 637
 638         u8         metadata_reg_c_0[0x20];
 639
 640         u8         metadata_reg_a[0x20];
 641
 642         u8         reserved_at_1a0[0x8];
 643
 644         u8         macsec_syndrome[0x8];
 645         u8         ipsec_syndrome[0x8];
 646         u8         reserved_at_1b8[0x8];
 647
 648         u8         reserved_at_1c0[0x40];
 649 };
 650
 651 struct mlx5_ifc_fte_match_set_misc3_bits {
 652         u8         inner_tcp_seq_num[0x20];
 653
 654         u8         outer_tcp_seq_num[0x20];
 655
 656         u8         inner_tcp_ack_num[0x20];
 657
 658         u8         outer_tcp_ack_num[0x20];
 659
 660         u8         reserved_at_80[0x8];
 661         u8         outer_vxlan_gpe_vni[0x18];
 662
 663         u8         outer_vxlan_gpe_next_protocol[0x8];
 664         u8         outer_vxlan_gpe_flags[0x8];
 665         u8         reserved_at_b0[0x10];
 666
 667         u8         icmp_header_data[0x20];
 668
 669         u8         icmpv6_header_data[0x20];
 670
 671         u8         icmp_type[0x8];
 672         u8         icmp_code[0x8];
 673         u8         icmpv6_type[0x8];
 674         u8         icmpv6_code[0x8];
 675
 676         u8         geneve_tlv_option_0_data[0x20];
 677
 678         u8         gtpu_teid[0x20];
 679
 680         u8         gtpu_msg_type[0x8];
 681         u8         gtpu_msg_flags[0x8];
 682         u8         reserved_at_170[0x10];
 683
 684         u8         gtpu_dw_2[0x20];
 685
 686         u8         gtpu_first_ext_dw_0[0x20];
 687
 688         u8         gtpu_dw_0[0x20];
 689
 690         u8         reserved_at_1e0[0x20];
 691 };
 692
 693 struct mlx5_ifc_fte_match_set_misc4_bits {
 694         u8         prog_sample_field_value_0[0x20];
 695
 696         u8         prog_sample_field_id_0[0x20];
 697
 698         u8         prog_sample_field_value_1[0x20];
 699
 700         u8         prog_sample_field_id_1[0x20];
 701
 702         u8         prog_sample_field_value_2[0x20];
 703
 704         u8         prog_sample_field_id_2[0x20];
 705
 706         u8         prog_sample_field_value_3[0x20];
 707
 708         u8         prog_sample_field_id_3[0x20];
 709
 710         u8         reserved_at_100[0x100];
 711 };
 712
 713 struct mlx5_ifc_fte_match_set_misc5_bits {
 714         u8         macsec_tag_0[0x20];
 715
 716         u8         macsec_tag_1[0x20];
 717
 718         u8         macsec_tag_2[0x20];
 719
 720         u8         macsec_tag_3[0x20];
 721
 722         u8         tunnel_header_0[0x20];
 723
 724         u8         tunnel_header_1[0x20];
 725
 726         u8         tunnel_header_2[0x20];
 727
 728         u8         tunnel_header_3[0x20];
 729
 730         u8         reserved_at_100[0x100];
 731 };
 732
 733 struct mlx5_ifc_cmd_pas_bits {
 734         u8         pa_h[0x20];
 735
 736         u8         pa_l[0x14];
 737         u8         reserved_at_34[0xc];
 738 };
 739
 740 struct mlx5_ifc_uint64_bits {
 741         u8         hi[0x20];
 742
 743         u8         lo[0x20];
 744 };
 745
 746 enum {
 747         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 748         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 749         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 750         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 751         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 752         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 753         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 754         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 755         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 756         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 757 };
 758
 759 struct mlx5_ifc_ads_bits {
 760         u8         fl[0x1];
 761         u8         free_ar[0x1];
 762         u8         reserved_at_2[0xe];
 763         u8         pkey_index[0x10];
 764
 765         u8         reserved_at_20[0x8];
 766         u8         grh[0x1];
 767         u8         mlid[0x7];
 768         u8         rlid[0x10];
 769
 770         u8         ack_timeout[0x5];
 771         u8         reserved_at_45[0x3];
 772         u8         src_addr_index[0x8];
 773         u8         reserved_at_50[0x4];
 774         u8         stat_rate[0x4];
 775         u8         hop_limit[0x8];
 776
 777         u8         reserved_at_60[0x4];
 778         u8         tclass[0x8];
 779         u8         flow_label[0x14];
 780
 781         u8         rgid_rip[16][0x8];
 782
 783         u8         reserved_at_100[0x4];
 784         u8         f_dscp[0x1];
 785         u8         f_ecn[0x1];
 786         u8         reserved_at_106[0x1];
 787         u8         f_eth_prio[0x1];
 788         u8         ecn[0x2];
 789         u8         dscp[0x6];
 790         u8         udp_sport[0x10];
 791
 792         u8         dei_cfi[0x1];
 793         u8         eth_prio[0x3];
 794         u8         sl[0x4];
 795         u8         vhca_port_num[0x8];
 796         u8         rmac_47_32[0x10];
 797
 798         u8         rmac_31_0[0x20];
 799 };
 800
 801 struct mlx5_ifc_flow_table_nic_cap_bits {
 802         u8         nic_rx_multi_path_tirs[0x1];
 803         u8         nic_rx_multi_path_tirs_fts[0x1];
 804         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 805         u8         reserved_at_3[0x4];
 806         u8         sw_owner_reformat_supported[0x1];
 807         u8         reserved_at_8[0x18];
 808
 809         u8         encap_general_header[0x1];
 810         u8         reserved_at_21[0xa];
 811         u8         log_max_packet_reformat_context[0x5];
 812         u8         reserved_at_30[0x6];
 813         u8         max_encap_header_size[0xa];
 814         u8         reserved_at_40[0x1c0];
 815
 816         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 817
 818         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 819
 820         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 821
 822         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 823
 824         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 825
 826         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 827
 828         u8         reserved_at_e00[0x700];
 829
 830         struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
 831
 832         u8         reserved_at_1580[0x280];
 833
 834         struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
 835
 836         u8         reserved_at_1880[0x780];
 837
 838         u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
 839
 840         u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
 841
 842         u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
 843
 844         u8         reserved_at_20c0[0x5f40];
 845 };
 846
 847 struct mlx5_ifc_port_selection_cap_bits {
 848         u8         reserved_at_0[0x10];
 849         u8         port_select_flow_table[0x1];
 850         u8         reserved_at_11[0x1];
 851         u8         port_select_flow_table_bypass[0x1];
 852         u8         reserved_at_13[0xd];
 853
 854         u8         reserved_at_20[0x1e0];
 855
 856         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
 857
 858         u8         reserved_at_400[0x7c00];
 859 };
 860
 861 enum {
 862         MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
 863         MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
 864         MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
 865         MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
 866         MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
 867         MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
 868         MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
 869         MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
 870 };
 871
 872 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 873         u8      fdb_to_vport_reg_c_id[0x8];
 874         u8      reserved_at_8[0xd];
 875         u8      fdb_modify_header_fwd_to_table[0x1];
 876         u8      fdb_ipv4_ttl_modify[0x1];
 877         u8      flow_source[0x1];
 878         u8      reserved_at_18[0x2];
 879         u8      multi_fdb_encap[0x1];
 880         u8      egress_acl_forward_to_vport[0x1];
 881         u8      fdb_multi_path_to_table[0x1];
 882         u8      reserved_at_1d[0x3];
 883
 884         u8      reserved_at_20[0x1e0];
 885
 886         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 887
 888         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 889
 890         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 891
 892         u8      reserved_at_800[0x1000];
 893
 894         u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
 895
 896         u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
 897
 898         u8      sw_steering_uplink_icm_address_rx[0x40];
 899
 900         u8      sw_steering_uplink_icm_address_tx[0x40];
 901
 902         u8      reserved_at_1900[0x6700];
 903 };
 904
 905 enum {
 906         MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
 907         MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
 908 };
 909
 910 struct mlx5_ifc_e_switch_cap_bits {
 911         u8         vport_svlan_strip[0x1];
 912         u8         vport_cvlan_strip[0x1];
 913         u8         vport_svlan_insert[0x1];
 914         u8         vport_cvlan_insert_if_not_exist[0x1];
 915         u8         vport_cvlan_insert_overwrite[0x1];
 916         u8         reserved_at_5[0x1];
 917         u8         vport_cvlan_insert_always[0x1];
 918         u8         esw_shared_ingress_acl[0x1];
 919         u8         esw_uplink_ingress_acl[0x1];
 920         u8         root_ft_on_other_esw[0x1];
 921         u8         reserved_at_a[0xf];
 922         u8         esw_functions_changed[0x1];
 923         u8         reserved_at_1a[0x1];
 924         u8         ecpf_vport_exists[0x1];
 925         u8         counter_eswitch_affinity[0x1];
 926         u8         merged_eswitch[0x1];
 927         u8         nic_vport_node_guid_modify[0x1];
 928         u8         nic_vport_port_guid_modify[0x1];
 929
 930         u8         vxlan_encap_decap[0x1];
 931         u8         nvgre_encap_decap[0x1];
 932         u8         reserved_at_22[0x1];
 933         u8         log_max_fdb_encap_uplink[0x5];
 934         u8         reserved_at_21[0x3];
 935         u8         log_max_packet_reformat_context[0x5];
 936         u8         reserved_2b[0x6];
 937         u8         max_encap_header_size[0xa];
 938
 939         u8         reserved_at_40[0xb];
 940         u8         log_max_esw_sf[0x5];
 941         u8         esw_sf_base_id[0x10];
 942
 943         u8         reserved_at_60[0x7a0];
 944
 945 };
 946
 947 struct mlx5_ifc_qos_cap_bits {
 948         u8         packet_pacing[0x1];
 949         u8         esw_scheduling[0x1];
 950         u8         esw_bw_share[0x1];
 951         u8         esw_rate_limit[0x1];
 952         u8         reserved_at_4[0x1];
 953         u8         packet_pacing_burst_bound[0x1];
 954         u8         packet_pacing_typical_size[0x1];
 955         u8         reserved_at_7[0x1];
 956         u8         nic_sq_scheduling[0x1];
 957         u8         nic_bw_share[0x1];
 958         u8         nic_rate_limit[0x1];
 959         u8         packet_pacing_uid[0x1];
 960         u8         log_esw_max_sched_depth[0x4];
 961         u8         reserved_at_10[0x10];
 962
 963         u8         reserved_at_20[0xb];
 964         u8         log_max_qos_nic_queue_group[0x5];
 965         u8         reserved_at_30[0x10];
 966
 967         u8         packet_pacing_max_rate[0x20];
 968
 969         u8         packet_pacing_min_rate[0x20];
 970
 971         u8         reserved_at_80[0x10];
 972         u8         packet_pacing_rate_table_size[0x10];
 973
 974         u8         esw_element_type[0x10];
 975         u8         esw_tsar_type[0x10];
 976
 977         u8         reserved_at_c0[0x10];
 978         u8         max_qos_para_vport[0x10];
 979
 980         u8         max_tsar_bw_share[0x20];
 981
 982         u8         reserved_at_100[0x20];
 983
 984         u8         reserved_at_120[0x3];
 985         u8         log_meter_aso_granularity[0x5];
 986         u8         reserved_at_128[0x3];
 987         u8         log_meter_aso_max_alloc[0x5];
 988         u8         reserved_at_130[0x3];
 989         u8         log_max_num_meter_aso[0x5];
 990         u8         reserved_at_138[0x8];
 991
 992         u8         reserved_at_140[0x6c0];
 993 };
 994
 995 struct mlx5_ifc_debug_cap_bits {
 996         u8         core_dump_general[0x1];
 997         u8         core_dump_qp[0x1];
 998         u8         reserved_at_2[0x7];
 999         u8         resource_dump[0x1];
1000         u8         reserved_at_a[0x16];
1001
1002         u8         reserved_at_20[0x2];
1003         u8         stall_detect[0x1];
1004         u8         reserved_at_23[0x1d];
1005
1006         u8         reserved_at_40[0x7c0];
1007 };
1008
1009 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1010         u8         csum_cap[0x1];
1011         u8         vlan_cap[0x1];
1012         u8         lro_cap[0x1];
1013         u8         lro_psh_flag[0x1];
1014         u8         lro_time_stamp[0x1];
1015         u8         reserved_at_5[0x2];
1016         u8         wqe_vlan_insert[0x1];
1017         u8         self_lb_en_modifiable[0x1];
1018         u8         reserved_at_9[0x2];
1019         u8         max_lso_cap[0x5];
1020         u8         multi_pkt_send_wqe[0x2];
1021         u8         wqe_inline_mode[0x2];
1022         u8         rss_ind_tbl_cap[0x4];
1023         u8         reg_umr_sq[0x1];
1024         u8         scatter_fcs[0x1];
1025         u8         enhanced_multi_pkt_send_wqe[0x1];
1026         u8         tunnel_lso_const_out_ip_id[0x1];
1027         u8         tunnel_lro_gre[0x1];
1028         u8         tunnel_lro_vxlan[0x1];
1029         u8         tunnel_stateless_gre[0x1];
1030         u8         tunnel_stateless_vxlan[0x1];
1031
1032         u8         swp[0x1];
1033         u8         swp_csum[0x1];
1034         u8         swp_lso[0x1];
1035         u8         cqe_checksum_full[0x1];
1036         u8         tunnel_stateless_geneve_tx[0x1];
1037         u8         tunnel_stateless_mpls_over_udp[0x1];
1038         u8         tunnel_stateless_mpls_over_gre[0x1];
1039         u8         tunnel_stateless_vxlan_gpe[0x1];
1040         u8         tunnel_stateless_ipv4_over_vxlan[0x1];
1041         u8         tunnel_stateless_ip_over_ip[0x1];
1042         u8         insert_trailer[0x1];
1043         u8         reserved_at_2b[0x1];
1044         u8         tunnel_stateless_ip_over_ip_rx[0x1];
1045         u8         tunnel_stateless_ip_over_ip_tx[0x1];
1046         u8         reserved_at_2e[0x2];
1047         u8         max_vxlan_udp_ports[0x8];
1048         u8         reserved_at_38[0x6];
1049         u8         max_geneve_opt_len[0x1];
1050         u8         tunnel_stateless_geneve_rx[0x1];
1051
1052         u8         reserved_at_40[0x10];
1053         u8         lro_min_mss_size[0x10];
1054
1055         u8         reserved_at_60[0x120];
1056
1057         u8         lro_timer_supported_periods[4][0x20];
1058
1059         u8         reserved_at_200[0x600];
1060 };
1061
1062 enum {
1063         MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1064         MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1065         MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1066 };
1067
1068 struct mlx5_ifc_roce_cap_bits {
1069         u8         roce_apm[0x1];
1070         u8         reserved_at_1[0x3];
1071         u8         sw_r_roce_src_udp_port[0x1];
1072         u8         fl_rc_qp_when_roce_disabled[0x1];
1073         u8         fl_rc_qp_when_roce_enabled[0x1];
1074         u8         reserved_at_7[0x17];
1075         u8         qp_ts_format[0x2];
1076
1077         u8         reserved_at_20[0x60];
1078
1079         u8         reserved_at_80[0xc];
1080         u8         l3_type[0x4];
1081         u8         reserved_at_90[0x8];
1082         u8         roce_version[0x8];
1083
1084         u8         reserved_at_a0[0x10];
1085         u8         r_roce_dest_udp_port[0x10];
1086
1087         u8         r_roce_max_src_udp_port[0x10];
1088         u8         r_roce_min_src_udp_port[0x10];
1089
1090         u8         reserved_at_e0[0x10];
1091         u8         roce_address_table_size[0x10];
1092
1093         u8         reserved_at_100[0x700];
1094 };
1095
1096 struct mlx5_ifc_sync_steering_in_bits {
1097         u8         opcode[0x10];
1098         u8         uid[0x10];
1099
1100         u8         reserved_at_20[0x10];
1101         u8         op_mod[0x10];
1102
1103         u8         reserved_at_40[0xc0];
1104 };
1105
1106 struct mlx5_ifc_sync_steering_out_bits {
1107         u8         status[0x8];
1108         u8         reserved_at_8[0x18];
1109
1110         u8         syndrome[0x20];
1111
1112         u8         reserved_at_40[0x40];
1113 };
1114
1115 struct mlx5_ifc_device_mem_cap_bits {
1116         u8         memic[0x1];
1117         u8         reserved_at_1[0x1f];
1118
1119         u8         reserved_at_20[0xb];
1120         u8         log_min_memic_alloc_size[0x5];
1121         u8         reserved_at_30[0x8];
1122         u8         log_max_memic_addr_alignment[0x8];
1123
1124         u8         memic_bar_start_addr[0x40];
1125
1126         u8         memic_bar_size[0x20];
1127
1128         u8         max_memic_size[0x20];
1129
1130         u8         steering_sw_icm_start_address[0x40];
1131
1132         u8         reserved_at_100[0x8];
1133         u8         log_header_modify_sw_icm_size[0x8];
1134         u8         reserved_at_110[0x2];
1135         u8         log_sw_icm_alloc_granularity[0x6];
1136         u8         log_steering_sw_icm_size[0x8];
1137
1138         u8         reserved_at_120[0x18];
1139         u8         log_header_modify_pattern_sw_icm_size[0x8];
1140
1141         u8         header_modify_sw_icm_start_address[0x40];
1142
1143         u8         reserved_at_180[0x40];
1144
1145         u8         header_modify_pattern_sw_icm_start_address[0x40];
1146
1147         u8         memic_operations[0x20];
1148
1149         u8         reserved_at_220[0x5e0];
1150 };
1151
1152 struct mlx5_ifc_device_event_cap_bits {
1153         u8         user_affiliated_events[4][0x40];
1154
1155         u8         user_unaffiliated_events[4][0x40];
1156 };
1157
1158 struct mlx5_ifc_virtio_emulation_cap_bits {
1159         u8         desc_tunnel_offload_type[0x1];
1160         u8         eth_frame_offload_type[0x1];
1161         u8         virtio_version_1_0[0x1];
1162         u8         device_features_bits_mask[0xd];
1163         u8         event_mode[0x8];
1164         u8         virtio_queue_type[0x8];
1165
1166         u8         max_tunnel_desc[0x10];
1167         u8         reserved_at_30[0x3];
1168         u8         log_doorbell_stride[0x5];
1169         u8         reserved_at_38[0x3];
1170         u8         log_doorbell_bar_size[0x5];
1171
1172         u8         doorbell_bar_offset[0x40];
1173
1174         u8         max_emulated_devices[0x8];
1175         u8         max_num_virtio_queues[0x18];
1176
1177         u8         reserved_at_a0[0x60];
1178
1179         u8         umem_1_buffer_param_a[0x20];
1180
1181         u8         umem_1_buffer_param_b[0x20];
1182
1183         u8         umem_2_buffer_param_a[0x20];
1184
1185         u8         umem_2_buffer_param_b[0x20];
1186
1187         u8         umem_3_buffer_param_a[0x20];
1188
1189         u8         umem_3_buffer_param_b[0x20];
1190
1191         u8         reserved_at_1c0[0x640];
1192 };
1193
1194 enum {
1195         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1196         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1197         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1198         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1199         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1200         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1201         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1202         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1203         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1204 };
1205
1206 enum {
1207         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1208         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1209         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1210         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1211         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1212         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1213         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1214         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1215         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1216 };
1217
1218 struct mlx5_ifc_atomic_caps_bits {
1219         u8         reserved_at_0[0x40];
1220
1221         u8         atomic_req_8B_endianness_mode[0x2];
1222         u8         reserved_at_42[0x4];
1223         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1224
1225         u8         reserved_at_47[0x19];
1226
1227         u8         reserved_at_60[0x20];
1228
1229         u8         reserved_at_80[0x10];
1230         u8         atomic_operations[0x10];
1231
1232         u8         reserved_at_a0[0x10];
1233         u8         atomic_size_qp[0x10];
1234
1235         u8         reserved_at_c0[0x10];
1236         u8         atomic_size_dc[0x10];
1237
1238         u8         reserved_at_e0[0x720];
1239 };
1240
1241 struct mlx5_ifc_odp_cap_bits {
1242         u8         reserved_at_0[0x40];
1243
1244         u8         sig[0x1];
1245         u8         reserved_at_41[0x1f];
1246
1247         u8         reserved_at_60[0x20];
1248
1249         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1250
1251         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1252
1253         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1254
1255         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1256
1257         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1258
1259         u8         reserved_at_120[0x6E0];
1260 };
1261
1262 struct mlx5_ifc_calc_op {
1263         u8        reserved_at_0[0x10];
1264         u8        reserved_at_10[0x9];
1265         u8        op_swap_endianness[0x1];
1266         u8        op_min[0x1];
1267         u8        op_xor[0x1];
1268         u8        op_or[0x1];
1269         u8        op_and[0x1];
1270         u8        op_max[0x1];
1271         u8        op_add[0x1];
1272 };
1273
1274 struct mlx5_ifc_vector_calc_cap_bits {
1275         u8         calc_matrix[0x1];
1276         u8         reserved_at_1[0x1f];
1277         u8         reserved_at_20[0x8];
1278         u8         max_vec_count[0x8];
1279         u8         reserved_at_30[0xd];
1280         u8         max_chunk_size[0x3];
1281         struct mlx5_ifc_calc_op calc0;
1282         struct mlx5_ifc_calc_op calc1;
1283         struct mlx5_ifc_calc_op calc2;
1284         struct mlx5_ifc_calc_op calc3;
1285
1286         u8         reserved_at_c0[0x720];
1287 };
1288
1289 struct mlx5_ifc_tls_cap_bits {
1290         u8         tls_1_2_aes_gcm_128[0x1];
1291         u8         tls_1_3_aes_gcm_128[0x1];
1292         u8         tls_1_2_aes_gcm_256[0x1];
1293         u8         tls_1_3_aes_gcm_256[0x1];
1294         u8         reserved_at_4[0x1c];
1295
1296         u8         reserved_at_20[0x7e0];
1297 };
1298
1299 struct mlx5_ifc_ipsec_cap_bits {
1300         u8         ipsec_full_offload[0x1];
1301         u8         ipsec_crypto_offload[0x1];
1302         u8         ipsec_esn[0x1];
1303         u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1304         u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1305         u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1306         u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1307         u8         reserved_at_7[0x4];
1308         u8         log_max_ipsec_offload[0x5];
1309         u8         reserved_at_10[0x10];
1310
1311         u8         min_log_ipsec_full_replay_window[0x8];
1312         u8         max_log_ipsec_full_replay_window[0x8];
1313         u8         reserved_at_30[0x7d0];
1314 };
1315
1316 struct mlx5_ifc_macsec_cap_bits {
1317         u8    macsec_epn[0x1];
1318         u8    reserved_at_1[0x2];
1319         u8    macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1320         u8    macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1321         u8    macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1322         u8    macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1323         u8    reserved_at_7[0x4];
1324         u8    log_max_macsec_offload[0x5];
1325         u8    reserved_at_10[0x10];
1326
1327         u8    min_log_macsec_full_replay_window[0x8];
1328         u8    max_log_macsec_full_replay_window[0x8];
1329         u8    reserved_at_30[0x10];
1330
1331         u8    reserved_at_40[0x7c0];
1332 };
1333
1334 enum {
1335         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1336         MLX5_WQ_TYPE_CYCLIC       = 0x1,
1337         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1338         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1339 };
1340
1341 enum {
1342         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1343         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1344 };
1345
1346 enum {
1347         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1348         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1349         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1350         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1351         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1352 };
1353
1354 enum {
1355         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1356         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1357         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1358         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1359         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1360         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1361 };
1362
1363 enum {
1364         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1365         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1366 };
1367
1368 enum {
1369         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1370         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1371         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1372 };
1373
1374 enum {
1375         MLX5_CAP_PORT_TYPE_IB  = 0x0,
1376         MLX5_CAP_PORT_TYPE_ETH = 0x1,
1377 };
1378
1379 enum {
1380         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
1381         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
1382         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
1383 };
1384
1385 enum {
1386         MLX5_FLEX_PARSER_GENEVE_ENABLED         = 1 << 3,
1387         MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED  = 1 << 4,
1388         MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED  = 1 << 5,
1389         MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED      = 1 << 7,
1390         MLX5_FLEX_PARSER_ICMP_V4_ENABLED        = 1 << 8,
1391         MLX5_FLEX_PARSER_ICMP_V6_ENABLED        = 1 << 9,
1392         MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1393         MLX5_FLEX_PARSER_GTPU_ENABLED           = 1 << 11,
1394         MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED      = 1 << 16,
1395         MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1396         MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED      = 1 << 18,
1397         MLX5_FLEX_PARSER_GTPU_TEID_ENABLED      = 1 << 19,
1398 };
1399
1400 enum {
1401         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1402         MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1403 };
1404
1405 #define MLX5_FC_BULK_SIZE_FACTOR 128
1406
1407 enum mlx5_fc_bulk_alloc_bitmask {
1408         MLX5_FC_BULK_128   = (1 << 0),
1409         MLX5_FC_BULK_256   = (1 << 1),
1410         MLX5_FC_BULK_512   = (1 << 2),
1411         MLX5_FC_BULK_1024  = (1 << 3),
1412         MLX5_FC_BULK_2048  = (1 << 4),
1413         MLX5_FC_BULK_4096  = (1 << 5),
1414         MLX5_FC_BULK_8192  = (1 << 6),
1415         MLX5_FC_BULK_16384 = (1 << 7),
1416 };
1417
1418 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1419
1420 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1421
1422 enum {
1423         MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1424         MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1425         MLX5_STEERING_FORMAT_CONNECTX_7   = 2,
1426 };
1427
1428 struct mlx5_ifc_cmd_hca_cap_bits {
1429         u8         reserved_at_0[0x10];
1430         u8         shared_object_to_user_object_allowed[0x1];
1431         u8         reserved_at_13[0xe];
1432         u8         vhca_resource_manager[0x1];
1433
1434         u8         hca_cap_2[0x1];
1435         u8         create_lag_when_not_master_up[0x1];
1436         u8         dtor[0x1];
1437         u8         event_on_vhca_state_teardown_request[0x1];
1438         u8         event_on_vhca_state_in_use[0x1];
1439         u8         event_on_vhca_state_active[0x1];
1440         u8         event_on_vhca_state_allocated[0x1];
1441         u8         event_on_vhca_state_invalid[0x1];
1442         u8         reserved_at_28[0x8];
1443         u8         vhca_id[0x10];
1444
1445         u8         reserved_at_40[0x40];
1446
1447         u8         log_max_srq_sz[0x8];
1448         u8         log_max_qp_sz[0x8];
1449         u8         event_cap[0x1];
1450         u8         reserved_at_91[0x2];
1451         u8         isolate_vl_tc_new[0x1];
1452         u8         reserved_at_94[0x4];
1453         u8         prio_tag_required[0x1];
1454         u8         reserved_at_99[0x2];
1455         u8         log_max_qp[0x5];
1456
1457         u8         reserved_at_a0[0x3];
1458         u8         ece_support[0x1];
1459         u8         reserved_at_a4[0x5];
1460         u8         reg_c_preserve[0x1];
1461         u8         reserved_at_aa[0x1];
1462         u8         log_max_srq[0x5];
1463         u8         reserved_at_b0[0x1];
1464         u8         uplink_follow[0x1];
1465         u8         ts_cqe_to_dest_cqn[0x1];
1466         u8         reserved_at_b3[0x7];
1467         u8         shampo[0x1];
1468         u8         reserved_at_bb[0x5];
1469
1470         u8         max_sgl_for_optimized_performance[0x8];
1471         u8         log_max_cq_sz[0x8];
1472         u8         relaxed_ordering_write_umr[0x1];
1473         u8         relaxed_ordering_read_umr[0x1];
1474         u8         reserved_at_d2[0x7];
1475         u8         virtio_net_device_emualtion_manager[0x1];
1476         u8         virtio_blk_device_emualtion_manager[0x1];
1477         u8         log_max_cq[0x5];
1478
1479         u8         log_max_eq_sz[0x8];
1480         u8         relaxed_ordering_write[0x1];
1481         u8         relaxed_ordering_read[0x1];
1482         u8         log_max_mkey[0x6];
1483         u8         reserved_at_f0[0x8];
1484         u8         dump_fill_mkey[0x1];
1485         u8         reserved_at_f9[0x2];
1486         u8         fast_teardown[0x1];
1487         u8         log_max_eq[0x4];
1488
1489         u8         max_indirection[0x8];
1490         u8         fixed_buffer_size[0x1];
1491         u8         log_max_mrw_sz[0x7];
1492         u8         force_teardown[0x1];
1493         u8         reserved_at_111[0x1];
1494         u8         log_max_bsf_list_size[0x6];
1495         u8         umr_extended_translation_offset[0x1];
1496         u8         null_mkey[0x1];
1497         u8         log_max_klm_list_size[0x6];
1498
1499         u8         reserved_at_120[0xa];
1500         u8         log_max_ra_req_dc[0x6];
1501         u8         reserved_at_130[0x2];
1502         u8         eth_wqe_too_small[0x1];
1503         u8         reserved_at_133[0x6];
1504         u8         vnic_env_cq_overrun[0x1];
1505         u8         log_max_ra_res_dc[0x6];
1506
1507         u8         reserved_at_140[0x5];
1508         u8         release_all_pages[0x1];
1509         u8         must_not_use[0x1];
1510         u8         reserved_at_147[0x2];
1511         u8         roce_accl[0x1];
1512         u8         log_max_ra_req_qp[0x6];
1513         u8         reserved_at_150[0xa];
1514         u8         log_max_ra_res_qp[0x6];
1515
1516         u8         end_pad[0x1];
1517         u8         cc_query_allowed[0x1];
1518         u8         cc_modify_allowed[0x1];
1519         u8         start_pad[0x1];
1520         u8         cache_line_128byte[0x1];
1521         u8         reserved_at_165[0x4];
1522         u8         rts2rts_qp_counters_set_id[0x1];
1523         u8         reserved_at_16a[0x2];
1524         u8         vnic_env_int_rq_oob[0x1];
1525         u8         sbcam_reg[0x1];
1526         u8         reserved_at_16e[0x1];
1527         u8         qcam_reg[0x1];
1528         u8         gid_table_size[0x10];
1529
1530         u8         out_of_seq_cnt[0x1];
1531         u8         vport_counters[0x1];
1532         u8         retransmission_q_counters[0x1];
1533         u8         debug[0x1];
1534         u8         modify_rq_counter_set_id[0x1];
1535         u8         rq_delay_drop[0x1];
1536         u8         max_qp_cnt[0xa];
1537         u8         pkey_table_size[0x10];
1538
1539         u8         vport_group_manager[0x1];
1540         u8         vhca_group_manager[0x1];
1541         u8         ib_virt[0x1];
1542         u8         eth_virt[0x1];
1543         u8         vnic_env_queue_counters[0x1];
1544         u8         ets[0x1];
1545         u8         nic_flow_table[0x1];
1546         u8         eswitch_manager[0x1];
1547         u8         device_memory[0x1];
1548         u8         mcam_reg[0x1];
1549         u8         pcam_reg[0x1];
1550         u8         local_ca_ack_delay[0x5];
1551         u8         port_module_event[0x1];
1552         u8         enhanced_error_q_counters[0x1];
1553         u8         ports_check[0x1];
1554         u8         reserved_at_1b3[0x1];
1555         u8         disable_link_up[0x1];
1556         u8         beacon_led[0x1];
1557         u8         port_type[0x2];
1558         u8         num_ports[0x8];
1559
1560         u8         reserved_at_1c0[0x1];
1561         u8         pps[0x1];
1562         u8         pps_modify[0x1];
1563         u8         log_max_msg[0x5];
1564         u8         reserved_at_1c8[0x4];
1565         u8         max_tc[0x4];
1566         u8         temp_warn_event[0x1];
1567         u8         dcbx[0x1];
1568         u8         general_notification_event[0x1];
1569         u8         reserved_at_1d3[0x2];
1570         u8         fpga[0x1];
1571         u8         rol_s[0x1];
1572         u8         rol_g[0x1];
1573         u8         reserved_at_1d8[0x1];
1574         u8         wol_s[0x1];
1575         u8         wol_g[0x1];
1576         u8         wol_a[0x1];
1577         u8         wol_b[0x1];
1578         u8         wol_m[0x1];
1579         u8         wol_u[0x1];
1580         u8         wol_p[0x1];
1581
1582         u8         stat_rate_support[0x10];
1583         u8         reserved_at_1f0[0x1];
1584         u8         pci_sync_for_fw_update_event[0x1];
1585         u8         reserved_at_1f2[0x6];
1586         u8         init2_lag_tx_port_affinity[0x1];
1587         u8         reserved_at_1fa[0x3];
1588         u8         cqe_version[0x4];
1589
1590         u8         compact_address_vector[0x1];
1591         u8         striding_rq[0x1];
1592         u8         reserved_at_202[0x1];
1593         u8         ipoib_enhanced_offloads[0x1];
1594         u8         ipoib_basic_offloads[0x1];
1595         u8         reserved_at_205[0x1];
1596         u8         repeated_block_disabled[0x1];
1597         u8         umr_modify_entity_size_disabled[0x1];
1598         u8         umr_modify_atomic_disabled[0x1];
1599         u8         umr_indirect_mkey_disabled[0x1];
1600         u8         umr_fence[0x2];
1601         u8         dc_req_scat_data_cqe[0x1];
1602         u8         reserved_at_20d[0x2];
1603         u8         drain_sigerr[0x1];
1604         u8         cmdif_checksum[0x2];
1605         u8         sigerr_cqe[0x1];
1606         u8         reserved_at_213[0x1];
1607         u8         wq_signature[0x1];
1608         u8         sctr_data_cqe[0x1];
1609         u8         reserved_at_216[0x1];
1610         u8         sho[0x1];
1611         u8         tph[0x1];
1612         u8         rf[0x1];
1613         u8         dct[0x1];
1614         u8         qos[0x1];
1615         u8         eth_net_offloads[0x1];
1616         u8         roce[0x1];
1617         u8         atomic[0x1];
1618         u8         reserved_at_21f[0x1];
1619
1620         u8         cq_oi[0x1];
1621         u8         cq_resize[0x1];
1622         u8         cq_moderation[0x1];
1623         u8         reserved_at_223[0x3];
1624         u8         cq_eq_remap[0x1];
1625         u8         pg[0x1];
1626         u8         block_lb_mc[0x1];
1627         u8         reserved_at_229[0x1];
1628         u8         scqe_break_moderation[0x1];
1629         u8         cq_period_start_from_cqe[0x1];
1630         u8         cd[0x1];
1631         u8         reserved_at_22d[0x1];
1632         u8         apm[0x1];
1633         u8         vector_calc[0x1];
1634         u8         umr_ptr_rlky[0x1];
1635         u8         imaicl[0x1];
1636         u8         qp_packet_based[0x1];
1637         u8         reserved_at_233[0x3];
1638         u8         qkv[0x1];
1639         u8         pkv[0x1];
1640         u8         set_deth_sqpn[0x1];
1641         u8         reserved_at_239[0x3];
1642         u8         xrc[0x1];
1643         u8         ud[0x1];
1644         u8         uc[0x1];
1645         u8         rc[0x1];
1646
1647         u8         uar_4k[0x1];
1648         u8         reserved_at_241[0x9];
1649         u8         uar_sz[0x6];
1650         u8         port_selection_cap[0x1];
1651         u8         reserved_at_248[0x1];
1652         u8         umem_uid_0[0x1];
1653         u8         reserved_at_250[0x5];
1654         u8         log_pg_sz[0x8];
1655
1656         u8         bf[0x1];
1657         u8         driver_version[0x1];
1658         u8         pad_tx_eth_packet[0x1];
1659         u8         reserved_at_263[0x3];
1660         u8         mkey_by_name[0x1];
1661         u8         reserved_at_267[0x4];
1662
1663         u8         log_bf_reg_size[0x5];
1664
1665         u8         reserved_at_270[0x6];
1666         u8         lag_dct[0x2];
1667         u8         lag_tx_port_affinity[0x1];
1668         u8         lag_native_fdb_selection[0x1];
1669         u8         reserved_at_27a[0x1];
1670         u8         lag_master[0x1];
1671         u8         num_lag_ports[0x4];
1672
1673         u8         reserved_at_280[0x10];
1674         u8         max_wqe_sz_sq[0x10];
1675
1676         u8         reserved_at_2a0[0x10];
1677         u8         max_wqe_sz_rq[0x10];
1678
1679         u8         max_flow_counter_31_16[0x10];
1680         u8         max_wqe_sz_sq_dc[0x10];
1681
1682         u8         reserved_at_2e0[0x7];
1683         u8         max_qp_mcg[0x19];
1684
1685         u8         reserved_at_300[0x10];
1686         u8         flow_counter_bulk_alloc[0x8];
1687         u8         log_max_mcg[0x8];
1688
1689         u8         reserved_at_320[0x3];
1690         u8         log_max_transport_domain[0x5];
1691         u8         reserved_at_328[0x3];
1692         u8         log_max_pd[0x5];
1693         u8         reserved_at_330[0xb];
1694         u8         log_max_xrcd[0x5];
1695
1696         u8         nic_receive_steering_discard[0x1];
1697         u8         receive_discard_vport_down[0x1];
1698         u8         transmit_discard_vport_down[0x1];
1699         u8         eq_overrun_count[0x1];
1700         u8         reserved_at_344[0x1];
1701         u8         invalid_command_count[0x1];
1702         u8         quota_exceeded_count[0x1];
1703         u8         reserved_at_347[0x1];
1704         u8         log_max_flow_counter_bulk[0x8];
1705         u8         max_flow_counter_15_0[0x10];
1706
1707
1708         u8         reserved_at_360[0x3];
1709         u8         log_max_rq[0x5];
1710         u8         reserved_at_368[0x3];
1711         u8         log_max_sq[0x5];
1712         u8         reserved_at_370[0x3];
1713         u8         log_max_tir[0x5];
1714         u8         reserved_at_378[0x3];
1715         u8         log_max_tis[0x5];
1716
1717         u8         basic_cyclic_rcv_wqe[0x1];
1718         u8         reserved_at_381[0x2];
1719         u8         log_max_rmp[0x5];
1720         u8         reserved_at_388[0x3];
1721         u8         log_max_rqt[0x5];
1722         u8         reserved_at_390[0x3];
1723         u8         log_max_rqt_size[0x5];
1724         u8         reserved_at_398[0x3];
1725         u8         log_max_tis_per_sq[0x5];
1726
1727         u8         ext_stride_num_range[0x1];
1728         u8         roce_rw_supported[0x1];
1729         u8         log_max_current_uc_list_wr_supported[0x1];
1730         u8         log_max_stride_sz_rq[0x5];
1731         u8         reserved_at_3a8[0x3];
1732         u8         log_min_stride_sz_rq[0x5];
1733         u8         reserved_at_3b0[0x3];
1734         u8         log_max_stride_sz_sq[0x5];
1735         u8         reserved_at_3b8[0x3];
1736         u8         log_min_stride_sz_sq[0x5];
1737
1738         u8         hairpin[0x1];
1739         u8         reserved_at_3c1[0x2];
1740         u8         log_max_hairpin_queues[0x5];
1741         u8         reserved_at_3c8[0x3];
1742         u8         log_max_hairpin_wq_data_sz[0x5];
1743         u8         reserved_at_3d0[0x3];
1744         u8         log_max_hairpin_num_packets[0x5];
1745         u8         reserved_at_3d8[0x3];
1746         u8         log_max_wq_sz[0x5];
1747
1748         u8         nic_vport_change_event[0x1];
1749         u8         disable_local_lb_uc[0x1];
1750         u8         disable_local_lb_mc[0x1];
1751         u8         log_min_hairpin_wq_data_sz[0x5];
1752         u8         reserved_at_3e8[0x2];
1753         u8         vhca_state[0x1];
1754         u8         log_max_vlan_list[0x5];
1755         u8         reserved_at_3f0[0x3];
1756         u8         log_max_current_mc_list[0x5];
1757         u8         reserved_at_3f8[0x3];
1758         u8         log_max_current_uc_list[0x5];
1759
1760         u8         general_obj_types[0x40];
1761
1762         u8         sq_ts_format[0x2];
1763         u8         rq_ts_format[0x2];
1764         u8         steering_format_version[0x4];
1765         u8         create_qp_start_hint[0x18];
1766
1767         u8         reserved_at_460[0x1];
1768         u8         ats[0x1];
1769         u8         reserved_at_462[0x1];
1770         u8         log_max_uctx[0x5];
1771         u8         reserved_at_468[0x2];
1772         u8         ipsec_offload[0x1];
1773         u8         log_max_umem[0x5];
1774         u8         max_num_eqs[0x10];
1775
1776         u8         reserved_at_480[0x1];
1777         u8         tls_tx[0x1];
1778         u8         tls_rx[0x1];
1779         u8         log_max_l2_table[0x5];
1780         u8         reserved_at_488[0x8];
1781         u8         log_uar_page_sz[0x10];
1782
1783         u8         reserved_at_4a0[0x20];
1784         u8         device_frequency_mhz[0x20];
1785         u8         device_frequency_khz[0x20];
1786
1787         u8         reserved_at_500[0x20];
1788         u8         num_of_uars_per_page[0x20];
1789
1790         u8         flex_parser_protocols[0x20];
1791
1792         u8         max_geneve_tlv_options[0x8];
1793         u8         reserved_at_568[0x3];
1794         u8         max_geneve_tlv_option_data_len[0x5];
1795         u8         reserved_at_570[0x9];
1796         u8         adv_virtualization[0x1];
1797         u8         reserved_at_57a[0x6];
1798
1799         u8         reserved_at_580[0xb];
1800         u8         log_max_dci_stream_channels[0x5];
1801         u8         reserved_at_590[0x3];
1802         u8         log_max_dci_errored_streams[0x5];
1803         u8         reserved_at_598[0x8];
1804
1805         u8         reserved_at_5a0[0x10];
1806         u8         enhanced_cqe_compression[0x1];
1807         u8         reserved_at_5b1[0x2];
1808         u8         log_max_dek[0x5];
1809         u8         reserved_at_5b8[0x4];
1810         u8         mini_cqe_resp_stride_index[0x1];
1811         u8         cqe_128_always[0x1];
1812         u8         cqe_compression_128[0x1];
1813         u8         cqe_compression[0x1];
1814
1815         u8         cqe_compression_timeout[0x10];
1816         u8         cqe_compression_max_num[0x10];
1817
1818         u8         reserved_at_5e0[0x8];
1819         u8         flex_parser_id_gtpu_dw_0[0x4];
1820         u8         reserved_at_5ec[0x4];
1821         u8         tag_matching[0x1];
1822         u8         rndv_offload_rc[0x1];
1823         u8         rndv_offload_dc[0x1];
1824         u8         log_tag_matching_list_sz[0x5];
1825         u8         reserved_at_5f8[0x3];
1826         u8         log_max_xrq[0x5];
1827
1828         u8         affiliate_nic_vport_criteria[0x8];
1829         u8         native_port_num[0x8];
1830         u8         num_vhca_ports[0x8];
1831         u8         flex_parser_id_gtpu_teid[0x4];
1832         u8         reserved_at_61c[0x2];
1833         u8         sw_owner_id[0x1];
1834         u8         reserved_at_61f[0x1];
1835
1836         u8         max_num_of_monitor_counters[0x10];
1837         u8         num_ppcnt_monitor_counters[0x10];
1838
1839         u8         max_num_sf[0x10];
1840         u8         num_q_monitor_counters[0x10];
1841
1842         u8         reserved_at_660[0x20];
1843
1844         u8         sf[0x1];
1845         u8         sf_set_partition[0x1];
1846         u8         reserved_at_682[0x1];
1847         u8         log_max_sf[0x5];
1848         u8         apu[0x1];
1849         u8         reserved_at_689[0x4];
1850         u8         migration[0x1];
1851         u8         reserved_at_68e[0x2];
1852         u8         log_min_sf_size[0x8];
1853         u8         max_num_sf_partitions[0x8];
1854
1855         u8         uctx_cap[0x20];
1856
1857         u8         reserved_at_6c0[0x4];
1858         u8         flex_parser_id_geneve_tlv_option_0[0x4];
1859         u8         flex_parser_id_icmp_dw1[0x4];
1860         u8         flex_parser_id_icmp_dw0[0x4];
1861         u8         flex_parser_id_icmpv6_dw1[0x4];
1862         u8         flex_parser_id_icmpv6_dw0[0x4];
1863         u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1864         u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1865
1866         u8         max_num_match_definer[0x10];
1867         u8         sf_base_id[0x10];
1868
1869         u8         flex_parser_id_gtpu_dw_2[0x4];
1870         u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
1871         u8         num_total_dynamic_vf_msix[0x18];
1872         u8         reserved_at_720[0x14];
1873         u8         dynamic_msix_table_size[0xc];
1874         u8         reserved_at_740[0xc];
1875         u8         min_dynamic_vf_msix_table_size[0x4];
1876         u8         reserved_at_750[0x4];
1877         u8         max_dynamic_vf_msix_table_size[0xc];
1878
1879         u8         reserved_at_760[0x20];
1880         u8         vhca_tunnel_commands[0x40];
1881         u8         match_definer_format_supported[0x40];
1882 };
1883
1884 struct mlx5_ifc_cmd_hca_cap_2_bits {
1885         u8         reserved_at_0[0x80];
1886
1887         u8         migratable[0x1];
1888         u8         reserved_at_81[0x1f];
1889
1890         u8         max_reformat_insert_size[0x8];
1891         u8         max_reformat_insert_offset[0x8];
1892         u8         max_reformat_remove_size[0x8];
1893         u8         max_reformat_remove_offset[0x8];
1894
1895         u8         reserved_at_c0[0x8];
1896         u8         migration_multi_load[0x1];
1897         u8         migration_tracking_state[0x1];
1898         u8         reserved_at_ca[0x16];
1899
1900         u8         reserved_at_e0[0xc0];
1901
1902         u8         reserved_at_1a0[0xb];
1903         u8         log_min_mkey_entity_size[0x5];
1904         u8         reserved_at_1b0[0x10];
1905
1906         u8         reserved_at_1c0[0x60];
1907
1908         u8         reserved_at_220[0x1];
1909         u8         sw_vhca_id_valid[0x1];
1910         u8         sw_vhca_id[0xe];
1911         u8         reserved_at_230[0x10];
1912
1913         u8         reserved_at_240[0xb];
1914         u8         ts_cqe_metadata_size2wqe_counter[0x5];
1915         u8         reserved_at_250[0x10];
1916
1917         u8         reserved_at_260[0x5a0];
1918 };
1919
1920 enum mlx5_ifc_flow_destination_type {
1921         MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1922         MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1923         MLX5_IFC_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1924         MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1925         MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK       = 0x8,
1926 };
1927
1928 enum mlx5_flow_table_miss_action {
1929         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1930         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1931         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1932 };
1933
1934 struct mlx5_ifc_dest_format_struct_bits {
1935         u8         destination_type[0x8];
1936         u8         destination_id[0x18];
1937
1938         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1939         u8         packet_reformat[0x1];
1940         u8         reserved_at_22[0xe];
1941         u8         destination_eswitch_owner_vhca_id[0x10];
1942 };
1943
1944 struct mlx5_ifc_flow_counter_list_bits {
1945         u8         flow_counter_id[0x20];
1946
1947         u8         reserved_at_20[0x20];
1948 };
1949
1950 struct mlx5_ifc_extended_dest_format_bits {
1951         struct mlx5_ifc_dest_format_struct_bits destination_entry;
1952
1953         u8         packet_reformat_id[0x20];
1954
1955         u8         reserved_at_60[0x20];
1956 };
1957
1958 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1959         struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1960         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1961 };
1962
1963 struct mlx5_ifc_fte_match_param_bits {
1964         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1965
1966         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1967
1968         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1969
1970         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1971
1972         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1973
1974         struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1975
1976         struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
1977
1978         u8         reserved_at_e00[0x200];
1979 };
1980
1981 enum {
1982         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1983         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1984         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1985         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1986         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1987 };
1988
1989 struct mlx5_ifc_rx_hash_field_select_bits {
1990         u8         l3_prot_type[0x1];
1991         u8         l4_prot_type[0x1];
1992         u8         selected_fields[0x1e];
1993 };
1994
1995 enum {
1996         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1997         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1998 };
1999
2000 enum {
2001         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
2002         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
2003 };
2004
2005 struct mlx5_ifc_wq_bits {
2006         u8         wq_type[0x4];
2007         u8         wq_signature[0x1];
2008         u8         end_padding_mode[0x2];
2009         u8         cd_slave[0x1];
2010         u8         reserved_at_8[0x18];
2011
2012         u8         hds_skip_first_sge[0x1];
2013         u8         log2_hds_buf_size[0x3];
2014         u8         reserved_at_24[0x7];
2015         u8         page_offset[0x5];
2016         u8         lwm[0x10];
2017
2018         u8         reserved_at_40[0x8];
2019         u8         pd[0x18];
2020
2021         u8         reserved_at_60[0x8];
2022         u8         uar_page[0x18];
2023
2024         u8         dbr_addr[0x40];
2025
2026         u8         hw_counter[0x20];
2027
2028         u8         sw_counter[0x20];
2029
2030         u8         reserved_at_100[0xc];
2031         u8         log_wq_stride[0x4];
2032         u8         reserved_at_110[0x3];
2033         u8         log_wq_pg_sz[0x5];
2034         u8         reserved_at_118[0x3];
2035         u8         log_wq_sz[0x5];
2036
2037         u8         dbr_umem_valid[0x1];
2038         u8         wq_umem_valid[0x1];
2039         u8         reserved_at_122[0x1];
2040         u8         log_hairpin_num_packets[0x5];
2041         u8         reserved_at_128[0x3];
2042         u8         log_hairpin_data_sz[0x5];
2043
2044         u8         reserved_at_130[0x4];
2045         u8         log_wqe_num_of_strides[0x4];
2046         u8         two_byte_shift_en[0x1];
2047         u8         reserved_at_139[0x4];
2048         u8         log_wqe_stride_size[0x3];
2049
2050         u8         reserved_at_140[0x80];
2051
2052         u8         headers_mkey[0x20];
2053
2054         u8         shampo_enable[0x1];
2055         u8         reserved_at_1e1[0x4];
2056         u8         log_reservation_size[0x3];
2057         u8         reserved_at_1e8[0x5];
2058         u8         log_max_num_of_packets_per_reservation[0x3];
2059         u8         reserved_at_1f0[0x6];
2060         u8         log_headers_entry_size[0x2];
2061         u8         reserved_at_1f8[0x4];
2062         u8         log_headers_buffer_entry_num[0x4];
2063
2064         u8         reserved_at_200[0x400];
2065
2066         struct mlx5_ifc_cmd_pas_bits pas[];
2067 };
2068
2069 struct mlx5_ifc_rq_num_bits {
2070         u8         reserved_at_0[0x8];
2071         u8         rq_num[0x18];
2072 };
2073
2074 struct mlx5_ifc_mac_address_layout_bits {
2075         u8         reserved_at_0[0x10];
2076         u8         mac_addr_47_32[0x10];
2077
2078         u8         mac_addr_31_0[0x20];
2079 };
2080
2081 struct mlx5_ifc_vlan_layout_bits {
2082         u8         reserved_at_0[0x14];
2083         u8         vlan[0x0c];
2084
2085         u8         reserved_at_20[0x20];
2086 };
2087
2088 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
2089         u8         reserved_at_0[0xa0];
2090
2091         u8         min_time_between_cnps[0x20];
2092
2093         u8         reserved_at_c0[0x12];
2094         u8         cnp_dscp[0x6];
2095         u8         reserved_at_d8[0x4];
2096         u8         cnp_prio_mode[0x1];
2097         u8         cnp_802p_prio[0x3];
2098
2099         u8         reserved_at_e0[0x720];
2100 };
2101
2102 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
2103         u8         reserved_at_0[0x60];
2104
2105         u8         reserved_at_60[0x4];
2106         u8         clamp_tgt_rate[0x1];
2107         u8         reserved_at_65[0x3];
2108         u8         clamp_tgt_rate_after_time_inc[0x1];
2109         u8         reserved_at_69[0x17];
2110
2111         u8         reserved_at_80[0x20];
2112
2113         u8         rpg_time_reset[0x20];
2114
2115         u8         rpg_byte_reset[0x20];
2116
2117         u8         rpg_threshold[0x20];
2118
2119         u8         rpg_max_rate[0x20];
2120
2121         u8         rpg_ai_rate[0x20];
2122
2123         u8         rpg_hai_rate[0x20];
2124
2125         u8         rpg_gd[0x20];
2126
2127         u8         rpg_min_dec_fac[0x20];
2128
2129         u8         rpg_min_rate[0x20];
2130
2131         u8         reserved_at_1c0[0xe0];
2132
2133         u8         rate_to_set_on_first_cnp[0x20];
2134
2135         u8         dce_tcp_g[0x20];
2136
2137         u8         dce_tcp_rtt[0x20];
2138
2139         u8         rate_reduce_monitor_period[0x20];
2140
2141         u8         reserved_at_320[0x20];
2142
2143         u8         initial_alpha_value[0x20];
2144
2145         u8         reserved_at_360[0x4a0];
2146 };
2147
2148 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
2149         u8         reserved_at_0[0x80];
2150
2151         u8         rppp_max_rps[0x20];
2152
2153         u8         rpg_time_reset[0x20];
2154
2155         u8         rpg_byte_reset[0x20];
2156
2157         u8         rpg_threshold[0x20];
2158
2159         u8         rpg_max_rate[0x20];
2160
2161         u8         rpg_ai_rate[0x20];
2162
2163         u8         rpg_hai_rate[0x20];
2164
2165         u8         rpg_gd[0x20];
2166
2167         u8         rpg_min_dec_fac[0x20];
2168
2169         u8         rpg_min_rate[0x20];
2170
2171         u8         reserved_at_1c0[0x640];
2172 };
2173
2174 enum {
2175         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
2176         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
2177         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
2178 };
2179
2180 struct mlx5_ifc_resize_field_select_bits {
2181         u8         resize_field_select[0x20];
2182 };
2183
2184 struct mlx5_ifc_resource_dump_bits {
2185         u8         more_dump[0x1];
2186         u8         inline_dump[0x1];
2187         u8         reserved_at_2[0xa];
2188         u8         seq_num[0x4];
2189         u8         segment_type[0x10];
2190
2191         u8         reserved_at_20[0x10];
2192         u8         vhca_id[0x10];
2193
2194         u8         index1[0x20];
2195
2196         u8         index2[0x20];
2197
2198         u8         num_of_obj1[0x10];
2199         u8         num_of_obj2[0x10];
2200
2201         u8         reserved_at_a0[0x20];
2202
2203         u8         device_opaque[0x40];
2204
2205         u8         mkey[0x20];
2206
2207         u8         size[0x20];
2208
2209         u8         address[0x40];
2210
2211         u8         inline_data[52][0x20];
2212 };
2213
2214 struct mlx5_ifc_resource_dump_menu_record_bits {
2215         u8         reserved_at_0[0x4];
2216         u8         num_of_obj2_supports_active[0x1];
2217         u8         num_of_obj2_supports_all[0x1];
2218         u8         must_have_num_of_obj2[0x1];
2219         u8         support_num_of_obj2[0x1];
2220         u8         num_of_obj1_supports_active[0x1];
2221         u8         num_of_obj1_supports_all[0x1];
2222         u8         must_have_num_of_obj1[0x1];
2223         u8         support_num_of_obj1[0x1];
2224         u8         must_have_index2[0x1];
2225         u8         support_index2[0x1];
2226         u8         must_have_index1[0x1];
2227         u8         support_index1[0x1];
2228         u8         segment_type[0x10];
2229
2230         u8         segment_name[4][0x20];
2231
2232         u8         index1_name[4][0x20];
2233
2234         u8         index2_name[4][0x20];
2235 };
2236
2237 struct mlx5_ifc_resource_dump_segment_header_bits {
2238         u8         length_dw[0x10];
2239         u8         segment_type[0x10];
2240 };
2241
2242 struct mlx5_ifc_resource_dump_command_segment_bits {
2243         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2244
2245         u8         segment_called[0x10];
2246         u8         vhca_id[0x10];
2247
2248         u8         index1[0x20];
2249
2250         u8         index2[0x20];
2251
2252         u8         num_of_obj1[0x10];
2253         u8         num_of_obj2[0x10];
2254 };
2255
2256 struct mlx5_ifc_resource_dump_error_segment_bits {
2257         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2258
2259         u8         reserved_at_20[0x10];
2260         u8         syndrome_id[0x10];
2261
2262         u8         reserved_at_40[0x40];
2263
2264         u8         error[8][0x20];
2265 };
2266
2267 struct mlx5_ifc_resource_dump_info_segment_bits {
2268         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2269
2270         u8         reserved_at_20[0x18];
2271         u8         dump_version[0x8];
2272
2273         u8         hw_version[0x20];
2274
2275         u8         fw_version[0x20];
2276 };
2277
2278 struct mlx5_ifc_resource_dump_menu_segment_bits {
2279         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2280
2281         u8         reserved_at_20[0x10];
2282         u8         num_of_records[0x10];
2283
2284         struct mlx5_ifc_resource_dump_menu_record_bits record[];
2285 };
2286
2287 struct mlx5_ifc_resource_dump_resource_segment_bits {
2288         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2289
2290         u8         reserved_at_20[0x20];
2291
2292         u8         index1[0x20];
2293
2294         u8         index2[0x20];
2295
2296         u8         payload[][0x20];
2297 };
2298
2299 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2300         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2301 };
2302
2303 struct mlx5_ifc_menu_resource_dump_response_bits {
2304         struct mlx5_ifc_resource_dump_info_segment_bits info;
2305         struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2306         struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2307         struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2308 };
2309
2310 enum {
2311         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2312         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2313         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2314         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2315 };
2316
2317 struct mlx5_ifc_modify_field_select_bits {
2318         u8         modify_field_select[0x20];
2319 };
2320
2321 struct mlx5_ifc_field_select_r_roce_np_bits {
2322         u8         field_select_r_roce_np[0x20];
2323 };
2324
2325 struct mlx5_ifc_field_select_r_roce_rp_bits {
2326         u8         field_select_r_roce_rp[0x20];
2327 };
2328
2329 enum {
2330         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2331         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2332         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2333         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2334         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2335         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2336         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2337         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2338         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2339         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2340 };
2341
2342 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2343         u8         field_select_8021qaurp[0x20];
2344 };
2345
2346 struct mlx5_ifc_phys_layer_cntrs_bits {
2347         u8         time_since_last_clear_high[0x20];
2348
2349         u8         time_since_last_clear_low[0x20];
2350
2351         u8         symbol_errors_high[0x20];
2352
2353         u8         symbol_errors_low[0x20];
2354
2355         u8         sync_headers_errors_high[0x20];
2356
2357         u8         sync_headers_errors_low[0x20];
2358
2359         u8         edpl_bip_errors_lane0_high[0x20];
2360
2361         u8         edpl_bip_errors_lane0_low[0x20];
2362
2363         u8         edpl_bip_errors_lane1_high[0x20];
2364
2365         u8         edpl_bip_errors_lane1_low[0x20];
2366
2367         u8         edpl_bip_errors_lane2_high[0x20];
2368
2369         u8         edpl_bip_errors_lane2_low[0x20];
2370
2371         u8         edpl_bip_errors_lane3_high[0x20];
2372
2373         u8         edpl_bip_errors_lane3_low[0x20];
2374
2375         u8         fc_fec_corrected_blocks_lane0_high[0x20];
2376
2377         u8         fc_fec_corrected_blocks_lane0_low[0x20];
2378
2379         u8         fc_fec_corrected_blocks_lane1_high[0x20];
2380
2381         u8         fc_fec_corrected_blocks_lane1_low[0x20];
2382
2383         u8         fc_fec_corrected_blocks_lane2_high[0x20];
2384
2385         u8         fc_fec_corrected_blocks_lane2_low[0x20];
2386
2387         u8         fc_fec_corrected_blocks_lane3_high[0x20];
2388
2389         u8         fc_fec_corrected_blocks_lane3_low[0x20];
2390
2391         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2392
2393         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2394
2395         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2396
2397         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2398
2399         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2400
2401         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2402
2403         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2404
2405         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2406
2407         u8         rs_fec_corrected_blocks_high[0x20];
2408
2409         u8         rs_fec_corrected_blocks_low[0x20];
2410
2411         u8         rs_fec_uncorrectable_blocks_high[0x20];
2412
2413         u8         rs_fec_uncorrectable_blocks_low[0x20];
2414
2415         u8         rs_fec_no_errors_blocks_high[0x20];
2416
2417         u8         rs_fec_no_errors_blocks_low[0x20];
2418
2419         u8         rs_fec_single_error_blocks_high[0x20];
2420
2421         u8         rs_fec_single_error_blocks_low[0x20];
2422
2423         u8         rs_fec_corrected_symbols_total_high[0x20];
2424
2425         u8         rs_fec_corrected_symbols_total_low[0x20];
2426
2427         u8         rs_fec_corrected_symbols_lane0_high[0x20];
2428
2429         u8         rs_fec_corrected_symbols_lane0_low[0x20];
2430
2431         u8         rs_fec_corrected_symbols_lane1_high[0x20];
2432
2433         u8         rs_fec_corrected_symbols_lane1_low[0x20];
2434
2435         u8         rs_fec_corrected_symbols_lane2_high[0x20];
2436
2437         u8         rs_fec_corrected_symbols_lane2_low[0x20];
2438
2439         u8         rs_fec_corrected_symbols_lane3_high[0x20];
2440
2441         u8         rs_fec_corrected_symbols_lane3_low[0x20];
2442
2443         u8         link_down_events[0x20];
2444
2445         u8         successful_recovery_events[0x20];
2446
2447         u8         reserved_at_640[0x180];
2448 };
2449
2450 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2451         u8         time_since_last_clear_high[0x20];
2452
2453         u8         time_since_last_clear_low[0x20];
2454
2455         u8         phy_received_bits_high[0x20];
2456
2457         u8         phy_received_bits_low[0x20];
2458
2459         u8         phy_symbol_errors_high[0x20];
2460
2461         u8         phy_symbol_errors_low[0x20];
2462
2463         u8         phy_corrected_bits_high[0x20];
2464
2465         u8         phy_corrected_bits_low[0x20];
2466
2467         u8         phy_corrected_bits_lane0_high[0x20];
2468
2469         u8         phy_corrected_bits_lane0_low[0x20];
2470
2471         u8         phy_corrected_bits_lane1_high[0x20];
2472
2473         u8         phy_corrected_bits_lane1_low[0x20];
2474
2475         u8         phy_corrected_bits_lane2_high[0x20];
2476
2477         u8         phy_corrected_bits_lane2_low[0x20];
2478
2479         u8         phy_corrected_bits_lane3_high[0x20];
2480
2481         u8         phy_corrected_bits_lane3_low[0x20];
2482
2483         u8         reserved_at_200[0x5c0];
2484 };
2485
2486 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2487         u8         symbol_error_counter[0x10];
2488
2489         u8         link_error_recovery_counter[0x8];
2490
2491         u8         link_downed_counter[0x8];
2492
2493         u8         port_rcv_errors[0x10];
2494
2495         u8         port_rcv_remote_physical_errors[0x10];
2496
2497         u8         port_rcv_switch_relay_errors[0x10];
2498
2499         u8         port_xmit_discards[0x10];
2500
2501         u8         port_xmit_constraint_errors[0x8];
2502
2503         u8         port_rcv_constraint_errors[0x8];
2504
2505         u8         reserved_at_70[0x8];
2506
2507         u8         link_overrun_errors[0x8];
2508
2509         u8         reserved_at_80[0x10];
2510
2511         u8         vl_15_dropped[0x10];
2512
2513         u8         reserved_at_a0[0x80];
2514
2515         u8         port_xmit_wait[0x20];
2516 };
2517
2518 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2519         u8         transmit_queue_high[0x20];
2520
2521         u8         transmit_queue_low[0x20];
2522
2523         u8         no_buffer_discard_uc_high[0x20];
2524
2525         u8         no_buffer_discard_uc_low[0x20];
2526
2527         u8         reserved_at_80[0x740];
2528 };
2529
2530 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2531         u8         wred_discard_high[0x20];
2532
2533         u8         wred_discard_low[0x20];
2534
2535         u8         ecn_marked_tc_high[0x20];
2536
2537         u8         ecn_marked_tc_low[0x20];
2538
2539         u8         reserved_at_80[0x740];
2540 };
2541
2542 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2543         u8         rx_octets_high[0x20];
2544
2545         u8         rx_octets_low[0x20];
2546
2547         u8         reserved_at_40[0xc0];
2548
2549         u8         rx_frames_high[0x20];
2550
2551         u8         rx_frames_low[0x20];
2552
2553         u8         tx_octets_high[0x20];
2554
2555         u8         tx_octets_low[0x20];
2556
2557         u8         reserved_at_180[0xc0];
2558
2559         u8         tx_frames_high[0x20];
2560
2561         u8         tx_frames_low[0x20];
2562
2563         u8         rx_pause_high[0x20];
2564
2565         u8         rx_pause_low[0x20];
2566
2567         u8         rx_pause_duration_high[0x20];
2568
2569         u8         rx_pause_duration_low[0x20];
2570
2571         u8         tx_pause_high[0x20];
2572
2573         u8         tx_pause_low[0x20];
2574
2575         u8         tx_pause_duration_high[0x20];
2576
2577         u8         tx_pause_duration_low[0x20];
2578
2579         u8         rx_pause_transition_high[0x20];
2580
2581         u8         rx_pause_transition_low[0x20];
2582
2583         u8         rx_discards_high[0x20];
2584
2585         u8         rx_discards_low[0x20];
2586
2587         u8         device_stall_minor_watermark_cnt_high[0x20];
2588
2589         u8         device_stall_minor_watermark_cnt_low[0x20];
2590
2591         u8         device_stall_critical_watermark_cnt_high[0x20];
2592
2593         u8         device_stall_critical_watermark_cnt_low[0x20];
2594
2595         u8         reserved_at_480[0x340];
2596 };
2597
2598 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2599         u8         port_transmit_wait_high[0x20];
2600
2601         u8         port_transmit_wait_low[0x20];
2602
2603         u8         reserved_at_40[0x100];
2604
2605         u8         rx_buffer_almost_full_high[0x20];
2606
2607         u8         rx_buffer_almost_full_low[0x20];
2608
2609         u8         rx_buffer_full_high[0x20];
2610
2611         u8         rx_buffer_full_low[0x20];
2612
2613         u8         rx_icrc_encapsulated_high[0x20];
2614
2615         u8         rx_icrc_encapsulated_low[0x20];
2616
2617         u8         reserved_at_200[0x5c0];
2618 };
2619
2620 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2621         u8         dot3stats_alignment_errors_high[0x20];
2622
2623         u8         dot3stats_alignment_errors_low[0x20];
2624
2625         u8         dot3stats_fcs_errors_high[0x20];
2626
2627         u8         dot3stats_fcs_errors_low[0x20];
2628
2629         u8         dot3stats_single_collision_frames_high[0x20];
2630
2631         u8         dot3stats_single_collision_frames_low[0x20];
2632
2633         u8         dot3stats_multiple_collision_frames_high[0x20];
2634
2635         u8         dot3stats_multiple_collision_frames_low[0x20];
2636
2637         u8         dot3stats_sqe_test_errors_high[0x20];
2638
2639         u8         dot3stats_sqe_test_errors_low[0x20];
2640
2641         u8         dot3stats_deferred_transmissions_high[0x20];
2642
2643         u8         dot3stats_deferred_transmissions_low[0x20];
2644
2645         u8         dot3stats_late_collisions_high[0x20];
2646
2647         u8         dot3stats_late_collisions_low[0x20];
2648
2649         u8         dot3stats_excessive_collisions_high[0x20];
2650
2651         u8         dot3stats_excessive_collisions_low[0x20];
2652
2653         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2654
2655         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2656
2657         u8         dot3stats_carrier_sense_errors_high[0x20];
2658
2659         u8         dot3stats_carrier_sense_errors_low[0x20];
2660
2661         u8         dot3stats_frame_too_longs_high[0x20];
2662
2663         u8         dot3stats_frame_too_longs_low[0x20];
2664
2665         u8         dot3stats_internal_mac_receive_errors_high[0x20];
2666
2667         u8         dot3stats_internal_mac_receive_errors_low[0x20];
2668
2669         u8         dot3stats_symbol_errors_high[0x20];
2670
2671         u8         dot3stats_symbol_errors_low[0x20];
2672
2673         u8         dot3control_in_unknown_opcodes_high[0x20];
2674
2675         u8         dot3control_in_unknown_opcodes_low[0x20];
2676
2677         u8         dot3in_pause_frames_high[0x20];
2678
2679         u8         dot3in_pause_frames_low[0x20];
2680
2681         u8         dot3out_pause_frames_high[0x20];
2682
2683         u8         dot3out_pause_frames_low[0x20];
2684
2685         u8         reserved_at_400[0x3c0];
2686 };
2687
2688 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2689         u8         ether_stats_drop_events_high[0x20];
2690
2691         u8         ether_stats_drop_events_low[0x20];
2692
2693         u8         ether_stats_octets_high[0x20];
2694
2695         u8         ether_stats_octets_low[0x20];
2696
2697         u8         ether_stats_pkts_high[0x20];
2698
2699         u8         ether_stats_pkts_low[0x20];
2700
2701         u8         ether_stats_broadcast_pkts_high[0x20];
2702
2703         u8         ether_stats_broadcast_pkts_low[0x20];
2704
2705         u8         ether_stats_multicast_pkts_high[0x20];
2706
2707         u8         ether_stats_multicast_pkts_low[0x20];
2708
2709         u8         ether_stats_crc_align_errors_high[0x20];
2710
2711         u8         ether_stats_crc_align_errors_low[0x20];
2712
2713         u8         ether_stats_undersize_pkts_high[0x20];
2714
2715         u8         ether_stats_undersize_pkts_low[0x20];
2716
2717         u8         ether_stats_oversize_pkts_high[0x20];
2718
2719         u8         ether_stats_oversize_pkts_low[0x20];
2720
2721         u8         ether_stats_fragments_high[0x20];
2722
2723         u8         ether_stats_fragments_low[0x20];
2724
2725         u8         ether_stats_jabbers_high[0x20];
2726
2727         u8         ether_stats_jabbers_low[0x20];
2728
2729         u8         ether_stats_collisions_high[0x20];
2730
2731         u8         ether_stats_collisions_low[0x20];
2732
2733         u8         ether_stats_pkts64octets_high[0x20];
2734
2735         u8         ether_stats_pkts64octets_low[0x20];
2736
2737         u8         ether_stats_pkts65to127octets_high[0x20];
2738
2739         u8         ether_stats_pkts65to127octets_low[0x20];
2740
2741         u8         ether_stats_pkts128to255octets_high[0x20];
2742
2743         u8         ether_stats_pkts128to255octets_low[0x20];
2744
2745         u8         ether_stats_pkts256to511octets_high[0x20];
2746
2747         u8         ether_stats_pkts256to511octets_low[0x20];
2748
2749         u8         ether_stats_pkts512to1023octets_high[0x20];
2750
2751         u8         ether_stats_pkts512to1023octets_low[0x20];
2752
2753         u8         ether_stats_pkts1024to1518octets_high[0x20];
2754
2755         u8         ether_stats_pkts1024to1518octets_low[0x20];
2756
2757         u8         ether_stats_pkts1519to2047octets_high[0x20];
2758
2759         u8         ether_stats_pkts1519to2047octets_low[0x20];
2760
2761         u8         ether_stats_pkts2048to4095octets_high[0x20];
2762
2763         u8         ether_stats_pkts2048to4095octets_low[0x20];
2764
2765         u8         ether_stats_pkts4096to8191octets_high[0x20];
2766
2767         u8         ether_stats_pkts4096to8191octets_low[0x20];
2768
2769         u8         ether_stats_pkts8192to10239octets_high[0x20];
2770
2771         u8         ether_stats_pkts8192to10239octets_low[0x20];
2772
2773         u8         reserved_at_540[0x280];
2774 };
2775
2776 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2777         u8         if_in_octets_high[0x20];
2778
2779         u8         if_in_octets_low[0x20];
2780
2781         u8         if_in_ucast_pkts_high[0x20];
2782
2783         u8         if_in_ucast_pkts_low[0x20];
2784
2785         u8         if_in_discards_high[0x20];
2786
2787         u8         if_in_discards_low[0x20];
2788
2789         u8         if_in_errors_high[0x20];
2790
2791         u8         if_in_errors_low[0x20];
2792
2793         u8         if_in_unknown_protos_high[0x20];
2794
2795         u8         if_in_unknown_protos_low[0x20];
2796
2797         u8         if_out_octets_high[0x20];
2798
2799         u8         if_out_octets_low[0x20];
2800
2801         u8         if_out_ucast_pkts_high[0x20];
2802
2803         u8         if_out_ucast_pkts_low[0x20];
2804
2805         u8         if_out_discards_high[0x20];
2806
2807         u8         if_out_discards_low[0x20];
2808
2809         u8         if_out_errors_high[0x20];
2810
2811         u8         if_out_errors_low[0x20];
2812
2813         u8         if_in_multicast_pkts_high[0x20];
2814
2815         u8         if_in_multicast_pkts_low[0x20];
2816
2817         u8         if_in_broadcast_pkts_high[0x20];
2818
2819         u8         if_in_broadcast_pkts_low[0x20];
2820
2821         u8         if_out_multicast_pkts_high[0x20];
2822
2823         u8         if_out_multicast_pkts_low[0x20];
2824
2825         u8         if_out_broadcast_pkts_high[0x20];
2826
2827         u8         if_out_broadcast_pkts_low[0x20];
2828
2829         u8         reserved_at_340[0x480];
2830 };
2831
2832 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2833         u8         a_frames_transmitted_ok_high[0x20];
2834
2835         u8         a_frames_transmitted_ok_low[0x20];
2836
2837         u8         a_frames_received_ok_high[0x20];
2838
2839         u8         a_frames_received_ok_low[0x20];
2840
2841         u8         a_frame_check_sequence_errors_high[0x20];
2842
2843         u8         a_frame_check_sequence_errors_low[0x20];
2844
2845         u8         a_alignment_errors_high[0x20];
2846
2847         u8         a_alignment_errors_low[0x20];
2848
2849         u8         a_octets_transmitted_ok_high[0x20];
2850
2851         u8         a_octets_transmitted_ok_low[0x20];
2852
2853         u8         a_octets_received_ok_high[0x20];
2854
2855         u8         a_octets_received_ok_low[0x20];
2856
2857         u8         a_multicast_frames_xmitted_ok_high[0x20];
2858
2859         u8         a_multicast_frames_xmitted_ok_low[0x20];
2860
2861         u8         a_broadcast_frames_xmitted_ok_high[0x20];
2862
2863         u8         a_broadcast_frames_xmitted_ok_low[0x20];
2864
2865         u8         a_multicast_frames_received_ok_high[0x20];
2866
2867         u8         a_multicast_frames_received_ok_low[0x20];
2868
2869         u8         a_broadcast_frames_received_ok_high[0x20];
2870
2871         u8         a_broadcast_frames_received_ok_low[0x20];
2872
2873         u8         a_in_range_length_errors_high[0x20];
2874
2875         u8         a_in_range_length_errors_low[0x20];
2876
2877         u8         a_out_of_range_length_field_high[0x20];
2878
2879         u8         a_out_of_range_length_field_low[0x20];
2880
2881         u8         a_frame_too_long_errors_high[0x20];
2882
2883         u8         a_frame_too_long_errors_low[0x20];
2884
2885         u8         a_symbol_error_during_carrier_high[0x20];
2886
2887         u8         a_symbol_error_during_carrier_low[0x20];
2888
2889         u8         a_mac_control_frames_transmitted_high[0x20];
2890
2891         u8         a_mac_control_frames_transmitted_low[0x20];
2892
2893         u8         a_mac_control_frames_received_high[0x20];
2894
2895         u8         a_mac_control_frames_received_low[0x20];
2896
2897         u8         a_unsupported_opcodes_received_high[0x20];
2898
2899         u8         a_unsupported_opcodes_received_low[0x20];
2900
2901         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2902
2903         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2904
2905         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2906
2907         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2908
2909         u8         reserved_at_4c0[0x300];
2910 };
2911
2912 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2913         u8         life_time_counter_high[0x20];
2914
2915         u8         life_time_counter_low[0x20];
2916
2917         u8         rx_errors[0x20];
2918
2919         u8         tx_errors[0x20];
2920
2921         u8         l0_to_recovery_eieos[0x20];
2922
2923         u8         l0_to_recovery_ts[0x20];
2924
2925         u8         l0_to_recovery_framing[0x20];
2926
2927         u8         l0_to_recovery_retrain[0x20];
2928
2929         u8         crc_error_dllp[0x20];
2930
2931         u8         crc_error_tlp[0x20];
2932
2933         u8         tx_overflow_buffer_pkt_high[0x20];
2934
2935         u8         tx_overflow_buffer_pkt_low[0x20];
2936
2937         u8         outbound_stalled_reads[0x20];
2938
2939         u8         outbound_stalled_writes[0x20];
2940
2941         u8         outbound_stalled_reads_events[0x20];
2942
2943         u8         outbound_stalled_writes_events[0x20];
2944
2945         u8         reserved_at_200[0x5c0];
2946 };
2947
2948 struct mlx5_ifc_cmd_inter_comp_event_bits {
2949         u8         command_completion_vector[0x20];
2950
2951         u8         reserved_at_20[0xc0];
2952 };
2953
2954 struct mlx5_ifc_stall_vl_event_bits {
2955         u8         reserved_at_0[0x18];
2956         u8         port_num[0x1];
2957         u8         reserved_at_19[0x3];
2958         u8         vl[0x4];
2959
2960         u8         reserved_at_20[0xa0];
2961 };
2962
2963 struct mlx5_ifc_db_bf_congestion_event_bits {
2964         u8         event_subtype[0x8];
2965         u8         reserved_at_8[0x8];
2966         u8         congestion_level[0x8];
2967         u8         reserved_at_18[0x8];
2968
2969         u8         reserved_at_20[0xa0];
2970 };
2971
2972 struct mlx5_ifc_gpio_event_bits {
2973         u8         reserved_at_0[0x60];
2974
2975         u8         gpio_event_hi[0x20];
2976
2977         u8         gpio_event_lo[0x20];
2978
2979         u8         reserved_at_a0[0x40];
2980 };
2981
2982 struct mlx5_ifc_port_state_change_event_bits {
2983         u8         reserved_at_0[0x40];
2984
2985         u8         port_num[0x4];
2986         u8         reserved_at_44[0x1c];
2987
2988         u8         reserved_at_60[0x80];
2989 };
2990
2991 struct mlx5_ifc_dropped_packet_logged_bits {
2992         u8         reserved_at_0[0xe0];
2993 };
2994
2995 struct mlx5_ifc_default_timeout_bits {
2996         u8         to_multiplier[0x3];
2997         u8         reserved_at_3[0x9];
2998         u8         to_value[0x14];
2999 };
3000
3001 struct mlx5_ifc_dtor_reg_bits {
3002         u8         reserved_at_0[0x20];
3003
3004         struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
3005
3006         u8         reserved_at_40[0x60];
3007
3008         struct mlx5_ifc_default_timeout_bits health_poll_to;
3009
3010         struct mlx5_ifc_default_timeout_bits full_crdump_to;
3011
3012         struct mlx5_ifc_default_timeout_bits fw_reset_to;
3013
3014         struct mlx5_ifc_default_timeout_bits flush_on_err_to;
3015
3016         struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
3017
3018         struct mlx5_ifc_default_timeout_bits tear_down_to;
3019
3020         struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
3021
3022         struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
3023
3024         struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
3025
3026         u8         reserved_at_1c0[0x40];
3027 };
3028
3029 enum {
3030         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
3031         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
3032 };
3033
3034 struct mlx5_ifc_cq_error_bits {
3035         u8         reserved_at_0[0x8];
3036         u8         cqn[0x18];
3037
3038         u8         reserved_at_20[0x20];
3039
3040         u8         reserved_at_40[0x18];
3041         u8         syndrome[0x8];
3042
3043         u8         reserved_at_60[0x80];
3044 };
3045
3046 struct mlx5_ifc_rdma_page_fault_event_bits {
3047         u8         bytes_committed[0x20];
3048
3049         u8         r_key[0x20];
3050
3051         u8         reserved_at_40[0x10];
3052         u8         packet_len[0x10];
3053
3054         u8         rdma_op_len[0x20];
3055
3056         u8         rdma_va[0x40];
3057
3058         u8         reserved_at_c0[0x5];
3059         u8         rdma[0x1];
3060         u8         write[0x1];
3061         u8         requestor[0x1];
3062         u8         qp_number[0x18];
3063 };
3064
3065 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
3066         u8         bytes_committed[0x20];
3067
3068         u8         reserved_at_20[0x10];
3069         u8         wqe_index[0x10];
3070
3071         u8         reserved_at_40[0x10];
3072         u8         len[0x10];
3073
3074         u8         reserved_at_60[0x60];
3075
3076         u8         reserved_at_c0[0x5];
3077         u8         rdma[0x1];
3078         u8         write_read[0x1];
3079         u8         requestor[0x1];
3080         u8         qpn[0x18];
3081 };
3082
3083 struct mlx5_ifc_qp_events_bits {
3084         u8         reserved_at_0[0xa0];
3085
3086         u8         type[0x8];
3087         u8         reserved_at_a8[0x18];
3088
3089         u8         reserved_at_c0[0x8];
3090         u8         qpn_rqn_sqn[0x18];
3091 };
3092
3093 struct mlx5_ifc_dct_events_bits {
3094         u8         reserved_at_0[0xc0];
3095
3096         u8         reserved_at_c0[0x8];
3097         u8         dct_number[0x18];
3098 };
3099
3100 struct mlx5_ifc_comp_event_bits {
3101         u8         reserved_at_0[0xc0];
3102
3103         u8         reserved_at_c0[0x8];
3104         u8         cq_number[0x18];
3105 };
3106
3107 enum {
3108         MLX5_QPC_STATE_RST        = 0x0,
3109         MLX5_QPC_STATE_INIT       = 0x1,
3110         MLX5_QPC_STATE_RTR        = 0x2,
3111         MLX5_QPC_STATE_RTS        = 0x3,
3112         MLX5_QPC_STATE_SQER       = 0x4,
3113         MLX5_QPC_STATE_ERR        = 0x6,
3114         MLX5_QPC_STATE_SQD        = 0x7,
3115         MLX5_QPC_STATE_SUSPENDED  = 0x9,
3116 };
3117
3118 enum {
3119         MLX5_QPC_ST_RC            = 0x0,
3120         MLX5_QPC_ST_UC            = 0x1,
3121         MLX5_QPC_ST_UD            = 0x2,
3122         MLX5_QPC_ST_XRC           = 0x3,
3123         MLX5_QPC_ST_DCI           = 0x5,
3124         MLX5_QPC_ST_QP0           = 0x7,
3125         MLX5_QPC_ST_QP1           = 0x8,
3126         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
3127         MLX5_QPC_ST_REG_UMR       = 0xc,
3128 };
3129
3130 enum {
3131         MLX5_QPC_PM_STATE_ARMED     = 0x0,
3132         MLX5_QPC_PM_STATE_REARM     = 0x1,
3133         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
3134         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
3135 };
3136
3137 enum {
3138         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
3139 };
3140
3141 enum {
3142         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
3143         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
3144 };
3145
3146 enum {
3147         MLX5_QPC_MTU_256_BYTES        = 0x1,
3148         MLX5_QPC_MTU_512_BYTES        = 0x2,
3149         MLX5_QPC_MTU_1K_BYTES         = 0x3,
3150         MLX5_QPC_MTU_2K_BYTES         = 0x4,
3151         MLX5_QPC_MTU_4K_BYTES         = 0x5,
3152         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
3153 };
3154
3155 enum {
3156         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
3157         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
3158         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
3159         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
3160         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
3161         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
3162         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
3163         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
3164 };
3165
3166 enum {
3167         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
3168         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
3169         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
3170 };
3171
3172 enum {
3173         MLX5_QPC_CS_RES_DISABLE    = 0x0,
3174         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
3175         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
3176 };
3177
3178 enum {
3179         MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3180         MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
3181         MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
3182 };
3183
3184 struct mlx5_ifc_qpc_bits {
3185         u8         state[0x4];
3186         u8         lag_tx_port_affinity[0x4];
3187         u8         st[0x8];
3188         u8         reserved_at_10[0x2];
3189         u8         isolate_vl_tc[0x1];
3190         u8         pm_state[0x2];
3191         u8         reserved_at_15[0x1];
3192         u8         req_e2e_credit_mode[0x2];
3193         u8         offload_type[0x4];
3194         u8         end_padding_mode[0x2];
3195         u8         reserved_at_1e[0x2];
3196
3197         u8         wq_signature[0x1];
3198         u8         block_lb_mc[0x1];
3199         u8         atomic_like_write_en[0x1];
3200         u8         latency_sensitive[0x1];
3201         u8         reserved_at_24[0x1];
3202         u8         drain_sigerr[0x1];
3203         u8         reserved_at_26[0x2];
3204         u8         pd[0x18];
3205
3206         u8         mtu[0x3];
3207         u8         log_msg_max[0x5];
3208         u8         reserved_at_48[0x1];
3209         u8         log_rq_size[0x4];
3210         u8         log_rq_stride[0x3];
3211         u8         no_sq[0x1];
3212         u8         log_sq_size[0x4];
3213         u8         reserved_at_55[0x3];
3214         u8         ts_format[0x2];
3215         u8         reserved_at_5a[0x1];
3216         u8         rlky[0x1];
3217         u8         ulp_stateless_offload_mode[0x4];
3218
3219         u8         counter_set_id[0x8];
3220         u8         uar_page[0x18];
3221
3222         u8         reserved_at_80[0x8];
3223         u8         user_index[0x18];
3224
3225         u8         reserved_at_a0[0x3];
3226         u8         log_page_size[0x5];
3227         u8         remote_qpn[0x18];
3228
3229         struct mlx5_ifc_ads_bits primary_address_path;
3230
3231         struct mlx5_ifc_ads_bits secondary_address_path;
3232
3233         u8         log_ack_req_freq[0x4];
3234         u8         reserved_at_384[0x4];
3235         u8         log_sra_max[0x3];
3236         u8         reserved_at_38b[0x2];
3237         u8         retry_count[0x3];
3238         u8         rnr_retry[0x3];
3239         u8         reserved_at_393[0x1];
3240         u8         fre[0x1];
3241         u8         cur_rnr_retry[0x3];
3242         u8         cur_retry_count[0x3];
3243         u8         reserved_at_39b[0x5];
3244
3245         u8         reserved_at_3a0[0x20];
3246
3247         u8         reserved_at_3c0[0x8];
3248         u8         next_send_psn[0x18];
3249
3250         u8         reserved_at_3e0[0x3];
3251         u8         log_num_dci_stream_channels[0x5];
3252         u8         cqn_snd[0x18];
3253
3254         u8         reserved_at_400[0x3];
3255         u8         log_num_dci_errored_streams[0x5];
3256         u8         deth_sqpn[0x18];
3257
3258         u8         reserved_at_420[0x20];
3259
3260         u8         reserved_at_440[0x8];
3261         u8         last_acked_psn[0x18];
3262
3263         u8         reserved_at_460[0x8];
3264         u8         ssn[0x18];
3265
3266         u8         reserved_at_480[0x8];
3267         u8         log_rra_max[0x3];
3268         u8         reserved_at_48b[0x1];
3269         u8         atomic_mode[0x4];
3270         u8         rre[0x1];
3271         u8         rwe[0x1];
3272         u8         rae[0x1];
3273         u8         reserved_at_493[0x1];
3274         u8         page_offset[0x6];
3275         u8         reserved_at_49a[0x3];
3276         u8         cd_slave_receive[0x1];
3277         u8         cd_slave_send[0x1];
3278         u8         cd_master[0x1];
3279
3280         u8         reserved_at_4a0[0x3];
3281         u8         min_rnr_nak[0x5];
3282         u8         next_rcv_psn[0x18];
3283
3284         u8         reserved_at_4c0[0x8];
3285         u8         xrcd[0x18];
3286
3287         u8         reserved_at_4e0[0x8];
3288         u8         cqn_rcv[0x18];
3289
3290         u8         dbr_addr[0x40];
3291
3292         u8         q_key[0x20];
3293
3294         u8         reserved_at_560[0x5];
3295         u8         rq_type[0x3];
3296         u8         srqn_rmpn_xrqn[0x18];
3297
3298         u8         reserved_at_580[0x8];
3299         u8         rmsn[0x18];
3300
3301         u8         hw_sq_wqebb_counter[0x10];
3302         u8         sw_sq_wqebb_counter[0x10];
3303
3304         u8         hw_rq_counter[0x20];
3305
3306         u8         sw_rq_counter[0x20];
3307
3308         u8         reserved_at_600[0x20];
3309
3310         u8         reserved_at_620[0xf];
3311         u8         cgs[0x1];
3312         u8         cs_req[0x8];
3313         u8         cs_res[0x8];
3314
3315         u8         dc_access_key[0x40];
3316
3317         u8         reserved_at_680[0x3];
3318         u8         dbr_umem_valid[0x1];
3319
3320         u8         reserved_at_684[0xbc];
3321 };
3322
3323 struct mlx5_ifc_roce_addr_layout_bits {
3324         u8         source_l3_address[16][0x8];
3325
3326         u8         reserved_at_80[0x3];
3327         u8         vlan_valid[0x1];
3328         u8         vlan_id[0xc];
3329         u8         source_mac_47_32[0x10];
3330
3331         u8         source_mac_31_0[0x20];
3332
3333         u8         reserved_at_c0[0x14];
3334         u8         roce_l3_type[0x4];
3335         u8         roce_version[0x8];
3336
3337         u8         reserved_at_e0[0x20];
3338 };
3339
3340 struct mlx5_ifc_shampo_cap_bits {
3341         u8    reserved_at_0[0x3];
3342         u8    shampo_log_max_reservation_size[0x5];
3343         u8    reserved_at_8[0x3];
3344         u8    shampo_log_min_reservation_size[0x5];
3345         u8    shampo_min_mss_size[0x10];
3346
3347         u8    reserved_at_20[0x3];
3348         u8    shampo_max_log_headers_entry_size[0x5];
3349         u8    reserved_at_28[0x18];
3350
3351         u8    reserved_at_40[0x7c0];
3352 };
3353
3354 union mlx5_ifc_hca_cap_union_bits {
3355         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3356         struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3357         struct mlx5_ifc_odp_cap_bits odp_cap;
3358         struct mlx5_ifc_atomic_caps_bits atomic_caps;
3359         struct mlx5_ifc_roce_cap_bits roce_cap;
3360         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3361         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3362         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3363         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3364         struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3365         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
3366         struct mlx5_ifc_qos_cap_bits qos_cap;
3367         struct mlx5_ifc_debug_cap_bits debug_cap;
3368         struct mlx5_ifc_fpga_cap_bits fpga_cap;
3369         struct mlx5_ifc_tls_cap_bits tls_cap;
3370         struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3371         struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3372         struct mlx5_ifc_shampo_cap_bits shampo_cap;
3373         struct mlx5_ifc_macsec_cap_bits macsec_cap;
3374         u8         reserved_at_0[0x8000];
3375 };
3376
3377 enum {
3378         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3379         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3380         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3381         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3382         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3383         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3384         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3385         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3386         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3387         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3388         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3389         MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3390         MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
3391         MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
3392 };
3393
3394 enum {
3395         MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3396         MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3397         MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3398 };
3399
3400 enum {
3401         MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC   = 0x0,
3402         MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC  = 0x1,
3403 };
3404
3405 struct mlx5_ifc_vlan_bits {
3406         u8         ethtype[0x10];
3407         u8         prio[0x3];
3408         u8         cfi[0x1];
3409         u8         vid[0xc];
3410 };
3411
3412 enum {
3413         MLX5_FLOW_METER_COLOR_RED       = 0x0,
3414         MLX5_FLOW_METER_COLOR_YELLOW    = 0x1,
3415         MLX5_FLOW_METER_COLOR_GREEN     = 0x2,
3416         MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3,
3417 };
3418
3419 enum {
3420         MLX5_EXE_ASO_FLOW_METER         = 0x2,
3421 };
3422
3423 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3424         u8        return_reg_id[0x4];
3425         u8        aso_type[0x4];
3426         u8        reserved_at_8[0x14];
3427         u8        action[0x1];
3428         u8        init_color[0x2];
3429         u8        meter_id[0x1];
3430 };
3431
3432 union mlx5_ifc_exe_aso_ctrl {
3433         struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3434 };
3435
3436 struct mlx5_ifc_execute_aso_bits {
3437         u8        valid[0x1];
3438         u8        reserved_at_1[0x7];
3439         u8        aso_object_id[0x18];
3440
3441         union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3442 };
3443
3444 struct mlx5_ifc_flow_context_bits {
3445         struct mlx5_ifc_vlan_bits push_vlan;
3446
3447         u8         group_id[0x20];
3448
3449         u8         reserved_at_40[0x8];
3450         u8         flow_tag[0x18];
3451
3452         u8         reserved_at_60[0x10];
3453         u8         action[0x10];
3454
3455         u8         extended_destination[0x1];
3456         u8         reserved_at_81[0x1];
3457         u8         flow_source[0x2];
3458         u8         encrypt_decrypt_type[0x4];
3459         u8         destination_list_size[0x18];
3460
3461         u8         reserved_at_a0[0x8];
3462         u8         flow_counter_list_size[0x18];
3463
3464         u8         packet_reformat_id[0x20];
3465
3466         u8         modify_header_id[0x20];
3467
3468         struct mlx5_ifc_vlan_bits push_vlan_2;
3469
3470         u8         encrypt_decrypt_obj_id[0x20];
3471         u8         reserved_at_140[0xc0];
3472
3473         struct mlx5_ifc_fte_match_param_bits match_value;
3474
3475         struct mlx5_ifc_execute_aso_bits execute_aso[4];
3476
3477         u8         reserved_at_1300[0x500];
3478
3479         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3480 };
3481
3482 enum {
3483         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3484         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3485 };
3486
3487 struct mlx5_ifc_xrc_srqc_bits {
3488         u8         state[0x4];
3489         u8         log_xrc_srq_size[0x4];
3490         u8         reserved_at_8[0x18];
3491
3492         u8         wq_signature[0x1];
3493         u8         cont_srq[0x1];
3494         u8         reserved_at_22[0x1];
3495         u8         rlky[0x1];
3496         u8         basic_cyclic_rcv_wqe[0x1];
3497         u8         log_rq_stride[0x3];
3498         u8         xrcd[0x18];
3499
3500         u8         page_offset[0x6];
3501         u8         reserved_at_46[0x1];
3502         u8         dbr_umem_valid[0x1];
3503         u8         cqn[0x18];
3504
3505         u8         reserved_at_60[0x20];
3506
3507         u8         user_index_equal_xrc_srqn[0x1];
3508         u8         reserved_at_81[0x1];
3509         u8         log_page_size[0x6];
3510         u8         user_index[0x18];
3511
3512         u8         reserved_at_a0[0x20];
3513
3514         u8         reserved_at_c0[0x8];
3515         u8         pd[0x18];
3516
3517         u8         lwm[0x10];
3518         u8         wqe_cnt[0x10];
3519
3520         u8         reserved_at_100[0x40];
3521
3522         u8         db_record_addr_h[0x20];
3523
3524         u8         db_record_addr_l[0x1e];
3525         u8         reserved_at_17e[0x2];
3526
3527         u8         reserved_at_180[0x80];
3528 };
3529
3530 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3531         u8         counter_error_queues[0x20];
3532
3533         u8         total_error_queues[0x20];
3534
3535         u8         send_queue_priority_update_flow[0x20];
3536
3537         u8         reserved_at_60[0x20];
3538
3539         u8         nic_receive_steering_discard[0x40];
3540
3541         u8         receive_discard_vport_down[0x40];
3542
3543         u8         transmit_discard_vport_down[0x40];
3544
3545         u8         async_eq_overrun[0x20];
3546
3547         u8         comp_eq_overrun[0x20];
3548
3549         u8         reserved_at_180[0x20];
3550
3551         u8         invalid_command[0x20];
3552
3553         u8         quota_exceeded_command[0x20];
3554
3555         u8         internal_rq_out_of_buffer[0x20];
3556
3557         u8         cq_overrun[0x20];
3558
3559         u8         eth_wqe_too_small[0x20];
3560
3561         u8         reserved_at_220[0xdc0];
3562 };
3563
3564 struct mlx5_ifc_traffic_counter_bits {
3565         u8         packets[0x40];
3566
3567         u8         octets[0x40];
3568 };
3569
3570 struct mlx5_ifc_tisc_bits {
3571         u8         strict_lag_tx_port_affinity[0x1];
3572         u8         tls_en[0x1];
3573         u8         reserved_at_2[0x2];
3574         u8         lag_tx_port_affinity[0x04];
3575
3576         u8         reserved_at_8[0x4];
3577         u8         prio[0x4];
3578         u8         reserved_at_10[0x10];
3579
3580         u8         reserved_at_20[0x100];
3581
3582         u8         reserved_at_120[0x8];
3583         u8         transport_domain[0x18];
3584
3585         u8         reserved_at_140[0x8];
3586         u8         underlay_qpn[0x18];
3587
3588         u8         reserved_at_160[0x8];
3589         u8         pd[0x18];
3590
3591         u8         reserved_at_180[0x380];
3592 };
3593
3594 enum {
3595         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3596         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3597 };
3598
3599 enum {
3600         MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO  = BIT(0),
3601         MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO  = BIT(1),
3602 };
3603
3604 enum {
3605         MLX5_RX_HASH_FN_NONE           = 0x0,
3606         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3607         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3608 };
3609
3610 enum {
3611         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3612         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3613 };
3614
3615 struct mlx5_ifc_tirc_bits {
3616         u8         reserved_at_0[0x20];
3617
3618         u8         disp_type[0x4];
3619         u8         tls_en[0x1];
3620         u8         reserved_at_25[0x1b];
3621
3622         u8         reserved_at_40[0x40];
3623
3624         u8         reserved_at_80[0x4];
3625         u8         lro_timeout_period_usecs[0x10];
3626         u8         packet_merge_mask[0x4];
3627         u8         lro_max_ip_payload_size[0x8];
3628
3629         u8         reserved_at_a0[0x40];
3630
3631         u8         reserved_at_e0[0x8];
3632         u8         inline_rqn[0x18];
3633
3634         u8         rx_hash_symmetric[0x1];
3635         u8         reserved_at_101[0x1];
3636         u8         tunneled_offload_en[0x1];
3637         u8         reserved_at_103[0x5];
3638         u8         indirect_table[0x18];
3639
3640         u8         rx_hash_fn[0x4];
3641         u8         reserved_at_124[0x2];
3642         u8         self_lb_block[0x2];
3643         u8         transport_domain[0x18];
3644
3645         u8         rx_hash_toeplitz_key[10][0x20];
3646
3647         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3648
3649         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3650
3651         u8         reserved_at_2c0[0x4c0];
3652 };
3653
3654 enum {
3655         MLX5_SRQC_STATE_GOOD   = 0x0,
3656         MLX5_SRQC_STATE_ERROR  = 0x1,
3657 };
3658
3659 struct mlx5_ifc_srqc_bits {
3660         u8         state[0x4];
3661         u8         log_srq_size[0x4];
3662         u8         reserved_at_8[0x18];
3663
3664         u8         wq_signature[0x1];
3665         u8         cont_srq[0x1];
3666         u8         reserved_at_22[0x1];
3667         u8         rlky[0x1];
3668         u8         reserved_at_24[0x1];
3669         u8         log_rq_stride[0x3];
3670         u8         xrcd[0x18];
3671
3672         u8         page_offset[0x6];
3673         u8         reserved_at_46[0x2];
3674         u8         cqn[0x18];
3675
3676         u8         reserved_at_60[0x20];
3677
3678         u8         reserved_at_80[0x2];
3679         u8         log_page_size[0x6];
3680         u8         reserved_at_88[0x18];
3681
3682         u8         reserved_at_a0[0x20];
3683
3684         u8         reserved_at_c0[0x8];
3685         u8         pd[0x18];
3686
3687         u8         lwm[0x10];
3688         u8         wqe_cnt[0x10];
3689
3690         u8         reserved_at_100[0x40];
3691
3692         u8         dbr_addr[0x40];
3693
3694         u8         reserved_at_180[0x80];
3695 };
3696
3697 enum {
3698         MLX5_SQC_STATE_RST  = 0x0,
3699         MLX5_SQC_STATE_RDY  = 0x1,
3700         MLX5_SQC_STATE_ERR  = 0x3,
3701 };
3702
3703 struct mlx5_ifc_sqc_bits {
3704         u8         rlky[0x1];
3705         u8         cd_master[0x1];
3706         u8         fre[0x1];
3707         u8         flush_in_error_en[0x1];
3708         u8         allow_multi_pkt_send_wqe[0x1];
3709         u8         min_wqe_inline_mode[0x3];
3710         u8         state[0x4];
3711         u8         reg_umr[0x1];
3712         u8         allow_swp[0x1];
3713         u8         hairpin[0x1];
3714         u8         reserved_at_f[0xb];
3715         u8         ts_format[0x2];
3716         u8         reserved_at_1c[0x4];
3717
3718         u8         reserved_at_20[0x8];
3719         u8         user_index[0x18];
3720
3721         u8         reserved_at_40[0x8];
3722         u8         cqn[0x18];
3723
3724         u8         reserved_at_60[0x8];
3725         u8         hairpin_peer_rq[0x18];
3726
3727         u8         reserved_at_80[0x10];
3728         u8         hairpin_peer_vhca[0x10];
3729
3730         u8         reserved_at_a0[0x20];
3731
3732         u8         reserved_at_c0[0x8];
3733         u8         ts_cqe_to_dest_cqn[0x18];
3734
3735         u8         reserved_at_e0[0x10];
3736         u8         packet_pacing_rate_limit_index[0x10];
3737         u8         tis_lst_sz[0x10];
3738         u8         qos_queue_group_id[0x10];
3739
3740         u8         reserved_at_120[0x40];
3741
3742         u8         reserved_at_160[0x8];
3743         u8         tis_num_0[0x18];
3744
3745         struct mlx5_ifc_wq_bits wq;
3746 };
3747
3748 enum {
3749         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3750         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3751         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3752         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3753         SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
3754 };
3755
3756 enum {
3757         ELEMENT_TYPE_CAP_MASK_TASR              = 1 << 0,
3758         ELEMENT_TYPE_CAP_MASK_VPORT             = 1 << 1,
3759         ELEMENT_TYPE_CAP_MASK_VPORT_TC          = 1 << 2,
3760         ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC     = 1 << 3,
3761 };
3762
3763 struct mlx5_ifc_scheduling_context_bits {
3764         u8         element_type[0x8];
3765         u8         reserved_at_8[0x18];
3766
3767         u8         element_attributes[0x20];
3768
3769         u8         parent_element_id[0x20];
3770
3771         u8         reserved_at_60[0x40];
3772
3773         u8         bw_share[0x20];
3774
3775         u8         max_average_bw[0x20];
3776
3777         u8         reserved_at_e0[0x120];
3778 };
3779
3780 struct mlx5_ifc_rqtc_bits {
3781         u8    reserved_at_0[0xa0];
3782
3783         u8    reserved_at_a0[0x5];
3784         u8    list_q_type[0x3];
3785         u8    reserved_at_a8[0x8];
3786         u8    rqt_max_size[0x10];
3787
3788         u8    rq_vhca_id_format[0x1];
3789         u8    reserved_at_c1[0xf];
3790         u8    rqt_actual_size[0x10];
3791
3792         u8    reserved_at_e0[0x6a0];
3793
3794         struct mlx5_ifc_rq_num_bits rq_num[];
3795 };
3796
3797 enum {
3798         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3799         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3800 };
3801
3802 enum {
3803         MLX5_RQC_STATE_RST  = 0x0,
3804         MLX5_RQC_STATE_RDY  = 0x1,
3805         MLX5_RQC_STATE_ERR  = 0x3,
3806 };
3807
3808 enum {
3809         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE    = 0x0,
3810         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE  = 0x1,
3811         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE    = 0x2,
3812 };
3813
3814 enum {
3815         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH    = 0x0,
3816         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED    = 0x1,
3817         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE  = 0x2,
3818 };
3819
3820 struct mlx5_ifc_rqc_bits {
3821         u8         rlky[0x1];
3822         u8         delay_drop_en[0x1];
3823         u8         scatter_fcs[0x1];
3824         u8         vsd[0x1];
3825         u8         mem_rq_type[0x4];
3826         u8         state[0x4];
3827         u8         reserved_at_c[0x1];
3828         u8         flush_in_error_en[0x1];
3829         u8         hairpin[0x1];
3830         u8         reserved_at_f[0xb];
3831         u8         ts_format[0x2];
3832         u8         reserved_at_1c[0x4];
3833
3834         u8         reserved_at_20[0x8];
3835         u8         user_index[0x18];
3836
3837         u8         reserved_at_40[0x8];
3838         u8         cqn[0x18];
3839
3840         u8         counter_set_id[0x8];
3841         u8         reserved_at_68[0x18];
3842
3843         u8         reserved_at_80[0x8];
3844         u8         rmpn[0x18];
3845
3846         u8         reserved_at_a0[0x8];
3847         u8         hairpin_peer_sq[0x18];
3848
3849         u8         reserved_at_c0[0x10];
3850         u8         hairpin_peer_vhca[0x10];
3851
3852         u8         reserved_at_e0[0x46];
3853         u8         shampo_no_match_alignment_granularity[0x2];
3854         u8         reserved_at_128[0x6];
3855         u8         shampo_match_criteria_type[0x2];
3856         u8         reservation_timeout[0x10];
3857
3858         u8         reserved_at_140[0x40];
3859
3860         struct mlx5_ifc_wq_bits wq;
3861 };
3862
3863 enum {
3864         MLX5_RMPC_STATE_RDY  = 0x1,
3865         MLX5_RMPC_STATE_ERR  = 0x3,
3866 };
3867
3868 struct mlx5_ifc_rmpc_bits {
3869         u8         reserved_at_0[0x8];
3870         u8         state[0x4];
3871         u8         reserved_at_c[0x14];
3872
3873         u8         basic_cyclic_rcv_wqe[0x1];
3874         u8         reserved_at_21[0x1f];
3875
3876         u8         reserved_at_40[0x140];
3877
3878         struct mlx5_ifc_wq_bits wq;
3879 };
3880
3881 enum {
3882         VHCA_ID_TYPE_HW = 0,
3883         VHCA_ID_TYPE_SW = 1,
3884 };
3885
3886 struct mlx5_ifc_nic_vport_context_bits {
3887         u8         reserved_at_0[0x5];
3888         u8         min_wqe_inline_mode[0x3];
3889         u8         reserved_at_8[0x15];
3890         u8         disable_mc_local_lb[0x1];
3891         u8         disable_uc_local_lb[0x1];
3892         u8         roce_en[0x1];
3893
3894         u8         arm_change_event[0x1];
3895         u8         reserved_at_21[0x1a];
3896         u8         event_on_mtu[0x1];
3897         u8         event_on_promisc_change[0x1];
3898         u8         event_on_vlan_change[0x1];
3899         u8         event_on_mc_address_change[0x1];
3900         u8         event_on_uc_address_change[0x1];
3901
3902         u8         vhca_id_type[0x1];
3903         u8         reserved_at_41[0xb];
3904         u8         affiliation_criteria[0x4];
3905         u8         affiliated_vhca_id[0x10];
3906
3907         u8         reserved_at_60[0xd0];
3908
3909         u8         mtu[0x10];
3910
3911         u8         system_image_guid[0x40];
3912         u8         port_guid[0x40];
3913         u8         node_guid[0x40];
3914
3915         u8         reserved_at_200[0x140];
3916         u8         qkey_violation_counter[0x10];
3917         u8         reserved_at_350[0x430];
3918
3919         u8         promisc_uc[0x1];
3920         u8         promisc_mc[0x1];
3921         u8         promisc_all[0x1];
3922         u8         reserved_at_783[0x2];
3923         u8         allowed_list_type[0x3];
3924         u8         reserved_at_788[0xc];
3925         u8         allowed_list_size[0xc];
3926
3927         struct mlx5_ifc_mac_address_layout_bits permanent_address;
3928
3929         u8         reserved_at_7e0[0x20];
3930
3931         u8         current_uc_mac_address[][0x40];
3932 };
3933
3934 enum {
3935         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
3936         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
3937         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
3938         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
3939         MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3940         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3941 };
3942
3943 struct mlx5_ifc_mkc_bits {
3944         u8         reserved_at_0[0x1];
3945         u8         free[0x1];
3946         u8         reserved_at_2[0x1];
3947         u8         access_mode_4_2[0x3];
3948         u8         reserved_at_6[0x7];
3949         u8         relaxed_ordering_write[0x1];
3950         u8         reserved_at_e[0x1];
3951         u8         small_fence_on_rdma_read_response[0x1];
3952         u8         umr_en[0x1];
3953         u8         a[0x1];
3954         u8         rw[0x1];
3955         u8         rr[0x1];
3956         u8         lw[0x1];
3957         u8         lr[0x1];
3958         u8         access_mode_1_0[0x2];
3959         u8         reserved_at_18[0x2];
3960         u8         ma_translation_mode[0x2];
3961         u8         reserved_at_1c[0x4];
3962
3963         u8         qpn[0x18];
3964         u8         mkey_7_0[0x8];
3965
3966         u8         reserved_at_40[0x20];
3967
3968         u8         length64[0x1];
3969         u8         bsf_en[0x1];
3970         u8         sync_umr[0x1];
3971         u8         reserved_at_63[0x2];
3972         u8         expected_sigerr_count[0x1];
3973         u8         reserved_at_66[0x1];
3974         u8         en_rinval[0x1];
3975         u8         pd[0x18];
3976
3977         u8         start_addr[0x40];
3978
3979         u8         len[0x40];
3980
3981         u8         bsf_octword_size[0x20];
3982
3983         u8         reserved_at_120[0x80];
3984
3985         u8         translations_octword_size[0x20];
3986
3987         u8         reserved_at_1c0[0x19];
3988         u8         relaxed_ordering_read[0x1];
3989         u8         reserved_at_1d9[0x1];
3990         u8         log_page_size[0x5];
3991
3992         u8         reserved_at_1e0[0x20];
3993 };
3994
3995 struct mlx5_ifc_pkey_bits {
3996         u8         reserved_at_0[0x10];
3997         u8         pkey[0x10];
3998 };
3999
4000 struct mlx5_ifc_array128_auto_bits {
4001         u8         array128_auto[16][0x8];
4002 };
4003
4004 struct mlx5_ifc_hca_vport_context_bits {
4005         u8         field_select[0x20];
4006
4007         u8         reserved_at_20[0xe0];
4008
4009         u8         sm_virt_aware[0x1];
4010         u8         has_smi[0x1];
4011         u8         has_raw[0x1];
4012         u8         grh_required[0x1];
4013         u8         reserved_at_104[0xc];
4014         u8         port_physical_state[0x4];
4015         u8         vport_state_policy[0x4];
4016         u8         port_state[0x4];
4017         u8         vport_state[0x4];
4018
4019         u8         reserved_at_120[0x20];
4020
4021         u8         system_image_guid[0x40];
4022
4023         u8         port_guid[0x40];
4024
4025         u8         node_guid[0x40];
4026
4027         u8         cap_mask1[0x20];
4028
4029         u8         cap_mask1_field_select[0x20];
4030
4031         u8         cap_mask2[0x20];
4032
4033         u8         cap_mask2_field_select[0x20];
4034
4035         u8         reserved_at_280[0x80];
4036
4037         u8         lid[0x10];
4038         u8         reserved_at_310[0x4];
4039         u8         init_type_reply[0x4];
4040         u8         lmc[0x3];
4041         u8         subnet_timeout[0x5];
4042
4043         u8         sm_lid[0x10];
4044         u8         sm_sl[0x4];
4045         u8         reserved_at_334[0xc];
4046
4047         u8         qkey_violation_counter[0x10];
4048         u8         pkey_violation_counter[0x10];
4049
4050         u8         reserved_at_360[0xca0];
4051 };
4052
4053 struct mlx5_ifc_esw_vport_context_bits {
4054         u8         fdb_to_vport_reg_c[0x1];
4055         u8         reserved_at_1[0x2];
4056         u8         vport_svlan_strip[0x1];
4057         u8         vport_cvlan_strip[0x1];
4058         u8         vport_svlan_insert[0x1];
4059         u8         vport_cvlan_insert[0x2];
4060         u8         fdb_to_vport_reg_c_id[0x8];
4061         u8         reserved_at_10[0x10];
4062
4063         u8         reserved_at_20[0x20];
4064
4065         u8         svlan_cfi[0x1];
4066         u8         svlan_pcp[0x3];
4067         u8         svlan_id[0xc];
4068         u8         cvlan_cfi[0x1];
4069         u8         cvlan_pcp[0x3];
4070         u8         cvlan_id[0xc];
4071
4072         u8         reserved_at_60[0x720];
4073
4074         u8         sw_steering_vport_icm_address_rx[0x40];
4075
4076         u8         sw_steering_vport_icm_address_tx[0x40];
4077 };
4078
4079 enum {
4080         MLX5_EQC_STATUS_OK                = 0x0,
4081         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
4082 };
4083
4084 enum {
4085         MLX5_EQC_ST_ARMED  = 0x9,
4086         MLX5_EQC_ST_FIRED  = 0xa,
4087 };
4088
4089 struct mlx5_ifc_eqc_bits {
4090         u8         status[0x4];
4091         u8         reserved_at_4[0x9];
4092         u8         ec[0x1];
4093         u8         oi[0x1];
4094         u8         reserved_at_f[0x5];
4095         u8         st[0x4];
4096         u8         reserved_at_18[0x8];
4097
4098         u8         reserved_at_20[0x20];
4099
4100         u8         reserved_at_40[0x14];
4101         u8         page_offset[0x6];
4102         u8         reserved_at_5a[0x6];
4103
4104         u8         reserved_at_60[0x3];
4105         u8         log_eq_size[0x5];
4106         u8         uar_page[0x18];
4107
4108         u8         reserved_at_80[0x20];
4109
4110         u8         reserved_at_a0[0x14];
4111         u8         intr[0xc];
4112
4113         u8         reserved_at_c0[0x3];
4114         u8         log_page_size[0x5];
4115         u8         reserved_at_c8[0x18];
4116
4117         u8         reserved_at_e0[0x60];
4118
4119         u8         reserved_at_140[0x8];
4120         u8         consumer_counter[0x18];
4121
4122         u8         reserved_at_160[0x8];
4123         u8         producer_counter[0x18];
4124
4125         u8         reserved_at_180[0x80];
4126 };
4127
4128 enum {
4129         MLX5_DCTC_STATE_ACTIVE    = 0x0,
4130         MLX5_DCTC_STATE_DRAINING  = 0x1,
4131         MLX5_DCTC_STATE_DRAINED   = 0x2,
4132 };
4133
4134 enum {
4135         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
4136         MLX5_DCTC_CS_RES_NA         = 0x1,
4137         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
4138 };
4139
4140 enum {
4141         MLX5_DCTC_MTU_256_BYTES  = 0x1,
4142         MLX5_DCTC_MTU_512_BYTES  = 0x2,
4143         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
4144         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
4145         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
4146 };
4147
4148 struct mlx5_ifc_dctc_bits {
4149         u8         reserved_at_0[0x4];
4150         u8         state[0x4];
4151         u8         reserved_at_8[0x18];
4152
4153         u8         reserved_at_20[0x8];
4154         u8         user_index[0x18];
4155
4156         u8         reserved_at_40[0x8];
4157         u8         cqn[0x18];
4158
4159         u8         counter_set_id[0x8];
4160         u8         atomic_mode[0x4];
4161         u8         rre[0x1];
4162         u8         rwe[0x1];
4163         u8         rae[0x1];
4164         u8         atomic_like_write_en[0x1];
4165         u8         latency_sensitive[0x1];
4166         u8         rlky[0x1];
4167         u8         free_ar[0x1];
4168         u8         reserved_at_73[0xd];
4169
4170         u8         reserved_at_80[0x8];
4171         u8         cs_res[0x8];
4172         u8         reserved_at_90[0x3];
4173         u8         min_rnr_nak[0x5];
4174         u8         reserved_at_98[0x8];
4175
4176         u8         reserved_at_a0[0x8];
4177         u8         srqn_xrqn[0x18];
4178
4179         u8         reserved_at_c0[0x8];
4180         u8         pd[0x18];
4181
4182         u8         tclass[0x8];
4183         u8         reserved_at_e8[0x4];
4184         u8         flow_label[0x14];
4185
4186         u8         dc_access_key[0x40];
4187
4188         u8         reserved_at_140[0x5];
4189         u8         mtu[0x3];
4190         u8         port[0x8];
4191         u8         pkey_index[0x10];
4192
4193         u8         reserved_at_160[0x8];
4194         u8         my_addr_index[0x8];
4195         u8         reserved_at_170[0x8];
4196         u8         hop_limit[0x8];
4197
4198         u8         dc_access_key_violation_count[0x20];
4199
4200         u8         reserved_at_1a0[0x14];
4201         u8         dei_cfi[0x1];
4202         u8         eth_prio[0x3];
4203         u8         ecn[0x2];
4204         u8         dscp[0x6];
4205
4206         u8         reserved_at_1c0[0x20];
4207         u8         ece[0x20];
4208 };
4209
4210 enum {
4211         MLX5_CQC_STATUS_OK             = 0x0,
4212         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
4213         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
4214 };
4215
4216 enum {
4217         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
4218         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
4219 };
4220
4221 enum {
4222         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
4223         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
4224         MLX5_CQC_ST_FIRED                                 = 0xa,
4225 };
4226
4227 enum {
4228         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4229         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4230         MLX5_CQ_PERIOD_NUM_MODES
4231 };
4232
4233 struct mlx5_ifc_cqc_bits {
4234         u8         status[0x4];
4235         u8         reserved_at_4[0x2];
4236         u8         dbr_umem_valid[0x1];
4237         u8         apu_cq[0x1];
4238         u8         cqe_sz[0x3];
4239         u8         cc[0x1];
4240         u8         reserved_at_c[0x1];
4241         u8         scqe_break_moderation_en[0x1];
4242         u8         oi[0x1];
4243         u8         cq_period_mode[0x2];
4244         u8         cqe_comp_en[0x1];
4245         u8         mini_cqe_res_format[0x2];
4246         u8         st[0x4];
4247         u8         reserved_at_18[0x6];
4248         u8         cqe_compression_layout[0x2];
4249
4250         u8         reserved_at_20[0x20];
4251
4252         u8         reserved_at_40[0x14];
4253         u8         page_offset[0x6];
4254         u8         reserved_at_5a[0x6];
4255
4256         u8         reserved_at_60[0x3];
4257         u8         log_cq_size[0x5];
4258         u8         uar_page[0x18];
4259
4260         u8         reserved_at_80[0x4];
4261         u8         cq_period[0xc];
4262         u8         cq_max_count[0x10];
4263
4264         u8         c_eqn_or_apu_element[0x20];
4265
4266         u8         reserved_at_c0[0x3];
4267         u8         log_page_size[0x5];
4268         u8         reserved_at_c8[0x18];
4269
4270         u8         reserved_at_e0[0x20];
4271
4272         u8         reserved_at_100[0x8];
4273         u8         last_notified_index[0x18];
4274
4275         u8         reserved_at_120[0x8];
4276         u8         last_solicit_index[0x18];
4277
4278         u8         reserved_at_140[0x8];
4279         u8         consumer_counter[0x18];
4280
4281         u8         reserved_at_160[0x8];
4282         u8         producer_counter[0x18];
4283
4284         u8         reserved_at_180[0x40];
4285
4286         u8         dbr_addr[0x40];
4287 };
4288
4289 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4290         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4291         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4292         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4293         u8         reserved_at_0[0x800];
4294 };
4295
4296 struct mlx5_ifc_query_adapter_param_block_bits {
4297         u8         reserved_at_0[0xc0];
4298
4299         u8         reserved_at_c0[0x8];
4300         u8         ieee_vendor_id[0x18];
4301
4302         u8         reserved_at_e0[0x10];
4303         u8         vsd_vendor_id[0x10];
4304
4305         u8         vsd[208][0x8];
4306
4307         u8         vsd_contd_psid[16][0x8];
4308 };
4309
4310 enum {
4311         MLX5_XRQC_STATE_GOOD   = 0x0,
4312         MLX5_XRQC_STATE_ERROR  = 0x1,
4313 };
4314
4315 enum {
4316         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4317         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4318 };
4319
4320 enum {
4321         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4322 };
4323
4324 struct mlx5_ifc_tag_matching_topology_context_bits {
4325         u8         log_matching_list_sz[0x4];
4326         u8         reserved_at_4[0xc];
4327         u8         append_next_index[0x10];
4328
4329         u8         sw_phase_cnt[0x10];
4330         u8         hw_phase_cnt[0x10];
4331
4332         u8         reserved_at_40[0x40];
4333 };
4334
4335 struct mlx5_ifc_xrqc_bits {
4336         u8         state[0x4];
4337         u8         rlkey[0x1];
4338         u8         reserved_at_5[0xf];
4339         u8         topology[0x4];
4340         u8         reserved_at_18[0x4];
4341         u8         offload[0x4];
4342
4343         u8         reserved_at_20[0x8];
4344         u8         user_index[0x18];
4345
4346         u8         reserved_at_40[0x8];
4347         u8         cqn[0x18];
4348
4349         u8         reserved_at_60[0xa0];
4350
4351         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4352
4353         u8         reserved_at_180[0x280];
4354
4355         struct mlx5_ifc_wq_bits wq;
4356 };
4357
4358 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4359         struct mlx5_ifc_modify_field_select_bits modify_field_select;
4360         struct mlx5_ifc_resize_field_select_bits resize_field_select;
4361         u8         reserved_at_0[0x20];
4362 };
4363
4364 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4365         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4366         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4367         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4368         u8         reserved_at_0[0x20];
4369 };
4370
4371 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4372         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4373         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4374         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4375         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4376         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4377         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4378         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4379         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4380         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4381         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4382         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4383         u8         reserved_at_0[0x7c0];
4384 };
4385
4386 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4387         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4388         u8         reserved_at_0[0x7c0];
4389 };
4390
4391 union mlx5_ifc_event_auto_bits {
4392         struct mlx5_ifc_comp_event_bits comp_event;
4393         struct mlx5_ifc_dct_events_bits dct_events;
4394         struct mlx5_ifc_qp_events_bits qp_events;
4395         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4396         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4397         struct mlx5_ifc_cq_error_bits cq_error;
4398         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4399         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4400         struct mlx5_ifc_gpio_event_bits gpio_event;
4401         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4402         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4403         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4404         u8         reserved_at_0[0xe0];
4405 };
4406
4407 struct mlx5_ifc_health_buffer_bits {
4408         u8         reserved_at_0[0x100];
4409
4410         u8         assert_existptr[0x20];
4411
4412         u8         assert_callra[0x20];
4413
4414         u8         reserved_at_140[0x20];
4415
4416         u8         time[0x20];
4417
4418         u8         fw_version[0x20];
4419
4420         u8         hw_id[0x20];
4421
4422         u8         rfr[0x1];
4423         u8         reserved_at_1c1[0x3];
4424         u8         valid[0x1];
4425         u8         severity[0x3];
4426         u8         reserved_at_1c8[0x18];
4427
4428         u8         irisc_index[0x8];
4429         u8         synd[0x8];
4430         u8         ext_synd[0x10];
4431 };
4432
4433 struct mlx5_ifc_register_loopback_control_bits {
4434         u8         no_lb[0x1];
4435         u8         reserved_at_1[0x7];
4436         u8         port[0x8];
4437         u8         reserved_at_10[0x10];
4438
4439         u8         reserved_at_20[0x60];
4440 };
4441
4442 struct mlx5_ifc_vport_tc_element_bits {
4443         u8         traffic_class[0x4];
4444         u8         reserved_at_4[0xc];
4445         u8         vport_number[0x10];
4446 };
4447
4448 struct mlx5_ifc_vport_element_bits {
4449         u8         reserved_at_0[0x10];
4450         u8         vport_number[0x10];
4451 };
4452
4453 enum {
4454         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4455         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4456         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4457 };
4458
4459 struct mlx5_ifc_tsar_element_bits {
4460         u8         reserved_at_0[0x8];
4461         u8         tsar_type[0x8];
4462         u8         reserved_at_10[0x10];
4463 };
4464
4465 enum {
4466         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4467         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4468 };
4469
4470 struct mlx5_ifc_teardown_hca_out_bits {
4471         u8         status[0x8];
4472         u8         reserved_at_8[0x18];
4473
4474         u8         syndrome[0x20];
4475
4476         u8         reserved_at_40[0x3f];
4477
4478         u8         state[0x1];
4479 };
4480
4481 enum {
4482         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
4483         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
4484         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4485 };
4486
4487 struct mlx5_ifc_teardown_hca_in_bits {
4488         u8         opcode[0x10];
4489         u8         reserved_at_10[0x10];
4490
4491         u8         reserved_at_20[0x10];
4492         u8         op_mod[0x10];
4493
4494         u8         reserved_at_40[0x10];
4495         u8         profile[0x10];
4496
4497         u8         reserved_at_60[0x20];
4498 };
4499
4500 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4501         u8         status[0x8];
4502         u8         reserved_at_8[0x18];
4503
4504         u8         syndrome[0x20];
4505
4506         u8         reserved_at_40[0x40];
4507 };
4508
4509 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4510         u8         opcode[0x10];
4511         u8         uid[0x10];
4512
4513         u8         reserved_at_20[0x10];
4514         u8         op_mod[0x10];
4515
4516         u8         reserved_at_40[0x8];
4517         u8         qpn[0x18];
4518
4519         u8         reserved_at_60[0x20];
4520
4521         u8         opt_param_mask[0x20];
4522
4523         u8         reserved_at_a0[0x20];
4524
4525         struct mlx5_ifc_qpc_bits qpc;
4526
4527         u8         reserved_at_800[0x80];
4528 };
4529
4530 struct mlx5_ifc_sqd2rts_qp_out_bits {
4531         u8         status[0x8];
4532         u8         reserved_at_8[0x18];
4533
4534         u8         syndrome[0x20];
4535
4536         u8         reserved_at_40[0x40];
4537 };
4538
4539 struct mlx5_ifc_sqd2rts_qp_in_bits {
4540         u8         opcode[0x10];
4541         u8         uid[0x10];
4542
4543         u8         reserved_at_20[0x10];
4544         u8         op_mod[0x10];
4545
4546         u8         reserved_at_40[0x8];
4547         u8         qpn[0x18];
4548
4549         u8         reserved_at_60[0x20];
4550
4551         u8         opt_param_mask[0x20];
4552
4553         u8         reserved_at_a0[0x20];
4554
4555         struct mlx5_ifc_qpc_bits qpc;
4556
4557         u8         reserved_at_800[0x80];
4558 };
4559
4560 struct mlx5_ifc_set_roce_address_out_bits {
4561         u8         status[0x8];
4562         u8         reserved_at_8[0x18];
4563
4564         u8         syndrome[0x20];
4565
4566         u8         reserved_at_40[0x40];
4567 };
4568
4569 struct mlx5_ifc_set_roce_address_in_bits {
4570         u8         opcode[0x10];
4571         u8         reserved_at_10[0x10];
4572
4573         u8         reserved_at_20[0x10];
4574         u8         op_mod[0x10];
4575
4576         u8         roce_address_index[0x10];
4577         u8         reserved_at_50[0xc];
4578         u8         vhca_port_num[0x4];
4579
4580         u8         reserved_at_60[0x20];
4581
4582         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4583 };
4584
4585 struct mlx5_ifc_set_mad_demux_out_bits {
4586         u8         status[0x8];
4587         u8         reserved_at_8[0x18];
4588
4589         u8         syndrome[0x20];
4590
4591         u8         reserved_at_40[0x40];
4592 };
4593
4594 enum {
4595         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4596         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4597 };
4598
4599 struct mlx5_ifc_set_mad_demux_in_bits {
4600         u8         opcode[0x10];
4601         u8         reserved_at_10[0x10];
4602
4603         u8         reserved_at_20[0x10];
4604         u8         op_mod[0x10];
4605
4606         u8         reserved_at_40[0x20];
4607
4608         u8         reserved_at_60[0x6];
4609         u8         demux_mode[0x2];
4610         u8         reserved_at_68[0x18];
4611 };
4612
4613 struct mlx5_ifc_set_l2_table_entry_out_bits {
4614         u8         status[0x8];
4615         u8         reserved_at_8[0x18];
4616
4617         u8         syndrome[0x20];
4618
4619         u8         reserved_at_40[0x40];
4620 };
4621
4622 struct mlx5_ifc_set_l2_table_entry_in_bits {
4623         u8         opcode[0x10];
4624         u8         reserved_at_10[0x10];
4625
4626         u8         reserved_at_20[0x10];
4627         u8         op_mod[0x10];
4628
4629         u8         reserved_at_40[0x60];
4630
4631         u8         reserved_at_a0[0x8];
4632         u8         table_index[0x18];
4633
4634         u8         reserved_at_c0[0x20];
4635
4636         u8         reserved_at_e0[0x13];
4637         u8         vlan_valid[0x1];
4638         u8         vlan[0xc];
4639
4640         struct mlx5_ifc_mac_address_layout_bits mac_address;
4641
4642         u8         reserved_at_140[0xc0];
4643 };
4644
4645 struct mlx5_ifc_set_issi_out_bits {
4646         u8         status[0x8];
4647         u8         reserved_at_8[0x18];
4648
4649         u8         syndrome[0x20];
4650
4651         u8         reserved_at_40[0x40];
4652 };
4653
4654 struct mlx5_ifc_set_issi_in_bits {
4655         u8         opcode[0x10];
4656         u8         reserved_at_10[0x10];
4657
4658         u8         reserved_at_20[0x10];
4659         u8         op_mod[0x10];
4660
4661         u8         reserved_at_40[0x10];
4662         u8         current_issi[0x10];
4663
4664         u8         reserved_at_60[0x20];
4665 };
4666
4667 struct mlx5_ifc_set_hca_cap_out_bits {
4668         u8         status[0x8];
4669         u8         reserved_at_8[0x18];
4670
4671         u8         syndrome[0x20];
4672
4673         u8         reserved_at_40[0x40];
4674 };
4675
4676 struct mlx5_ifc_set_hca_cap_in_bits {
4677         u8         opcode[0x10];
4678         u8         reserved_at_10[0x10];
4679
4680         u8         reserved_at_20[0x10];
4681         u8         op_mod[0x10];
4682
4683         u8         other_function[0x1];
4684         u8         reserved_at_41[0xf];
4685         u8         function_id[0x10];
4686
4687         u8         reserved_at_60[0x20];
4688
4689         union mlx5_ifc_hca_cap_union_bits capability;
4690 };
4691
4692 enum {
4693         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
4694         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
4695         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
4696         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
4697         MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
4698 };
4699
4700 struct mlx5_ifc_set_fte_out_bits {
4701         u8         status[0x8];
4702         u8         reserved_at_8[0x18];
4703
4704         u8         syndrome[0x20];
4705
4706         u8         reserved_at_40[0x40];
4707 };
4708
4709 struct mlx5_ifc_set_fte_in_bits {
4710         u8         opcode[0x10];
4711         u8         reserved_at_10[0x10];
4712
4713         u8         reserved_at_20[0x10];
4714         u8         op_mod[0x10];
4715
4716         u8         other_vport[0x1];
4717         u8         reserved_at_41[0xf];
4718         u8         vport_number[0x10];
4719
4720         u8         reserved_at_60[0x20];
4721
4722         u8         table_type[0x8];
4723         u8         reserved_at_88[0x18];
4724
4725         u8         reserved_at_a0[0x8];
4726         u8         table_id[0x18];
4727
4728         u8         ignore_flow_level[0x1];
4729         u8         reserved_at_c1[0x17];
4730         u8         modify_enable_mask[0x8];
4731
4732         u8         reserved_at_e0[0x20];
4733
4734         u8         flow_index[0x20];
4735
4736         u8         reserved_at_120[0xe0];
4737
4738         struct mlx5_ifc_flow_context_bits flow_context;
4739 };
4740
4741 struct mlx5_ifc_rts2rts_qp_out_bits {
4742         u8         status[0x8];
4743         u8         reserved_at_8[0x18];
4744
4745         u8         syndrome[0x20];
4746
4747         u8         reserved_at_40[0x20];
4748         u8         ece[0x20];
4749 };
4750
4751 struct mlx5_ifc_rts2rts_qp_in_bits {
4752         u8         opcode[0x10];
4753         u8         uid[0x10];
4754
4755         u8         reserved_at_20[0x10];
4756         u8         op_mod[0x10];
4757
4758         u8         reserved_at_40[0x8];
4759         u8         qpn[0x18];
4760
4761         u8         reserved_at_60[0x20];
4762
4763         u8         opt_param_mask[0x20];
4764
4765         u8         ece[0x20];
4766
4767         struct mlx5_ifc_qpc_bits qpc;
4768
4769         u8         reserved_at_800[0x80];
4770 };
4771
4772 struct mlx5_ifc_rtr2rts_qp_out_bits {
4773         u8         status[0x8];
4774         u8         reserved_at_8[0x18];
4775
4776         u8         syndrome[0x20];
4777
4778         u8         reserved_at_40[0x20];
4779         u8         ece[0x20];
4780 };
4781
4782 struct mlx5_ifc_rtr2rts_qp_in_bits {
4783         u8         opcode[0x10];
4784         u8         uid[0x10];
4785
4786         u8         reserved_at_20[0x10];
4787         u8         op_mod[0x10];
4788
4789         u8         reserved_at_40[0x8];
4790         u8         qpn[0x18];
4791
4792         u8         reserved_at_60[0x20];
4793
4794         u8         opt_param_mask[0x20];
4795
4796         u8         ece[0x20];
4797
4798         struct mlx5_ifc_qpc_bits qpc;
4799
4800         u8         reserved_at_800[0x80];
4801 };
4802
4803 struct mlx5_ifc_rst2init_qp_out_bits {
4804         u8         status[0x8];
4805         u8         reserved_at_8[0x18];
4806
4807         u8         syndrome[0x20];
4808
4809         u8         reserved_at_40[0x20];
4810         u8         ece[0x20];
4811 };
4812
4813 struct mlx5_ifc_rst2init_qp_in_bits {
4814         u8         opcode[0x10];
4815         u8         uid[0x10];
4816
4817         u8         reserved_at_20[0x10];
4818         u8         op_mod[0x10];
4819
4820         u8         reserved_at_40[0x8];
4821         u8         qpn[0x18];
4822
4823         u8         reserved_at_60[0x20];
4824
4825         u8         opt_param_mask[0x20];
4826
4827         u8         ece[0x20];
4828
4829         struct mlx5_ifc_qpc_bits qpc;
4830
4831         u8         reserved_at_800[0x80];
4832 };
4833
4834 struct mlx5_ifc_query_xrq_out_bits {
4835         u8         status[0x8];
4836         u8         reserved_at_8[0x18];
4837
4838         u8         syndrome[0x20];
4839
4840         u8         reserved_at_40[0x40];
4841
4842         struct mlx5_ifc_xrqc_bits xrq_context;
4843 };
4844
4845 struct mlx5_ifc_query_xrq_in_bits {
4846         u8         opcode[0x10];
4847         u8         reserved_at_10[0x10];
4848
4849         u8         reserved_at_20[0x10];
4850         u8         op_mod[0x10];
4851
4852         u8         reserved_at_40[0x8];
4853         u8         xrqn[0x18];
4854
4855         u8         reserved_at_60[0x20];
4856 };
4857
4858 struct mlx5_ifc_query_xrc_srq_out_bits {
4859         u8         status[0x8];
4860         u8         reserved_at_8[0x18];
4861
4862         u8         syndrome[0x20];
4863
4864         u8         reserved_at_40[0x40];
4865
4866         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4867
4868         u8         reserved_at_280[0x600];
4869
4870         u8         pas[][0x40];
4871 };
4872
4873 struct mlx5_ifc_query_xrc_srq_in_bits {
4874         u8         opcode[0x10];
4875         u8         reserved_at_10[0x10];
4876
4877         u8         reserved_at_20[0x10];
4878         u8         op_mod[0x10];
4879
4880         u8         reserved_at_40[0x8];
4881         u8         xrc_srqn[0x18];
4882
4883         u8         reserved_at_60[0x20];
4884 };
4885
4886 enum {
4887         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4888         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4889 };
4890
4891 struct mlx5_ifc_query_vport_state_out_bits {
4892         u8         status[0x8];
4893         u8         reserved_at_8[0x18];
4894
4895         u8         syndrome[0x20];
4896
4897         u8         reserved_at_40[0x20];
4898
4899         u8         reserved_at_60[0x18];
4900         u8         admin_state[0x4];
4901         u8         state[0x4];
4902 };
4903
4904 enum {
4905         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
4906         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
4907         MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
4908 };
4909
4910 struct mlx5_ifc_arm_monitor_counter_in_bits {
4911         u8         opcode[0x10];
4912         u8         uid[0x10];
4913
4914         u8         reserved_at_20[0x10];
4915         u8         op_mod[0x10];
4916
4917         u8         reserved_at_40[0x20];
4918
4919         u8         reserved_at_60[0x20];
4920 };
4921
4922 struct mlx5_ifc_arm_monitor_counter_out_bits {
4923         u8         status[0x8];
4924         u8         reserved_at_8[0x18];
4925
4926         u8         syndrome[0x20];
4927
4928         u8         reserved_at_40[0x40];
4929 };
4930
4931 enum {
4932         MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
4933         MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4934 };
4935
4936 enum mlx5_monitor_counter_ppcnt {
4937         MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
4938         MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
4939         MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
4940         MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4941         MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
4942         MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
4943 };
4944
4945 enum {
4946         MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
4947 };
4948
4949 struct mlx5_ifc_monitor_counter_output_bits {
4950         u8         reserved_at_0[0x4];
4951         u8         type[0x4];
4952         u8         reserved_at_8[0x8];
4953         u8         counter[0x10];
4954
4955         u8         counter_group_id[0x20];
4956 };
4957
4958 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4959 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
4960 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4961                                           MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4962
4963 struct mlx5_ifc_set_monitor_counter_in_bits {
4964         u8         opcode[0x10];
4965         u8         uid[0x10];
4966
4967         u8         reserved_at_20[0x10];
4968         u8         op_mod[0x10];
4969
4970         u8         reserved_at_40[0x10];
4971         u8         num_of_counters[0x10];
4972
4973         u8         reserved_at_60[0x20];
4974
4975         struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4976 };
4977
4978 struct mlx5_ifc_set_monitor_counter_out_bits {
4979         u8         status[0x8];
4980         u8         reserved_at_8[0x18];
4981
4982         u8         syndrome[0x20];
4983
4984         u8         reserved_at_40[0x40];
4985 };
4986
4987 struct mlx5_ifc_query_vport_state_in_bits {
4988         u8         opcode[0x10];
4989         u8         reserved_at_10[0x10];
4990
4991         u8         reserved_at_20[0x10];
4992         u8         op_mod[0x10];
4993
4994         u8         other_vport[0x1];
4995         u8         reserved_at_41[0xf];
4996         u8         vport_number[0x10];
4997
4998         u8         reserved_at_60[0x20];
4999 };
5000
5001 struct mlx5_ifc_query_vnic_env_out_bits {
5002         u8         status[0x8];
5003         u8         reserved_at_8[0x18];
5004
5005         u8         syndrome[0x20];
5006
5007         u8         reserved_at_40[0x40];
5008
5009         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
5010 };
5011
5012 enum {
5013         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
5014 };
5015
5016 struct mlx5_ifc_query_vnic_env_in_bits {
5017         u8         opcode[0x10];
5018         u8         reserved_at_10[0x10];
5019
5020         u8         reserved_at_20[0x10];
5021         u8         op_mod[0x10];
5022
5023         u8         other_vport[0x1];
5024         u8         reserved_at_41[0xf];
5025         u8         vport_number[0x10];
5026
5027         u8         reserved_at_60[0x20];
5028 };
5029
5030 struct mlx5_ifc_query_vport_counter_out_bits {
5031         u8         status[0x8];
5032         u8         reserved_at_8[0x18];
5033
5034         u8         syndrome[0x20];
5035
5036         u8         reserved_at_40[0x40];
5037
5038         struct mlx5_ifc_traffic_counter_bits received_errors;
5039
5040         struct mlx5_ifc_traffic_counter_bits transmit_errors;
5041
5042         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
5043
5044         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
5045
5046         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
5047
5048         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
5049
5050         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
5051
5052         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
5053
5054         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
5055
5056         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
5057
5058         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
5059
5060         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
5061
5062         u8         reserved_at_680[0xa00];
5063 };
5064
5065 enum {
5066         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
5067 };
5068
5069 struct mlx5_ifc_query_vport_counter_in_bits {
5070         u8         opcode[0x10];
5071         u8         reserved_at_10[0x10];
5072
5073         u8         reserved_at_20[0x10];
5074         u8         op_mod[0x10];
5075
5076         u8         other_vport[0x1];
5077         u8         reserved_at_41[0xb];
5078         u8         port_num[0x4];
5079         u8         vport_number[0x10];
5080
5081         u8         reserved_at_60[0x60];
5082
5083         u8         clear[0x1];
5084         u8         reserved_at_c1[0x1f];
5085
5086         u8         reserved_at_e0[0x20];
5087 };
5088
5089 struct mlx5_ifc_query_tis_out_bits {
5090         u8         status[0x8];
5091         u8         reserved_at_8[0x18];
5092
5093         u8         syndrome[0x20];
5094
5095         u8         reserved_at_40[0x40];
5096
5097         struct mlx5_ifc_tisc_bits tis_context;
5098 };
5099
5100 struct mlx5_ifc_query_tis_in_bits {
5101         u8         opcode[0x10];
5102         u8         reserved_at_10[0x10];
5103
5104         u8         reserved_at_20[0x10];
5105         u8         op_mod[0x10];
5106
5107         u8         reserved_at_40[0x8];
5108         u8         tisn[0x18];
5109
5110         u8         reserved_at_60[0x20];
5111 };
5112
5113 struct mlx5_ifc_query_tir_out_bits {
5114         u8         status[0x8];
5115         u8         reserved_at_8[0x18];
5116
5117         u8         syndrome[0x20];
5118
5119         u8         reserved_at_40[0xc0];
5120
5121         struct mlx5_ifc_tirc_bits tir_context;
5122 };
5123
5124 struct mlx5_ifc_query_tir_in_bits {
5125         u8         opcode[0x10];
5126         u8         reserved_at_10[0x10];
5127
5128         u8         reserved_at_20[0x10];
5129         u8         op_mod[0x10];
5130
5131         u8         reserved_at_40[0x8];
5132         u8         tirn[0x18];
5133
5134         u8         reserved_at_60[0x20];
5135 };
5136
5137 struct mlx5_ifc_query_srq_out_bits {
5138         u8         status[0x8];
5139         u8         reserved_at_8[0x18];
5140
5141         u8         syndrome[0x20];
5142
5143         u8         reserved_at_40[0x40];
5144
5145         struct mlx5_ifc_srqc_bits srq_context_entry;
5146
5147         u8         reserved_at_280[0x600];
5148
5149         u8         pas[][0x40];
5150 };
5151
5152 struct mlx5_ifc_query_srq_in_bits {
5153         u8         opcode[0x10];
5154         u8         reserved_at_10[0x10];
5155
5156         u8         reserved_at_20[0x10];
5157         u8         op_mod[0x10];
5158
5159         u8         reserved_at_40[0x8];
5160         u8         srqn[0x18];
5161
5162         u8         reserved_at_60[0x20];
5163 };
5164
5165 struct mlx5_ifc_query_sq_out_bits {
5166         u8         status[0x8];
5167         u8         reserved_at_8[0x18];
5168
5169         u8         syndrome[0x20];
5170
5171         u8         reserved_at_40[0xc0];
5172
5173         struct mlx5_ifc_sqc_bits sq_context;
5174 };
5175
5176 struct mlx5_ifc_query_sq_in_bits {
5177         u8         opcode[0x10];
5178         u8         reserved_at_10[0x10];
5179
5180         u8         reserved_at_20[0x10];
5181         u8         op_mod[0x10];
5182
5183         u8         reserved_at_40[0x8];
5184         u8         sqn[0x18];
5185
5186         u8         reserved_at_60[0x20];
5187 };
5188
5189 struct mlx5_ifc_query_special_contexts_out_bits {
5190         u8         status[0x8];
5191         u8         reserved_at_8[0x18];
5192
5193         u8         syndrome[0x20];
5194
5195         u8         dump_fill_mkey[0x20];
5196
5197         u8         resd_lkey[0x20];
5198
5199         u8         null_mkey[0x20];
5200
5201         u8         reserved_at_a0[0x60];
5202 };
5203
5204 struct mlx5_ifc_query_special_contexts_in_bits {
5205         u8         opcode[0x10];
5206         u8         reserved_at_10[0x10];
5207
5208         u8         reserved_at_20[0x10];
5209         u8         op_mod[0x10];
5210
5211         u8         reserved_at_40[0x40];
5212 };
5213
5214 struct mlx5_ifc_query_scheduling_element_out_bits {
5215         u8         opcode[0x10];
5216         u8         reserved_at_10[0x10];
5217
5218         u8         reserved_at_20[0x10];
5219         u8         op_mod[0x10];
5220
5221         u8         reserved_at_40[0xc0];
5222
5223         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5224
5225         u8         reserved_at_300[0x100];
5226 };
5227
5228 enum {
5229         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5230         SCHEDULING_HIERARCHY_NIC = 0x3,
5231 };
5232
5233 struct mlx5_ifc_query_scheduling_element_in_bits {
5234         u8         opcode[0x10];
5235         u8         reserved_at_10[0x10];
5236
5237         u8         reserved_at_20[0x10];
5238         u8         op_mod[0x10];
5239
5240         u8         scheduling_hierarchy[0x8];
5241         u8         reserved_at_48[0x18];
5242
5243         u8         scheduling_element_id[0x20];
5244
5245         u8         reserved_at_80[0x180];
5246 };
5247
5248 struct mlx5_ifc_query_rqt_out_bits {
5249         u8         status[0x8];
5250         u8         reserved_at_8[0x18];
5251
5252         u8         syndrome[0x20];
5253
5254         u8         reserved_at_40[0xc0];
5255
5256         struct mlx5_ifc_rqtc_bits rqt_context;
5257 };
5258
5259 struct mlx5_ifc_query_rqt_in_bits {
5260         u8         opcode[0x10];
5261         u8         reserved_at_10[0x10];
5262
5263         u8         reserved_at_20[0x10];
5264         u8         op_mod[0x10];
5265
5266         u8         reserved_at_40[0x8];
5267         u8         rqtn[0x18];
5268
5269         u8         reserved_at_60[0x20];
5270 };
5271
5272 struct mlx5_ifc_query_rq_out_bits {
5273         u8         status[0x8];
5274         u8         reserved_at_8[0x18];
5275
5276         u8         syndrome[0x20];
5277
5278         u8         reserved_at_40[0xc0];
5279
5280         struct mlx5_ifc_rqc_bits rq_context;
5281 };
5282
5283 struct mlx5_ifc_query_rq_in_bits {
5284         u8         opcode[0x10];
5285         u8         reserved_at_10[0x10];
5286
5287         u8         reserved_at_20[0x10];
5288         u8         op_mod[0x10];
5289
5290         u8         reserved_at_40[0x8];
5291         u8         rqn[0x18];
5292
5293         u8         reserved_at_60[0x20];
5294 };
5295
5296 struct mlx5_ifc_query_roce_address_out_bits {
5297         u8         status[0x8];
5298         u8         reserved_at_8[0x18];
5299
5300         u8         syndrome[0x20];
5301
5302         u8         reserved_at_40[0x40];
5303
5304         struct mlx5_ifc_roce_addr_layout_bits roce_address;
5305 };
5306
5307 struct mlx5_ifc_query_roce_address_in_bits {
5308         u8         opcode[0x10];
5309         u8         reserved_at_10[0x10];
5310
5311         u8         reserved_at_20[0x10];
5312         u8         op_mod[0x10];
5313
5314         u8         roce_address_index[0x10];
5315         u8         reserved_at_50[0xc];
5316         u8         vhca_port_num[0x4];
5317
5318         u8         reserved_at_60[0x20];
5319 };
5320
5321 struct mlx5_ifc_query_rmp_out_bits {
5322         u8         status[0x8];
5323         u8         reserved_at_8[0x18];
5324
5325         u8         syndrome[0x20];
5326
5327         u8         reserved_at_40[0xc0];
5328
5329         struct mlx5_ifc_rmpc_bits rmp_context;
5330 };
5331
5332 struct mlx5_ifc_query_rmp_in_bits {
5333         u8         opcode[0x10];
5334         u8         reserved_at_10[0x10];
5335
5336         u8         reserved_at_20[0x10];
5337         u8         op_mod[0x10];
5338
5339         u8         reserved_at_40[0x8];
5340         u8         rmpn[0x18];
5341
5342         u8         reserved_at_60[0x20];
5343 };
5344
5345 struct mlx5_ifc_query_qp_out_bits {
5346         u8         status[0x8];
5347         u8         reserved_at_8[0x18];
5348
5349         u8         syndrome[0x20];
5350
5351         u8         reserved_at_40[0x40];
5352
5353         u8         opt_param_mask[0x20];
5354
5355         u8         ece[0x20];
5356
5357         struct mlx5_ifc_qpc_bits qpc;
5358
5359         u8         reserved_at_800[0x80];
5360
5361         u8         pas[][0x40];
5362 };
5363
5364 struct mlx5_ifc_query_qp_in_bits {
5365         u8         opcode[0x10];
5366         u8         reserved_at_10[0x10];
5367
5368         u8         reserved_at_20[0x10];
5369         u8         op_mod[0x10];
5370
5371         u8         reserved_at_40[0x8];
5372         u8         qpn[0x18];
5373
5374         u8         reserved_at_60[0x20];
5375 };
5376
5377 struct mlx5_ifc_query_q_counter_out_bits {
5378         u8         status[0x8];
5379         u8         reserved_at_8[0x18];
5380
5381         u8         syndrome[0x20];
5382
5383         u8         reserved_at_40[0x40];
5384
5385         u8         rx_write_requests[0x20];
5386
5387         u8         reserved_at_a0[0x20];
5388
5389         u8         rx_read_requests[0x20];
5390
5391         u8         reserved_at_e0[0x20];
5392
5393         u8         rx_atomic_requests[0x20];
5394
5395         u8         reserved_at_120[0x20];
5396
5397         u8         rx_dct_connect[0x20];
5398
5399         u8         reserved_at_160[0x20];
5400
5401         u8         out_of_buffer[0x20];
5402
5403         u8         reserved_at_1a0[0x20];
5404
5405         u8         out_of_sequence[0x20];
5406
5407         u8         reserved_at_1e0[0x20];
5408
5409         u8         duplicate_request[0x20];
5410
5411         u8         reserved_at_220[0x20];
5412
5413         u8         rnr_nak_retry_err[0x20];
5414
5415         u8         reserved_at_260[0x20];
5416
5417         u8         packet_seq_err[0x20];
5418
5419         u8         reserved_at_2a0[0x20];
5420
5421         u8         implied_nak_seq_err[0x20];
5422
5423         u8         reserved_at_2e0[0x20];
5424
5425         u8         local_ack_timeout_err[0x20];
5426
5427         u8         reserved_at_320[0xa0];
5428
5429         u8         resp_local_length_error[0x20];
5430
5431         u8         req_local_length_error[0x20];
5432
5433         u8         resp_local_qp_error[0x20];
5434
5435         u8         local_operation_error[0x20];
5436
5437         u8         resp_local_protection[0x20];
5438
5439         u8         req_local_protection[0x20];
5440
5441         u8         resp_cqe_error[0x20];
5442
5443         u8         req_cqe_error[0x20];
5444
5445         u8         req_mw_binding[0x20];
5446
5447         u8         req_bad_response[0x20];
5448
5449         u8         req_remote_invalid_request[0x20];
5450
5451         u8         resp_remote_invalid_request[0x20];
5452
5453         u8         req_remote_access_errors[0x20];
5454
5455         u8         resp_remote_access_errors[0x20];
5456
5457         u8         req_remote_operation_errors[0x20];
5458
5459         u8         req_transport_retries_exceeded[0x20];
5460
5461         u8         cq_overflow[0x20];
5462
5463         u8         resp_cqe_flush_error[0x20];
5464
5465         u8         req_cqe_flush_error[0x20];
5466
5467         u8         reserved_at_620[0x20];
5468
5469         u8         roce_adp_retrans[0x20];
5470
5471         u8         roce_adp_retrans_to[0x20];
5472
5473         u8         roce_slow_restart[0x20];
5474
5475         u8         roce_slow_restart_cnps[0x20];
5476
5477         u8         roce_slow_restart_trans[0x20];
5478
5479         u8         reserved_at_6e0[0x120];
5480 };
5481
5482 struct mlx5_ifc_query_q_counter_in_bits {
5483         u8         opcode[0x10];
5484         u8         reserved_at_10[0x10];
5485
5486         u8         reserved_at_20[0x10];
5487         u8         op_mod[0x10];
5488
5489         u8         reserved_at_40[0x80];
5490
5491         u8         clear[0x1];
5492         u8         reserved_at_c1[0x1f];
5493
5494         u8         reserved_at_e0[0x18];
5495         u8         counter_set_id[0x8];
5496 };
5497
5498 struct mlx5_ifc_query_pages_out_bits {
5499         u8         status[0x8];
5500         u8         reserved_at_8[0x18];
5501
5502         u8         syndrome[0x20];
5503
5504         u8         embedded_cpu_function[0x1];
5505         u8         reserved_at_41[0xf];
5506         u8         function_id[0x10];
5507
5508         u8         num_pages[0x20];
5509 };
5510
5511 enum {
5512         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
5513         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
5514         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
5515 };
5516
5517 struct mlx5_ifc_query_pages_in_bits {
5518         u8         opcode[0x10];
5519         u8         reserved_at_10[0x10];
5520
5521         u8         reserved_at_20[0x10];
5522         u8         op_mod[0x10];
5523
5524         u8         embedded_cpu_function[0x1];
5525         u8         reserved_at_41[0xf];
5526         u8         function_id[0x10];
5527
5528         u8         reserved_at_60[0x20];
5529 };
5530
5531 struct mlx5_ifc_query_nic_vport_context_out_bits {
5532         u8         status[0x8];
5533         u8         reserved_at_8[0x18];
5534
5535         u8         syndrome[0x20];
5536
5537         u8         reserved_at_40[0x40];
5538
5539         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5540 };
5541
5542 struct mlx5_ifc_query_nic_vport_context_in_bits {
5543         u8         opcode[0x10];
5544         u8         reserved_at_10[0x10];
5545
5546         u8         reserved_at_20[0x10];
5547         u8         op_mod[0x10];
5548
5549         u8         other_vport[0x1];
5550         u8         reserved_at_41[0xf];
5551         u8         vport_number[0x10];
5552
5553         u8         reserved_at_60[0x5];
5554         u8         allowed_list_type[0x3];
5555         u8         reserved_at_68[0x18];
5556 };
5557
5558 struct mlx5_ifc_query_mkey_out_bits {
5559         u8         status[0x8];
5560         u8         reserved_at_8[0x18];
5561
5562         u8         syndrome[0x20];
5563
5564         u8         reserved_at_40[0x40];
5565
5566         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5567
5568         u8         reserved_at_280[0x600];
5569
5570         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5571
5572         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5573 };
5574
5575 struct mlx5_ifc_query_mkey_in_bits {
5576         u8         opcode[0x10];
5577         u8         reserved_at_10[0x10];
5578
5579         u8         reserved_at_20[0x10];
5580         u8         op_mod[0x10];
5581
5582         u8         reserved_at_40[0x8];
5583         u8         mkey_index[0x18];
5584
5585         u8         pg_access[0x1];
5586         u8         reserved_at_61[0x1f];
5587 };
5588
5589 struct mlx5_ifc_query_mad_demux_out_bits {
5590         u8         status[0x8];
5591         u8         reserved_at_8[0x18];
5592
5593         u8         syndrome[0x20];
5594
5595         u8         reserved_at_40[0x40];
5596
5597         u8         mad_dumux_parameters_block[0x20];
5598 };
5599
5600 struct mlx5_ifc_query_mad_demux_in_bits {
5601         u8         opcode[0x10];
5602         u8         reserved_at_10[0x10];
5603
5604         u8         reserved_at_20[0x10];
5605         u8         op_mod[0x10];
5606
5607         u8         reserved_at_40[0x40];
5608 };
5609
5610 struct mlx5_ifc_query_l2_table_entry_out_bits {
5611         u8         status[0x8];
5612         u8         reserved_at_8[0x18];
5613
5614         u8         syndrome[0x20];
5615
5616         u8         reserved_at_40[0xa0];
5617
5618         u8         reserved_at_e0[0x13];
5619         u8         vlan_valid[0x1];
5620         u8         vlan[0xc];
5621
5622         struct mlx5_ifc_mac_address_layout_bits mac_address;
5623
5624         u8         reserved_at_140[0xc0];
5625 };
5626
5627 struct mlx5_ifc_query_l2_table_entry_in_bits {
5628         u8         opcode[0x10];
5629         u8         reserved_at_10[0x10];
5630
5631         u8         reserved_at_20[0x10];
5632         u8         op_mod[0x10];
5633
5634         u8         reserved_at_40[0x60];
5635
5636         u8         reserved_at_a0[0x8];
5637         u8         table_index[0x18];
5638
5639         u8         reserved_at_c0[0x140];
5640 };
5641
5642 struct mlx5_ifc_query_issi_out_bits {
5643         u8         status[0x8];
5644         u8         reserved_at_8[0x18];
5645
5646         u8         syndrome[0x20];
5647
5648         u8         reserved_at_40[0x10];
5649         u8         current_issi[0x10];
5650
5651         u8         reserved_at_60[0xa0];
5652
5653         u8         reserved_at_100[76][0x8];
5654         u8         supported_issi_dw0[0x20];
5655 };
5656
5657 struct mlx5_ifc_query_issi_in_bits {
5658         u8         opcode[0x10];
5659         u8         reserved_at_10[0x10];
5660
5661         u8         reserved_at_20[0x10];
5662         u8         op_mod[0x10];
5663
5664         u8         reserved_at_40[0x40];
5665 };
5666
5667 struct mlx5_ifc_set_driver_version_out_bits {
5668         u8         status[0x8];
5669         u8         reserved_0[0x18];
5670
5671         u8         syndrome[0x20];
5672         u8         reserved_1[0x40];
5673 };
5674
5675 struct mlx5_ifc_set_driver_version_in_bits {
5676         u8         opcode[0x10];
5677         u8         reserved_0[0x10];
5678
5679         u8         reserved_1[0x10];
5680         u8         op_mod[0x10];
5681
5682         u8         reserved_2[0x40];
5683         u8         driver_version[64][0x8];
5684 };
5685
5686 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5687         u8         status[0x8];
5688         u8         reserved_at_8[0x18];
5689
5690         u8         syndrome[0x20];
5691
5692         u8         reserved_at_40[0x40];
5693
5694         struct mlx5_ifc_pkey_bits pkey[];
5695 };
5696
5697 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5698         u8         opcode[0x10];
5699         u8         reserved_at_10[0x10];
5700
5701         u8         reserved_at_20[0x10];
5702         u8         op_mod[0x10];
5703
5704         u8         other_vport[0x1];
5705         u8         reserved_at_41[0xb];
5706         u8         port_num[0x4];
5707         u8         vport_number[0x10];
5708
5709         u8         reserved_at_60[0x10];
5710         u8         pkey_index[0x10];
5711 };
5712
5713 enum {
5714         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
5715         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
5716         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5717 };
5718
5719 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5720         u8         status[0x8];
5721         u8         reserved_at_8[0x18];
5722
5723         u8         syndrome[0x20];
5724
5725         u8         reserved_at_40[0x20];
5726
5727         u8         gids_num[0x10];
5728         u8         reserved_at_70[0x10];
5729
5730         struct mlx5_ifc_array128_auto_bits gid[];
5731 };
5732
5733 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5734         u8         opcode[0x10];
5735         u8         reserved_at_10[0x10];
5736
5737         u8         reserved_at_20[0x10];
5738         u8         op_mod[0x10];
5739
5740         u8         other_vport[0x1];
5741         u8         reserved_at_41[0xb];
5742         u8         port_num[0x4];
5743         u8         vport_number[0x10];
5744
5745         u8         reserved_at_60[0x10];
5746         u8         gid_index[0x10];
5747 };
5748
5749 struct mlx5_ifc_query_hca_vport_context_out_bits {
5750         u8         status[0x8];
5751         u8         reserved_at_8[0x18];
5752
5753         u8         syndrome[0x20];
5754
5755         u8         reserved_at_40[0x40];
5756
5757         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5758 };
5759
5760 struct mlx5_ifc_query_hca_vport_context_in_bits {
5761         u8         opcode[0x10];
5762         u8         reserved_at_10[0x10];
5763
5764         u8         reserved_at_20[0x10];
5765         u8         op_mod[0x10];
5766
5767         u8         other_vport[0x1];
5768         u8         reserved_at_41[0xb];
5769         u8         port_num[0x4];
5770         u8         vport_number[0x10];
5771
5772         u8         reserved_at_60[0x20];
5773 };
5774
5775 struct mlx5_ifc_query_hca_cap_out_bits {
5776         u8         status[0x8];
5777         u8         reserved_at_8[0x18];
5778
5779         u8         syndrome[0x20];
5780
5781         u8         reserved_at_40[0x40];
5782
5783         union mlx5_ifc_hca_cap_union_bits capability;
5784 };
5785
5786 struct mlx5_ifc_query_hca_cap_in_bits {
5787         u8         opcode[0x10];
5788         u8         reserved_at_10[0x10];
5789
5790         u8         reserved_at_20[0x10];
5791         u8         op_mod[0x10];
5792
5793         u8         other_function[0x1];
5794         u8         reserved_at_41[0xf];
5795         u8         function_id[0x10];
5796
5797         u8         reserved_at_60[0x20];
5798 };
5799
5800 struct mlx5_ifc_other_hca_cap_bits {
5801         u8         roce[0x1];
5802         u8         reserved_at_1[0x27f];
5803 };
5804
5805 struct mlx5_ifc_query_other_hca_cap_out_bits {
5806         u8         status[0x8];
5807         u8         reserved_at_8[0x18];
5808
5809         u8         syndrome[0x20];
5810
5811         u8         reserved_at_40[0x40];
5812
5813         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5814 };
5815
5816 struct mlx5_ifc_query_other_hca_cap_in_bits {
5817         u8         opcode[0x10];
5818         u8         reserved_at_10[0x10];
5819
5820         u8         reserved_at_20[0x10];
5821         u8         op_mod[0x10];
5822
5823         u8         reserved_at_40[0x10];
5824         u8         function_id[0x10];
5825
5826         u8         reserved_at_60[0x20];
5827 };
5828
5829 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5830         u8         status[0x8];
5831         u8         reserved_at_8[0x18];
5832
5833         u8         syndrome[0x20];
5834
5835         u8         reserved_at_40[0x40];
5836 };
5837
5838 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5839         u8         opcode[0x10];
5840         u8         reserved_at_10[0x10];
5841
5842         u8         reserved_at_20[0x10];
5843         u8         op_mod[0x10];
5844
5845         u8         reserved_at_40[0x10];
5846         u8         function_id[0x10];
5847         u8         field_select[0x20];
5848
5849         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5850 };
5851
5852 struct mlx5_ifc_flow_table_context_bits {
5853         u8         reformat_en[0x1];
5854         u8         decap_en[0x1];
5855         u8         sw_owner[0x1];
5856         u8         termination_table[0x1];
5857         u8         table_miss_action[0x4];
5858         u8         level[0x8];
5859         u8         reserved_at_10[0x8];
5860         u8         log_size[0x8];
5861
5862         u8         reserved_at_20[0x8];
5863         u8         table_miss_id[0x18];
5864
5865         u8         reserved_at_40[0x8];
5866         u8         lag_master_next_table_id[0x18];
5867
5868         u8         reserved_at_60[0x60];
5869
5870         u8         sw_owner_icm_root_1[0x40];
5871
5872         u8         sw_owner_icm_root_0[0x40];
5873
5874 };
5875
5876 struct mlx5_ifc_query_flow_table_out_bits {
5877         u8         status[0x8];
5878         u8         reserved_at_8[0x18];
5879
5880         u8         syndrome[0x20];
5881
5882         u8         reserved_at_40[0x80];
5883
5884         struct mlx5_ifc_flow_table_context_bits flow_table_context;
5885 };
5886
5887 struct mlx5_ifc_query_flow_table_in_bits {
5888         u8         opcode[0x10];
5889         u8         reserved_at_10[0x10];
5890
5891         u8         reserved_at_20[0x10];
5892         u8         op_mod[0x10];
5893
5894         u8         reserved_at_40[0x40];
5895
5896         u8         table_type[0x8];
5897         u8         reserved_at_88[0x18];
5898
5899         u8         reserved_at_a0[0x8];
5900         u8         table_id[0x18];
5901
5902         u8         reserved_at_c0[0x140];
5903 };
5904
5905 struct mlx5_ifc_query_fte_out_bits {
5906         u8         status[0x8];
5907         u8         reserved_at_8[0x18];
5908
5909         u8         syndrome[0x20];
5910
5911         u8         reserved_at_40[0x1c0];
5912
5913         struct mlx5_ifc_flow_context_bits flow_context;
5914 };
5915
5916 struct mlx5_ifc_query_fte_in_bits {
5917         u8         opcode[0x10];
5918         u8         reserved_at_10[0x10];
5919
5920         u8         reserved_at_20[0x10];
5921         u8         op_mod[0x10];
5922
5923         u8         reserved_at_40[0x40];
5924
5925         u8         table_type[0x8];
5926         u8         reserved_at_88[0x18];
5927
5928         u8         reserved_at_a0[0x8];
5929         u8         table_id[0x18];
5930
5931         u8         reserved_at_c0[0x40];
5932
5933         u8         flow_index[0x20];
5934
5935         u8         reserved_at_120[0xe0];
5936 };
5937
5938 struct mlx5_ifc_match_definer_format_0_bits {
5939         u8         reserved_at_0[0x100];
5940
5941         u8         metadata_reg_c_0[0x20];
5942
5943         u8         metadata_reg_c_1[0x20];
5944
5945         u8         outer_dmac_47_16[0x20];
5946
5947         u8         outer_dmac_15_0[0x10];
5948         u8         outer_ethertype[0x10];
5949
5950         u8         reserved_at_180[0x1];
5951         u8         sx_sniffer[0x1];
5952         u8         functional_lb[0x1];
5953         u8         outer_ip_frag[0x1];
5954         u8         outer_qp_type[0x2];
5955         u8         outer_encap_type[0x2];
5956         u8         port_number[0x2];
5957         u8         outer_l3_type[0x2];
5958         u8         outer_l4_type[0x2];
5959         u8         outer_first_vlan_type[0x2];
5960         u8         outer_first_vlan_prio[0x3];
5961         u8         outer_first_vlan_cfi[0x1];
5962         u8         outer_first_vlan_vid[0xc];
5963
5964         u8         outer_l4_type_ext[0x4];
5965         u8         reserved_at_1a4[0x2];
5966         u8         outer_ipsec_layer[0x2];
5967         u8         outer_l2_type[0x2];
5968         u8         force_lb[0x1];
5969         u8         outer_l2_ok[0x1];
5970         u8         outer_l3_ok[0x1];
5971         u8         outer_l4_ok[0x1];
5972         u8         outer_second_vlan_type[0x2];
5973         u8         outer_second_vlan_prio[0x3];
5974         u8         outer_second_vlan_cfi[0x1];
5975         u8         outer_second_vlan_vid[0xc];
5976
5977         u8         outer_smac_47_16[0x20];
5978
5979         u8         outer_smac_15_0[0x10];
5980         u8         inner_ipv4_checksum_ok[0x1];
5981         u8         inner_l4_checksum_ok[0x1];
5982         u8         outer_ipv4_checksum_ok[0x1];
5983         u8         outer_l4_checksum_ok[0x1];
5984         u8         inner_l3_ok[0x1];
5985         u8         inner_l4_ok[0x1];
5986         u8         outer_l3_ok_duplicate[0x1];
5987         u8         outer_l4_ok_duplicate[0x1];
5988         u8         outer_tcp_cwr[0x1];
5989         u8         outer_tcp_ece[0x1];
5990         u8         outer_tcp_urg[0x1];
5991         u8         outer_tcp_ack[0x1];
5992         u8         outer_tcp_psh[0x1];
5993         u8         outer_tcp_rst[0x1];
5994         u8         outer_tcp_syn[0x1];
5995         u8         outer_tcp_fin[0x1];
5996 };
5997
5998 struct mlx5_ifc_match_definer_format_22_bits {
5999         u8         reserved_at_0[0x100];
6000
6001         u8         outer_ip_src_addr[0x20];
6002
6003         u8         outer_ip_dest_addr[0x20];
6004
6005         u8         outer_l4_sport[0x10];
6006         u8         outer_l4_dport[0x10];
6007
6008         u8         reserved_at_160[0x1];
6009         u8         sx_sniffer[0x1];
6010         u8         functional_lb[0x1];
6011         u8         outer_ip_frag[0x1];
6012         u8         outer_qp_type[0x2];
6013         u8         outer_encap_type[0x2];
6014         u8         port_number[0x2];
6015         u8         outer_l3_type[0x2];
6016         u8         outer_l4_type[0x2];
6017         u8         outer_first_vlan_type[0x2];
6018         u8         outer_first_vlan_prio[0x3];
6019         u8         outer_first_vlan_cfi[0x1];
6020         u8         outer_first_vlan_vid[0xc];
6021
6022         u8         metadata_reg_c_0[0x20];
6023
6024         u8         outer_dmac_47_16[0x20];
6025
6026         u8         outer_smac_47_16[0x20];
6027
6028         u8         outer_smac_15_0[0x10];
6029         u8         outer_dmac_15_0[0x10];
6030 };
6031
6032 struct mlx5_ifc_match_definer_format_23_bits {
6033         u8         reserved_at_0[0x100];
6034
6035         u8         inner_ip_src_addr[0x20];
6036
6037         u8         inner_ip_dest_addr[0x20];
6038
6039         u8         inner_l4_sport[0x10];
6040         u8         inner_l4_dport[0x10];
6041
6042         u8         reserved_at_160[0x1];
6043         u8         sx_sniffer[0x1];
6044         u8         functional_lb[0x1];
6045         u8         inner_ip_frag[0x1];
6046         u8         inner_qp_type[0x2];
6047         u8         inner_encap_type[0x2];
6048         u8         port_number[0x2];
6049         u8         inner_l3_type[0x2];
6050         u8         inner_l4_type[0x2];
6051         u8         inner_first_vlan_type[0x2];
6052         u8         inner_first_vlan_prio[0x3];
6053         u8         inner_first_vlan_cfi[0x1];
6054         u8         inner_first_vlan_vid[0xc];
6055
6056         u8         tunnel_header_0[0x20];
6057
6058         u8         inner_dmac_47_16[0x20];
6059
6060         u8         inner_smac_47_16[0x20];
6061
6062         u8         inner_smac_15_0[0x10];
6063         u8         inner_dmac_15_0[0x10];
6064 };
6065
6066 struct mlx5_ifc_match_definer_format_29_bits {
6067         u8         reserved_at_0[0xc0];
6068
6069         u8         outer_ip_dest_addr[0x80];
6070
6071         u8         outer_ip_src_addr[0x80];
6072
6073         u8         outer_l4_sport[0x10];
6074         u8         outer_l4_dport[0x10];
6075
6076         u8         reserved_at_1e0[0x20];
6077 };
6078
6079 struct mlx5_ifc_match_definer_format_30_bits {
6080         u8         reserved_at_0[0xa0];
6081
6082         u8         outer_ip_dest_addr[0x80];
6083
6084         u8         outer_ip_src_addr[0x80];
6085
6086         u8         outer_dmac_47_16[0x20];
6087
6088         u8         outer_smac_47_16[0x20];
6089
6090         u8         outer_smac_15_0[0x10];
6091         u8         outer_dmac_15_0[0x10];
6092 };
6093
6094 struct mlx5_ifc_match_definer_format_31_bits {
6095         u8         reserved_at_0[0xc0];
6096
6097         u8         inner_ip_dest_addr[0x80];
6098
6099         u8         inner_ip_src_addr[0x80];
6100
6101         u8         inner_l4_sport[0x10];
6102         u8         inner_l4_dport[0x10];
6103
6104         u8         reserved_at_1e0[0x20];
6105 };
6106
6107 struct mlx5_ifc_match_definer_format_32_bits {
6108         u8         reserved_at_0[0xa0];
6109
6110         u8         inner_ip_dest_addr[0x80];
6111
6112         u8         inner_ip_src_addr[0x80];
6113
6114         u8         inner_dmac_47_16[0x20];
6115
6116         u8         inner_smac_47_16[0x20];
6117
6118         u8         inner_smac_15_0[0x10];
6119         u8         inner_dmac_15_0[0x10];
6120 };
6121
6122 enum {
6123         MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61,
6124 };
6125
6126 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0
6127 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48
6128 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9
6129 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8
6130
6131 struct mlx5_ifc_match_definer_match_mask_bits {
6132         u8         reserved_at_1c0[5][0x20];
6133         u8         match_dw_8[0x20];
6134         u8         match_dw_7[0x20];
6135         u8         match_dw_6[0x20];
6136         u8         match_dw_5[0x20];
6137         u8         match_dw_4[0x20];
6138         u8         match_dw_3[0x20];
6139         u8         match_dw_2[0x20];
6140         u8         match_dw_1[0x20];
6141         u8         match_dw_0[0x20];
6142
6143         u8         match_byte_7[0x8];
6144         u8         match_byte_6[0x8];
6145         u8         match_byte_5[0x8];
6146         u8         match_byte_4[0x8];
6147
6148         u8         match_byte_3[0x8];
6149         u8         match_byte_2[0x8];
6150         u8         match_byte_1[0x8];
6151         u8         match_byte_0[0x8];
6152 };
6153
6154 struct mlx5_ifc_match_definer_bits {
6155         u8         modify_field_select[0x40];
6156
6157         u8         reserved_at_40[0x40];
6158
6159         u8         reserved_at_80[0x10];
6160         u8         format_id[0x10];
6161
6162         u8         reserved_at_a0[0x60];
6163
6164         u8         format_select_dw3[0x8];
6165         u8         format_select_dw2[0x8];
6166         u8         format_select_dw1[0x8];
6167         u8         format_select_dw0[0x8];
6168
6169         u8         format_select_dw7[0x8];
6170         u8         format_select_dw6[0x8];
6171         u8         format_select_dw5[0x8];
6172         u8         format_select_dw4[0x8];
6173
6174         u8         reserved_at_100[0x18];
6175         u8         format_select_dw8[0x8];
6176
6177         u8         reserved_at_120[0x20];
6178
6179         u8         format_select_byte3[0x8];
6180         u8         format_select_byte2[0x8];
6181         u8         format_select_byte1[0x8];
6182         u8         format_select_byte0[0x8];
6183
6184         u8         format_select_byte7[0x8];
6185         u8         format_select_byte6[0x8];
6186         u8         format_select_byte5[0x8];
6187         u8         format_select_byte4[0x8];
6188
6189         u8         reserved_at_180[0x40];
6190
6191         union {
6192                 struct {
6193                         u8         match_mask[16][0x20];
6194                 };
6195                 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format;
6196         };
6197 };
6198
6199 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6200         u8         opcode[0x10];
6201         u8         uid[0x10];
6202
6203         u8         vhca_tunnel_id[0x10];
6204         u8         obj_type[0x10];
6205
6206         u8         obj_id[0x20];
6207
6208         u8         reserved_at_60[0x3];
6209         u8         log_obj_range[0x5];
6210         u8         reserved_at_68[0x18];
6211 };
6212
6213 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6214         u8         status[0x8];
6215         u8         reserved_at_8[0x18];
6216
6217         u8         syndrome[0x20];
6218
6219         u8         obj_id[0x20];
6220
6221         u8         reserved_at_60[0x20];
6222 };
6223
6224 struct mlx5_ifc_create_match_definer_in_bits {
6225         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6226
6227         struct mlx5_ifc_match_definer_bits obj_context;
6228 };
6229
6230 struct mlx5_ifc_create_match_definer_out_bits {
6231         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6232 };
6233
6234 enum {
6235         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6236         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6237         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6238         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6239         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6240         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6241         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6242 };
6243
6244 struct mlx5_ifc_query_flow_group_out_bits {
6245         u8         status[0x8];
6246         u8         reserved_at_8[0x18];
6247
6248         u8         syndrome[0x20];
6249
6250         u8         reserved_at_40[0xa0];
6251
6252         u8         start_flow_index[0x20];
6253
6254         u8         reserved_at_100[0x20];
6255
6256         u8         end_flow_index[0x20];
6257
6258         u8         reserved_at_140[0xa0];
6259
6260         u8         reserved_at_1e0[0x18];
6261         u8         match_criteria_enable[0x8];
6262
6263         struct mlx5_ifc_fte_match_param_bits match_criteria;
6264
6265         u8         reserved_at_1200[0xe00];
6266 };
6267
6268 struct mlx5_ifc_query_flow_group_in_bits {
6269         u8         opcode[0x10];
6270         u8         reserved_at_10[0x10];
6271
6272         u8         reserved_at_20[0x10];
6273         u8         op_mod[0x10];
6274
6275         u8         reserved_at_40[0x40];
6276
6277         u8         table_type[0x8];
6278         u8         reserved_at_88[0x18];
6279
6280         u8         reserved_at_a0[0x8];
6281         u8         table_id[0x18];
6282
6283         u8         group_id[0x20];
6284
6285         u8         reserved_at_e0[0x120];
6286 };
6287
6288 struct mlx5_ifc_query_flow_counter_out_bits {
6289         u8         status[0x8];
6290         u8         reserved_at_8[0x18];
6291
6292         u8         syndrome[0x20];
6293
6294         u8         reserved_at_40[0x40];
6295
6296         struct mlx5_ifc_traffic_counter_bits flow_statistics[];
6297 };
6298
6299 struct mlx5_ifc_query_flow_counter_in_bits {
6300         u8         opcode[0x10];
6301         u8         reserved_at_10[0x10];
6302
6303         u8         reserved_at_20[0x10];
6304         u8         op_mod[0x10];
6305
6306         u8         reserved_at_40[0x80];
6307
6308         u8         clear[0x1];
6309         u8         reserved_at_c1[0xf];
6310         u8         num_of_counters[0x10];
6311
6312         u8         flow_counter_id[0x20];
6313 };
6314
6315 struct mlx5_ifc_query_esw_vport_context_out_bits {
6316         u8         status[0x8];
6317         u8         reserved_at_8[0x18];
6318
6319         u8         syndrome[0x20];
6320
6321         u8         reserved_at_40[0x40];
6322
6323         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6324 };
6325
6326 struct mlx5_ifc_query_esw_vport_context_in_bits {
6327         u8         opcode[0x10];
6328         u8         reserved_at_10[0x10];
6329
6330         u8         reserved_at_20[0x10];
6331         u8         op_mod[0x10];
6332
6333         u8         other_vport[0x1];
6334         u8         reserved_at_41[0xf];
6335         u8         vport_number[0x10];
6336
6337         u8         reserved_at_60[0x20];
6338 };
6339
6340 struct mlx5_ifc_modify_esw_vport_context_out_bits {
6341         u8         status[0x8];
6342         u8         reserved_at_8[0x18];
6343
6344         u8         syndrome[0x20];
6345
6346         u8         reserved_at_40[0x40];
6347 };
6348
6349 struct mlx5_ifc_esw_vport_context_fields_select_bits {
6350         u8         reserved_at_0[0x1b];
6351         u8         fdb_to_vport_reg_c_id[0x1];
6352         u8         vport_cvlan_insert[0x1];
6353         u8         vport_svlan_insert[0x1];
6354         u8         vport_cvlan_strip[0x1];
6355         u8         vport_svlan_strip[0x1];
6356 };
6357
6358 struct mlx5_ifc_modify_esw_vport_context_in_bits {
6359         u8         opcode[0x10];
6360         u8         reserved_at_10[0x10];
6361
6362         u8         reserved_at_20[0x10];
6363         u8         op_mod[0x10];
6364
6365         u8         other_vport[0x1];
6366         u8         reserved_at_41[0xf];
6367         u8         vport_number[0x10];
6368
6369         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6370
6371         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6372 };
6373
6374 struct mlx5_ifc_query_eq_out_bits {
6375         u8         status[0x8];
6376         u8         reserved_at_8[0x18];
6377
6378         u8         syndrome[0x20];
6379
6380         u8         reserved_at_40[0x40];
6381
6382         struct mlx5_ifc_eqc_bits eq_context_entry;
6383
6384         u8         reserved_at_280[0x40];
6385
6386         u8         event_bitmask[0x40];
6387
6388         u8         reserved_at_300[0x580];
6389
6390         u8         pas[][0x40];
6391 };
6392
6393 struct mlx5_ifc_query_eq_in_bits {
6394         u8         opcode[0x10];
6395         u8         reserved_at_10[0x10];
6396
6397         u8         reserved_at_20[0x10];
6398         u8         op_mod[0x10];
6399
6400         u8         reserved_at_40[0x18];
6401         u8         eq_number[0x8];
6402
6403         u8         reserved_at_60[0x20];
6404 };
6405
6406 struct mlx5_ifc_packet_reformat_context_in_bits {
6407         u8         reformat_type[0x8];
6408         u8         reserved_at_8[0x4];
6409         u8         reformat_param_0[0x4];
6410         u8         reserved_at_10[0x6];
6411         u8         reformat_data_size[0xa];
6412
6413         u8         reformat_param_1[0x8];
6414         u8         reserved_at_28[0x8];
6415         u8         reformat_data[2][0x8];
6416
6417         u8         more_reformat_data[][0x8];
6418 };
6419
6420 struct mlx5_ifc_query_packet_reformat_context_out_bits {
6421         u8         status[0x8];
6422         u8         reserved_at_8[0x18];
6423
6424         u8         syndrome[0x20];
6425
6426         u8         reserved_at_40[0xa0];
6427
6428         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
6429 };
6430
6431 struct mlx5_ifc_query_packet_reformat_context_in_bits {
6432         u8         opcode[0x10];
6433         u8         reserved_at_10[0x10];
6434
6435         u8         reserved_at_20[0x10];
6436         u8         op_mod[0x10];
6437
6438         u8         packet_reformat_id[0x20];
6439
6440         u8         reserved_at_60[0xa0];
6441 };
6442
6443 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
6444         u8         status[0x8];
6445         u8         reserved_at_8[0x18];
6446
6447         u8         syndrome[0x20];
6448
6449         u8         packet_reformat_id[0x20];
6450
6451         u8         reserved_at_60[0x20];
6452 };
6453
6454 enum {
6455         MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
6456         MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
6457         MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
6458 };
6459
6460 enum mlx5_reformat_ctx_type {
6461         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
6462         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
6463         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
6464         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
6465         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
6466         MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
6467         MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
6468         MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
6469         MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
6470         MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
6471         MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
6472         MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
6473 };
6474
6475 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
6476         u8         opcode[0x10];
6477         u8         reserved_at_10[0x10];
6478
6479         u8         reserved_at_20[0x10];
6480         u8         op_mod[0x10];
6481
6482         u8         reserved_at_40[0xa0];
6483
6484         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
6485 };
6486
6487 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
6488         u8         status[0x8];
6489         u8         reserved_at_8[0x18];
6490
6491         u8         syndrome[0x20];
6492
6493         u8         reserved_at_40[0x40];
6494 };
6495
6496 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
6497         u8         opcode[0x10];
6498         u8         reserved_at_10[0x10];
6499
6500         u8         reserved_20[0x10];
6501         u8         op_mod[0x10];
6502
6503         u8         packet_reformat_id[0x20];
6504
6505         u8         reserved_60[0x20];
6506 };
6507
6508 struct mlx5_ifc_set_action_in_bits {
6509         u8         action_type[0x4];
6510         u8         field[0xc];
6511         u8         reserved_at_10[0x3];
6512         u8         offset[0x5];
6513         u8         reserved_at_18[0x3];
6514         u8         length[0x5];
6515
6516         u8         data[0x20];
6517 };
6518
6519 struct mlx5_ifc_add_action_in_bits {
6520         u8         action_type[0x4];
6521         u8         field[0xc];
6522         u8         reserved_at_10[0x10];
6523
6524         u8         data[0x20];
6525 };
6526
6527 struct mlx5_ifc_copy_action_in_bits {
6528         u8         action_type[0x4];
6529         u8         src_field[0xc];
6530         u8         reserved_at_10[0x3];
6531         u8         src_offset[0x5];
6532         u8         reserved_at_18[0x3];
6533         u8         length[0x5];
6534
6535         u8         reserved_at_20[0x4];
6536         u8         dst_field[0xc];
6537         u8         reserved_at_30[0x3];
6538         u8         dst_offset[0x5];
6539         u8         reserved_at_38[0x8];
6540 };
6541
6542 union mlx5_ifc_set_add_copy_action_in_auto_bits {
6543         struct mlx5_ifc_set_action_in_bits  set_action_in;
6544         struct mlx5_ifc_add_action_in_bits  add_action_in;
6545         struct mlx5_ifc_copy_action_in_bits copy_action_in;
6546         u8         reserved_at_0[0x40];
6547 };
6548
6549 enum {
6550         MLX5_ACTION_TYPE_SET   = 0x1,
6551         MLX5_ACTION_TYPE_ADD   = 0x2,
6552         MLX5_ACTION_TYPE_COPY  = 0x3,
6553 };
6554
6555 enum {
6556         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
6557         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
6558         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
6559         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
6560         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
6561         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
6562         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
6563         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
6564         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
6565         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
6566         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
6567         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
6568         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
6569         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
6570         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
6571         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
6572         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
6573         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
6574         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
6575         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
6576         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
6577         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
6578         MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
6579         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
6580         MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
6581         MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
6582         MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
6583         MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
6584         MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
6585         MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
6586         MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
6587         MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
6588         MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
6589         MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
6590         MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
6591         MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
6592         MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
6593         MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
6594         MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
6595 };
6596
6597 struct mlx5_ifc_alloc_modify_header_context_out_bits {
6598         u8         status[0x8];
6599         u8         reserved_at_8[0x18];
6600
6601         u8         syndrome[0x20];
6602
6603         u8         modify_header_id[0x20];
6604
6605         u8         reserved_at_60[0x20];
6606 };
6607
6608 struct mlx5_ifc_alloc_modify_header_context_in_bits {
6609         u8         opcode[0x10];
6610         u8         reserved_at_10[0x10];
6611
6612         u8         reserved_at_20[0x10];
6613         u8         op_mod[0x10];
6614
6615         u8         reserved_at_40[0x20];
6616
6617         u8         table_type[0x8];
6618         u8         reserved_at_68[0x10];
6619         u8         num_of_actions[0x8];
6620
6621         union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
6622 };
6623
6624 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
6625         u8         status[0x8];
6626         u8         reserved_at_8[0x18];
6627
6628         u8         syndrome[0x20];
6629
6630         u8         reserved_at_40[0x40];
6631 };
6632
6633 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
6634         u8         opcode[0x10];
6635         u8         reserved_at_10[0x10];
6636
6637         u8         reserved_at_20[0x10];
6638         u8         op_mod[0x10];
6639
6640         u8         modify_header_id[0x20];
6641
6642         u8         reserved_at_60[0x20];
6643 };
6644
6645 struct mlx5_ifc_query_modify_header_context_in_bits {
6646         u8         opcode[0x10];
6647         u8         uid[0x10];
6648
6649         u8         reserved_at_20[0x10];
6650         u8         op_mod[0x10];
6651
6652         u8         modify_header_id[0x20];
6653
6654         u8         reserved_at_60[0xa0];
6655 };
6656
6657 struct mlx5_ifc_query_dct_out_bits {
6658         u8         status[0x8];
6659         u8         reserved_at_8[0x18];
6660
6661         u8         syndrome[0x20];
6662
6663         u8         reserved_at_40[0x40];
6664
6665         struct mlx5_ifc_dctc_bits dct_context_entry;
6666
6667         u8         reserved_at_280[0x180];
6668 };
6669
6670 struct mlx5_ifc_query_dct_in_bits {
6671         u8         opcode[0x10];
6672         u8         reserved_at_10[0x10];
6673
6674         u8         reserved_at_20[0x10];
6675         u8         op_mod[0x10];
6676
6677         u8         reserved_at_40[0x8];
6678         u8         dctn[0x18];
6679
6680         u8         reserved_at_60[0x20];
6681 };
6682
6683 struct mlx5_ifc_query_cq_out_bits {
6684         u8         status[0x8];
6685         u8         reserved_at_8[0x18];
6686
6687         u8         syndrome[0x20];
6688
6689         u8         reserved_at_40[0x40];
6690
6691         struct mlx5_ifc_cqc_bits cq_context;
6692
6693         u8         reserved_at_280[0x600];
6694
6695         u8         pas[][0x40];
6696 };
6697
6698 struct mlx5_ifc_query_cq_in_bits {
6699         u8         opcode[0x10];
6700         u8         reserved_at_10[0x10];
6701
6702         u8         reserved_at_20[0x10];
6703         u8         op_mod[0x10];
6704
6705         u8         reserved_at_40[0x8];
6706         u8         cqn[0x18];
6707
6708         u8         reserved_at_60[0x20];
6709 };
6710
6711 struct mlx5_ifc_query_cong_status_out_bits {
6712         u8         status[0x8];
6713         u8         reserved_at_8[0x18];
6714
6715         u8         syndrome[0x20];
6716
6717         u8         reserved_at_40[0x20];
6718
6719         u8         enable[0x1];
6720         u8         tag_enable[0x1];
6721         u8         reserved_at_62[0x1e];
6722 };
6723
6724 struct mlx5_ifc_query_cong_status_in_bits {
6725         u8         opcode[0x10];
6726         u8         reserved_at_10[0x10];
6727
6728         u8         reserved_at_20[0x10];
6729         u8         op_mod[0x10];
6730
6731         u8         reserved_at_40[0x18];
6732         u8         priority[0x4];
6733         u8         cong_protocol[0x4];
6734
6735         u8         reserved_at_60[0x20];
6736 };
6737
6738 struct mlx5_ifc_query_cong_statistics_out_bits {
6739         u8         status[0x8];
6740         u8         reserved_at_8[0x18];
6741
6742         u8         syndrome[0x20];
6743
6744         u8         reserved_at_40[0x40];
6745
6746         u8         rp_cur_flows[0x20];
6747
6748         u8         sum_flows[0x20];
6749
6750         u8         rp_cnp_ignored_high[0x20];
6751
6752         u8         rp_cnp_ignored_low[0x20];
6753
6754         u8         rp_cnp_handled_high[0x20];
6755
6756         u8         rp_cnp_handled_low[0x20];
6757
6758         u8         reserved_at_140[0x100];
6759
6760         u8         time_stamp_high[0x20];
6761
6762         u8         time_stamp_low[0x20];
6763
6764         u8         accumulators_period[0x20];
6765
6766         u8         np_ecn_marked_roce_packets_high[0x20];
6767
6768         u8         np_ecn_marked_roce_packets_low[0x20];
6769
6770         u8         np_cnp_sent_high[0x20];
6771
6772         u8         np_cnp_sent_low[0x20];
6773
6774         u8         reserved_at_320[0x560];
6775 };
6776
6777 struct mlx5_ifc_query_cong_statistics_in_bits {
6778         u8         opcode[0x10];
6779         u8         reserved_at_10[0x10];
6780
6781         u8         reserved_at_20[0x10];
6782         u8         op_mod[0x10];
6783
6784         u8         clear[0x1];
6785         u8         reserved_at_41[0x1f];
6786
6787         u8         reserved_at_60[0x20];
6788 };
6789
6790 struct mlx5_ifc_query_cong_params_out_bits {
6791         u8         status[0x8];
6792         u8         reserved_at_8[0x18];
6793
6794         u8         syndrome[0x20];
6795
6796         u8         reserved_at_40[0x40];
6797
6798         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6799 };
6800
6801 struct mlx5_ifc_query_cong_params_in_bits {
6802         u8         opcode[0x10];
6803         u8         reserved_at_10[0x10];
6804
6805         u8         reserved_at_20[0x10];
6806         u8         op_mod[0x10];
6807
6808         u8         reserved_at_40[0x1c];
6809         u8         cong_protocol[0x4];
6810
6811         u8         reserved_at_60[0x20];
6812 };
6813
6814 struct mlx5_ifc_query_adapter_out_bits {
6815         u8         status[0x8];
6816         u8         reserved_at_8[0x18];
6817
6818         u8         syndrome[0x20];
6819
6820         u8         reserved_at_40[0x40];
6821
6822         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6823 };
6824
6825 struct mlx5_ifc_query_adapter_in_bits {
6826         u8         opcode[0x10];
6827         u8         reserved_at_10[0x10];
6828
6829         u8         reserved_at_20[0x10];
6830         u8         op_mod[0x10];
6831
6832         u8         reserved_at_40[0x40];
6833 };
6834
6835 struct mlx5_ifc_qp_2rst_out_bits {
6836         u8         status[0x8];
6837         u8         reserved_at_8[0x18];
6838
6839         u8         syndrome[0x20];
6840
6841         u8         reserved_at_40[0x40];
6842 };
6843
6844 struct mlx5_ifc_qp_2rst_in_bits {
6845         u8         opcode[0x10];
6846         u8         uid[0x10];
6847
6848         u8         reserved_at_20[0x10];
6849         u8         op_mod[0x10];
6850
6851         u8         reserved_at_40[0x8];
6852         u8         qpn[0x18];
6853
6854         u8         reserved_at_60[0x20];
6855 };
6856
6857 struct mlx5_ifc_qp_2err_out_bits {
6858         u8         status[0x8];
6859         u8         reserved_at_8[0x18];
6860
6861         u8         syndrome[0x20];
6862
6863         u8         reserved_at_40[0x40];
6864 };
6865
6866 struct mlx5_ifc_qp_2err_in_bits {
6867         u8         opcode[0x10];
6868         u8         uid[0x10];
6869
6870         u8         reserved_at_20[0x10];
6871         u8         op_mod[0x10];
6872
6873         u8         reserved_at_40[0x8];
6874         u8         qpn[0x18];
6875
6876         u8         reserved_at_60[0x20];
6877 };
6878
6879 struct mlx5_ifc_page_fault_resume_out_bits {
6880         u8         status[0x8];
6881         u8         reserved_at_8[0x18];
6882
6883         u8         syndrome[0x20];
6884
6885         u8         reserved_at_40[0x40];
6886 };
6887
6888 struct mlx5_ifc_page_fault_resume_in_bits {
6889         u8         opcode[0x10];
6890         u8         reserved_at_10[0x10];
6891
6892         u8         reserved_at_20[0x10];
6893         u8         op_mod[0x10];
6894
6895         u8         error[0x1];
6896         u8         reserved_at_41[0x4];
6897         u8         page_fault_type[0x3];
6898         u8         wq_number[0x18];
6899
6900         u8         reserved_at_60[0x8];
6901         u8         token[0x18];
6902 };
6903
6904 struct mlx5_ifc_nop_out_bits {
6905         u8         status[0x8];
6906         u8         reserved_at_8[0x18];
6907
6908         u8         syndrome[0x20];
6909
6910         u8         reserved_at_40[0x40];
6911 };
6912
6913 struct mlx5_ifc_nop_in_bits {
6914         u8         opcode[0x10];
6915         u8         reserved_at_10[0x10];
6916
6917         u8         reserved_at_20[0x10];
6918         u8         op_mod[0x10];
6919
6920         u8         reserved_at_40[0x40];
6921 };
6922
6923 struct mlx5_ifc_modify_vport_state_out_bits {
6924         u8         status[0x8];
6925         u8         reserved_at_8[0x18];
6926
6927         u8         syndrome[0x20];
6928
6929         u8         reserved_at_40[0x40];
6930 };
6931
6932 struct mlx5_ifc_modify_vport_state_in_bits {
6933         u8         opcode[0x10];
6934         u8         reserved_at_10[0x10];
6935
6936         u8         reserved_at_20[0x10];
6937         u8         op_mod[0x10];
6938
6939         u8         other_vport[0x1];
6940         u8         reserved_at_41[0xf];
6941         u8         vport_number[0x10];
6942
6943         u8         reserved_at_60[0x18];
6944         u8         admin_state[0x4];
6945         u8         reserved_at_7c[0x4];
6946 };
6947
6948 struct mlx5_ifc_modify_tis_out_bits {
6949         u8         status[0x8];
6950         u8         reserved_at_8[0x18];
6951
6952         u8         syndrome[0x20];
6953
6954         u8         reserved_at_40[0x40];
6955 };
6956
6957 struct mlx5_ifc_modify_tis_bitmask_bits {
6958         u8         reserved_at_0[0x20];
6959
6960         u8         reserved_at_20[0x1d];
6961         u8         lag_tx_port_affinity[0x1];
6962         u8         strict_lag_tx_port_affinity[0x1];
6963         u8         prio[0x1];
6964 };
6965
6966 struct mlx5_ifc_modify_tis_in_bits {
6967         u8         opcode[0x10];
6968         u8         uid[0x10];
6969
6970         u8         reserved_at_20[0x10];
6971         u8         op_mod[0x10];
6972
6973         u8         reserved_at_40[0x8];
6974         u8         tisn[0x18];
6975
6976         u8         reserved_at_60[0x20];
6977
6978         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6979
6980         u8         reserved_at_c0[0x40];
6981
6982         struct mlx5_ifc_tisc_bits ctx;
6983 };
6984
6985 struct mlx5_ifc_modify_tir_bitmask_bits {
6986         u8         reserved_at_0[0x20];
6987
6988         u8         reserved_at_20[0x1b];
6989         u8         self_lb_en[0x1];
6990         u8         reserved_at_3c[0x1];
6991         u8         hash[0x1];
6992         u8         reserved_at_3e[0x1];
6993         u8         packet_merge[0x1];
6994 };
6995
6996 struct mlx5_ifc_modify_tir_out_bits {
6997         u8         status[0x8];
6998         u8         reserved_at_8[0x18];
6999
7000         u8         syndrome[0x20];
7001
7002         u8         reserved_at_40[0x40];
7003 };
7004
7005 struct mlx5_ifc_modify_tir_in_bits {
7006         u8         opcode[0x10];
7007         u8         uid[0x10];
7008
7009         u8         reserved_at_20[0x10];
7010         u8         op_mod[0x10];
7011
7012         u8         reserved_at_40[0x8];
7013         u8         tirn[0x18];
7014
7015         u8         reserved_at_60[0x20];
7016
7017         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
7018
7019         u8         reserved_at_c0[0x40];
7020
7021         struct mlx5_ifc_tirc_bits ctx;
7022 };
7023
7024 struct mlx5_ifc_modify_sq_out_bits {
7025         u8         status[0x8];
7026         u8         reserved_at_8[0x18];
7027
7028         u8         syndrome[0x20];
7029
7030         u8         reserved_at_40[0x40];
7031 };
7032
7033 struct mlx5_ifc_modify_sq_in_bits {
7034         u8         opcode[0x10];
7035         u8         uid[0x10];
7036
7037         u8         reserved_at_20[0x10];
7038         u8         op_mod[0x10];
7039
7040         u8         sq_state[0x4];
7041         u8         reserved_at_44[0x4];
7042         u8         sqn[0x18];
7043
7044         u8         reserved_at_60[0x20];
7045
7046         u8         modify_bitmask[0x40];
7047
7048         u8         reserved_at_c0[0x40];
7049
7050         struct mlx5_ifc_sqc_bits ctx;
7051 };
7052
7053 struct mlx5_ifc_modify_scheduling_element_out_bits {
7054         u8         status[0x8];
7055         u8         reserved_at_8[0x18];
7056
7057         u8         syndrome[0x20];
7058
7059         u8         reserved_at_40[0x1c0];
7060 };
7061
7062 enum {
7063         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
7064         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
7065 };
7066
7067 struct mlx5_ifc_modify_scheduling_element_in_bits {
7068         u8         opcode[0x10];
7069         u8         reserved_at_10[0x10];
7070
7071         u8         reserved_at_20[0x10];
7072         u8         op_mod[0x10];
7073
7074         u8         scheduling_hierarchy[0x8];
7075         u8         reserved_at_48[0x18];
7076
7077         u8         scheduling_element_id[0x20];
7078
7079         u8         reserved_at_80[0x20];
7080
7081         u8         modify_bitmask[0x20];
7082
7083         u8         reserved_at_c0[0x40];
7084
7085         struct mlx5_ifc_scheduling_context_bits scheduling_context;
7086
7087         u8         reserved_at_300[0x100];
7088 };
7089
7090 struct mlx5_ifc_modify_rqt_out_bits {
7091         u8         status[0x8];
7092         u8         reserved_at_8[0x18];
7093
7094         u8         syndrome[0x20];
7095
7096         u8         reserved_at_40[0x40];
7097 };
7098
7099 struct mlx5_ifc_rqt_bitmask_bits {
7100         u8         reserved_at_0[0x20];
7101
7102         u8         reserved_at_20[0x1f];
7103         u8         rqn_list[0x1];
7104 };
7105
7106 struct mlx5_ifc_modify_rqt_in_bits {
7107         u8         opcode[0x10];
7108         u8         uid[0x10];
7109
7110         u8         reserved_at_20[0x10];
7111         u8         op_mod[0x10];
7112
7113         u8         reserved_at_40[0x8];
7114         u8         rqtn[0x18];
7115
7116         u8         reserved_at_60[0x20];
7117
7118         struct mlx5_ifc_rqt_bitmask_bits bitmask;
7119
7120         u8         reserved_at_c0[0x40];
7121
7122         struct mlx5_ifc_rqtc_bits ctx;
7123 };
7124
7125 struct mlx5_ifc_modify_rq_out_bits {
7126         u8         status[0x8];
7127         u8         reserved_at_8[0x18];
7128
7129         u8         syndrome[0x20];
7130
7131         u8         reserved_at_40[0x40];
7132 };
7133
7134 enum {
7135         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
7136         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
7137         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
7138 };
7139
7140 struct mlx5_ifc_modify_rq_in_bits {
7141         u8         opcode[0x10];
7142         u8         uid[0x10];
7143
7144         u8         reserved_at_20[0x10];
7145         u8         op_mod[0x10];
7146
7147         u8         rq_state[0x4];
7148         u8         reserved_at_44[0x4];
7149         u8         rqn[0x18];
7150
7151         u8         reserved_at_60[0x20];
7152
7153         u8         modify_bitmask[0x40];
7154
7155         u8         reserved_at_c0[0x40];
7156
7157         struct mlx5_ifc_rqc_bits ctx;
7158 };
7159
7160 struct mlx5_ifc_modify_rmp_out_bits {
7161         u8         status[0x8];
7162         u8         reserved_at_8[0x18];
7163
7164         u8         syndrome[0x20];
7165
7166         u8         reserved_at_40[0x40];
7167 };
7168
7169 struct mlx5_ifc_rmp_bitmask_bits {
7170         u8         reserved_at_0[0x20];
7171
7172         u8         reserved_at_20[0x1f];
7173         u8         lwm[0x1];
7174 };
7175
7176 struct mlx5_ifc_modify_rmp_in_bits {
7177         u8         opcode[0x10];
7178         u8         uid[0x10];
7179
7180         u8         reserved_at_20[0x10];
7181         u8         op_mod[0x10];
7182
7183         u8         rmp_state[0x4];
7184         u8         reserved_at_44[0x4];
7185         u8         rmpn[0x18];
7186
7187         u8         reserved_at_60[0x20];
7188
7189         struct mlx5_ifc_rmp_bitmask_bits bitmask;
7190
7191         u8         reserved_at_c0[0x40];
7192
7193         struct mlx5_ifc_rmpc_bits ctx;
7194 };
7195
7196 struct mlx5_ifc_modify_nic_vport_context_out_bits {
7197         u8         status[0x8];
7198         u8         reserved_at_8[0x18];
7199
7200         u8         syndrome[0x20];
7201
7202         u8         reserved_at_40[0x40];
7203 };
7204
7205 struct mlx5_ifc_modify_nic_vport_field_select_bits {
7206         u8         reserved_at_0[0x12];
7207         u8         affiliation[0x1];
7208         u8         reserved_at_13[0x1];
7209         u8         disable_uc_local_lb[0x1];
7210         u8         disable_mc_local_lb[0x1];
7211         u8         node_guid[0x1];
7212         u8         port_guid[0x1];
7213         u8         min_inline[0x1];
7214         u8         mtu[0x1];
7215         u8         change_event[0x1];
7216         u8         promisc[0x1];
7217         u8         permanent_address[0x1];
7218         u8         addresses_list[0x1];
7219         u8         roce_en[0x1];
7220         u8         reserved_at_1f[0x1];
7221 };
7222
7223 struct mlx5_ifc_modify_nic_vport_context_in_bits {
7224         u8         opcode[0x10];
7225         u8         reserved_at_10[0x10];
7226
7227         u8         reserved_at_20[0x10];
7228         u8         op_mod[0x10];
7229
7230         u8         other_vport[0x1];
7231         u8         reserved_at_41[0xf];
7232         u8         vport_number[0x10];
7233
7234         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
7235
7236         u8         reserved_at_80[0x780];
7237
7238         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
7239 };
7240
7241 struct mlx5_ifc_modify_hca_vport_context_out_bits {
7242         u8         status[0x8];
7243         u8         reserved_at_8[0x18];
7244
7245         u8         syndrome[0x20];
7246
7247         u8         reserved_at_40[0x40];
7248 };
7249
7250 struct mlx5_ifc_modify_hca_vport_context_in_bits {
7251         u8         opcode[0x10];
7252         u8         reserved_at_10[0x10];
7253
7254         u8         reserved_at_20[0x10];
7255         u8         op_mod[0x10];
7256
7257         u8         other_vport[0x1];
7258         u8         reserved_at_41[0xb];
7259         u8         port_num[0x4];
7260         u8         vport_number[0x10];
7261
7262         u8         reserved_at_60[0x20];
7263
7264         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
7265 };
7266
7267 struct mlx5_ifc_modify_cq_out_bits {
7268         u8         status[0x8];
7269         u8         reserved_at_8[0x18];
7270
7271         u8         syndrome[0x20];
7272
7273         u8         reserved_at_40[0x40];
7274 };
7275
7276 enum {
7277         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
7278         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
7279 };
7280
7281 struct mlx5_ifc_modify_cq_in_bits {
7282         u8         opcode[0x10];
7283         u8         uid[0x10];
7284
7285         u8         reserved_at_20[0x10];
7286         u8         op_mod[0x10];
7287
7288         u8         reserved_at_40[0x8];
7289         u8         cqn[0x18];
7290
7291         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
7292
7293         struct mlx5_ifc_cqc_bits cq_context;
7294
7295         u8         reserved_at_280[0x60];
7296
7297         u8         cq_umem_valid[0x1];
7298         u8         reserved_at_2e1[0x1f];
7299
7300         u8         reserved_at_300[0x580];
7301
7302         u8         pas[][0x40];
7303 };
7304
7305 struct mlx5_ifc_modify_cong_status_out_bits {
7306         u8         status[0x8];
7307         u8         reserved_at_8[0x18];
7308
7309         u8         syndrome[0x20];
7310
7311         u8         reserved_at_40[0x40];
7312 };
7313
7314 struct mlx5_ifc_modify_cong_status_in_bits {
7315         u8         opcode[0x10];
7316         u8         reserved_at_10[0x10];
7317
7318         u8         reserved_at_20[0x10];
7319         u8         op_mod[0x10];
7320
7321         u8         reserved_at_40[0x18];
7322         u8         priority[0x4];
7323         u8         cong_protocol[0x4];
7324
7325         u8         enable[0x1];
7326         u8         tag_enable[0x1];
7327         u8         reserved_at_62[0x1e];
7328 };
7329
7330 struct mlx5_ifc_modify_cong_params_out_bits {
7331         u8         status[0x8];
7332         u8         reserved_at_8[0x18];
7333
7334         u8         syndrome[0x20];
7335
7336         u8         reserved_at_40[0x40];
7337 };
7338
7339 struct mlx5_ifc_modify_cong_params_in_bits {
7340         u8         opcode[0x10];
7341         u8         reserved_at_10[0x10];
7342
7343         u8         reserved_at_20[0x10];
7344         u8         op_mod[0x10];
7345
7346         u8         reserved_at_40[0x1c];
7347         u8         cong_protocol[0x4];
7348
7349         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7350
7351         u8         reserved_at_80[0x80];
7352
7353         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7354 };
7355
7356 struct mlx5_ifc_manage_pages_out_bits {
7357         u8         status[0x8];
7358         u8         reserved_at_8[0x18];
7359
7360         u8         syndrome[0x20];
7361
7362         u8         output_num_entries[0x20];
7363
7364         u8         reserved_at_60[0x20];
7365
7366         u8         pas[][0x40];
7367 };
7368
7369 enum {
7370         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
7371         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
7372         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
7373 };
7374
7375 struct mlx5_ifc_manage_pages_in_bits {
7376         u8         opcode[0x10];
7377         u8         reserved_at_10[0x10];
7378
7379         u8         reserved_at_20[0x10];
7380         u8         op_mod[0x10];
7381
7382         u8         embedded_cpu_function[0x1];
7383         u8         reserved_at_41[0xf];
7384         u8         function_id[0x10];
7385
7386         u8         input_num_entries[0x20];
7387
7388         u8         pas[][0x40];
7389 };
7390
7391 struct mlx5_ifc_mad_ifc_out_bits {
7392         u8         status[0x8];
7393         u8         reserved_at_8[0x18];
7394
7395         u8         syndrome[0x20];
7396
7397         u8         reserved_at_40[0x40];
7398
7399         u8         response_mad_packet[256][0x8];
7400 };
7401
7402 struct mlx5_ifc_mad_ifc_in_bits {
7403         u8         opcode[0x10];
7404         u8         reserved_at_10[0x10];
7405
7406         u8         reserved_at_20[0x10];
7407         u8         op_mod[0x10];
7408
7409         u8         remote_lid[0x10];
7410         u8         reserved_at_50[0x8];
7411         u8         port[0x8];
7412
7413         u8         reserved_at_60[0x20];
7414
7415         u8         mad[256][0x8];
7416 };
7417
7418 struct mlx5_ifc_init_hca_out_bits {
7419         u8         status[0x8];
7420         u8         reserved_at_8[0x18];
7421
7422         u8         syndrome[0x20];
7423
7424         u8         reserved_at_40[0x40];
7425 };
7426
7427 struct mlx5_ifc_init_hca_in_bits {
7428         u8         opcode[0x10];
7429         u8         reserved_at_10[0x10];
7430
7431         u8         reserved_at_20[0x10];
7432         u8         op_mod[0x10];
7433
7434         u8         reserved_at_40[0x20];
7435
7436         u8         reserved_at_60[0x2];
7437         u8         sw_vhca_id[0xe];
7438         u8         reserved_at_70[0x10];
7439
7440         u8         sw_owner_id[4][0x20];
7441 };
7442
7443 struct mlx5_ifc_init2rtr_qp_out_bits {
7444         u8         status[0x8];
7445         u8         reserved_at_8[0x18];
7446
7447         u8         syndrome[0x20];
7448
7449         u8         reserved_at_40[0x20];
7450         u8         ece[0x20];
7451 };
7452
7453 struct mlx5_ifc_init2rtr_qp_in_bits {
7454         u8         opcode[0x10];
7455         u8         uid[0x10];
7456
7457         u8         reserved_at_20[0x10];
7458         u8         op_mod[0x10];
7459
7460         u8         reserved_at_40[0x8];
7461         u8         qpn[0x18];
7462
7463         u8         reserved_at_60[0x20];
7464
7465         u8         opt_param_mask[0x20];
7466
7467         u8         ece[0x20];
7468
7469         struct mlx5_ifc_qpc_bits qpc;
7470
7471         u8         reserved_at_800[0x80];
7472 };
7473
7474 struct mlx5_ifc_init2init_qp_out_bits {
7475         u8         status[0x8];
7476         u8         reserved_at_8[0x18];
7477
7478         u8         syndrome[0x20];
7479
7480         u8         reserved_at_40[0x20];
7481         u8         ece[0x20];
7482 };
7483
7484 struct mlx5_ifc_init2init_qp_in_bits {
7485         u8         opcode[0x10];
7486         u8         uid[0x10];
7487
7488         u8         reserved_at_20[0x10];
7489         u8         op_mod[0x10];
7490
7491         u8         reserved_at_40[0x8];
7492         u8         qpn[0x18];
7493
7494         u8         reserved_at_60[0x20];
7495
7496         u8         opt_param_mask[0x20];
7497
7498         u8         ece[0x20];
7499
7500         struct mlx5_ifc_qpc_bits qpc;
7501
7502         u8         reserved_at_800[0x80];
7503 };
7504
7505 struct mlx5_ifc_get_dropped_packet_log_out_bits {
7506         u8         status[0x8];
7507         u8         reserved_at_8[0x18];
7508
7509         u8         syndrome[0x20];
7510
7511         u8         reserved_at_40[0x40];
7512
7513         u8         packet_headers_log[128][0x8];
7514
7515         u8         packet_syndrome[64][0x8];
7516 };
7517
7518 struct mlx5_ifc_get_dropped_packet_log_in_bits {
7519         u8         opcode[0x10];
7520         u8         reserved_at_10[0x10];
7521
7522         u8         reserved_at_20[0x10];
7523         u8         op_mod[0x10];
7524
7525         u8         reserved_at_40[0x40];
7526 };
7527
7528 struct mlx5_ifc_gen_eqe_in_bits {
7529         u8         opcode[0x10];
7530         u8         reserved_at_10[0x10];
7531
7532         u8         reserved_at_20[0x10];
7533         u8         op_mod[0x10];
7534
7535         u8         reserved_at_40[0x18];
7536         u8         eq_number[0x8];
7537
7538         u8         reserved_at_60[0x20];
7539
7540         u8         eqe[64][0x8];
7541 };
7542
7543 struct mlx5_ifc_gen_eq_out_bits {
7544         u8         status[0x8];
7545         u8         reserved_at_8[0x18];
7546
7547         u8         syndrome[0x20];
7548
7549         u8         reserved_at_40[0x40];
7550 };
7551
7552 struct mlx5_ifc_enable_hca_out_bits {
7553         u8         status[0x8];
7554         u8         reserved_at_8[0x18];
7555
7556         u8         syndrome[0x20];
7557
7558         u8         reserved_at_40[0x20];
7559 };
7560
7561 struct mlx5_ifc_enable_hca_in_bits {
7562         u8         opcode[0x10];
7563         u8         reserved_at_10[0x10];
7564
7565         u8         reserved_at_20[0x10];
7566         u8         op_mod[0x10];
7567
7568         u8         embedded_cpu_function[0x1];
7569         u8         reserved_at_41[0xf];
7570         u8         function_id[0x10];
7571
7572         u8         reserved_at_60[0x20];
7573 };
7574
7575 struct mlx5_ifc_drain_dct_out_bits {
7576         u8         status[0x8];
7577         u8         reserved_at_8[0x18];
7578
7579         u8         syndrome[0x20];
7580
7581         u8         reserved_at_40[0x40];
7582 };
7583
7584 struct mlx5_ifc_drain_dct_in_bits {
7585         u8         opcode[0x10];
7586         u8         uid[0x10];
7587
7588         u8         reserved_at_20[0x10];
7589         u8         op_mod[0x10];
7590
7591         u8         reserved_at_40[0x8];
7592         u8         dctn[0x18];
7593
7594         u8         reserved_at_60[0x20];
7595 };
7596
7597 struct mlx5_ifc_disable_hca_out_bits {
7598         u8         status[0x8];
7599         u8         reserved_at_8[0x18];
7600
7601         u8         syndrome[0x20];
7602
7603         u8         reserved_at_40[0x20];
7604 };
7605
7606 struct mlx5_ifc_disable_hca_in_bits {
7607         u8         opcode[0x10];
7608         u8         reserved_at_10[0x10];
7609
7610         u8         reserved_at_20[0x10];
7611         u8         op_mod[0x10];
7612
7613         u8         embedded_cpu_function[0x1];
7614         u8         reserved_at_41[0xf];
7615         u8         function_id[0x10];
7616
7617         u8         reserved_at_60[0x20];
7618 };
7619
7620 struct mlx5_ifc_detach_from_mcg_out_bits {
7621         u8         status[0x8];
7622         u8         reserved_at_8[0x18];
7623
7624         u8         syndrome[0x20];
7625
7626         u8         reserved_at_40[0x40];
7627 };
7628
7629 struct mlx5_ifc_detach_from_mcg_in_bits {
7630         u8         opcode[0x10];
7631         u8         uid[0x10];
7632
7633         u8         reserved_at_20[0x10];
7634         u8         op_mod[0x10];
7635
7636         u8         reserved_at_40[0x8];
7637         u8         qpn[0x18];
7638
7639         u8         reserved_at_60[0x20];
7640
7641         u8         multicast_gid[16][0x8];
7642 };
7643
7644 struct mlx5_ifc_destroy_xrq_out_bits {
7645         u8         status[0x8];
7646         u8         reserved_at_8[0x18];
7647
7648         u8         syndrome[0x20];
7649
7650         u8         reserved_at_40[0x40];
7651 };
7652
7653 struct mlx5_ifc_destroy_xrq_in_bits {
7654         u8         opcode[0x10];
7655         u8         uid[0x10];
7656
7657         u8         reserved_at_20[0x10];
7658         u8         op_mod[0x10];
7659
7660         u8         reserved_at_40[0x8];
7661         u8         xrqn[0x18];
7662
7663         u8         reserved_at_60[0x20];
7664 };
7665
7666 struct mlx5_ifc_destroy_xrc_srq_out_bits {
7667         u8         status[0x8];
7668         u8         reserved_at_8[0x18];
7669
7670         u8         syndrome[0x20];
7671
7672         u8         reserved_at_40[0x40];
7673 };
7674
7675 struct mlx5_ifc_destroy_xrc_srq_in_bits {
7676         u8         opcode[0x10];
7677         u8         uid[0x10];
7678
7679         u8         reserved_at_20[0x10];
7680         u8         op_mod[0x10];
7681
7682         u8         reserved_at_40[0x8];
7683         u8         xrc_srqn[0x18];
7684
7685         u8         reserved_at_60[0x20];
7686 };
7687
7688 struct mlx5_ifc_destroy_tis_out_bits {
7689         u8         status[0x8];
7690         u8         reserved_at_8[0x18];
7691
7692         u8         syndrome[0x20];
7693
7694         u8         reserved_at_40[0x40];
7695 };
7696
7697 struct mlx5_ifc_destroy_tis_in_bits {
7698         u8         opcode[0x10];
7699         u8         uid[0x10];
7700
7701         u8         reserved_at_20[0x10];
7702         u8         op_mod[0x10];
7703
7704         u8         reserved_at_40[0x8];
7705         u8         tisn[0x18];
7706
7707         u8         reserved_at_60[0x20];
7708 };
7709
7710 struct mlx5_ifc_destroy_tir_out_bits {
7711         u8         status[0x8];
7712         u8         reserved_at_8[0x18];
7713
7714         u8         syndrome[0x20];
7715
7716         u8         reserved_at_40[0x40];
7717 };
7718
7719 struct mlx5_ifc_destroy_tir_in_bits {
7720         u8         opcode[0x10];
7721         u8         uid[0x10];
7722
7723         u8         reserved_at_20[0x10];
7724         u8         op_mod[0x10];
7725
7726         u8         reserved_at_40[0x8];
7727         u8         tirn[0x18];
7728
7729         u8         reserved_at_60[0x20];
7730 };
7731
7732 struct mlx5_ifc_destroy_srq_out_bits {
7733         u8         status[0x8];
7734         u8         reserved_at_8[0x18];
7735
7736         u8         syndrome[0x20];
7737
7738         u8         reserved_at_40[0x40];
7739 };
7740
7741 struct mlx5_ifc_destroy_srq_in_bits {
7742         u8         opcode[0x10];
7743         u8         uid[0x10];
7744
7745         u8         reserved_at_20[0x10];
7746         u8         op_mod[0x10];
7747
7748         u8         reserved_at_40[0x8];
7749         u8         srqn[0x18];
7750
7751         u8         reserved_at_60[0x20];
7752 };
7753
7754 struct mlx5_ifc_destroy_sq_out_bits {
7755         u8         status[0x8];
7756         u8         reserved_at_8[0x18];
7757
7758         u8         syndrome[0x20];
7759
7760         u8         reserved_at_40[0x40];
7761 };
7762
7763 struct mlx5_ifc_destroy_sq_in_bits {
7764         u8         opcode[0x10];
7765         u8         uid[0x10];
7766
7767         u8         reserved_at_20[0x10];
7768         u8         op_mod[0x10];
7769
7770         u8         reserved_at_40[0x8];
7771         u8         sqn[0x18];
7772
7773         u8         reserved_at_60[0x20];
7774 };
7775
7776 struct mlx5_ifc_destroy_scheduling_element_out_bits {
7777         u8         status[0x8];
7778         u8         reserved_at_8[0x18];
7779
7780         u8         syndrome[0x20];
7781
7782         u8         reserved_at_40[0x1c0];
7783 };
7784
7785 struct mlx5_ifc_destroy_scheduling_element_in_bits {
7786         u8         opcode[0x10];
7787         u8         reserved_at_10[0x10];
7788
7789         u8         reserved_at_20[0x10];
7790         u8         op_mod[0x10];
7791
7792         u8         scheduling_hierarchy[0x8];
7793         u8         reserved_at_48[0x18];
7794
7795         u8         scheduling_element_id[0x20];
7796
7797         u8         reserved_at_80[0x180];
7798 };
7799
7800 struct mlx5_ifc_destroy_rqt_out_bits {
7801         u8         status[0x8];
7802         u8         reserved_at_8[0x18];
7803
7804         u8         syndrome[0x20];
7805
7806         u8         reserved_at_40[0x40];
7807 };
7808
7809 struct mlx5_ifc_destroy_rqt_in_bits {
7810         u8         opcode[0x10];
7811         u8         uid[0x10];
7812
7813         u8         reserved_at_20[0x10];
7814         u8         op_mod[0x10];
7815
7816         u8         reserved_at_40[0x8];
7817         u8         rqtn[0x18];
7818
7819         u8         reserved_at_60[0x20];
7820 };
7821
7822 struct mlx5_ifc_destroy_rq_out_bits {
7823         u8         status[0x8];
7824         u8         reserved_at_8[0x18];
7825
7826         u8         syndrome[0x20];
7827
7828         u8         reserved_at_40[0x40];
7829 };
7830
7831 struct mlx5_ifc_destroy_rq_in_bits {
7832         u8         opcode[0x10];
7833         u8         uid[0x10];
7834
7835         u8         reserved_at_20[0x10];
7836         u8         op_mod[0x10];
7837
7838         u8         reserved_at_40[0x8];
7839         u8         rqn[0x18];
7840
7841         u8         reserved_at_60[0x20];
7842 };
7843
7844 struct mlx5_ifc_set_delay_drop_params_in_bits {
7845         u8         opcode[0x10];
7846         u8         reserved_at_10[0x10];
7847
7848         u8         reserved_at_20[0x10];
7849         u8         op_mod[0x10];
7850
7851         u8         reserved_at_40[0x20];
7852
7853         u8         reserved_at_60[0x10];
7854         u8         delay_drop_timeout[0x10];
7855 };
7856
7857 struct mlx5_ifc_set_delay_drop_params_out_bits {
7858         u8         status[0x8];
7859         u8         reserved_at_8[0x18];
7860
7861         u8         syndrome[0x20];
7862
7863         u8         reserved_at_40[0x40];
7864 };
7865
7866 struct mlx5_ifc_destroy_rmp_out_bits {
7867         u8         status[0x8];
7868         u8         reserved_at_8[0x18];
7869
7870         u8         syndrome[0x20];
7871
7872         u8         reserved_at_40[0x40];
7873 };
7874
7875 struct mlx5_ifc_destroy_rmp_in_bits {
7876         u8         opcode[0x10];
7877         u8         uid[0x10];
7878
7879         u8         reserved_at_20[0x10];
7880         u8         op_mod[0x10];
7881
7882         u8         reserved_at_40[0x8];
7883         u8         rmpn[0x18];
7884
7885         u8         reserved_at_60[0x20];
7886 };
7887
7888 struct mlx5_ifc_destroy_qp_out_bits {
7889         u8         status[0x8];
7890         u8         reserved_at_8[0x18];
7891
7892         u8         syndrome[0x20];
7893
7894         u8         reserved_at_40[0x40];
7895 };
7896
7897 struct mlx5_ifc_destroy_qp_in_bits {
7898         u8         opcode[0x10];
7899         u8         uid[0x10];
7900
7901         u8         reserved_at_20[0x10];
7902         u8         op_mod[0x10];
7903
7904         u8         reserved_at_40[0x8];
7905         u8         qpn[0x18];
7906
7907         u8         reserved_at_60[0x20];
7908 };
7909
7910 struct mlx5_ifc_destroy_psv_out_bits {
7911         u8         status[0x8];
7912         u8         reserved_at_8[0x18];
7913
7914         u8         syndrome[0x20];
7915
7916         u8         reserved_at_40[0x40];
7917 };
7918
7919 struct mlx5_ifc_destroy_psv_in_bits {
7920         u8         opcode[0x10];
7921         u8         reserved_at_10[0x10];
7922
7923         u8         reserved_at_20[0x10];
7924         u8         op_mod[0x10];
7925
7926         u8         reserved_at_40[0x8];
7927         u8         psvn[0x18];
7928
7929         u8         reserved_at_60[0x20];
7930 };
7931
7932 struct mlx5_ifc_destroy_mkey_out_bits {
7933         u8         status[0x8];
7934         u8         reserved_at_8[0x18];
7935
7936         u8         syndrome[0x20];
7937
7938         u8         reserved_at_40[0x40];
7939 };
7940
7941 struct mlx5_ifc_destroy_mkey_in_bits {
7942         u8         opcode[0x10];
7943         u8         uid[0x10];
7944
7945         u8         reserved_at_20[0x10];
7946         u8         op_mod[0x10];
7947
7948         u8         reserved_at_40[0x8];
7949         u8         mkey_index[0x18];
7950
7951         u8         reserved_at_60[0x20];
7952 };
7953
7954 struct mlx5_ifc_destroy_flow_table_out_bits {
7955         u8         status[0x8];
7956         u8         reserved_at_8[0x18];
7957
7958         u8         syndrome[0x20];
7959
7960         u8         reserved_at_40[0x40];
7961 };
7962
7963 struct mlx5_ifc_destroy_flow_table_in_bits {
7964         u8         opcode[0x10];
7965         u8         reserved_at_10[0x10];
7966
7967         u8         reserved_at_20[0x10];
7968         u8         op_mod[0x10];
7969
7970         u8         other_vport[0x1];
7971         u8         reserved_at_41[0xf];
7972         u8         vport_number[0x10];
7973
7974         u8         reserved_at_60[0x20];
7975
7976         u8         table_type[0x8];
7977         u8         reserved_at_88[0x18];
7978
7979         u8         reserved_at_a0[0x8];
7980         u8         table_id[0x18];
7981
7982         u8         reserved_at_c0[0x140];
7983 };
7984
7985 struct mlx5_ifc_destroy_flow_group_out_bits {
7986         u8         status[0x8];
7987         u8         reserved_at_8[0x18];
7988
7989         u8         syndrome[0x20];
7990
7991         u8         reserved_at_40[0x40];
7992 };
7993
7994 struct mlx5_ifc_destroy_flow_group_in_bits {
7995         u8         opcode[0x10];
7996         u8         reserved_at_10[0x10];
7997
7998         u8         reserved_at_20[0x10];
7999         u8         op_mod[0x10];
8000
8001         u8         other_vport[0x1];
8002         u8         reserved_at_41[0xf];
8003         u8         vport_number[0x10];
8004
8005         u8         reserved_at_60[0x20];
8006
8007         u8         table_type[0x8];
8008         u8         reserved_at_88[0x18];
8009
8010         u8         reserved_at_a0[0x8];
8011         u8         table_id[0x18];
8012
8013         u8         group_id[0x20];
8014
8015         u8         reserved_at_e0[0x120];
8016 };
8017
8018 struct mlx5_ifc_destroy_eq_out_bits {
8019         u8         status[0x8];
8020         u8         reserved_at_8[0x18];
8021
8022         u8         syndrome[0x20];
8023
8024         u8         reserved_at_40[0x40];
8025 };
8026
8027 struct mlx5_ifc_destroy_eq_in_bits {
8028         u8         opcode[0x10];
8029         u8         reserved_at_10[0x10];
8030
8031         u8         reserved_at_20[0x10];
8032         u8         op_mod[0x10];
8033
8034         u8         reserved_at_40[0x18];
8035         u8         eq_number[0x8];
8036
8037         u8         reserved_at_60[0x20];
8038 };
8039
8040 struct mlx5_ifc_destroy_dct_out_bits {
8041         u8         status[0x8];
8042         u8         reserved_at_8[0x18];
8043
8044         u8         syndrome[0x20];
8045
8046         u8         reserved_at_40[0x40];
8047 };
8048
8049 struct mlx5_ifc_destroy_dct_in_bits {
8050         u8         opcode[0x10];
8051         u8         uid[0x10];
8052
8053         u8         reserved_at_20[0x10];
8054         u8         op_mod[0x10];
8055
8056         u8         reserved_at_40[0x8];
8057         u8         dctn[0x18];
8058
8059         u8         reserved_at_60[0x20];
8060 };
8061
8062 struct mlx5_ifc_destroy_cq_out_bits {
8063         u8         status[0x8];
8064         u8         reserved_at_8[0x18];
8065
8066         u8         syndrome[0x20];
8067
8068         u8         reserved_at_40[0x40];
8069 };
8070
8071 struct mlx5_ifc_destroy_cq_in_bits {
8072         u8         opcode[0x10];
8073         u8         uid[0x10];
8074
8075         u8         reserved_at_20[0x10];
8076         u8         op_mod[0x10];
8077
8078         u8         reserved_at_40[0x8];
8079         u8         cqn[0x18];
8080
8081         u8         reserved_at_60[0x20];
8082 };
8083
8084 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
8085         u8         status[0x8];
8086         u8         reserved_at_8[0x18];
8087
8088         u8         syndrome[0x20];
8089
8090         u8         reserved_at_40[0x40];
8091 };
8092
8093 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
8094         u8         opcode[0x10];
8095         u8         reserved_at_10[0x10];
8096
8097         u8         reserved_at_20[0x10];
8098         u8         op_mod[0x10];
8099
8100         u8         reserved_at_40[0x20];
8101
8102         u8         reserved_at_60[0x10];
8103         u8         vxlan_udp_port[0x10];
8104 };
8105
8106 struct mlx5_ifc_delete_l2_table_entry_out_bits {
8107         u8         status[0x8];
8108         u8         reserved_at_8[0x18];
8109
8110         u8         syndrome[0x20];
8111
8112         u8         reserved_at_40[0x40];
8113 };
8114
8115 struct mlx5_ifc_delete_l2_table_entry_in_bits {
8116         u8         opcode[0x10];
8117         u8         reserved_at_10[0x10];
8118
8119         u8         reserved_at_20[0x10];
8120         u8         op_mod[0x10];
8121
8122         u8         reserved_at_40[0x60];
8123
8124         u8         reserved_at_a0[0x8];
8125         u8         table_index[0x18];
8126
8127         u8         reserved_at_c0[0x140];
8128 };
8129
8130 struct mlx5_ifc_delete_fte_out_bits {
8131         u8         status[0x8];
8132         u8         reserved_at_8[0x18];
8133
8134         u8         syndrome[0x20];
8135
8136         u8         reserved_at_40[0x40];
8137 };
8138
8139 struct mlx5_ifc_delete_fte_in_bits {
8140         u8         opcode[0x10];
8141         u8         reserved_at_10[0x10];
8142
8143         u8         reserved_at_20[0x10];
8144         u8         op_mod[0x10];
8145
8146         u8         other_vport[0x1];
8147         u8         reserved_at_41[0xf];
8148         u8         vport_number[0x10];
8149
8150         u8         reserved_at_60[0x20];
8151
8152         u8         table_type[0x8];
8153         u8         reserved_at_88[0x18];
8154
8155         u8         reserved_at_a0[0x8];
8156         u8         table_id[0x18];
8157
8158         u8         reserved_at_c0[0x40];
8159
8160         u8         flow_index[0x20];
8161
8162         u8         reserved_at_120[0xe0];
8163 };
8164
8165 struct mlx5_ifc_dealloc_xrcd_out_bits {
8166         u8         status[0x8];
8167         u8         reserved_at_8[0x18];
8168
8169         u8         syndrome[0x20];
8170
8171         u8         reserved_at_40[0x40];
8172 };
8173
8174 struct mlx5_ifc_dealloc_xrcd_in_bits {
8175         u8         opcode[0x10];
8176         u8         uid[0x10];
8177
8178         u8         reserved_at_20[0x10];
8179         u8         op_mod[0x10];
8180
8181         u8         reserved_at_40[0x8];
8182         u8         xrcd[0x18];
8183
8184         u8         reserved_at_60[0x20];
8185 };
8186
8187 struct mlx5_ifc_dealloc_uar_out_bits {
8188         u8         status[0x8];
8189         u8         reserved_at_8[0x18];
8190
8191         u8         syndrome[0x20];
8192
8193         u8         reserved_at_40[0x40];
8194 };
8195
8196 struct mlx5_ifc_dealloc_uar_in_bits {
8197         u8         opcode[0x10];
8198         u8         uid[0x10];
8199
8200         u8         reserved_at_20[0x10];
8201         u8         op_mod[0x10];
8202
8203         u8         reserved_at_40[0x8];
8204         u8         uar[0x18];
8205
8206         u8         reserved_at_60[0x20];
8207 };
8208
8209 struct mlx5_ifc_dealloc_transport_domain_out_bits {
8210         u8         status[0x8];
8211         u8         reserved_at_8[0x18];
8212
8213         u8         syndrome[0x20];
8214
8215         u8         reserved_at_40[0x40];
8216 };
8217
8218 struct mlx5_ifc_dealloc_transport_domain_in_bits {
8219         u8         opcode[0x10];
8220         u8         uid[0x10];
8221
8222         u8         reserved_at_20[0x10];
8223         u8         op_mod[0x10];
8224
8225         u8         reserved_at_40[0x8];
8226         u8         transport_domain[0x18];
8227
8228         u8         reserved_at_60[0x20];
8229 };
8230
8231 struct mlx5_ifc_dealloc_q_counter_out_bits {
8232         u8         status[0x8];
8233         u8         reserved_at_8[0x18];
8234
8235         u8         syndrome[0x20];
8236
8237         u8         reserved_at_40[0x40];
8238 };
8239
8240 struct mlx5_ifc_dealloc_q_counter_in_bits {
8241         u8         opcode[0x10];
8242         u8         reserved_at_10[0x10];
8243
8244         u8         reserved_at_20[0x10];
8245         u8         op_mod[0x10];
8246
8247         u8         reserved_at_40[0x18];
8248         u8         counter_set_id[0x8];
8249
8250         u8         reserved_at_60[0x20];
8251 };
8252
8253 struct mlx5_ifc_dealloc_pd_out_bits {
8254         u8         status[0x8];
8255         u8         reserved_at_8[0x18];
8256
8257         u8         syndrome[0x20];
8258
8259         u8         reserved_at_40[0x40];
8260 };
8261
8262 struct mlx5_ifc_dealloc_pd_in_bits {
8263         u8         opcode[0x10];
8264         u8         uid[0x10];
8265
8266         u8         reserved_at_20[0x10];
8267         u8         op_mod[0x10];
8268
8269         u8         reserved_at_40[0x8];
8270         u8         pd[0x18];
8271
8272         u8         reserved_at_60[0x20];
8273 };
8274
8275 struct mlx5_ifc_dealloc_flow_counter_out_bits {
8276         u8         status[0x8];
8277         u8         reserved_at_8[0x18];
8278
8279         u8         syndrome[0x20];
8280
8281         u8         reserved_at_40[0x40];
8282 };
8283
8284 struct mlx5_ifc_dealloc_flow_counter_in_bits {
8285         u8         opcode[0x10];
8286         u8         reserved_at_10[0x10];
8287
8288         u8         reserved_at_20[0x10];
8289         u8         op_mod[0x10];
8290
8291         u8         flow_counter_id[0x20];
8292
8293         u8         reserved_at_60[0x20];
8294 };
8295
8296 struct mlx5_ifc_create_xrq_out_bits {
8297         u8         status[0x8];
8298         u8         reserved_at_8[0x18];
8299
8300         u8         syndrome[0x20];
8301
8302         u8         reserved_at_40[0x8];
8303         u8         xrqn[0x18];
8304
8305         u8         reserved_at_60[0x20];
8306 };
8307
8308 struct mlx5_ifc_create_xrq_in_bits {
8309         u8         opcode[0x10];
8310         u8         uid[0x10];
8311
8312         u8         reserved_at_20[0x10];
8313         u8         op_mod[0x10];
8314
8315         u8         reserved_at_40[0x40];
8316
8317         struct mlx5_ifc_xrqc_bits xrq_context;
8318 };
8319
8320 struct mlx5_ifc_create_xrc_srq_out_bits {
8321         u8         status[0x8];
8322         u8         reserved_at_8[0x18];
8323
8324         u8         syndrome[0x20];
8325
8326         u8         reserved_at_40[0x8];
8327         u8         xrc_srqn[0x18];
8328
8329         u8         reserved_at_60[0x20];
8330 };
8331
8332 struct mlx5_ifc_create_xrc_srq_in_bits {
8333         u8         opcode[0x10];
8334         u8         uid[0x10];
8335
8336         u8         reserved_at_20[0x10];
8337         u8         op_mod[0x10];
8338
8339         u8         reserved_at_40[0x40];
8340
8341         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
8342
8343         u8         reserved_at_280[0x60];
8344
8345         u8         xrc_srq_umem_valid[0x1];
8346         u8         reserved_at_2e1[0x1f];
8347
8348         u8         reserved_at_300[0x580];
8349
8350         u8         pas[][0x40];
8351 };
8352
8353 struct mlx5_ifc_create_tis_out_bits {
8354         u8         status[0x8];
8355         u8         reserved_at_8[0x18];
8356
8357         u8         syndrome[0x20];
8358
8359         u8         reserved_at_40[0x8];
8360         u8         tisn[0x18];
8361
8362         u8         reserved_at_60[0x20];
8363 };
8364
8365 struct mlx5_ifc_create_tis_in_bits {
8366         u8         opcode[0x10];
8367         u8         uid[0x10];
8368
8369         u8         reserved_at_20[0x10];
8370         u8         op_mod[0x10];
8371
8372         u8         reserved_at_40[0xc0];
8373
8374         struct mlx5_ifc_tisc_bits ctx;
8375 };
8376
8377 struct mlx5_ifc_create_tir_out_bits {
8378         u8         status[0x8];
8379         u8         icm_address_63_40[0x18];
8380
8381         u8         syndrome[0x20];
8382
8383         u8         icm_address_39_32[0x8];
8384         u8         tirn[0x18];
8385
8386         u8         icm_address_31_0[0x20];
8387 };
8388
8389 struct mlx5_ifc_create_tir_in_bits {
8390         u8         opcode[0x10];
8391         u8         uid[0x10];
8392
8393         u8         reserved_at_20[0x10];
8394         u8         op_mod[0x10];
8395
8396         u8         reserved_at_40[0xc0];
8397
8398         struct mlx5_ifc_tirc_bits ctx;
8399 };
8400
8401 struct mlx5_ifc_create_srq_out_bits {
8402         u8         status[0x8];
8403         u8         reserved_at_8[0x18];
8404
8405         u8         syndrome[0x20];
8406
8407         u8         reserved_at_40[0x8];
8408         u8         srqn[0x18];
8409
8410         u8         reserved_at_60[0x20];
8411 };
8412
8413 struct mlx5_ifc_create_srq_in_bits {
8414         u8         opcode[0x10];
8415         u8         uid[0x10];
8416
8417         u8         reserved_at_20[0x10];
8418         u8         op_mod[0x10];
8419
8420         u8         reserved_at_40[0x40];
8421
8422         struct mlx5_ifc_srqc_bits srq_context_entry;
8423
8424         u8         reserved_at_280[0x600];
8425
8426         u8         pas[][0x40];
8427 };
8428
8429 struct mlx5_ifc_create_sq_out_bits {
8430         u8         status[0x8];
8431         u8         reserved_at_8[0x18];
8432
8433         u8         syndrome[0x20];
8434
8435         u8         reserved_at_40[0x8];
8436         u8         sqn[0x18];
8437
8438         u8         reserved_at_60[0x20];
8439 };
8440
8441 struct mlx5_ifc_create_sq_in_bits {
8442         u8         opcode[0x10];
8443         u8         uid[0x10];
8444
8445         u8         reserved_at_20[0x10];
8446         u8         op_mod[0x10];
8447
8448         u8         reserved_at_40[0xc0];
8449
8450         struct mlx5_ifc_sqc_bits ctx;
8451 };
8452
8453 struct mlx5_ifc_create_scheduling_element_out_bits {
8454         u8         status[0x8];
8455         u8         reserved_at_8[0x18];
8456
8457         u8         syndrome[0x20];
8458
8459         u8         reserved_at_40[0x40];
8460
8461         u8         scheduling_element_id[0x20];
8462
8463         u8         reserved_at_a0[0x160];
8464 };
8465
8466 struct mlx5_ifc_create_scheduling_element_in_bits {
8467         u8         opcode[0x10];
8468         u8         reserved_at_10[0x10];
8469
8470         u8         reserved_at_20[0x10];
8471         u8         op_mod[0x10];
8472
8473         u8         scheduling_hierarchy[0x8];
8474         u8         reserved_at_48[0x18];
8475
8476         u8         reserved_at_60[0xa0];
8477
8478         struct mlx5_ifc_scheduling_context_bits scheduling_context;
8479
8480         u8         reserved_at_300[0x100];
8481 };
8482
8483 struct mlx5_ifc_create_rqt_out_bits {
8484         u8         status[0x8];
8485         u8         reserved_at_8[0x18];
8486
8487         u8         syndrome[0x20];
8488
8489         u8         reserved_at_40[0x8];
8490         u8         rqtn[0x18];
8491
8492         u8         reserved_at_60[0x20];
8493 };
8494
8495 struct mlx5_ifc_create_rqt_in_bits {
8496         u8         opcode[0x10];
8497         u8         uid[0x10];
8498
8499         u8         reserved_at_20[0x10];
8500         u8         op_mod[0x10];
8501
8502         u8         reserved_at_40[0xc0];
8503
8504         struct mlx5_ifc_rqtc_bits rqt_context;
8505 };
8506
8507 struct mlx5_ifc_create_rq_out_bits {
8508         u8         status[0x8];
8509         u8         reserved_at_8[0x18];
8510
8511         u8         syndrome[0x20];
8512
8513         u8         reserved_at_40[0x8];
8514         u8         rqn[0x18];
8515
8516         u8         reserved_at_60[0x20];
8517 };
8518
8519 struct mlx5_ifc_create_rq_in_bits {
8520         u8         opcode[0x10];
8521         u8         uid[0x10];
8522
8523         u8         reserved_at_20[0x10];
8524         u8         op_mod[0x10];
8525
8526         u8         reserved_at_40[0xc0];
8527
8528         struct mlx5_ifc_rqc_bits ctx;
8529 };
8530
8531 struct mlx5_ifc_create_rmp_out_bits {
8532         u8         status[0x8];
8533         u8         reserved_at_8[0x18];
8534
8535         u8         syndrome[0x20];
8536
8537         u8         reserved_at_40[0x8];
8538         u8         rmpn[0x18];
8539
8540         u8         reserved_at_60[0x20];
8541 };
8542
8543 struct mlx5_ifc_create_rmp_in_bits {
8544         u8         opcode[0x10];
8545         u8         uid[0x10];
8546
8547         u8         reserved_at_20[0x10];
8548         u8         op_mod[0x10];
8549
8550         u8         reserved_at_40[0xc0];
8551
8552         struct mlx5_ifc_rmpc_bits ctx;
8553 };
8554
8555 struct mlx5_ifc_create_qp_out_bits {
8556         u8         status[0x8];
8557         u8         reserved_at_8[0x18];
8558
8559         u8         syndrome[0x20];
8560
8561         u8         reserved_at_40[0x8];
8562         u8         qpn[0x18];
8563
8564         u8         ece[0x20];
8565 };
8566
8567 struct mlx5_ifc_create_qp_in_bits {
8568         u8         opcode[0x10];
8569         u8         uid[0x10];
8570
8571         u8         reserved_at_20[0x10];
8572         u8         op_mod[0x10];
8573
8574         u8         reserved_at_40[0x8];
8575         u8         input_qpn[0x18];
8576
8577         u8         reserved_at_60[0x20];
8578         u8         opt_param_mask[0x20];
8579
8580         u8         ece[0x20];
8581
8582         struct mlx5_ifc_qpc_bits qpc;
8583
8584         u8         reserved_at_800[0x60];
8585
8586         u8         wq_umem_valid[0x1];
8587         u8         reserved_at_861[0x1f];
8588
8589         u8         pas[][0x40];
8590 };
8591
8592 struct mlx5_ifc_create_psv_out_bits {
8593         u8         status[0x8];
8594         u8         reserved_at_8[0x18];
8595
8596         u8         syndrome[0x20];
8597
8598         u8         reserved_at_40[0x40];
8599
8600         u8         reserved_at_80[0x8];
8601         u8         psv0_index[0x18];
8602
8603         u8         reserved_at_a0[0x8];
8604         u8         psv1_index[0x18];
8605
8606         u8         reserved_at_c0[0x8];
8607         u8         psv2_index[0x18];
8608
8609         u8         reserved_at_e0[0x8];
8610         u8         psv3_index[0x18];
8611 };
8612
8613 struct mlx5_ifc_create_psv_in_bits {
8614         u8         opcode[0x10];
8615         u8         reserved_at_10[0x10];
8616
8617         u8         reserved_at_20[0x10];
8618         u8         op_mod[0x10];
8619
8620         u8         num_psv[0x4];
8621         u8         reserved_at_44[0x4];
8622         u8         pd[0x18];
8623
8624         u8         reserved_at_60[0x20];
8625 };
8626
8627 struct mlx5_ifc_create_mkey_out_bits {
8628         u8         status[0x8];
8629         u8         reserved_at_8[0x18];
8630
8631         u8         syndrome[0x20];
8632
8633         u8         reserved_at_40[0x8];
8634         u8         mkey_index[0x18];
8635
8636         u8         reserved_at_60[0x20];
8637 };
8638
8639 struct mlx5_ifc_create_mkey_in_bits {
8640         u8         opcode[0x10];
8641         u8         uid[0x10];
8642
8643         u8         reserved_at_20[0x10];
8644         u8         op_mod[0x10];
8645
8646         u8         reserved_at_40[0x20];
8647
8648         u8         pg_access[0x1];
8649         u8         mkey_umem_valid[0x1];
8650         u8         reserved_at_62[0x1e];
8651
8652         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8653
8654         u8         reserved_at_280[0x80];
8655
8656         u8         translations_octword_actual_size[0x20];
8657
8658         u8         reserved_at_320[0x560];
8659
8660         u8         klm_pas_mtt[][0x20];
8661 };
8662
8663 enum {
8664         MLX5_FLOW_TABLE_TYPE_NIC_RX             = 0x0,
8665         MLX5_FLOW_TABLE_TYPE_NIC_TX             = 0x1,
8666         MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL     = 0x2,
8667         MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL    = 0x3,
8668         MLX5_FLOW_TABLE_TYPE_FDB                = 0X4,
8669         MLX5_FLOW_TABLE_TYPE_SNIFFER_RX         = 0X5,
8670         MLX5_FLOW_TABLE_TYPE_SNIFFER_TX         = 0X6,
8671 };
8672
8673 struct mlx5_ifc_create_flow_table_out_bits {
8674         u8         status[0x8];
8675         u8         icm_address_63_40[0x18];
8676
8677         u8         syndrome[0x20];
8678
8679         u8         icm_address_39_32[0x8];
8680         u8         table_id[0x18];
8681
8682         u8         icm_address_31_0[0x20];
8683 };
8684
8685 struct mlx5_ifc_create_flow_table_in_bits {
8686         u8         opcode[0x10];
8687         u8         uid[0x10];
8688
8689         u8         reserved_at_20[0x10];
8690         u8         op_mod[0x10];
8691
8692         u8         other_vport[0x1];
8693         u8         reserved_at_41[0xf];
8694         u8         vport_number[0x10];
8695
8696         u8         reserved_at_60[0x20];
8697
8698         u8         table_type[0x8];
8699         u8         reserved_at_88[0x18];
8700
8701         u8         reserved_at_a0[0x20];
8702
8703         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8704 };
8705
8706 struct mlx5_ifc_create_flow_group_out_bits {
8707         u8         status[0x8];
8708         u8         reserved_at_8[0x18];
8709
8710         u8         syndrome[0x20];
8711
8712         u8         reserved_at_40[0x8];
8713         u8         group_id[0x18];
8714
8715         u8         reserved_at_60[0x20];
8716 };
8717
8718 enum {
8719         MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE  = 0x0,
8720         MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT     = 0x1,
8721 };
8722
8723 enum {
8724         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
8725         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
8726         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
8727         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8728 };
8729
8730 struct mlx5_ifc_create_flow_group_in_bits {
8731         u8         opcode[0x10];
8732         u8         reserved_at_10[0x10];
8733
8734         u8         reserved_at_20[0x10];
8735         u8         op_mod[0x10];
8736
8737         u8         other_vport[0x1];
8738         u8         reserved_at_41[0xf];
8739         u8         vport_number[0x10];
8740
8741         u8         reserved_at_60[0x20];
8742
8743         u8         table_type[0x8];
8744         u8         reserved_at_88[0x4];
8745         u8         group_type[0x4];
8746         u8         reserved_at_90[0x10];
8747
8748         u8         reserved_at_a0[0x8];
8749         u8         table_id[0x18];
8750
8751         u8         source_eswitch_owner_vhca_id_valid[0x1];
8752
8753         u8         reserved_at_c1[0x1f];
8754
8755         u8         start_flow_index[0x20];
8756
8757         u8         reserved_at_100[0x20];
8758
8759         u8         end_flow_index[0x20];
8760
8761         u8         reserved_at_140[0x10];
8762         u8         match_definer_id[0x10];
8763
8764         u8         reserved_at_160[0x80];
8765
8766         u8         reserved_at_1e0[0x18];
8767         u8         match_criteria_enable[0x8];
8768
8769         struct mlx5_ifc_fte_match_param_bits match_criteria;
8770
8771         u8         reserved_at_1200[0xe00];
8772 };
8773
8774 struct mlx5_ifc_create_eq_out_bits {
8775         u8         status[0x8];
8776         u8         reserved_at_8[0x18];
8777
8778         u8         syndrome[0x20];
8779
8780         u8         reserved_at_40[0x18];
8781         u8         eq_number[0x8];
8782
8783         u8         reserved_at_60[0x20];
8784 };
8785
8786 struct mlx5_ifc_create_eq_in_bits {
8787         u8         opcode[0x10];
8788         u8         uid[0x10];
8789
8790         u8         reserved_at_20[0x10];
8791         u8         op_mod[0x10];
8792
8793         u8         reserved_at_40[0x40];
8794
8795         struct mlx5_ifc_eqc_bits eq_context_entry;
8796
8797         u8         reserved_at_280[0x40];
8798
8799         u8         event_bitmask[4][0x40];
8800
8801         u8         reserved_at_3c0[0x4c0];
8802
8803         u8         pas[][0x40];
8804 };
8805
8806 struct mlx5_ifc_create_dct_out_bits {
8807         u8         status[0x8];
8808         u8         reserved_at_8[0x18];
8809
8810         u8         syndrome[0x20];
8811
8812         u8         reserved_at_40[0x8];
8813         u8         dctn[0x18];
8814
8815         u8         ece[0x20];
8816 };
8817
8818 struct mlx5_ifc_create_dct_in_bits {
8819         u8         opcode[0x10];
8820         u8         uid[0x10];
8821
8822         u8         reserved_at_20[0x10];
8823         u8         op_mod[0x10];
8824
8825         u8         reserved_at_40[0x40];
8826
8827         struct mlx5_ifc_dctc_bits dct_context_entry;
8828
8829         u8         reserved_at_280[0x180];
8830 };
8831
8832 struct mlx5_ifc_create_cq_out_bits {
8833         u8         status[0x8];
8834         u8         reserved_at_8[0x18];
8835
8836         u8         syndrome[0x20];
8837
8838         u8         reserved_at_40[0x8];
8839         u8         cqn[0x18];
8840
8841         u8         reserved_at_60[0x20];
8842 };
8843
8844 struct mlx5_ifc_create_cq_in_bits {
8845         u8         opcode[0x10];
8846         u8         uid[0x10];
8847
8848         u8         reserved_at_20[0x10];
8849         u8         op_mod[0x10];
8850
8851         u8         reserved_at_40[0x40];
8852
8853         struct mlx5_ifc_cqc_bits cq_context;
8854
8855         u8         reserved_at_280[0x60];
8856
8857         u8         cq_umem_valid[0x1];
8858         u8         reserved_at_2e1[0x59f];
8859
8860         u8         pas[][0x40];
8861 };
8862
8863 struct mlx5_ifc_config_int_moderation_out_bits {
8864         u8         status[0x8];
8865         u8         reserved_at_8[0x18];
8866
8867         u8         syndrome[0x20];
8868
8869         u8         reserved_at_40[0x4];
8870         u8         min_delay[0xc];
8871         u8         int_vector[0x10];
8872
8873         u8         reserved_at_60[0x20];
8874 };
8875
8876 enum {
8877         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
8878         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
8879 };
8880
8881 struct mlx5_ifc_config_int_moderation_in_bits {
8882         u8         opcode[0x10];
8883         u8         reserved_at_10[0x10];
8884
8885         u8         reserved_at_20[0x10];
8886         u8         op_mod[0x10];
8887
8888         u8         reserved_at_40[0x4];
8889         u8         min_delay[0xc];
8890         u8         int_vector[0x10];
8891
8892         u8         reserved_at_60[0x20];
8893 };
8894
8895 struct mlx5_ifc_attach_to_mcg_out_bits {
8896         u8         status[0x8];
8897         u8         reserved_at_8[0x18];
8898
8899         u8         syndrome[0x20];
8900
8901         u8         reserved_at_40[0x40];
8902 };
8903
8904 struct mlx5_ifc_attach_to_mcg_in_bits {
8905         u8         opcode[0x10];
8906         u8         uid[0x10];
8907
8908         u8         reserved_at_20[0x10];
8909         u8         op_mod[0x10];
8910
8911         u8         reserved_at_40[0x8];
8912         u8         qpn[0x18];
8913
8914         u8         reserved_at_60[0x20];
8915
8916         u8         multicast_gid[16][0x8];
8917 };
8918
8919 struct mlx5_ifc_arm_xrq_out_bits {
8920         u8         status[0x8];
8921         u8         reserved_at_8[0x18];
8922
8923         u8         syndrome[0x20];
8924
8925         u8         reserved_at_40[0x40];
8926 };
8927
8928 struct mlx5_ifc_arm_xrq_in_bits {
8929         u8         opcode[0x10];
8930         u8         reserved_at_10[0x10];
8931
8932         u8         reserved_at_20[0x10];
8933         u8         op_mod[0x10];
8934
8935         u8         reserved_at_40[0x8];
8936         u8         xrqn[0x18];
8937
8938         u8         reserved_at_60[0x10];
8939         u8         lwm[0x10];
8940 };
8941
8942 struct mlx5_ifc_arm_xrc_srq_out_bits {
8943         u8         status[0x8];
8944         u8         reserved_at_8[0x18];
8945
8946         u8         syndrome[0x20];
8947
8948         u8         reserved_at_40[0x40];
8949 };
8950
8951 enum {
8952         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
8953 };
8954
8955 struct mlx5_ifc_arm_xrc_srq_in_bits {
8956         u8         opcode[0x10];
8957         u8         uid[0x10];
8958
8959         u8         reserved_at_20[0x10];
8960         u8         op_mod[0x10];
8961
8962         u8         reserved_at_40[0x8];
8963         u8         xrc_srqn[0x18];
8964
8965         u8         reserved_at_60[0x10];
8966         u8         lwm[0x10];
8967 };
8968
8969 struct mlx5_ifc_arm_rq_out_bits {
8970         u8         status[0x8];
8971         u8         reserved_at_8[0x18];
8972
8973         u8         syndrome[0x20];
8974
8975         u8         reserved_at_40[0x40];
8976 };
8977
8978 enum {
8979         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8980         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8981 };
8982
8983 struct mlx5_ifc_arm_rq_in_bits {
8984         u8         opcode[0x10];
8985         u8         uid[0x10];
8986
8987         u8         reserved_at_20[0x10];
8988         u8         op_mod[0x10];
8989
8990         u8         reserved_at_40[0x8];
8991         u8         srq_number[0x18];
8992
8993         u8         reserved_at_60[0x10];
8994         u8         lwm[0x10];
8995 };
8996
8997 struct mlx5_ifc_arm_dct_out_bits {
8998         u8         status[0x8];
8999         u8         reserved_at_8[0x18];
9000
9001         u8         syndrome[0x20];
9002
9003         u8         reserved_at_40[0x40];
9004 };
9005
9006 struct mlx5_ifc_arm_dct_in_bits {
9007         u8         opcode[0x10];
9008         u8         reserved_at_10[0x10];
9009
9010         u8         reserved_at_20[0x10];
9011         u8         op_mod[0x10];
9012
9013         u8         reserved_at_40[0x8];
9014         u8         dct_number[0x18];
9015
9016         u8         reserved_at_60[0x20];
9017 };
9018
9019 struct mlx5_ifc_alloc_xrcd_out_bits {
9020         u8         status[0x8];
9021         u8         reserved_at_8[0x18];
9022
9023         u8         syndrome[0x20];
9024
9025         u8         reserved_at_40[0x8];
9026         u8         xrcd[0x18];
9027
9028         u8         reserved_at_60[0x20];
9029 };
9030
9031 struct mlx5_ifc_alloc_xrcd_in_bits {
9032         u8         opcode[0x10];
9033         u8         uid[0x10];
9034
9035         u8         reserved_at_20[0x10];
9036         u8         op_mod[0x10];
9037
9038         u8         reserved_at_40[0x40];
9039 };
9040
9041 struct mlx5_ifc_alloc_uar_out_bits {
9042         u8         status[0x8];
9043         u8         reserved_at_8[0x18];
9044
9045         u8         syndrome[0x20];
9046
9047         u8         reserved_at_40[0x8];
9048         u8         uar[0x18];
9049
9050         u8         reserved_at_60[0x20];
9051 };
9052
9053 struct mlx5_ifc_alloc_uar_in_bits {
9054         u8         opcode[0x10];
9055         u8         uid[0x10];
9056
9057         u8         reserved_at_20[0x10];
9058         u8         op_mod[0x10];
9059
9060         u8         reserved_at_40[0x40];
9061 };
9062
9063 struct mlx5_ifc_alloc_transport_domain_out_bits {
9064         u8         status[0x8];
9065         u8         reserved_at_8[0x18];
9066
9067         u8         syndrome[0x20];
9068
9069         u8         reserved_at_40[0x8];
9070         u8         transport_domain[0x18];
9071
9072         u8         reserved_at_60[0x20];
9073 };
9074
9075 struct mlx5_ifc_alloc_transport_domain_in_bits {
9076         u8         opcode[0x10];
9077         u8         uid[0x10];
9078
9079         u8         reserved_at_20[0x10];
9080         u8         op_mod[0x10];
9081
9082         u8         reserved_at_40[0x40];
9083 };
9084
9085 struct mlx5_ifc_alloc_q_counter_out_bits {
9086         u8         status[0x8];
9087         u8         reserved_at_8[0x18];
9088
9089         u8         syndrome[0x20];
9090
9091         u8         reserved_at_40[0x18];
9092         u8         counter_set_id[0x8];
9093
9094         u8         reserved_at_60[0x20];
9095 };
9096
9097 struct mlx5_ifc_alloc_q_counter_in_bits {
9098         u8         opcode[0x10];
9099         u8         uid[0x10];
9100
9101         u8         reserved_at_20[0x10];
9102         u8         op_mod[0x10];
9103
9104         u8         reserved_at_40[0x40];
9105 };
9106
9107 struct mlx5_ifc_alloc_pd_out_bits {
9108         u8         status[0x8];
9109         u8         reserved_at_8[0x18];
9110
9111         u8         syndrome[0x20];
9112
9113         u8         reserved_at_40[0x8];
9114         u8         pd[0x18];
9115
9116         u8         reserved_at_60[0x20];
9117 };
9118
9119 struct mlx5_ifc_alloc_pd_in_bits {
9120         u8         opcode[0x10];
9121         u8         uid[0x10];
9122
9123         u8         reserved_at_20[0x10];
9124         u8         op_mod[0x10];
9125
9126         u8         reserved_at_40[0x40];
9127 };
9128
9129 struct mlx5_ifc_alloc_flow_counter_out_bits {
9130         u8         status[0x8];
9131         u8         reserved_at_8[0x18];
9132
9133         u8         syndrome[0x20];
9134
9135         u8         flow_counter_id[0x20];
9136
9137         u8         reserved_at_60[0x20];
9138 };
9139
9140 struct mlx5_ifc_alloc_flow_counter_in_bits {
9141         u8         opcode[0x10];
9142         u8         reserved_at_10[0x10];
9143
9144         u8         reserved_at_20[0x10];
9145         u8         op_mod[0x10];
9146
9147         u8         reserved_at_40[0x38];
9148         u8         flow_counter_bulk[0x8];
9149 };
9150
9151 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
9152         u8         status[0x8];
9153         u8         reserved_at_8[0x18];
9154
9155         u8         syndrome[0x20];
9156
9157         u8         reserved_at_40[0x40];
9158 };
9159
9160 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
9161         u8         opcode[0x10];
9162         u8         reserved_at_10[0x10];
9163
9164         u8         reserved_at_20[0x10];
9165         u8         op_mod[0x10];
9166
9167         u8         reserved_at_40[0x20];
9168
9169         u8         reserved_at_60[0x10];
9170         u8         vxlan_udp_port[0x10];
9171 };
9172
9173 struct mlx5_ifc_set_pp_rate_limit_out_bits {
9174         u8         status[0x8];
9175         u8         reserved_at_8[0x18];
9176
9177         u8         syndrome[0x20];
9178
9179         u8         reserved_at_40[0x40];
9180 };
9181
9182 struct mlx5_ifc_set_pp_rate_limit_context_bits {
9183         u8         rate_limit[0x20];
9184
9185         u8         burst_upper_bound[0x20];
9186
9187         u8         reserved_at_40[0x10];
9188         u8         typical_packet_size[0x10];
9189
9190         u8         reserved_at_60[0x120];
9191 };
9192
9193 struct mlx5_ifc_set_pp_rate_limit_in_bits {
9194         u8         opcode[0x10];
9195         u8         uid[0x10];
9196
9197         u8         reserved_at_20[0x10];
9198         u8         op_mod[0x10];
9199
9200         u8         reserved_at_40[0x10];
9201         u8         rate_limit_index[0x10];
9202
9203         u8         reserved_at_60[0x20];
9204
9205         struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
9206 };
9207
9208 struct mlx5_ifc_access_register_out_bits {
9209         u8         status[0x8];
9210         u8         reserved_at_8[0x18];
9211
9212         u8         syndrome[0x20];
9213
9214         u8         reserved_at_40[0x40];
9215
9216         u8         register_data[][0x20];
9217 };
9218
9219 enum {
9220         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
9221         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
9222 };
9223
9224 struct mlx5_ifc_access_register_in_bits {
9225         u8         opcode[0x10];
9226         u8         reserved_at_10[0x10];
9227
9228         u8         reserved_at_20[0x10];
9229         u8         op_mod[0x10];
9230
9231         u8         reserved_at_40[0x10];
9232         u8         register_id[0x10];
9233
9234         u8         argument[0x20];
9235
9236         u8         register_data[][0x20];
9237 };
9238
9239 struct mlx5_ifc_sltp_reg_bits {
9240         u8         status[0x4];
9241         u8         version[0x4];
9242         u8         local_port[0x8];
9243         u8         pnat[0x2];
9244         u8         reserved_at_12[0x2];
9245         u8         lane[0x4];
9246         u8         reserved_at_18[0x8];
9247
9248         u8         reserved_at_20[0x20];
9249
9250         u8         reserved_at_40[0x7];
9251         u8         polarity[0x1];
9252         u8         ob_tap0[0x8];
9253         u8         ob_tap1[0x8];
9254         u8         ob_tap2[0x8];
9255
9256         u8         reserved_at_60[0xc];
9257         u8         ob_preemp_mode[0x4];
9258         u8         ob_reg[0x8];
9259         u8         ob_bias[0x8];
9260
9261         u8         reserved_at_80[0x20];
9262 };
9263
9264 struct mlx5_ifc_slrg_reg_bits {
9265         u8         status[0x4];
9266         u8         version[0x4];
9267         u8         local_port[0x8];
9268         u8         pnat[0x2];
9269         u8         reserved_at_12[0x2];
9270         u8         lane[0x4];
9271         u8         reserved_at_18[0x8];
9272
9273         u8         time_to_link_up[0x10];
9274         u8         reserved_at_30[0xc];
9275         u8         grade_lane_speed[0x4];
9276
9277         u8         grade_version[0x8];
9278         u8         grade[0x18];
9279
9280         u8         reserved_at_60[0x4];
9281         u8         height_grade_type[0x4];
9282         u8         height_grade[0x18];
9283
9284         u8         height_dz[0x10];
9285         u8         height_dv[0x10];
9286
9287         u8         reserved_at_a0[0x10];
9288         u8         height_sigma[0x10];
9289
9290         u8         reserved_at_c0[0x20];
9291
9292         u8         reserved_at_e0[0x4];
9293         u8         phase_grade_type[0x4];
9294         u8         phase_grade[0x18];
9295
9296         u8         reserved_at_100[0x8];
9297         u8         phase_eo_pos[0x8];
9298         u8         reserved_at_110[0x8];
9299         u8         phase_eo_neg[0x8];
9300
9301         u8         ffe_set_tested[0x10];
9302         u8         test_errors_per_lane[0x10];
9303 };
9304
9305 struct mlx5_ifc_pvlc_reg_bits {
9306         u8         reserved_at_0[0x8];
9307         u8         local_port[0x8];
9308         u8         reserved_at_10[0x10];
9309
9310         u8         reserved_at_20[0x1c];
9311         u8         vl_hw_cap[0x4];
9312
9313         u8         reserved_at_40[0x1c];
9314         u8         vl_admin[0x4];
9315
9316         u8         reserved_at_60[0x1c];
9317         u8         vl_operational[0x4];
9318 };
9319
9320 struct mlx5_ifc_pude_reg_bits {
9321         u8         swid[0x8];
9322         u8         local_port[0x8];
9323         u8         reserved_at_10[0x4];
9324         u8         admin_status[0x4];
9325         u8         reserved_at_18[0x4];
9326         u8         oper_status[0x4];
9327
9328         u8         reserved_at_20[0x60];
9329 };
9330
9331 struct mlx5_ifc_ptys_reg_bits {
9332         u8         reserved_at_0[0x1];
9333         u8         an_disable_admin[0x1];
9334         u8         an_disable_cap[0x1];
9335         u8         reserved_at_3[0x5];
9336         u8         local_port[0x8];
9337         u8         reserved_at_10[0xd];
9338         u8         proto_mask[0x3];
9339
9340         u8         an_status[0x4];
9341         u8         reserved_at_24[0xc];
9342         u8         data_rate_oper[0x10];
9343
9344         u8         ext_eth_proto_capability[0x20];
9345
9346         u8         eth_proto_capability[0x20];
9347
9348         u8         ib_link_width_capability[0x10];
9349         u8         ib_proto_capability[0x10];
9350
9351         u8         ext_eth_proto_admin[0x20];
9352
9353         u8         eth_proto_admin[0x20];
9354
9355         u8         ib_link_width_admin[0x10];
9356         u8         ib_proto_admin[0x10];
9357
9358         u8         ext_eth_proto_oper[0x20];
9359
9360         u8         eth_proto_oper[0x20];
9361
9362         u8         ib_link_width_oper[0x10];
9363         u8         ib_proto_oper[0x10];
9364
9365         u8         reserved_at_160[0x1c];
9366         u8         connector_type[0x4];
9367
9368         u8         eth_proto_lp_advertise[0x20];
9369
9370         u8         reserved_at_1a0[0x60];
9371 };
9372
9373 struct mlx5_ifc_mlcr_reg_bits {
9374         u8         reserved_at_0[0x8];
9375         u8         local_port[0x8];
9376         u8         reserved_at_10[0x20];
9377
9378         u8         beacon_duration[0x10];
9379         u8         reserved_at_40[0x10];
9380
9381         u8         beacon_remain[0x10];
9382 };
9383
9384 struct mlx5_ifc_ptas_reg_bits {
9385         u8         reserved_at_0[0x20];
9386
9387         u8         algorithm_options[0x10];
9388         u8         reserved_at_30[0x4];
9389         u8         repetitions_mode[0x4];
9390         u8         num_of_repetitions[0x8];
9391
9392         u8         grade_version[0x8];
9393         u8         height_grade_type[0x4];
9394         u8         phase_grade_type[0x4];
9395         u8         height_grade_weight[0x8];
9396         u8         phase_grade_weight[0x8];
9397
9398         u8         gisim_measure_bits[0x10];
9399         u8         adaptive_tap_measure_bits[0x10];
9400
9401         u8         ber_bath_high_error_threshold[0x10];
9402         u8         ber_bath_mid_error_threshold[0x10];
9403
9404         u8         ber_bath_low_error_threshold[0x10];
9405         u8         one_ratio_high_threshold[0x10];
9406
9407         u8         one_ratio_high_mid_threshold[0x10];
9408         u8         one_ratio_low_mid_threshold[0x10];
9409
9410         u8         one_ratio_low_threshold[0x10];
9411         u8         ndeo_error_threshold[0x10];
9412
9413         u8         mixer_offset_step_size[0x10];
9414         u8         reserved_at_110[0x8];
9415         u8         mix90_phase_for_voltage_bath[0x8];
9416
9417         u8         mixer_offset_start[0x10];
9418         u8         mixer_offset_end[0x10];
9419
9420         u8         reserved_at_140[0x15];
9421         u8         ber_test_time[0xb];
9422 };
9423
9424 struct mlx5_ifc_pspa_reg_bits {
9425         u8         swid[0x8];
9426         u8         local_port[0x8];
9427         u8         sub_port[0x8];
9428         u8         reserved_at_18[0x8];
9429
9430         u8         reserved_at_20[0x20];
9431 };
9432
9433 struct mlx5_ifc_pqdr_reg_bits {
9434         u8         reserved_at_0[0x8];
9435         u8         local_port[0x8];
9436         u8         reserved_at_10[0x5];
9437         u8         prio[0x3];
9438         u8         reserved_at_18[0x6];
9439         u8         mode[0x2];
9440
9441         u8         reserved_at_20[0x20];
9442
9443         u8         reserved_at_40[0x10];
9444         u8         min_threshold[0x10];
9445
9446         u8         reserved_at_60[0x10];
9447         u8         max_threshold[0x10];
9448
9449         u8         reserved_at_80[0x10];
9450         u8         mark_probability_denominator[0x10];
9451
9452         u8         reserved_at_a0[0x60];
9453 };
9454
9455 struct mlx5_ifc_ppsc_reg_bits {
9456         u8         reserved_at_0[0x8];
9457         u8         local_port[0x8];
9458         u8         reserved_at_10[0x10];
9459
9460         u8         reserved_at_20[0x60];
9461
9462         u8         reserved_at_80[0x1c];
9463         u8         wrps_admin[0x4];
9464
9465         u8         reserved_at_a0[0x1c];
9466         u8         wrps_status[0x4];
9467
9468         u8         reserved_at_c0[0x8];
9469         u8         up_threshold[0x8];
9470         u8         reserved_at_d0[0x8];
9471         u8         down_threshold[0x8];
9472
9473         u8         reserved_at_e0[0x20];
9474
9475         u8         reserved_at_100[0x1c];
9476         u8         srps_admin[0x4];
9477
9478         u8         reserved_at_120[0x1c];
9479         u8         srps_status[0x4];
9480
9481         u8         reserved_at_140[0x40];
9482 };
9483
9484 struct mlx5_ifc_pplr_reg_bits {
9485         u8         reserved_at_0[0x8];
9486         u8         local_port[0x8];
9487         u8         reserved_at_10[0x10];
9488
9489         u8         reserved_at_20[0x8];
9490         u8         lb_cap[0x8];
9491         u8         reserved_at_30[0x8];
9492         u8         lb_en[0x8];
9493 };
9494
9495 struct mlx5_ifc_pplm_reg_bits {
9496         u8         reserved_at_0[0x8];
9497         u8         local_port[0x8];
9498         u8         reserved_at_10[0x10];
9499
9500         u8         reserved_at_20[0x20];
9501
9502         u8         port_profile_mode[0x8];
9503         u8         static_port_profile[0x8];
9504         u8         active_port_profile[0x8];
9505         u8         reserved_at_58[0x8];
9506
9507         u8         retransmission_active[0x8];
9508         u8         fec_mode_active[0x18];
9509
9510         u8         rs_fec_correction_bypass_cap[0x4];
9511         u8         reserved_at_84[0x8];
9512         u8         fec_override_cap_56g[0x4];
9513         u8         fec_override_cap_100g[0x4];
9514         u8         fec_override_cap_50g[0x4];
9515         u8         fec_override_cap_25g[0x4];
9516         u8         fec_override_cap_10g_40g[0x4];
9517
9518         u8         rs_fec_correction_bypass_admin[0x4];
9519         u8         reserved_at_a4[0x8];
9520         u8         fec_override_admin_56g[0x4];
9521         u8         fec_override_admin_100g[0x4];
9522         u8         fec_override_admin_50g[0x4];
9523         u8         fec_override_admin_25g[0x4];
9524         u8         fec_override_admin_10g_40g[0x4];
9525
9526         u8         fec_override_cap_400g_8x[0x10];
9527         u8         fec_override_cap_200g_4x[0x10];
9528
9529         u8         fec_override_cap_100g_2x[0x10];
9530         u8         fec_override_cap_50g_1x[0x10];
9531
9532         u8         fec_override_admin_400g_8x[0x10];
9533         u8         fec_override_admin_200g_4x[0x10];
9534
9535         u8         fec_override_admin_100g_2x[0x10];
9536         u8         fec_override_admin_50g_1x[0x10];
9537
9538         u8         reserved_at_140[0x140];
9539 };
9540
9541 struct mlx5_ifc_ppcnt_reg_bits {
9542         u8         swid[0x8];
9543         u8         local_port[0x8];
9544         u8         pnat[0x2];
9545         u8         reserved_at_12[0x8];
9546         u8         grp[0x6];
9547
9548         u8         clr[0x1];
9549         u8         reserved_at_21[0x1c];
9550         u8         prio_tc[0x3];
9551
9552         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9553 };
9554
9555 struct mlx5_ifc_mpein_reg_bits {
9556         u8         reserved_at_0[0x2];
9557         u8         depth[0x6];
9558         u8         pcie_index[0x8];
9559         u8         node[0x8];
9560         u8         reserved_at_18[0x8];
9561
9562         u8         capability_mask[0x20];
9563
9564         u8         reserved_at_40[0x8];
9565         u8         link_width_enabled[0x8];
9566         u8         link_speed_enabled[0x10];
9567
9568         u8         lane0_physical_position[0x8];
9569         u8         link_width_active[0x8];
9570         u8         link_speed_active[0x10];
9571
9572         u8         num_of_pfs[0x10];
9573         u8         num_of_vfs[0x10];
9574
9575         u8         bdf0[0x10];
9576         u8         reserved_at_b0[0x10];
9577
9578         u8         max_read_request_size[0x4];
9579         u8         max_payload_size[0x4];
9580         u8         reserved_at_c8[0x5];
9581         u8         pwr_status[0x3];
9582         u8         port_type[0x4];
9583         u8         reserved_at_d4[0xb];
9584         u8         lane_reversal[0x1];
9585
9586         u8         reserved_at_e0[0x14];
9587         u8         pci_power[0xc];
9588
9589         u8         reserved_at_100[0x20];
9590
9591         u8         device_status[0x10];
9592         u8         port_state[0x8];
9593         u8         reserved_at_138[0x8];
9594
9595         u8         reserved_at_140[0x10];
9596         u8         receiver_detect_result[0x10];
9597
9598         u8         reserved_at_160[0x20];
9599 };
9600
9601 struct mlx5_ifc_mpcnt_reg_bits {
9602         u8         reserved_at_0[0x8];
9603         u8         pcie_index[0x8];
9604         u8         reserved_at_10[0xa];
9605         u8         grp[0x6];
9606
9607         u8         clr[0x1];
9608         u8         reserved_at_21[0x1f];
9609
9610         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
9611 };
9612
9613 struct mlx5_ifc_ppad_reg_bits {
9614         u8         reserved_at_0[0x3];
9615         u8         single_mac[0x1];
9616         u8         reserved_at_4[0x4];
9617         u8         local_port[0x8];
9618         u8         mac_47_32[0x10];
9619
9620         u8         mac_31_0[0x20];
9621
9622         u8         reserved_at_40[0x40];
9623 };
9624
9625 struct mlx5_ifc_pmtu_reg_bits {
9626         u8         reserved_at_0[0x8];
9627         u8         local_port[0x8];
9628         u8         reserved_at_10[0x10];
9629
9630         u8         max_mtu[0x10];
9631         u8         reserved_at_30[0x10];
9632
9633         u8         admin_mtu[0x10];
9634         u8         reserved_at_50[0x10];
9635
9636         u8         oper_mtu[0x10];
9637         u8         reserved_at_70[0x10];
9638 };
9639
9640 struct mlx5_ifc_pmpr_reg_bits {
9641         u8         reserved_at_0[0x8];
9642         u8         module[0x8];
9643         u8         reserved_at_10[0x10];
9644
9645         u8         reserved_at_20[0x18];
9646         u8         attenuation_5g[0x8];
9647
9648         u8         reserved_at_40[0x18];
9649         u8         attenuation_7g[0x8];
9650
9651         u8         reserved_at_60[0x18];
9652         u8         attenuation_12g[0x8];
9653 };
9654
9655 struct mlx5_ifc_pmpe_reg_bits {
9656         u8         reserved_at_0[0x8];
9657         u8         module[0x8];
9658         u8         reserved_at_10[0xc];
9659         u8         module_status[0x4];
9660
9661         u8         reserved_at_20[0x60];
9662 };
9663
9664 struct mlx5_ifc_pmpc_reg_bits {
9665         u8         module_state_updated[32][0x8];
9666 };
9667
9668 struct mlx5_ifc_pmlpn_reg_bits {
9669         u8         reserved_at_0[0x4];
9670         u8         mlpn_status[0x4];
9671         u8         local_port[0x8];
9672         u8         reserved_at_10[0x10];
9673
9674         u8         e[0x1];
9675         u8         reserved_at_21[0x1f];
9676 };
9677
9678 struct mlx5_ifc_pmlp_reg_bits {
9679         u8         rxtx[0x1];
9680         u8         reserved_at_1[0x7];
9681         u8         local_port[0x8];
9682         u8         reserved_at_10[0x8];
9683         u8         width[0x8];
9684
9685         u8         lane0_module_mapping[0x20];
9686
9687         u8         lane1_module_mapping[0x20];
9688
9689         u8         lane2_module_mapping[0x20];
9690
9691         u8         lane3_module_mapping[0x20];
9692
9693         u8         reserved_at_a0[0x160];
9694 };
9695
9696 struct mlx5_ifc_pmaos_reg_bits {
9697         u8         reserved_at_0[0x8];
9698         u8         module[0x8];
9699         u8         reserved_at_10[0x4];
9700         u8         admin_status[0x4];
9701         u8         reserved_at_18[0x4];
9702         u8         oper_status[0x4];
9703
9704         u8         ase[0x1];
9705         u8         ee[0x1];
9706         u8         reserved_at_22[0x1c];
9707         u8         e[0x2];
9708
9709         u8         reserved_at_40[0x40];
9710 };
9711
9712 struct mlx5_ifc_plpc_reg_bits {
9713         u8         reserved_at_0[0x4];
9714         u8         profile_id[0xc];
9715         u8         reserved_at_10[0x4];
9716         u8         proto_mask[0x4];
9717         u8         reserved_at_18[0x8];
9718
9719         u8         reserved_at_20[0x10];
9720         u8         lane_speed[0x10];
9721
9722         u8         reserved_at_40[0x17];
9723         u8         lpbf[0x1];
9724         u8         fec_mode_policy[0x8];
9725
9726         u8         retransmission_capability[0x8];
9727         u8         fec_mode_capability[0x18];
9728
9729         u8         retransmission_support_admin[0x8];
9730         u8         fec_mode_support_admin[0x18];
9731
9732         u8         retransmission_request_admin[0x8];
9733         u8         fec_mode_request_admin[0x18];
9734
9735         u8         reserved_at_c0[0x80];
9736 };
9737
9738 struct mlx5_ifc_plib_reg_bits {
9739         u8         reserved_at_0[0x8];
9740         u8         local_port[0x8];
9741         u8         reserved_at_10[0x8];
9742         u8         ib_port[0x8];
9743
9744         u8         reserved_at_20[0x60];
9745 };
9746
9747 struct mlx5_ifc_plbf_reg_bits {
9748         u8         reserved_at_0[0x8];
9749         u8         local_port[0x8];
9750         u8         reserved_at_10[0xd];
9751         u8         lbf_mode[0x3];
9752
9753         u8         reserved_at_20[0x20];
9754 };
9755
9756 struct mlx5_ifc_pipg_reg_bits {
9757         u8         reserved_at_0[0x8];
9758         u8         local_port[0x8];
9759         u8         reserved_at_10[0x10];
9760
9761         u8         dic[0x1];
9762         u8         reserved_at_21[0x19];
9763         u8         ipg[0x4];
9764         u8         reserved_at_3e[0x2];
9765 };
9766
9767 struct mlx5_ifc_pifr_reg_bits {
9768         u8         reserved_at_0[0x8];
9769         u8         local_port[0x8];
9770         u8         reserved_at_10[0x10];
9771
9772         u8         reserved_at_20[0xe0];
9773
9774         u8         port_filter[8][0x20];
9775
9776         u8         port_filter_update_en[8][0x20];
9777 };
9778
9779 struct mlx5_ifc_pfcc_reg_bits {
9780         u8         reserved_at_0[0x8];
9781         u8         local_port[0x8];
9782         u8         reserved_at_10[0xb];
9783         u8         ppan_mask_n[0x1];
9784         u8         minor_stall_mask[0x1];
9785         u8         critical_stall_mask[0x1];
9786         u8         reserved_at_1e[0x2];
9787
9788         u8         ppan[0x4];
9789         u8         reserved_at_24[0x4];
9790         u8         prio_mask_tx[0x8];
9791         u8         reserved_at_30[0x8];
9792         u8         prio_mask_rx[0x8];
9793
9794         u8         pptx[0x1];
9795         u8         aptx[0x1];
9796         u8         pptx_mask_n[0x1];
9797         u8         reserved_at_43[0x5];
9798         u8         pfctx[0x8];
9799         u8         reserved_at_50[0x10];
9800
9801         u8         pprx[0x1];
9802         u8         aprx[0x1];
9803         u8         pprx_mask_n[0x1];
9804         u8         reserved_at_63[0x5];
9805         u8         pfcrx[0x8];
9806         u8         reserved_at_70[0x10];
9807
9808         u8         device_stall_minor_watermark[0x10];
9809         u8         device_stall_critical_watermark[0x10];
9810
9811         u8         reserved_at_a0[0x60];
9812 };
9813
9814 struct mlx5_ifc_pelc_reg_bits {
9815         u8         op[0x4];
9816         u8         reserved_at_4[0x4];
9817         u8         local_port[0x8];
9818         u8         reserved_at_10[0x10];
9819
9820         u8         op_admin[0x8];
9821         u8         op_capability[0x8];
9822         u8         op_request[0x8];
9823         u8         op_active[0x8];
9824
9825         u8         admin[0x40];
9826
9827         u8         capability[0x40];
9828
9829         u8         request[0x40];
9830
9831         u8         active[0x40];
9832
9833         u8         reserved_at_140[0x80];
9834 };
9835
9836 struct mlx5_ifc_peir_reg_bits {
9837         u8         reserved_at_0[0x8];
9838         u8         local_port[0x8];
9839         u8         reserved_at_10[0x10];
9840
9841         u8         reserved_at_20[0xc];
9842         u8         error_count[0x4];
9843         u8         reserved_at_30[0x10];
9844
9845         u8         reserved_at_40[0xc];
9846         u8         lane[0x4];
9847         u8         reserved_at_50[0x8];
9848         u8         error_type[0x8];
9849 };
9850
9851 struct mlx5_ifc_mpegc_reg_bits {
9852         u8         reserved_at_0[0x30];
9853         u8         field_select[0x10];
9854
9855         u8         tx_overflow_sense[0x1];
9856         u8         mark_cqe[0x1];
9857         u8         mark_cnp[0x1];
9858         u8         reserved_at_43[0x1b];
9859         u8         tx_lossy_overflow_oper[0x2];
9860
9861         u8         reserved_at_60[0x100];
9862 };
9863
9864 enum {
9865         MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
9866         MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
9867         MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
9868 };
9869
9870 struct mlx5_ifc_mtutc_reg_bits {
9871         u8         reserved_at_0[0x1c];
9872         u8         operation[0x4];
9873
9874         u8         freq_adjustment[0x20];
9875
9876         u8         reserved_at_40[0x40];
9877
9878         u8         utc_sec[0x20];
9879
9880         u8         reserved_at_a0[0x2];
9881         u8         utc_nsec[0x1e];
9882
9883         u8         time_adjustment[0x20];
9884 };
9885
9886 struct mlx5_ifc_pcam_enhanced_features_bits {
9887         u8         reserved_at_0[0x68];
9888         u8         fec_50G_per_lane_in_pplm[0x1];
9889         u8         reserved_at_69[0x4];
9890         u8         rx_icrc_encapsulated_counter[0x1];
9891         u8         reserved_at_6e[0x4];
9892         u8         ptys_extended_ethernet[0x1];
9893         u8         reserved_at_73[0x3];
9894         u8         pfcc_mask[0x1];
9895         u8         reserved_at_77[0x3];
9896         u8         per_lane_error_counters[0x1];
9897         u8         rx_buffer_fullness_counters[0x1];
9898         u8         ptys_connector_type[0x1];
9899         u8         reserved_at_7d[0x1];
9900         u8         ppcnt_discard_group[0x1];
9901         u8         ppcnt_statistical_group[0x1];
9902 };
9903
9904 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9905         u8         port_access_reg_cap_mask_127_to_96[0x20];
9906         u8         port_access_reg_cap_mask_95_to_64[0x20];
9907
9908         u8         port_access_reg_cap_mask_63_to_36[0x1c];
9909         u8         pplm[0x1];
9910         u8         port_access_reg_cap_mask_34_to_32[0x3];
9911
9912         u8         port_access_reg_cap_mask_31_to_13[0x13];
9913         u8         pbmc[0x1];
9914         u8         pptb[0x1];
9915         u8         port_access_reg_cap_mask_10_to_09[0x2];
9916         u8         ppcnt[0x1];
9917         u8         port_access_reg_cap_mask_07_to_00[0x8];
9918 };
9919
9920 struct mlx5_ifc_pcam_reg_bits {
9921         u8         reserved_at_0[0x8];
9922         u8         feature_group[0x8];
9923         u8         reserved_at_10[0x8];
9924         u8         access_reg_group[0x8];
9925
9926         u8         reserved_at_20[0x20];
9927
9928         union {
9929                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
9930                 u8         reserved_at_0[0x80];
9931         } port_access_reg_cap_mask;
9932
9933         u8         reserved_at_c0[0x80];
9934
9935         union {
9936                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9937                 u8         reserved_at_0[0x80];
9938         } feature_cap_mask;
9939
9940         u8         reserved_at_1c0[0xc0];
9941 };
9942
9943 struct mlx5_ifc_mcam_enhanced_features_bits {
9944         u8         reserved_at_0[0x5d];
9945         u8         mcia_32dwords[0x1];
9946         u8         out_pulse_duration_ns[0x1];
9947         u8         npps_period[0x1];
9948         u8         reserved_at_60[0xa];
9949         u8         reset_state[0x1];
9950         u8         ptpcyc2realtime_modify[0x1];
9951         u8         reserved_at_6c[0x2];
9952         u8         pci_status_and_power[0x1];
9953         u8         reserved_at_6f[0x5];
9954         u8         mark_tx_action_cnp[0x1];
9955         u8         mark_tx_action_cqe[0x1];
9956         u8         dynamic_tx_overflow[0x1];
9957         u8         reserved_at_77[0x4];
9958         u8         pcie_outbound_stalled[0x1];
9959         u8         tx_overflow_buffer_pkt[0x1];
9960         u8         mtpps_enh_out_per_adj[0x1];
9961         u8         mtpps_fs[0x1];
9962         u8         pcie_performance_group[0x1];
9963 };
9964
9965 struct mlx5_ifc_mcam_access_reg_bits {
9966         u8         reserved_at_0[0x1c];
9967         u8         mcda[0x1];
9968         u8         mcc[0x1];
9969         u8         mcqi[0x1];
9970         u8         mcqs[0x1];
9971
9972         u8         regs_95_to_87[0x9];
9973         u8         mpegc[0x1];
9974         u8         mtutc[0x1];
9975         u8         regs_84_to_68[0x11];
9976         u8         tracer_registers[0x4];
9977
9978         u8         regs_63_to_46[0x12];
9979         u8         mrtc[0x1];
9980         u8         regs_44_to_32[0xd];
9981
9982         u8         regs_31_to_0[0x20];
9983 };
9984
9985 struct mlx5_ifc_mcam_access_reg_bits1 {
9986         u8         regs_127_to_96[0x20];
9987
9988         u8         regs_95_to_64[0x20];
9989
9990         u8         regs_63_to_32[0x20];
9991
9992         u8         regs_31_to_0[0x20];
9993 };
9994
9995 struct mlx5_ifc_mcam_access_reg_bits2 {
9996         u8         regs_127_to_99[0x1d];
9997         u8         mirc[0x1];
9998         u8         regs_97_to_96[0x2];
9999
10000         u8         regs_95_to_64[0x20];
10001
10002         u8         regs_63_to_32[0x20];
10003
10004         u8         regs_31_to_0[0x20];
10005 };
10006
10007 struct mlx5_ifc_mcam_reg_bits {
10008         u8         reserved_at_0[0x8];
10009         u8         feature_group[0x8];
10010         u8         reserved_at_10[0x8];
10011         u8         access_reg_group[0x8];
10012
10013         u8         reserved_at_20[0x20];
10014
10015         union {
10016                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
10017                 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
10018                 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
10019                 u8         reserved_at_0[0x80];
10020         } mng_access_reg_cap_mask;
10021
10022         u8         reserved_at_c0[0x80];
10023
10024         union {
10025                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
10026                 u8         reserved_at_0[0x80];
10027         } mng_feature_cap_mask;
10028
10029         u8         reserved_at_1c0[0x80];
10030 };
10031
10032 struct mlx5_ifc_qcam_access_reg_cap_mask {
10033         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
10034         u8         qpdpm[0x1];
10035         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
10036         u8         qdpm[0x1];
10037         u8         qpts[0x1];
10038         u8         qcap[0x1];
10039         u8         qcam_access_reg_cap_mask_0[0x1];
10040 };
10041
10042 struct mlx5_ifc_qcam_qos_feature_cap_mask {
10043         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
10044         u8         qpts_trust_both[0x1];
10045 };
10046
10047 struct mlx5_ifc_qcam_reg_bits {
10048         u8         reserved_at_0[0x8];
10049         u8         feature_group[0x8];
10050         u8         reserved_at_10[0x8];
10051         u8         access_reg_group[0x8];
10052         u8         reserved_at_20[0x20];
10053
10054         union {
10055                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
10056                 u8  reserved_at_0[0x80];
10057         } qos_access_reg_cap_mask;
10058
10059         u8         reserved_at_c0[0x80];
10060
10061         union {
10062                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
10063                 u8  reserved_at_0[0x80];
10064         } qos_feature_cap_mask;
10065
10066         u8         reserved_at_1c0[0x80];
10067 };
10068
10069 struct mlx5_ifc_core_dump_reg_bits {
10070         u8         reserved_at_0[0x18];
10071         u8         core_dump_type[0x8];
10072
10073         u8         reserved_at_20[0x30];
10074         u8         vhca_id[0x10];
10075
10076         u8         reserved_at_60[0x8];
10077         u8         qpn[0x18];
10078         u8         reserved_at_80[0x180];
10079 };
10080
10081 struct mlx5_ifc_pcap_reg_bits {
10082         u8         reserved_at_0[0x8];
10083         u8         local_port[0x8];
10084         u8         reserved_at_10[0x10];
10085
10086         u8         port_capability_mask[4][0x20];
10087 };
10088
10089 struct mlx5_ifc_paos_reg_bits {
10090         u8         swid[0x8];
10091         u8         local_port[0x8];
10092         u8         reserved_at_10[0x4];
10093         u8         admin_status[0x4];
10094         u8         reserved_at_18[0x4];
10095         u8         oper_status[0x4];
10096
10097         u8         ase[0x1];
10098         u8         ee[0x1];
10099         u8         reserved_at_22[0x1c];
10100         u8         e[0x2];
10101
10102         u8         reserved_at_40[0x40];
10103 };
10104
10105 struct mlx5_ifc_pamp_reg_bits {
10106         u8         reserved_at_0[0x8];
10107         u8         opamp_group[0x8];
10108         u8         reserved_at_10[0xc];
10109         u8         opamp_group_type[0x4];
10110
10111         u8         start_index[0x10];
10112         u8         reserved_at_30[0x4];
10113         u8         num_of_indices[0xc];
10114
10115         u8         index_data[18][0x10];
10116 };
10117
10118 struct mlx5_ifc_pcmr_reg_bits {
10119         u8         reserved_at_0[0x8];
10120         u8         local_port[0x8];
10121         u8         reserved_at_10[0x10];
10122
10123         u8         entropy_force_cap[0x1];
10124         u8         entropy_calc_cap[0x1];
10125         u8         entropy_gre_calc_cap[0x1];
10126         u8         reserved_at_23[0xf];
10127         u8         rx_ts_over_crc_cap[0x1];
10128         u8         reserved_at_33[0xb];
10129         u8         fcs_cap[0x1];
10130         u8         reserved_at_3f[0x1];
10131
10132         u8         entropy_force[0x1];
10133         u8         entropy_calc[0x1];
10134         u8         entropy_gre_calc[0x1];
10135         u8         reserved_at_43[0xf];
10136         u8         rx_ts_over_crc[0x1];
10137         u8         reserved_at_53[0xb];
10138         u8         fcs_chk[0x1];
10139         u8         reserved_at_5f[0x1];
10140 };
10141
10142 struct mlx5_ifc_lane_2_module_mapping_bits {
10143         u8         reserved_at_0[0x4];
10144         u8         rx_lane[0x4];
10145         u8         reserved_at_8[0x4];
10146         u8         tx_lane[0x4];
10147         u8         reserved_at_10[0x8];
10148         u8         module[0x8];
10149 };
10150
10151 struct mlx5_ifc_bufferx_reg_bits {
10152         u8         reserved_at_0[0x6];
10153         u8         lossy[0x1];
10154         u8         epsb[0x1];
10155         u8         reserved_at_8[0x8];
10156         u8         size[0x10];
10157
10158         u8         xoff_threshold[0x10];
10159         u8         xon_threshold[0x10];
10160 };
10161
10162 struct mlx5_ifc_set_node_in_bits {
10163         u8         node_description[64][0x8];
10164 };
10165
10166 struct mlx5_ifc_register_power_settings_bits {
10167         u8         reserved_at_0[0x18];
10168         u8         power_settings_level[0x8];
10169
10170         u8         reserved_at_20[0x60];
10171 };
10172
10173 struct mlx5_ifc_register_host_endianness_bits {
10174         u8         he[0x1];
10175         u8         reserved_at_1[0x1f];
10176
10177         u8         reserved_at_20[0x60];
10178 };
10179
10180 struct mlx5_ifc_umr_pointer_desc_argument_bits {
10181         u8         reserved_at_0[0x20];
10182
10183         u8         mkey[0x20];
10184
10185         u8         addressh_63_32[0x20];
10186
10187         u8         addressl_31_0[0x20];
10188 };
10189
10190 struct mlx5_ifc_ud_adrs_vector_bits {
10191         u8         dc_key[0x40];
10192
10193         u8         ext[0x1];
10194         u8         reserved_at_41[0x7];
10195         u8         destination_qp_dct[0x18];
10196
10197         u8         static_rate[0x4];
10198         u8         sl_eth_prio[0x4];
10199         u8         fl[0x1];
10200         u8         mlid[0x7];
10201         u8         rlid_udp_sport[0x10];
10202
10203         u8         reserved_at_80[0x20];
10204
10205         u8         rmac_47_16[0x20];
10206
10207         u8         rmac_15_0[0x10];
10208         u8         tclass[0x8];
10209         u8         hop_limit[0x8];
10210
10211         u8         reserved_at_e0[0x1];
10212         u8         grh[0x1];
10213         u8         reserved_at_e2[0x2];
10214         u8         src_addr_index[0x8];
10215         u8         flow_label[0x14];
10216
10217         u8         rgid_rip[16][0x8];
10218 };
10219
10220 struct mlx5_ifc_pages_req_event_bits {
10221         u8         reserved_at_0[0x10];
10222         u8         function_id[0x10];
10223
10224         u8         num_pages[0x20];
10225
10226         u8         reserved_at_40[0xa0];
10227 };
10228
10229 struct mlx5_ifc_eqe_bits {
10230         u8         reserved_at_0[0x8];
10231         u8         event_type[0x8];
10232         u8         reserved_at_10[0x8];
10233         u8         event_sub_type[0x8];
10234
10235         u8         reserved_at_20[0xe0];
10236
10237         union mlx5_ifc_event_auto_bits event_data;
10238
10239         u8         reserved_at_1e0[0x10];
10240         u8         signature[0x8];
10241         u8         reserved_at_1f8[0x7];
10242         u8         owner[0x1];
10243 };
10244
10245 enum {
10246         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
10247 };
10248
10249 struct mlx5_ifc_cmd_queue_entry_bits {
10250         u8         type[0x8];
10251         u8         reserved_at_8[0x18];
10252
10253         u8         input_length[0x20];
10254
10255         u8         input_mailbox_pointer_63_32[0x20];
10256
10257         u8         input_mailbox_pointer_31_9[0x17];
10258         u8         reserved_at_77[0x9];
10259
10260         u8         command_input_inline_data[16][0x8];
10261
10262         u8         command_output_inline_data[16][0x8];
10263
10264         u8         output_mailbox_pointer_63_32[0x20];
10265
10266         u8         output_mailbox_pointer_31_9[0x17];
10267         u8         reserved_at_1b7[0x9];
10268
10269         u8         output_length[0x20];
10270
10271         u8         token[0x8];
10272         u8         signature[0x8];
10273         u8         reserved_at_1f0[0x8];
10274         u8         status[0x7];
10275         u8         ownership[0x1];
10276 };
10277
10278 struct mlx5_ifc_cmd_out_bits {
10279         u8         status[0x8];
10280         u8         reserved_at_8[0x18];
10281
10282         u8         syndrome[0x20];
10283
10284         u8         command_output[0x20];
10285 };
10286
10287 struct mlx5_ifc_cmd_in_bits {
10288         u8         opcode[0x10];
10289         u8         reserved_at_10[0x10];
10290
10291         u8         reserved_at_20[0x10];
10292         u8         op_mod[0x10];
10293
10294         u8         command[][0x20];
10295 };
10296
10297 struct mlx5_ifc_cmd_if_box_bits {
10298         u8         mailbox_data[512][0x8];
10299
10300         u8         reserved_at_1000[0x180];
10301
10302         u8         next_pointer_63_32[0x20];
10303
10304         u8         next_pointer_31_10[0x16];
10305         u8         reserved_at_11b6[0xa];
10306
10307         u8         block_number[0x20];
10308
10309         u8         reserved_at_11e0[0x8];
10310         u8         token[0x8];
10311         u8         ctrl_signature[0x8];
10312         u8         signature[0x8];
10313 };
10314
10315 struct mlx5_ifc_mtt_bits {
10316         u8         ptag_63_32[0x20];
10317
10318         u8         ptag_31_8[0x18];
10319         u8         reserved_at_38[0x6];
10320         u8         wr_en[0x1];
10321         u8         rd_en[0x1];
10322 };
10323
10324 struct mlx5_ifc_query_wol_rol_out_bits {
10325         u8         status[0x8];
10326         u8         reserved_at_8[0x18];
10327
10328         u8         syndrome[0x20];
10329
10330         u8         reserved_at_40[0x10];
10331         u8         rol_mode[0x8];
10332         u8         wol_mode[0x8];
10333
10334         u8         reserved_at_60[0x20];
10335 };
10336
10337 struct mlx5_ifc_query_wol_rol_in_bits {
10338         u8         opcode[0x10];
10339         u8         reserved_at_10[0x10];
10340
10341         u8         reserved_at_20[0x10];
10342         u8         op_mod[0x10];
10343
10344         u8         reserved_at_40[0x40];
10345 };
10346
10347 struct mlx5_ifc_set_wol_rol_out_bits {
10348         u8         status[0x8];
10349         u8         reserved_at_8[0x18];
10350
10351         u8         syndrome[0x20];
10352
10353         u8         reserved_at_40[0x40];
10354 };
10355
10356 struct mlx5_ifc_set_wol_rol_in_bits {
10357         u8         opcode[0x10];
10358         u8         reserved_at_10[0x10];
10359
10360         u8         reserved_at_20[0x10];
10361         u8         op_mod[0x10];
10362
10363         u8         rol_mode_valid[0x1];
10364         u8         wol_mode_valid[0x1];
10365         u8         reserved_at_42[0xe];
10366         u8         rol_mode[0x8];
10367         u8         wol_mode[0x8];
10368
10369         u8         reserved_at_60[0x20];
10370 };
10371
10372 enum {
10373         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
10374         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
10375         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
10376 };
10377
10378 enum {
10379         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
10380         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
10381         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
10382 };
10383
10384 enum {
10385         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
10386         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
10387         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
10388         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
10389         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
10390         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
10391         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
10392         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
10393         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
10394         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
10395         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
10396 };
10397
10398 struct mlx5_ifc_initial_seg_bits {
10399         u8         fw_rev_minor[0x10];
10400         u8         fw_rev_major[0x10];
10401
10402         u8         cmd_interface_rev[0x10];
10403         u8         fw_rev_subminor[0x10];
10404
10405         u8         reserved_at_40[0x40];
10406
10407         u8         cmdq_phy_addr_63_32[0x20];
10408
10409         u8         cmdq_phy_addr_31_12[0x14];
10410         u8         reserved_at_b4[0x2];
10411         u8         nic_interface[0x2];
10412         u8         log_cmdq_size[0x4];
10413         u8         log_cmdq_stride[0x4];
10414
10415         u8         command_doorbell_vector[0x20];
10416
10417         u8         reserved_at_e0[0xf00];
10418
10419         u8         initializing[0x1];
10420         u8         reserved_at_fe1[0x4];
10421         u8         nic_interface_supported[0x3];
10422         u8         embedded_cpu[0x1];
10423         u8         reserved_at_fe9[0x17];
10424
10425         struct mlx5_ifc_health_buffer_bits health_buffer;
10426
10427         u8         no_dram_nic_offset[0x20];
10428
10429         u8         reserved_at_1220[0x6e40];
10430
10431         u8         reserved_at_8060[0x1f];
10432         u8         clear_int[0x1];
10433
10434         u8         health_syndrome[0x8];
10435         u8         health_counter[0x18];
10436
10437         u8         reserved_at_80a0[0x17fc0];
10438 };
10439
10440 struct mlx5_ifc_mtpps_reg_bits {
10441         u8         reserved_at_0[0xc];
10442         u8         cap_number_of_pps_pins[0x4];
10443         u8         reserved_at_10[0x4];
10444         u8         cap_max_num_of_pps_in_pins[0x4];
10445         u8         reserved_at_18[0x4];
10446         u8         cap_max_num_of_pps_out_pins[0x4];
10447
10448         u8         reserved_at_20[0x13];
10449         u8         cap_log_min_npps_period[0x5];
10450         u8         reserved_at_38[0x3];
10451         u8         cap_log_min_out_pulse_duration_ns[0x5];
10452
10453         u8         reserved_at_40[0x4];
10454         u8         cap_pin_3_mode[0x4];
10455         u8         reserved_at_48[0x4];
10456         u8         cap_pin_2_mode[0x4];
10457         u8         reserved_at_50[0x4];
10458         u8         cap_pin_1_mode[0x4];
10459         u8         reserved_at_58[0x4];
10460         u8         cap_pin_0_mode[0x4];
10461
10462         u8         reserved_at_60[0x4];
10463         u8         cap_pin_7_mode[0x4];
10464         u8         reserved_at_68[0x4];
10465         u8         cap_pin_6_mode[0x4];
10466         u8         reserved_at_70[0x4];
10467         u8         cap_pin_5_mode[0x4];
10468         u8         reserved_at_78[0x4];
10469         u8         cap_pin_4_mode[0x4];
10470
10471         u8         field_select[0x20];
10472         u8         reserved_at_a0[0x20];
10473
10474         u8         npps_period[0x40];
10475
10476         u8         enable[0x1];
10477         u8         reserved_at_101[0xb];
10478         u8         pattern[0x4];
10479         u8         reserved_at_110[0x4];
10480         u8         pin_mode[0x4];
10481         u8         pin[0x8];
10482
10483         u8         reserved_at_120[0x2];
10484         u8         out_pulse_duration_ns[0x1e];
10485
10486         u8         time_stamp[0x40];
10487
10488         u8         out_pulse_duration[0x10];
10489         u8         out_periodic_adjustment[0x10];
10490         u8         enhanced_out_periodic_adjustment[0x20];
10491
10492         u8         reserved_at_1c0[0x20];
10493 };
10494
10495 struct mlx5_ifc_mtppse_reg_bits {
10496         u8         reserved_at_0[0x18];
10497         u8         pin[0x8];
10498         u8         event_arm[0x1];
10499         u8         reserved_at_21[0x1b];
10500         u8         event_generation_mode[0x4];
10501         u8         reserved_at_40[0x40];
10502 };
10503
10504 struct mlx5_ifc_mcqs_reg_bits {
10505         u8         last_index_flag[0x1];
10506         u8         reserved_at_1[0x7];
10507         u8         fw_device[0x8];
10508         u8         component_index[0x10];
10509
10510         u8         reserved_at_20[0x10];
10511         u8         identifier[0x10];
10512
10513         u8         reserved_at_40[0x17];
10514         u8         component_status[0x5];
10515         u8         component_update_state[0x4];
10516
10517         u8         last_update_state_changer_type[0x4];
10518         u8         last_update_state_changer_host_id[0x4];
10519         u8         reserved_at_68[0x18];
10520 };
10521
10522 struct mlx5_ifc_mcqi_cap_bits {
10523         u8         supported_info_bitmask[0x20];
10524
10525         u8         component_size[0x20];
10526
10527         u8         max_component_size[0x20];
10528
10529         u8         log_mcda_word_size[0x4];
10530         u8         reserved_at_64[0xc];
10531         u8         mcda_max_write_size[0x10];
10532
10533         u8         rd_en[0x1];
10534         u8         reserved_at_81[0x1];
10535         u8         match_chip_id[0x1];
10536         u8         match_psid[0x1];
10537         u8         check_user_timestamp[0x1];
10538         u8         match_base_guid_mac[0x1];
10539         u8         reserved_at_86[0x1a];
10540 };
10541
10542 struct mlx5_ifc_mcqi_version_bits {
10543         u8         reserved_at_0[0x2];
10544         u8         build_time_valid[0x1];
10545         u8         user_defined_time_valid[0x1];
10546         u8         reserved_at_4[0x14];
10547         u8         version_string_length[0x8];
10548
10549         u8         version[0x20];
10550
10551         u8         build_time[0x40];
10552
10553         u8         user_defined_time[0x40];
10554
10555         u8         build_tool_version[0x20];
10556
10557         u8         reserved_at_e0[0x20];
10558
10559         u8         version_string[92][0x8];
10560 };
10561
10562 struct mlx5_ifc_mcqi_activation_method_bits {
10563         u8         pending_server_ac_power_cycle[0x1];
10564         u8         pending_server_dc_power_cycle[0x1];
10565         u8         pending_server_reboot[0x1];
10566         u8         pending_fw_reset[0x1];
10567         u8         auto_activate[0x1];
10568         u8         all_hosts_sync[0x1];
10569         u8         device_hw_reset[0x1];
10570         u8         reserved_at_7[0x19];
10571 };
10572
10573 union mlx5_ifc_mcqi_reg_data_bits {
10574         struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
10575         struct mlx5_ifc_mcqi_version_bits           mcqi_version;
10576         struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
10577 };
10578
10579 struct mlx5_ifc_mcqi_reg_bits {
10580         u8         read_pending_component[0x1];
10581         u8         reserved_at_1[0xf];
10582         u8         component_index[0x10];
10583
10584         u8         reserved_at_20[0x20];
10585
10586         u8         reserved_at_40[0x1b];
10587         u8         info_type[0x5];
10588
10589         u8         info_size[0x20];
10590
10591         u8         offset[0x20];
10592
10593         u8         reserved_at_a0[0x10];
10594         u8         data_size[0x10];
10595
10596         union mlx5_ifc_mcqi_reg_data_bits data[];
10597 };
10598
10599 struct mlx5_ifc_mcc_reg_bits {
10600         u8         reserved_at_0[0x4];
10601         u8         time_elapsed_since_last_cmd[0xc];
10602         u8         reserved_at_10[0x8];
10603         u8         instruction[0x8];
10604
10605         u8         reserved_at_20[0x10];
10606         u8         component_index[0x10];
10607
10608         u8         reserved_at_40[0x8];
10609         u8         update_handle[0x18];
10610
10611         u8         handle_owner_type[0x4];
10612         u8         handle_owner_host_id[0x4];
10613         u8         reserved_at_68[0x1];
10614         u8         control_progress[0x7];
10615         u8         error_code[0x8];
10616         u8         reserved_at_78[0x4];
10617         u8         control_state[0x4];
10618
10619         u8         component_size[0x20];
10620
10621         u8         reserved_at_a0[0x60];
10622 };
10623
10624 struct mlx5_ifc_mcda_reg_bits {
10625         u8         reserved_at_0[0x8];
10626         u8         update_handle[0x18];
10627
10628         u8         offset[0x20];
10629
10630         u8         reserved_at_40[0x10];
10631         u8         size[0x10];
10632
10633         u8         reserved_at_60[0x20];
10634
10635         u8         data[][0x20];
10636 };
10637
10638 enum {
10639         MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
10640         MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
10641         MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
10642         MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3,
10643         MLX5_MFRL_REG_RESET_STATE_NACK = 4,
10644 };
10645
10646 enum {
10647         MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
10648         MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
10649 };
10650
10651 enum {
10652         MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
10653         MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
10654         MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
10655 };
10656
10657 struct mlx5_ifc_mfrl_reg_bits {
10658         u8         reserved_at_0[0x20];
10659
10660         u8         reserved_at_20[0x2];
10661         u8         pci_sync_for_fw_update_start[0x1];
10662         u8         pci_sync_for_fw_update_resp[0x2];
10663         u8         rst_type_sel[0x3];
10664         u8         reserved_at_28[0x4];
10665         u8         reset_state[0x4];
10666         u8         reset_type[0x8];
10667         u8         reset_level[0x8];
10668 };
10669
10670 struct mlx5_ifc_mirc_reg_bits {
10671         u8         reserved_at_0[0x18];
10672         u8         status_code[0x8];
10673
10674         u8         reserved_at_20[0x20];
10675 };
10676
10677 struct mlx5_ifc_pddr_monitor_opcode_bits {
10678         u8         reserved_at_0[0x10];
10679         u8         monitor_opcode[0x10];
10680 };
10681
10682 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
10683         struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10684         u8         reserved_at_0[0x20];
10685 };
10686
10687 enum {
10688         /* Monitor opcodes */
10689         MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10690 };
10691
10692 struct mlx5_ifc_pddr_troubleshooting_page_bits {
10693         u8         reserved_at_0[0x10];
10694         u8         group_opcode[0x10];
10695
10696         union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
10697
10698         u8         reserved_at_40[0x20];
10699
10700         u8         status_message[59][0x20];
10701 };
10702
10703 union mlx5_ifc_pddr_reg_page_data_auto_bits {
10704         struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10705         u8         reserved_at_0[0x7c0];
10706 };
10707
10708 enum {
10709         MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
10710 };
10711
10712 struct mlx5_ifc_pddr_reg_bits {
10713         u8         reserved_at_0[0x8];
10714         u8         local_port[0x8];
10715         u8         pnat[0x2];
10716         u8         reserved_at_12[0xe];
10717
10718         u8         reserved_at_20[0x18];
10719         u8         page_select[0x8];
10720
10721         union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
10722 };
10723
10724 struct mlx5_ifc_mrtc_reg_bits {
10725         u8         time_synced[0x1];
10726         u8         reserved_at_1[0x1f];
10727
10728         u8         reserved_at_20[0x20];
10729
10730         u8         time_h[0x20];
10731
10732         u8         time_l[0x20];
10733 };
10734
10735 union mlx5_ifc_ports_control_registers_document_bits {
10736         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10737         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10738         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10739         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10740         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10741         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10742         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10743         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
10744         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
10745         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10746         struct mlx5_ifc_pamp_reg_bits pamp_reg;
10747         struct mlx5_ifc_paos_reg_bits paos_reg;
10748         struct mlx5_ifc_pcap_reg_bits pcap_reg;
10749         struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10750         struct mlx5_ifc_pddr_reg_bits pddr_reg;
10751         struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10752         struct mlx5_ifc_peir_reg_bits peir_reg;
10753         struct mlx5_ifc_pelc_reg_bits pelc_reg;
10754         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10755         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
10756         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10757         struct mlx5_ifc_pifr_reg_bits pifr_reg;
10758         struct mlx5_ifc_pipg_reg_bits pipg_reg;
10759         struct mlx5_ifc_plbf_reg_bits plbf_reg;
10760         struct mlx5_ifc_plib_reg_bits plib_reg;
10761         struct mlx5_ifc_plpc_reg_bits plpc_reg;
10762         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10763         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10764         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10765         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10766         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10767         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10768         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10769         struct mlx5_ifc_ppad_reg_bits ppad_reg;
10770         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
10771         struct mlx5_ifc_mpein_reg_bits mpein_reg;
10772         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
10773         struct mlx5_ifc_pplm_reg_bits pplm_reg;
10774         struct mlx5_ifc_pplr_reg_bits pplr_reg;
10775         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10776         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
10777         struct mlx5_ifc_pspa_reg_bits pspa_reg;
10778         struct mlx5_ifc_ptas_reg_bits ptas_reg;
10779         struct mlx5_ifc_ptys_reg_bits ptys_reg;
10780         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
10781         struct mlx5_ifc_pude_reg_bits pude_reg;
10782         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10783         struct mlx5_ifc_slrg_reg_bits slrg_reg;
10784         struct mlx5_ifc_sltp_reg_bits sltp_reg;
10785         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
10786         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
10787         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
10788         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
10789         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
10790         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
10791         struct mlx5_ifc_mcc_reg_bits mcc_reg;
10792         struct mlx5_ifc_mcda_reg_bits mcda_reg;
10793         struct mlx5_ifc_mirc_reg_bits mirc_reg;
10794         struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
10795         struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
10796         struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
10797         u8         reserved_at_0[0x60e0];
10798 };
10799
10800 union mlx5_ifc_debug_enhancements_document_bits {
10801         struct mlx5_ifc_health_buffer_bits health_buffer;
10802         u8         reserved_at_0[0x200];
10803 };
10804
10805 union mlx5_ifc_uplink_pci_interface_document_bits {
10806         struct mlx5_ifc_initial_seg_bits initial_seg;
10807         u8         reserved_at_0[0x20060];
10808 };
10809
10810 struct mlx5_ifc_set_flow_table_root_out_bits {
10811         u8         status[0x8];
10812         u8         reserved_at_8[0x18];
10813
10814         u8         syndrome[0x20];
10815
10816         u8         reserved_at_40[0x40];
10817 };
10818
10819 struct mlx5_ifc_set_flow_table_root_in_bits {
10820         u8         opcode[0x10];
10821         u8         reserved_at_10[0x10];
10822
10823         u8         reserved_at_20[0x10];
10824         u8         op_mod[0x10];
10825
10826         u8         other_vport[0x1];
10827         u8         reserved_at_41[0xf];
10828         u8         vport_number[0x10];
10829
10830         u8         reserved_at_60[0x20];
10831
10832         u8         table_type[0x8];
10833         u8         reserved_at_88[0x7];
10834         u8         table_of_other_vport[0x1];
10835         u8         table_vport_number[0x10];
10836
10837         u8         reserved_at_a0[0x8];
10838         u8         table_id[0x18];
10839
10840         u8         reserved_at_c0[0x8];
10841         u8         underlay_qpn[0x18];
10842         u8         table_eswitch_owner_vhca_id_valid[0x1];
10843         u8         reserved_at_e1[0xf];
10844         u8         table_eswitch_owner_vhca_id[0x10];
10845         u8         reserved_at_100[0x100];
10846 };
10847
10848 enum {
10849         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
10850         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
10851 };
10852
10853 struct mlx5_ifc_modify_flow_table_out_bits {
10854         u8         status[0x8];
10855         u8         reserved_at_8[0x18];
10856
10857         u8         syndrome[0x20];
10858
10859         u8         reserved_at_40[0x40];
10860 };
10861
10862 struct mlx5_ifc_modify_flow_table_in_bits {
10863         u8         opcode[0x10];
10864         u8         reserved_at_10[0x10];
10865
10866         u8         reserved_at_20[0x10];
10867         u8         op_mod[0x10];
10868
10869         u8         other_vport[0x1];
10870         u8         reserved_at_41[0xf];
10871         u8         vport_number[0x10];
10872
10873         u8         reserved_at_60[0x10];
10874         u8         modify_field_select[0x10];
10875
10876         u8         table_type[0x8];
10877         u8         reserved_at_88[0x18];
10878
10879         u8         reserved_at_a0[0x8];
10880         u8         table_id[0x18];
10881
10882         struct mlx5_ifc_flow_table_context_bits flow_table_context;
10883 };
10884
10885 struct mlx5_ifc_ets_tcn_config_reg_bits {
10886         u8         g[0x1];
10887         u8         b[0x1];
10888         u8         r[0x1];
10889         u8         reserved_at_3[0x9];
10890         u8         group[0x4];
10891         u8         reserved_at_10[0x9];
10892         u8         bw_allocation[0x7];
10893
10894         u8         reserved_at_20[0xc];
10895         u8         max_bw_units[0x4];
10896         u8         reserved_at_30[0x8];
10897         u8         max_bw_value[0x8];
10898 };
10899
10900 struct mlx5_ifc_ets_global_config_reg_bits {
10901         u8         reserved_at_0[0x2];
10902         u8         r[0x1];
10903         u8         reserved_at_3[0x1d];
10904
10905         u8         reserved_at_20[0xc];
10906         u8         max_bw_units[0x4];
10907         u8         reserved_at_30[0x8];
10908         u8         max_bw_value[0x8];
10909 };
10910
10911 struct mlx5_ifc_qetc_reg_bits {
10912         u8                                         reserved_at_0[0x8];
10913         u8                                         port_number[0x8];
10914         u8                                         reserved_at_10[0x30];
10915
10916         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
10917         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
10918 };
10919
10920 struct mlx5_ifc_qpdpm_dscp_reg_bits {
10921         u8         e[0x1];
10922         u8         reserved_at_01[0x0b];
10923         u8         prio[0x04];
10924 };
10925
10926 struct mlx5_ifc_qpdpm_reg_bits {
10927         u8                                     reserved_at_0[0x8];
10928         u8                                     local_port[0x8];
10929         u8                                     reserved_at_10[0x10];
10930         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
10931 };
10932
10933 struct mlx5_ifc_qpts_reg_bits {
10934         u8         reserved_at_0[0x8];
10935         u8         local_port[0x8];
10936         u8         reserved_at_10[0x2d];
10937         u8         trust_state[0x3];
10938 };
10939
10940 struct mlx5_ifc_pptb_reg_bits {
10941         u8         reserved_at_0[0x2];
10942         u8         mm[0x2];
10943         u8         reserved_at_4[0x4];
10944         u8         local_port[0x8];
10945         u8         reserved_at_10[0x6];
10946         u8         cm[0x1];
10947         u8         um[0x1];
10948         u8         pm[0x8];
10949
10950         u8         prio_x_buff[0x20];
10951
10952         u8         pm_msb[0x8];
10953         u8         reserved_at_48[0x10];
10954         u8         ctrl_buff[0x4];
10955         u8         untagged_buff[0x4];
10956 };
10957
10958 struct mlx5_ifc_sbcam_reg_bits {
10959         u8         reserved_at_0[0x8];
10960         u8         feature_group[0x8];
10961         u8         reserved_at_10[0x8];
10962         u8         access_reg_group[0x8];
10963
10964         u8         reserved_at_20[0x20];
10965
10966         u8         sb_access_reg_cap_mask[4][0x20];
10967
10968         u8         reserved_at_c0[0x80];
10969
10970         u8         sb_feature_cap_mask[4][0x20];
10971
10972         u8         reserved_at_1c0[0x40];
10973
10974         u8         cap_total_buffer_size[0x20];
10975
10976         u8         cap_cell_size[0x10];
10977         u8         cap_max_pg_buffers[0x8];
10978         u8         cap_num_pool_supported[0x8];
10979
10980         u8         reserved_at_240[0x8];
10981         u8         cap_sbsr_stat_size[0x8];
10982         u8         cap_max_tclass_data[0x8];
10983         u8         cap_max_cpu_ingress_tclass_sb[0x8];
10984 };
10985
10986 struct mlx5_ifc_pbmc_reg_bits {
10987         u8         reserved_at_0[0x8];
10988         u8         local_port[0x8];
10989         u8         reserved_at_10[0x10];
10990
10991         u8         xoff_timer_value[0x10];
10992         u8         xoff_refresh[0x10];
10993
10994         u8         reserved_at_40[0x9];
10995         u8         fullness_threshold[0x7];
10996         u8         port_buffer_size[0x10];
10997
10998         struct mlx5_ifc_bufferx_reg_bits buffer[10];
10999
11000         u8         reserved_at_2e0[0x80];
11001 };
11002
11003 struct mlx5_ifc_qtct_reg_bits {
11004         u8         reserved_at_0[0x8];
11005         u8         port_number[0x8];
11006         u8         reserved_at_10[0xd];
11007         u8         prio[0x3];
11008
11009         u8         reserved_at_20[0x1d];
11010         u8         tclass[0x3];
11011 };
11012
11013 struct mlx5_ifc_mcia_reg_bits {
11014         u8         l[0x1];
11015         u8         reserved_at_1[0x7];
11016         u8         module[0x8];
11017         u8         reserved_at_10[0x8];
11018         u8         status[0x8];
11019
11020         u8         i2c_device_address[0x8];
11021         u8         page_number[0x8];
11022         u8         device_address[0x10];
11023
11024         u8         reserved_at_40[0x10];
11025         u8         size[0x10];
11026
11027         u8         reserved_at_60[0x20];
11028
11029         u8         dword_0[0x20];
11030         u8         dword_1[0x20];
11031         u8         dword_2[0x20];
11032         u8         dword_3[0x20];
11033         u8         dword_4[0x20];
11034         u8         dword_5[0x20];
11035         u8         dword_6[0x20];
11036         u8         dword_7[0x20];
11037         u8         dword_8[0x20];
11038         u8         dword_9[0x20];
11039         u8         dword_10[0x20];
11040         u8         dword_11[0x20];
11041 };
11042
11043 struct mlx5_ifc_dcbx_param_bits {
11044         u8         dcbx_cee_cap[0x1];
11045         u8         dcbx_ieee_cap[0x1];
11046         u8         dcbx_standby_cap[0x1];
11047         u8         reserved_at_3[0x5];
11048         u8         port_number[0x8];
11049         u8         reserved_at_10[0xa];
11050         u8         max_application_table_size[6];
11051         u8         reserved_at_20[0x15];
11052         u8         version_oper[0x3];
11053         u8         reserved_at_38[5];
11054         u8         version_admin[0x3];
11055         u8         willing_admin[0x1];
11056         u8         reserved_at_41[0x3];
11057         u8         pfc_cap_oper[0x4];
11058         u8         reserved_at_48[0x4];
11059         u8         pfc_cap_admin[0x4];
11060         u8         reserved_at_50[0x4];
11061         u8         num_of_tc_oper[0x4];
11062         u8         reserved_at_58[0x4];
11063         u8         num_of_tc_admin[0x4];
11064         u8         remote_willing[0x1];
11065         u8         reserved_at_61[3];
11066         u8         remote_pfc_cap[4];
11067         u8         reserved_at_68[0x14];
11068         u8         remote_num_of_tc[0x4];
11069         u8         reserved_at_80[0x18];
11070         u8         error[0x8];
11071         u8         reserved_at_a0[0x160];
11072 };
11073
11074 enum {
11075         MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
11076         MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
11077         MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
11078 };
11079
11080 struct mlx5_ifc_lagc_bits {
11081         u8         fdb_selection_mode[0x1];
11082         u8         reserved_at_1[0x14];
11083         u8         port_select_mode[0x3];
11084         u8         reserved_at_18[0x5];
11085         u8         lag_state[0x3];
11086
11087         u8         reserved_at_20[0xc];
11088         u8         active_port[0x4];
11089         u8         reserved_at_30[0x4];
11090         u8         tx_remap_affinity_2[0x4];
11091         u8         reserved_at_38[0x4];
11092         u8         tx_remap_affinity_1[0x4];
11093 };
11094
11095 struct mlx5_ifc_create_lag_out_bits {
11096         u8         status[0x8];
11097         u8         reserved_at_8[0x18];
11098
11099         u8         syndrome[0x20];
11100
11101         u8         reserved_at_40[0x40];
11102 };
11103
11104 struct mlx5_ifc_create_lag_in_bits {
11105         u8         opcode[0x10];
11106         u8         reserved_at_10[0x10];
11107
11108         u8         reserved_at_20[0x10];
11109         u8         op_mod[0x10];
11110
11111         struct mlx5_ifc_lagc_bits ctx;
11112 };
11113
11114 struct mlx5_ifc_modify_lag_out_bits {
11115         u8         status[0x8];
11116         u8         reserved_at_8[0x18];
11117
11118         u8         syndrome[0x20];
11119
11120         u8         reserved_at_40[0x40];
11121 };
11122
11123 struct mlx5_ifc_modify_lag_in_bits {
11124         u8         opcode[0x10];
11125         u8         reserved_at_10[0x10];
11126
11127         u8         reserved_at_20[0x10];
11128         u8         op_mod[0x10];
11129
11130         u8         reserved_at_40[0x20];
11131         u8         field_select[0x20];
11132
11133         struct mlx5_ifc_lagc_bits ctx;
11134 };
11135
11136 struct mlx5_ifc_query_lag_out_bits {
11137         u8         status[0x8];
11138         u8         reserved_at_8[0x18];
11139
11140         u8         syndrome[0x20];
11141
11142         struct mlx5_ifc_lagc_bits ctx;
11143 };
11144
11145 struct mlx5_ifc_query_lag_in_bits {
11146         u8         opcode[0x10];
11147         u8         reserved_at_10[0x10];
11148
11149         u8         reserved_at_20[0x10];
11150         u8         op_mod[0x10];
11151
11152         u8         reserved_at_40[0x40];
11153 };
11154
11155 struct mlx5_ifc_destroy_lag_out_bits {
11156         u8         status[0x8];
11157         u8         reserved_at_8[0x18];
11158
11159         u8         syndrome[0x20];
11160
11161         u8         reserved_at_40[0x40];
11162 };
11163
11164 struct mlx5_ifc_destroy_lag_in_bits {
11165         u8         opcode[0x10];
11166         u8         reserved_at_10[0x10];
11167
11168         u8         reserved_at_20[0x10];
11169         u8         op_mod[0x10];
11170
11171         u8         reserved_at_40[0x40];
11172 };
11173
11174 struct mlx5_ifc_create_vport_lag_out_bits {
11175         u8         status[0x8];
11176         u8         reserved_at_8[0x18];
11177
11178         u8         syndrome[0x20];
11179
11180         u8         reserved_at_40[0x40];
11181 };
11182
11183 struct mlx5_ifc_create_vport_lag_in_bits {
11184         u8         opcode[0x10];
11185         u8         reserved_at_10[0x10];
11186
11187         u8         reserved_at_20[0x10];
11188         u8         op_mod[0x10];
11189
11190         u8         reserved_at_40[0x40];
11191 };
11192
11193 struct mlx5_ifc_destroy_vport_lag_out_bits {
11194         u8         status[0x8];
11195         u8         reserved_at_8[0x18];
11196
11197         u8         syndrome[0x20];
11198
11199         u8         reserved_at_40[0x40];
11200 };
11201
11202 struct mlx5_ifc_destroy_vport_lag_in_bits {
11203         u8         opcode[0x10];
11204         u8         reserved_at_10[0x10];
11205
11206         u8         reserved_at_20[0x10];
11207         u8         op_mod[0x10];
11208
11209         u8         reserved_at_40[0x40];
11210 };
11211
11212 enum {
11213         MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
11214         MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
11215 };
11216
11217 struct mlx5_ifc_modify_memic_in_bits {
11218         u8         opcode[0x10];
11219         u8         uid[0x10];
11220
11221         u8         reserved_at_20[0x10];
11222         u8         op_mod[0x10];
11223
11224         u8         reserved_at_40[0x20];
11225
11226         u8         reserved_at_60[0x18];
11227         u8         memic_operation_type[0x8];
11228
11229         u8         memic_start_addr[0x40];
11230
11231         u8         reserved_at_c0[0x140];
11232 };
11233
11234 struct mlx5_ifc_modify_memic_out_bits {
11235         u8         status[0x8];
11236         u8         reserved_at_8[0x18];
11237
11238         u8         syndrome[0x20];
11239
11240         u8         reserved_at_40[0x40];
11241
11242         u8         memic_operation_addr[0x40];
11243
11244         u8         reserved_at_c0[0x140];
11245 };
11246
11247 struct mlx5_ifc_alloc_memic_in_bits {
11248         u8         opcode[0x10];
11249         u8         reserved_at_10[0x10];
11250
11251         u8         reserved_at_20[0x10];
11252         u8         op_mod[0x10];
11253
11254         u8         reserved_at_30[0x20];
11255
11256         u8         reserved_at_40[0x18];
11257         u8         log_memic_addr_alignment[0x8];
11258
11259         u8         range_start_addr[0x40];
11260
11261         u8         range_size[0x20];
11262
11263         u8         memic_size[0x20];
11264 };
11265
11266 struct mlx5_ifc_alloc_memic_out_bits {
11267         u8         status[0x8];
11268         u8         reserved_at_8[0x18];
11269
11270         u8         syndrome[0x20];
11271
11272         u8         memic_start_addr[0x40];
11273 };
11274
11275 struct mlx5_ifc_dealloc_memic_in_bits {
11276         u8         opcode[0x10];
11277         u8         reserved_at_10[0x10];
11278
11279         u8         reserved_at_20[0x10];
11280         u8         op_mod[0x10];
11281
11282         u8         reserved_at_40[0x40];
11283
11284         u8         memic_start_addr[0x40];
11285
11286         u8         memic_size[0x20];
11287
11288         u8         reserved_at_e0[0x20];
11289 };
11290
11291 struct mlx5_ifc_dealloc_memic_out_bits {
11292         u8         status[0x8];
11293         u8         reserved_at_8[0x18];
11294
11295         u8         syndrome[0x20];
11296
11297         u8         reserved_at_40[0x40];
11298 };
11299
11300 struct mlx5_ifc_umem_bits {
11301         u8         reserved_at_0[0x80];
11302
11303         u8         ats[0x1];
11304         u8         reserved_at_81[0x1a];
11305         u8         log_page_size[0x5];
11306
11307         u8         page_offset[0x20];
11308
11309         u8         num_of_mtt[0x40];
11310
11311         struct mlx5_ifc_mtt_bits  mtt[];
11312 };
11313
11314 struct mlx5_ifc_uctx_bits {
11315         u8         cap[0x20];
11316
11317         u8         reserved_at_20[0x160];
11318 };
11319
11320 struct mlx5_ifc_sw_icm_bits {
11321         u8         modify_field_select[0x40];
11322
11323         u8         reserved_at_40[0x18];
11324         u8         log_sw_icm_size[0x8];
11325
11326         u8         reserved_at_60[0x20];
11327
11328         u8         sw_icm_start_addr[0x40];
11329
11330         u8         reserved_at_c0[0x140];
11331 };
11332
11333 struct mlx5_ifc_geneve_tlv_option_bits {
11334         u8         modify_field_select[0x40];
11335
11336         u8         reserved_at_40[0x18];
11337         u8         geneve_option_fte_index[0x8];
11338
11339         u8         option_class[0x10];
11340         u8         option_type[0x8];
11341         u8         reserved_at_78[0x3];
11342         u8         option_data_length[0x5];
11343
11344         u8         reserved_at_80[0x180];
11345 };
11346
11347 struct mlx5_ifc_create_umem_in_bits {
11348         u8         opcode[0x10];
11349         u8         uid[0x10];
11350
11351         u8         reserved_at_20[0x10];
11352         u8         op_mod[0x10];
11353
11354         u8         reserved_at_40[0x40];
11355
11356         struct mlx5_ifc_umem_bits  umem;
11357 };
11358
11359 struct mlx5_ifc_create_umem_out_bits {
11360         u8         status[0x8];
11361         u8         reserved_at_8[0x18];
11362
11363         u8         syndrome[0x20];
11364
11365         u8         reserved_at_40[0x8];
11366         u8         umem_id[0x18];
11367
11368         u8         reserved_at_60[0x20];
11369 };
11370
11371 struct mlx5_ifc_destroy_umem_in_bits {
11372         u8        opcode[0x10];
11373         u8        uid[0x10];
11374
11375         u8        reserved_at_20[0x10];
11376         u8        op_mod[0x10];
11377
11378         u8        reserved_at_40[0x8];
11379         u8        umem_id[0x18];
11380
11381         u8        reserved_at_60[0x20];
11382 };
11383
11384 struct mlx5_ifc_destroy_umem_out_bits {
11385         u8        status[0x8];
11386         u8        reserved_at_8[0x18];
11387
11388         u8        syndrome[0x20];
11389
11390         u8        reserved_at_40[0x40];
11391 };
11392
11393 struct mlx5_ifc_create_uctx_in_bits {
11394         u8         opcode[0x10];
11395         u8         reserved_at_10[0x10];
11396
11397         u8         reserved_at_20[0x10];
11398         u8         op_mod[0x10];
11399
11400         u8         reserved_at_40[0x40];
11401
11402         struct mlx5_ifc_uctx_bits  uctx;
11403 };
11404
11405 struct mlx5_ifc_create_uctx_out_bits {
11406         u8         status[0x8];
11407         u8         reserved_at_8[0x18];
11408
11409         u8         syndrome[0x20];
11410
11411         u8         reserved_at_40[0x10];
11412         u8         uid[0x10];
11413
11414         u8         reserved_at_60[0x20];
11415 };
11416
11417 struct mlx5_ifc_destroy_uctx_in_bits {
11418         u8         opcode[0x10];
11419         u8         reserved_at_10[0x10];
11420
11421         u8         reserved_at_20[0x10];
11422         u8         op_mod[0x10];
11423
11424         u8         reserved_at_40[0x10];
11425         u8         uid[0x10];
11426
11427         u8         reserved_at_60[0x20];
11428 };
11429
11430 struct mlx5_ifc_destroy_uctx_out_bits {
11431         u8         status[0x8];
11432         u8         reserved_at_8[0x18];
11433
11434         u8         syndrome[0x20];
11435
11436         u8          reserved_at_40[0x40];
11437 };
11438
11439 struct mlx5_ifc_create_sw_icm_in_bits {
11440         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11441         struct mlx5_ifc_sw_icm_bits                   sw_icm;
11442 };
11443
11444 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
11445         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11446         struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
11447 };
11448
11449 struct mlx5_ifc_mtrc_string_db_param_bits {
11450         u8         string_db_base_address[0x20];
11451
11452         u8         reserved_at_20[0x8];
11453         u8         string_db_size[0x18];
11454 };
11455
11456 struct mlx5_ifc_mtrc_cap_bits {
11457         u8         trace_owner[0x1];
11458         u8         trace_to_memory[0x1];
11459         u8         reserved_at_2[0x4];
11460         u8         trc_ver[0x2];
11461         u8         reserved_at_8[0x14];
11462         u8         num_string_db[0x4];
11463
11464         u8         first_string_trace[0x8];
11465         u8         num_string_trace[0x8];
11466         u8         reserved_at_30[0x28];
11467
11468         u8         log_max_trace_buffer_size[0x8];
11469
11470         u8         reserved_at_60[0x20];
11471
11472         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
11473
11474         u8         reserved_at_280[0x180];
11475 };
11476
11477 struct mlx5_ifc_mtrc_conf_bits {
11478         u8         reserved_at_0[0x1c];
11479         u8         trace_mode[0x4];
11480         u8         reserved_at_20[0x18];
11481         u8         log_trace_buffer_size[0x8];
11482         u8         trace_mkey[0x20];
11483         u8         reserved_at_60[0x3a0];
11484 };
11485
11486 struct mlx5_ifc_mtrc_stdb_bits {
11487         u8         string_db_index[0x4];
11488         u8         reserved_at_4[0x4];
11489         u8         read_size[0x18];
11490         u8         start_offset[0x20];
11491         u8         string_db_data[];
11492 };
11493
11494 struct mlx5_ifc_mtrc_ctrl_bits {
11495         u8         trace_status[0x2];
11496         u8         reserved_at_2[0x2];
11497         u8         arm_event[0x1];
11498         u8         reserved_at_5[0xb];
11499         u8         modify_field_select[0x10];
11500         u8         reserved_at_20[0x2b];
11501         u8         current_timestamp52_32[0x15];
11502         u8         current_timestamp31_0[0x20];
11503         u8         reserved_at_80[0x180];
11504 };
11505
11506 struct mlx5_ifc_host_params_context_bits {
11507         u8         host_number[0x8];
11508         u8         reserved_at_8[0x7];
11509         u8         host_pf_disabled[0x1];
11510         u8         host_num_of_vfs[0x10];
11511
11512         u8         host_total_vfs[0x10];
11513         u8         host_pci_bus[0x10];
11514
11515         u8         reserved_at_40[0x10];
11516         u8         host_pci_device[0x10];
11517
11518         u8         reserved_at_60[0x10];
11519         u8         host_pci_function[0x10];
11520
11521         u8         reserved_at_80[0x180];
11522 };
11523
11524 struct mlx5_ifc_query_esw_functions_in_bits {
11525         u8         opcode[0x10];
11526         u8         reserved_at_10[0x10];
11527
11528         u8         reserved_at_20[0x10];
11529         u8         op_mod[0x10];
11530
11531         u8         reserved_at_40[0x40];
11532 };
11533
11534 struct mlx5_ifc_query_esw_functions_out_bits {
11535         u8         status[0x8];
11536         u8         reserved_at_8[0x18];
11537
11538         u8         syndrome[0x20];
11539
11540         u8         reserved_at_40[0x40];
11541
11542         struct mlx5_ifc_host_params_context_bits host_params_context;
11543
11544         u8         reserved_at_280[0x180];
11545         u8         host_sf_enable[][0x40];
11546 };
11547
11548 struct mlx5_ifc_sf_partition_bits {
11549         u8         reserved_at_0[0x10];
11550         u8         log_num_sf[0x8];
11551         u8         log_sf_bar_size[0x8];
11552 };
11553
11554 struct mlx5_ifc_query_sf_partitions_out_bits {
11555         u8         status[0x8];
11556         u8         reserved_at_8[0x18];
11557
11558         u8         syndrome[0x20];
11559
11560         u8         reserved_at_40[0x18];
11561         u8         num_sf_partitions[0x8];
11562
11563         u8         reserved_at_60[0x20];
11564
11565         struct mlx5_ifc_sf_partition_bits sf_partition[];
11566 };
11567
11568 struct mlx5_ifc_query_sf_partitions_in_bits {
11569         u8         opcode[0x10];
11570         u8         reserved_at_10[0x10];
11571
11572         u8         reserved_at_20[0x10];
11573         u8         op_mod[0x10];
11574
11575         u8         reserved_at_40[0x40];
11576 };
11577
11578 struct mlx5_ifc_dealloc_sf_out_bits {
11579         u8         status[0x8];
11580         u8         reserved_at_8[0x18];
11581
11582         u8         syndrome[0x20];
11583
11584         u8         reserved_at_40[0x40];
11585 };
11586
11587 struct mlx5_ifc_dealloc_sf_in_bits {
11588         u8         opcode[0x10];
11589         u8         reserved_at_10[0x10];
11590
11591         u8         reserved_at_20[0x10];
11592         u8         op_mod[0x10];
11593
11594         u8         reserved_at_40[0x10];
11595         u8         function_id[0x10];
11596
11597         u8         reserved_at_60[0x20];
11598 };
11599
11600 struct mlx5_ifc_alloc_sf_out_bits {
11601         u8         status[0x8];
11602         u8         reserved_at_8[0x18];
11603
11604         u8         syndrome[0x20];
11605
11606         u8         reserved_at_40[0x40];
11607 };
11608
11609 struct mlx5_ifc_alloc_sf_in_bits {
11610         u8         opcode[0x10];
11611         u8         reserved_at_10[0x10];
11612
11613         u8         reserved_at_20[0x10];
11614         u8         op_mod[0x10];
11615
11616         u8         reserved_at_40[0x10];
11617         u8         function_id[0x10];
11618
11619         u8         reserved_at_60[0x20];
11620 };
11621
11622 struct mlx5_ifc_affiliated_event_header_bits {
11623         u8         reserved_at_0[0x10];
11624         u8         obj_type[0x10];
11625
11626         u8         obj_id[0x20];
11627 };
11628
11629 enum {
11630         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
11631         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
11632         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
11633         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24),
11634 };
11635
11636 enum {
11637         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
11638         MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
11639         MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
11640         MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
11641         MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
11642 };
11643
11644 enum {
11645         MLX5_IPSEC_OBJECT_ICV_LEN_16B,
11646 };
11647
11648 enum {
11649         MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
11650         MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
11651         MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
11652         MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
11653 };
11654
11655 enum {
11656         MLX5_IPSEC_ASO_MODE              = 0x0,
11657         MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
11658         MLX5_IPSEC_ASO_INC_SN            = 0x2,
11659 };
11660
11661 struct mlx5_ifc_ipsec_aso_bits {
11662         u8         valid[0x1];
11663         u8         reserved_at_201[0x1];
11664         u8         mode[0x2];
11665         u8         window_sz[0x2];
11666         u8         soft_lft_arm[0x1];
11667         u8         hard_lft_arm[0x1];
11668         u8         remove_flow_enable[0x1];
11669         u8         esn_event_arm[0x1];
11670         u8         reserved_at_20a[0x16];
11671
11672         u8         remove_flow_pkt_cnt[0x20];
11673
11674         u8         remove_flow_soft_lft[0x20];
11675
11676         u8         reserved_at_260[0x80];
11677
11678         u8         mode_parameter[0x20];
11679
11680         u8         replay_protection_window[0x100];
11681 };
11682
11683 struct mlx5_ifc_ipsec_obj_bits {
11684         u8         modify_field_select[0x40];
11685         u8         full_offload[0x1];
11686         u8         reserved_at_41[0x1];
11687         u8         esn_en[0x1];
11688         u8         esn_overlap[0x1];
11689         u8         reserved_at_44[0x2];
11690         u8         icv_length[0x2];
11691         u8         reserved_at_48[0x4];
11692         u8         aso_return_reg[0x4];
11693         u8         reserved_at_50[0x10];
11694
11695         u8         esn_msb[0x20];
11696
11697         u8         reserved_at_80[0x8];
11698         u8         dekn[0x18];
11699
11700         u8         salt[0x20];
11701
11702         u8         implicit_iv[0x40];
11703
11704         u8         reserved_at_100[0x8];
11705         u8         ipsec_aso_access_pd[0x18];
11706         u8         reserved_at_120[0xe0];
11707
11708         struct mlx5_ifc_ipsec_aso_bits ipsec_aso;
11709 };
11710
11711 struct mlx5_ifc_create_ipsec_obj_in_bits {
11712         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11713         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11714 };
11715
11716 enum {
11717         MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
11718         MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
11719 };
11720
11721 struct mlx5_ifc_query_ipsec_obj_out_bits {
11722         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11723         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11724 };
11725
11726 struct mlx5_ifc_modify_ipsec_obj_in_bits {
11727         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11728         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11729 };
11730
11731 enum {
11732         MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
11733 };
11734
11735 enum {
11736         MLX5_MACSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
11737         MLX5_MACSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
11738         MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
11739         MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
11740 };
11741
11742 #define MLX5_MACSEC_ASO_INC_SN  0x2
11743 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2
11744
11745 struct mlx5_ifc_macsec_aso_bits {
11746         u8    valid[0x1];
11747         u8    reserved_at_1[0x1];
11748         u8    mode[0x2];
11749         u8    window_size[0x2];
11750         u8    soft_lifetime_arm[0x1];
11751         u8    hard_lifetime_arm[0x1];
11752         u8    remove_flow_enable[0x1];
11753         u8    epn_event_arm[0x1];
11754         u8    reserved_at_a[0x16];
11755
11756         u8    remove_flow_packet_count[0x20];
11757
11758         u8    remove_flow_soft_lifetime[0x20];
11759
11760         u8    reserved_at_60[0x80];
11761
11762         u8    mode_parameter[0x20];
11763
11764         u8    replay_protection_window[8][0x20];
11765 };
11766
11767 struct mlx5_ifc_macsec_offload_obj_bits {
11768         u8    modify_field_select[0x40];
11769
11770         u8    confidentiality_en[0x1];
11771         u8    reserved_at_41[0x1];
11772         u8    epn_en[0x1];
11773         u8    epn_overlap[0x1];
11774         u8    reserved_at_44[0x2];
11775         u8    confidentiality_offset[0x2];
11776         u8    reserved_at_48[0x4];
11777         u8    aso_return_reg[0x4];
11778         u8    reserved_at_50[0x10];
11779
11780         u8    epn_msb[0x20];
11781
11782         u8    reserved_at_80[0x8];
11783         u8    dekn[0x18];
11784
11785         u8    reserved_at_a0[0x20];
11786
11787         u8    sci[0x40];
11788
11789         u8    reserved_at_100[0x8];
11790         u8    macsec_aso_access_pd[0x18];
11791
11792         u8    reserved_at_120[0x60];
11793
11794         u8    salt[3][0x20];
11795
11796         u8    reserved_at_1e0[0x20];
11797
11798         struct mlx5_ifc_macsec_aso_bits macsec_aso;
11799 };
11800
11801 struct mlx5_ifc_create_macsec_obj_in_bits {
11802         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11803         struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
11804 };
11805
11806 struct mlx5_ifc_modify_macsec_obj_in_bits {
11807         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11808         struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
11809 };
11810
11811 enum {
11812         MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
11813         MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1),
11814 };
11815
11816 struct mlx5_ifc_query_macsec_obj_out_bits {
11817         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11818         struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
11819 };
11820
11821 struct mlx5_ifc_encryption_key_obj_bits {
11822         u8         modify_field_select[0x40];
11823
11824         u8         reserved_at_40[0x14];
11825         u8         key_size[0x4];
11826         u8         reserved_at_58[0x4];
11827         u8         key_type[0x4];
11828
11829         u8         reserved_at_60[0x8];
11830         u8         pd[0x18];
11831
11832         u8         reserved_at_80[0x180];
11833         u8         key[8][0x20];
11834
11835         u8         reserved_at_300[0x500];
11836 };
11837
11838 struct mlx5_ifc_create_encryption_key_in_bits {
11839         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11840         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
11841 };
11842
11843 enum {
11844         MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH            = 0x0,
11845         MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2         = 0x1,
11846         MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG     = 0x2,
11847         MLX5_FLOW_METER_MODE_NUM_PACKETS                = 0x3,
11848 };
11849
11850 struct mlx5_ifc_flow_meter_parameters_bits {
11851         u8         valid[0x1];
11852         u8         bucket_overflow[0x1];
11853         u8         start_color[0x2];
11854         u8         both_buckets_on_green[0x1];
11855         u8         reserved_at_5[0x1];
11856         u8         meter_mode[0x2];
11857         u8         reserved_at_8[0x18];
11858
11859         u8         reserved_at_20[0x20];
11860
11861         u8         reserved_at_40[0x3];
11862         u8         cbs_exponent[0x5];
11863         u8         cbs_mantissa[0x8];
11864         u8         reserved_at_50[0x3];
11865         u8         cir_exponent[0x5];
11866         u8         cir_mantissa[0x8];
11867
11868         u8         reserved_at_60[0x20];
11869
11870         u8         reserved_at_80[0x3];
11871         u8         ebs_exponent[0x5];
11872         u8         ebs_mantissa[0x8];
11873         u8         reserved_at_90[0x3];
11874         u8         eir_exponent[0x5];
11875         u8         eir_mantissa[0x8];
11876
11877         u8         reserved_at_a0[0x60];
11878 };
11879
11880 struct mlx5_ifc_flow_meter_aso_obj_bits {
11881         u8         modify_field_select[0x40];
11882
11883         u8         reserved_at_40[0x40];
11884
11885         u8         reserved_at_80[0x8];
11886         u8         meter_aso_access_pd[0x18];
11887
11888         u8         reserved_at_a0[0x160];
11889
11890         struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
11891 };
11892
11893 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
11894         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
11895         struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
11896 };
11897
11898 struct mlx5_ifc_sampler_obj_bits {
11899         u8         modify_field_select[0x40];
11900
11901         u8         table_type[0x8];
11902         u8         level[0x8];
11903         u8         reserved_at_50[0xf];
11904         u8         ignore_flow_level[0x1];
11905
11906         u8         sample_ratio[0x20];
11907
11908         u8         reserved_at_80[0x8];
11909         u8         sample_table_id[0x18];
11910
11911         u8         reserved_at_a0[0x8];
11912         u8         default_table_id[0x18];
11913
11914         u8         sw_steering_icm_address_rx[0x40];
11915         u8         sw_steering_icm_address_tx[0x40];
11916
11917         u8         reserved_at_140[0xa0];
11918 };
11919
11920 struct mlx5_ifc_create_sampler_obj_in_bits {
11921         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11922         struct mlx5_ifc_sampler_obj_bits sampler_object;
11923 };
11924
11925 struct mlx5_ifc_query_sampler_obj_out_bits {
11926         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11927         struct mlx5_ifc_sampler_obj_bits sampler_object;
11928 };
11929
11930 enum {
11931         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
11932         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
11933 };
11934
11935 enum {
11936         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
11937         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
11938         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_MACSEC = 0x4,
11939 };
11940
11941 struct mlx5_ifc_tls_static_params_bits {
11942         u8         const_2[0x2];
11943         u8         tls_version[0x4];
11944         u8         const_1[0x2];
11945         u8         reserved_at_8[0x14];
11946         u8         encryption_standard[0x4];
11947
11948         u8         reserved_at_20[0x20];
11949
11950         u8         initial_record_number[0x40];
11951
11952         u8         resync_tcp_sn[0x20];
11953
11954         u8         gcm_iv[0x20];
11955
11956         u8         implicit_iv[0x40];
11957
11958         u8         reserved_at_100[0x8];
11959         u8         dek_index[0x18];
11960
11961         u8         reserved_at_120[0xe0];
11962 };
11963
11964 struct mlx5_ifc_tls_progress_params_bits {
11965         u8         next_record_tcp_sn[0x20];
11966
11967         u8         hw_resync_tcp_sn[0x20];
11968
11969         u8         record_tracker_state[0x2];
11970         u8         auth_state[0x2];
11971         u8         reserved_at_44[0x4];
11972         u8         hw_offset_record_number[0x18];
11973 };
11974
11975 enum {
11976         MLX5_MTT_PERM_READ      = 1 << 0,
11977         MLX5_MTT_PERM_WRITE     = 1 << 1,
11978         MLX5_MTT_PERM_RW        = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
11979 };
11980
11981 enum {
11982         MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR  = 0x0,
11983         MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER  = 0x1,
11984 };
11985
11986 struct mlx5_ifc_suspend_vhca_in_bits {
11987         u8         opcode[0x10];
11988         u8         uid[0x10];
11989
11990         u8         reserved_at_20[0x10];
11991         u8         op_mod[0x10];
11992
11993         u8         reserved_at_40[0x10];
11994         u8         vhca_id[0x10];
11995
11996         u8         reserved_at_60[0x20];
11997 };
11998
11999 struct mlx5_ifc_suspend_vhca_out_bits {
12000         u8         status[0x8];
12001         u8         reserved_at_8[0x18];
12002
12003         u8         syndrome[0x20];
12004
12005         u8         reserved_at_40[0x40];
12006 };
12007
12008 enum {
12009         MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER  = 0x0,
12010         MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR  = 0x1,
12011 };
12012
12013 struct mlx5_ifc_resume_vhca_in_bits {
12014         u8         opcode[0x10];
12015         u8         uid[0x10];
12016
12017         u8         reserved_at_20[0x10];
12018         u8         op_mod[0x10];
12019
12020         u8         reserved_at_40[0x10];
12021         u8         vhca_id[0x10];
12022
12023         u8         reserved_at_60[0x20];
12024 };
12025
12026 struct mlx5_ifc_resume_vhca_out_bits {
12027         u8         status[0x8];
12028         u8         reserved_at_8[0x18];
12029
12030         u8         syndrome[0x20];
12031
12032         u8         reserved_at_40[0x40];
12033 };
12034
12035 struct mlx5_ifc_query_vhca_migration_state_in_bits {
12036         u8         opcode[0x10];
12037         u8         uid[0x10];
12038
12039         u8         reserved_at_20[0x10];
12040         u8         op_mod[0x10];
12041
12042         u8         incremental[0x1];
12043         u8         reserved_at_41[0xf];
12044         u8         vhca_id[0x10];
12045
12046         u8         reserved_at_60[0x20];
12047 };
12048
12049 struct mlx5_ifc_query_vhca_migration_state_out_bits {
12050         u8         status[0x8];
12051         u8         reserved_at_8[0x18];
12052
12053         u8         syndrome[0x20];
12054
12055         u8         reserved_at_40[0x40];
12056
12057         u8         required_umem_size[0x20];
12058
12059         u8         reserved_at_a0[0x160];
12060 };
12061
12062 struct mlx5_ifc_save_vhca_state_in_bits {
12063         u8         opcode[0x10];
12064         u8         uid[0x10];
12065
12066         u8         reserved_at_20[0x10];
12067         u8         op_mod[0x10];
12068
12069         u8         incremental[0x1];
12070         u8         set_track[0x1];
12071         u8         reserved_at_42[0xe];
12072         u8         vhca_id[0x10];
12073
12074         u8         reserved_at_60[0x20];
12075
12076         u8         va[0x40];
12077
12078         u8         mkey[0x20];
12079
12080         u8         size[0x20];
12081 };
12082
12083 struct mlx5_ifc_save_vhca_state_out_bits {
12084         u8         status[0x8];
12085         u8         reserved_at_8[0x18];
12086
12087         u8         syndrome[0x20];
12088
12089         u8         actual_image_size[0x20];
12090
12091         u8         reserved_at_60[0x20];
12092 };
12093
12094 struct mlx5_ifc_load_vhca_state_in_bits {
12095         u8         opcode[0x10];
12096         u8         uid[0x10];
12097
12098         u8         reserved_at_20[0x10];
12099         u8         op_mod[0x10];
12100
12101         u8         reserved_at_40[0x10];
12102         u8         vhca_id[0x10];
12103
12104         u8         reserved_at_60[0x20];
12105
12106         u8         va[0x40];
12107
12108         u8         mkey[0x20];
12109
12110         u8         size[0x20];
12111 };
12112
12113 struct mlx5_ifc_load_vhca_state_out_bits {
12114         u8         status[0x8];
12115         u8         reserved_at_8[0x18];
12116
12117         u8         syndrome[0x20];
12118
12119         u8         reserved_at_40[0x40];
12120 };
12121
12122 struct mlx5_ifc_adv_virtualization_cap_bits {
12123         u8         reserved_at_0[0x3];
12124         u8         pg_track_log_max_num[0x5];
12125         u8         pg_track_max_num_range[0x8];
12126         u8         pg_track_log_min_addr_space[0x8];
12127         u8         pg_track_log_max_addr_space[0x8];
12128
12129         u8         reserved_at_20[0x3];
12130         u8         pg_track_log_min_msg_size[0x5];
12131         u8         reserved_at_28[0x3];
12132         u8         pg_track_log_max_msg_size[0x5];
12133         u8         reserved_at_30[0x3];
12134         u8         pg_track_log_min_page_size[0x5];
12135         u8         reserved_at_38[0x3];
12136         u8         pg_track_log_max_page_size[0x5];
12137
12138         u8         reserved_at_40[0x7c0];
12139 };
12140
12141 struct mlx5_ifc_page_track_report_entry_bits {
12142         u8         dirty_address_high[0x20];
12143
12144         u8         dirty_address_low[0x20];
12145 };
12146
12147 enum {
12148         MLX5_PAGE_TRACK_STATE_TRACKING,
12149         MLX5_PAGE_TRACK_STATE_REPORTING,
12150         MLX5_PAGE_TRACK_STATE_ERROR,
12151 };
12152
12153 struct mlx5_ifc_page_track_range_bits {
12154         u8         start_address[0x40];
12155
12156         u8         length[0x40];
12157 };
12158
12159 struct mlx5_ifc_page_track_bits {
12160         u8         modify_field_select[0x40];
12161
12162         u8         reserved_at_40[0x10];
12163         u8         vhca_id[0x10];
12164
12165         u8         reserved_at_60[0x20];
12166
12167         u8         state[0x4];
12168         u8         track_type[0x4];
12169         u8         log_addr_space_size[0x8];
12170         u8         reserved_at_90[0x3];
12171         u8         log_page_size[0x5];
12172         u8         reserved_at_98[0x3];
12173         u8         log_msg_size[0x5];
12174
12175         u8         reserved_at_a0[0x8];
12176         u8         reporting_qpn[0x18];
12177
12178         u8         reserved_at_c0[0x18];
12179         u8         num_ranges[0x8];
12180
12181         u8         reserved_at_e0[0x20];
12182
12183         u8         range_start_address[0x40];
12184
12185         u8         length[0x40];
12186
12187         struct     mlx5_ifc_page_track_range_bits track_range[0];
12188 };
12189
12190 struct mlx5_ifc_create_page_track_obj_in_bits {
12191         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12192         struct mlx5_ifc_page_track_bits obj_context;
12193 };
12194
12195 struct mlx5_ifc_modify_page_track_obj_in_bits {
12196         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12197         struct mlx5_ifc_page_track_bits obj_context;
12198 };
12199
12200 #endif /* MLX5_IFC_H */