2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
86 MLX5_CMD_OP_CREATE_MKEY = 0x200,
87 MLX5_CMD_OP_QUERY_MKEY = 0x201,
88 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
89 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
90 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
91 MLX5_CMD_OP_CREATE_EQ = 0x301,
92 MLX5_CMD_OP_DESTROY_EQ = 0x302,
93 MLX5_CMD_OP_QUERY_EQ = 0x303,
94 MLX5_CMD_OP_GEN_EQE = 0x304,
95 MLX5_CMD_OP_CREATE_CQ = 0x400,
96 MLX5_CMD_OP_DESTROY_CQ = 0x401,
97 MLX5_CMD_OP_QUERY_CQ = 0x402,
98 MLX5_CMD_OP_MODIFY_CQ = 0x403,
99 MLX5_CMD_OP_CREATE_QP = 0x500,
100 MLX5_CMD_OP_DESTROY_QP = 0x501,
101 MLX5_CMD_OP_RST2INIT_QP = 0x502,
102 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
103 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
104 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
105 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
106 MLX5_CMD_OP_2ERR_QP = 0x507,
107 MLX5_CMD_OP_2RST_QP = 0x50a,
108 MLX5_CMD_OP_QUERY_QP = 0x50b,
109 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
110 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
111 MLX5_CMD_OP_CREATE_PSV = 0x600,
112 MLX5_CMD_OP_DESTROY_PSV = 0x601,
113 MLX5_CMD_OP_CREATE_SRQ = 0x700,
114 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
115 MLX5_CMD_OP_QUERY_SRQ = 0x702,
116 MLX5_CMD_OP_ARM_RQ = 0x703,
117 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
118 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
119 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
120 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
121 MLX5_CMD_OP_CREATE_DCT = 0x710,
122 MLX5_CMD_OP_DESTROY_DCT = 0x711,
123 MLX5_CMD_OP_DRAIN_DCT = 0x712,
124 MLX5_CMD_OP_QUERY_DCT = 0x713,
125 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
126 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
127 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
128 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
129 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
130 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
131 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
132 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
133 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
134 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
135 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
136 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
137 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
138 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
139 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
140 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
141 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
142 MLX5_CMD_OP_ALLOC_PD = 0x800,
143 MLX5_CMD_OP_DEALLOC_PD = 0x801,
144 MLX5_CMD_OP_ALLOC_UAR = 0x802,
145 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
146 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
147 MLX5_CMD_OP_ACCESS_REG = 0x805,
148 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
149 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
150 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
151 MLX5_CMD_OP_MAD_IFC = 0x50d,
152 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
153 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
154 MLX5_CMD_OP_NOP = 0x80d,
155 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
156 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
157 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
158 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
159 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
160 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
161 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
162 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
163 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
164 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
165 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
166 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
167 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
168 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
169 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
170 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
171 MLX5_CMD_OP_CREATE_TIR = 0x900,
172 MLX5_CMD_OP_MODIFY_TIR = 0x901,
173 MLX5_CMD_OP_DESTROY_TIR = 0x902,
174 MLX5_CMD_OP_QUERY_TIR = 0x903,
175 MLX5_CMD_OP_CREATE_SQ = 0x904,
176 MLX5_CMD_OP_MODIFY_SQ = 0x905,
177 MLX5_CMD_OP_DESTROY_SQ = 0x906,
178 MLX5_CMD_OP_QUERY_SQ = 0x907,
179 MLX5_CMD_OP_CREATE_RQ = 0x908,
180 MLX5_CMD_OP_MODIFY_RQ = 0x909,
181 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
182 MLX5_CMD_OP_QUERY_RQ = 0x90b,
183 MLX5_CMD_OP_CREATE_RMP = 0x90c,
184 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
185 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
186 MLX5_CMD_OP_QUERY_RMP = 0x90f,
187 MLX5_CMD_OP_CREATE_TIS = 0x912,
188 MLX5_CMD_OP_MODIFY_TIS = 0x913,
189 MLX5_CMD_OP_DESTROY_TIS = 0x914,
190 MLX5_CMD_OP_QUERY_TIS = 0x915,
191 MLX5_CMD_OP_CREATE_RQT = 0x916,
192 MLX5_CMD_OP_MODIFY_RQT = 0x917,
193 MLX5_CMD_OP_DESTROY_RQT = 0x918,
194 MLX5_CMD_OP_QUERY_RQT = 0x919,
195 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
196 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
197 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
198 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
199 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
200 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
201 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
202 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
203 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
204 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
205 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c
208 struct mlx5_ifc_flow_table_fields_supported_bits {
211 u8 outer_ether_type[0x1];
212 u8 reserved_at_3[0x1];
213 u8 outer_first_prio[0x1];
214 u8 outer_first_cfi[0x1];
215 u8 outer_first_vid[0x1];
216 u8 reserved_at_7[0x1];
217 u8 outer_second_prio[0x1];
218 u8 outer_second_cfi[0x1];
219 u8 outer_second_vid[0x1];
220 u8 reserved_at_b[0x1];
224 u8 outer_ip_protocol[0x1];
225 u8 outer_ip_ecn[0x1];
226 u8 outer_ip_dscp[0x1];
227 u8 outer_udp_sport[0x1];
228 u8 outer_udp_dport[0x1];
229 u8 outer_tcp_sport[0x1];
230 u8 outer_tcp_dport[0x1];
231 u8 outer_tcp_flags[0x1];
232 u8 outer_gre_protocol[0x1];
233 u8 outer_gre_key[0x1];
234 u8 outer_vxlan_vni[0x1];
235 u8 reserved_at_1a[0x5];
236 u8 source_eswitch_port[0x1];
240 u8 inner_ether_type[0x1];
241 u8 reserved_at_23[0x1];
242 u8 inner_first_prio[0x1];
243 u8 inner_first_cfi[0x1];
244 u8 inner_first_vid[0x1];
245 u8 reserved_at_27[0x1];
246 u8 inner_second_prio[0x1];
247 u8 inner_second_cfi[0x1];
248 u8 inner_second_vid[0x1];
249 u8 reserved_at_2b[0x1];
253 u8 inner_ip_protocol[0x1];
254 u8 inner_ip_ecn[0x1];
255 u8 inner_ip_dscp[0x1];
256 u8 inner_udp_sport[0x1];
257 u8 inner_udp_dport[0x1];
258 u8 inner_tcp_sport[0x1];
259 u8 inner_tcp_dport[0x1];
260 u8 inner_tcp_flags[0x1];
261 u8 reserved_at_37[0x9];
263 u8 reserved_at_40[0x40];
266 struct mlx5_ifc_flow_table_prop_layout_bits {
268 u8 reserved_at_1[0x2];
269 u8 flow_modify_en[0x1];
271 u8 identified_miss_table_mode[0x1];
272 u8 flow_table_modify[0x1];
273 u8 reserved_at_7[0x19];
275 u8 reserved_at_20[0x2];
276 u8 log_max_ft_size[0x6];
277 u8 reserved_at_28[0x10];
278 u8 max_ft_level[0x8];
280 u8 reserved_at_40[0x20];
282 u8 reserved_at_60[0x18];
283 u8 log_max_ft_num[0x8];
285 u8 reserved_at_80[0x18];
286 u8 log_max_destination[0x8];
288 u8 reserved_at_a0[0x18];
289 u8 log_max_flow[0x8];
291 u8 reserved_at_c0[0x40];
293 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
295 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
298 struct mlx5_ifc_odp_per_transport_service_cap_bits {
303 u8 reserved_at_4[0x1];
305 u8 reserved_at_6[0x1a];
308 struct mlx5_ifc_ipv4_layout_bits {
309 u8 reserved_at_0[0x60];
314 struct mlx5_ifc_ipv6_layout_bits {
318 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
319 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
320 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
321 u8 reserved_at_0[0x80];
324 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
341 u8 reserved_at_91[0x1];
343 u8 reserved_at_93[0x4];
349 u8 reserved_at_c0[0x20];
354 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
356 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
359 struct mlx5_ifc_fte_match_set_misc_bits {
360 u8 reserved_at_0[0x20];
362 u8 reserved_at_20[0x10];
363 u8 source_port[0x10];
365 u8 outer_second_prio[0x3];
366 u8 outer_second_cfi[0x1];
367 u8 outer_second_vid[0xc];
368 u8 inner_second_prio[0x3];
369 u8 inner_second_cfi[0x1];
370 u8 inner_second_vid[0xc];
372 u8 outer_second_vlan_tag[0x1];
373 u8 inner_second_vlan_tag[0x1];
374 u8 reserved_at_62[0xe];
375 u8 gre_protocol[0x10];
381 u8 reserved_at_b8[0x8];
383 u8 reserved_at_c0[0x20];
385 u8 reserved_at_e0[0xc];
386 u8 outer_ipv6_flow_label[0x14];
388 u8 reserved_at_100[0xc];
389 u8 inner_ipv6_flow_label[0x14];
391 u8 reserved_at_120[0xe0];
394 struct mlx5_ifc_cmd_pas_bits {
398 u8 reserved_at_34[0xc];
401 struct mlx5_ifc_uint64_bits {
408 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
409 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
410 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
411 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
412 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
413 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
414 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
415 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
416 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
417 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
420 struct mlx5_ifc_ads_bits {
423 u8 reserved_at_2[0xe];
426 u8 reserved_at_20[0x8];
432 u8 reserved_at_45[0x3];
433 u8 src_addr_index[0x8];
434 u8 reserved_at_50[0x4];
438 u8 reserved_at_60[0x4];
442 u8 rgid_rip[16][0x8];
444 u8 reserved_at_100[0x4];
447 u8 reserved_at_106[0x1];
462 struct mlx5_ifc_flow_table_nic_cap_bits {
463 u8 reserved_at_0[0x200];
465 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
467 u8 reserved_at_400[0x200];
469 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
471 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
473 u8 reserved_at_a00[0x200];
475 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
477 u8 reserved_at_e00[0x7200];
480 struct mlx5_ifc_flow_table_eswitch_cap_bits {
481 u8 reserved_at_0[0x200];
483 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
485 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
487 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
489 u8 reserved_at_800[0x7800];
492 struct mlx5_ifc_e_switch_cap_bits {
493 u8 vport_svlan_strip[0x1];
494 u8 vport_cvlan_strip[0x1];
495 u8 vport_svlan_insert[0x1];
496 u8 vport_cvlan_insert_if_not_exist[0x1];
497 u8 vport_cvlan_insert_overwrite[0x1];
498 u8 reserved_at_5[0x1b];
500 u8 reserved_at_20[0x7e0];
503 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
507 u8 lro_psh_flag[0x1];
508 u8 lro_time_stamp[0x1];
509 u8 reserved_at_5[0x3];
510 u8 self_lb_en_modifiable[0x1];
511 u8 reserved_at_9[0x2];
513 u8 reserved_at_10[0x4];
514 u8 rss_ind_tbl_cap[0x4];
515 u8 reserved_at_18[0x3];
516 u8 tunnel_lso_const_out_ip_id[0x1];
517 u8 reserved_at_1c[0x2];
518 u8 tunnel_statless_gre[0x1];
519 u8 tunnel_stateless_vxlan[0x1];
521 u8 reserved_at_20[0x20];
523 u8 reserved_at_40[0x10];
524 u8 lro_min_mss_size[0x10];
526 u8 reserved_at_60[0x120];
528 u8 lro_timer_supported_periods[4][0x20];
530 u8 reserved_at_200[0x600];
533 struct mlx5_ifc_roce_cap_bits {
535 u8 reserved_at_1[0x1f];
537 u8 reserved_at_20[0x60];
539 u8 reserved_at_80[0xc];
541 u8 reserved_at_90[0x8];
542 u8 roce_version[0x8];
544 u8 reserved_at_a0[0x10];
545 u8 r_roce_dest_udp_port[0x10];
547 u8 r_roce_max_src_udp_port[0x10];
548 u8 r_roce_min_src_udp_port[0x10];
550 u8 reserved_at_e0[0x10];
551 u8 roce_address_table_size[0x10];
553 u8 reserved_at_100[0x700];
557 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
558 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
559 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
560 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
561 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
562 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
563 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
564 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
565 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
569 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
570 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
571 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
572 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
573 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
574 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
575 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
576 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
577 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
580 struct mlx5_ifc_atomic_caps_bits {
581 u8 reserved_at_0[0x40];
583 u8 atomic_req_8B_endianess_mode[0x2];
584 u8 reserved_at_42[0x4];
585 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
587 u8 reserved_at_47[0x19];
589 u8 reserved_at_60[0x20];
591 u8 reserved_at_80[0x10];
592 u8 atomic_operations[0x10];
594 u8 reserved_at_a0[0x10];
595 u8 atomic_size_qp[0x10];
597 u8 reserved_at_c0[0x10];
598 u8 atomic_size_dc[0x10];
600 u8 reserved_at_e0[0x720];
603 struct mlx5_ifc_odp_cap_bits {
604 u8 reserved_at_0[0x40];
607 u8 reserved_at_41[0x1f];
609 u8 reserved_at_60[0x20];
611 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
613 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
615 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
617 u8 reserved_at_e0[0x720];
621 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
622 MLX5_WQ_TYPE_CYCLIC = 0x1,
623 MLX5_WQ_TYPE_STRQ = 0x2,
627 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
628 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
632 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
633 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
634 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
635 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
636 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
640 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
641 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
642 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
643 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
644 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
645 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
649 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
650 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
654 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
655 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
656 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
660 MLX5_CAP_PORT_TYPE_IB = 0x0,
661 MLX5_CAP_PORT_TYPE_ETH = 0x1,
664 struct mlx5_ifc_cmd_hca_cap_bits {
665 u8 reserved_at_0[0x80];
667 u8 log_max_srq_sz[0x8];
668 u8 log_max_qp_sz[0x8];
669 u8 reserved_at_90[0xb];
672 u8 reserved_at_a0[0xb];
674 u8 reserved_at_b0[0x10];
676 u8 reserved_at_c0[0x8];
677 u8 log_max_cq_sz[0x8];
678 u8 reserved_at_d0[0xb];
681 u8 log_max_eq_sz[0x8];
682 u8 reserved_at_e8[0x2];
683 u8 log_max_mkey[0x6];
684 u8 reserved_at_f0[0xc];
687 u8 max_indirection[0x8];
688 u8 reserved_at_108[0x1];
689 u8 log_max_mrw_sz[0x7];
690 u8 reserved_at_110[0x2];
691 u8 log_max_bsf_list_size[0x6];
692 u8 reserved_at_118[0x2];
693 u8 log_max_klm_list_size[0x6];
695 u8 reserved_at_120[0xa];
696 u8 log_max_ra_req_dc[0x6];
697 u8 reserved_at_130[0xa];
698 u8 log_max_ra_res_dc[0x6];
700 u8 reserved_at_140[0xa];
701 u8 log_max_ra_req_qp[0x6];
702 u8 reserved_at_150[0xa];
703 u8 log_max_ra_res_qp[0x6];
706 u8 cc_query_allowed[0x1];
707 u8 cc_modify_allowed[0x1];
708 u8 reserved_at_163[0xd];
709 u8 gid_table_size[0x10];
711 u8 out_of_seq_cnt[0x1];
712 u8 vport_counters[0x1];
713 u8 reserved_at_182[0x4];
715 u8 pkey_table_size[0x10];
717 u8 vport_group_manager[0x1];
718 u8 vhca_group_manager[0x1];
721 u8 reserved_at_1a4[0x1];
723 u8 nic_flow_table[0x1];
724 u8 eswitch_flow_table[0x1];
726 u8 reserved_at_1a8[0x2];
727 u8 local_ca_ack_delay[0x5];
728 u8 reserved_at_1af[0x6];
732 u8 reserved_at_1bf[0x3];
734 u8 reserved_at_1c7[0x4];
736 u8 reserved_at_1cf[0x6];
739 u8 reserved_at_1d7[0x1];
748 u8 stat_rate_support[0x10];
749 u8 reserved_at_1ef[0xc];
752 u8 compact_address_vector[0x1];
753 u8 reserved_at_200[0xe];
754 u8 drain_sigerr[0x1];
755 u8 cmdif_checksum[0x2];
757 u8 reserved_at_212[0x1];
758 u8 wq_signature[0x1];
759 u8 sctr_data_cqe[0x1];
760 u8 reserved_at_215[0x1];
765 u8 reserved_at_21a[0x1];
766 u8 eth_net_offloads[0x1];
769 u8 reserved_at_21e[0x1];
773 u8 cq_moderation[0x1];
774 u8 reserved_at_222[0x3];
778 u8 reserved_at_228[0x1];
779 u8 scqe_break_moderation[0x1];
780 u8 reserved_at_22a[0x1];
782 u8 reserved_at_22c[0x1];
784 u8 reserved_at_22e[0x7];
787 u8 reserved_at_237[0x4];
793 u8 reserved_at_23f[0xa];
795 u8 reserved_at_24f[0x8];
799 u8 reserved_at_260[0x1];
800 u8 pad_tx_eth_packet[0x1];
801 u8 reserved_at_262[0x8];
802 u8 log_bf_reg_size[0x5];
803 u8 reserved_at_26f[0x10];
805 u8 reserved_at_27f[0x10];
806 u8 max_wqe_sz_sq[0x10];
808 u8 reserved_at_29f[0x10];
809 u8 max_wqe_sz_rq[0x10];
811 u8 reserved_at_2bf[0x10];
812 u8 max_wqe_sz_sq_dc[0x10];
814 u8 reserved_at_2df[0x7];
817 u8 reserved_at_2ff[0x18];
820 u8 reserved_at_31f[0x3];
821 u8 log_max_transport_domain[0x5];
822 u8 reserved_at_327[0x3];
824 u8 reserved_at_32f[0xb];
825 u8 log_max_xrcd[0x5];
827 u8 reserved_at_33f[0x20];
829 u8 reserved_at_35f[0x3];
831 u8 reserved_at_367[0x3];
833 u8 reserved_at_36f[0x3];
835 u8 reserved_at_377[0x3];
838 u8 basic_cyclic_rcv_wqe[0x1];
839 u8 reserved_at_380[0x2];
841 u8 reserved_at_387[0x3];
843 u8 reserved_at_38f[0x3];
844 u8 log_max_rqt_size[0x5];
845 u8 reserved_at_397[0x3];
846 u8 log_max_tis_per_sq[0x5];
848 u8 reserved_at_39f[0x3];
849 u8 log_max_stride_sz_rq[0x5];
850 u8 reserved_at_3a7[0x3];
851 u8 log_min_stride_sz_rq[0x5];
852 u8 reserved_at_3af[0x3];
853 u8 log_max_stride_sz_sq[0x5];
854 u8 reserved_at_3b7[0x3];
855 u8 log_min_stride_sz_sq[0x5];
857 u8 reserved_at_3bf[0x1b];
858 u8 log_max_wq_sz[0x5];
860 u8 nic_vport_change_event[0x1];
861 u8 reserved_at_3e0[0xa];
862 u8 log_max_vlan_list[0x5];
863 u8 reserved_at_3ef[0x3];
864 u8 log_max_current_mc_list[0x5];
865 u8 reserved_at_3f7[0x3];
866 u8 log_max_current_uc_list[0x5];
868 u8 reserved_at_3ff[0x80];
870 u8 reserved_at_47f[0x3];
871 u8 log_max_l2_table[0x5];
872 u8 reserved_at_487[0x8];
873 u8 log_uar_page_sz[0x10];
875 u8 reserved_at_49f[0x20];
876 u8 device_frequency_mhz[0x20];
877 u8 device_frequency_khz[0x20];
878 u8 reserved_at_4ff[0x5f];
881 u8 cqe_zip_timeout[0x10];
882 u8 cqe_zip_max_num[0x10];
884 u8 reserved_at_57f[0x220];
887 enum mlx5_flow_destination_type {
888 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
889 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
890 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
893 struct mlx5_ifc_dest_format_struct_bits {
894 u8 destination_type[0x8];
895 u8 destination_id[0x18];
897 u8 reserved_at_20[0x20];
900 struct mlx5_ifc_fte_match_param_bits {
901 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
903 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
905 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
907 u8 reserved_at_600[0xa00];
911 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
912 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
913 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
914 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
915 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
918 struct mlx5_ifc_rx_hash_field_select_bits {
919 u8 l3_prot_type[0x1];
920 u8 l4_prot_type[0x1];
921 u8 selected_fields[0x1e];
925 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
926 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
930 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
931 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
934 struct mlx5_ifc_wq_bits {
936 u8 wq_signature[0x1];
937 u8 end_padding_mode[0x2];
939 u8 reserved_at_8[0x18];
941 u8 hds_skip_first_sge[0x1];
942 u8 log2_hds_buf_size[0x3];
943 u8 reserved_at_24[0x7];
947 u8 reserved_at_40[0x8];
950 u8 reserved_at_60[0x8];
959 u8 reserved_at_100[0xc];
960 u8 log_wq_stride[0x4];
961 u8 reserved_at_110[0x3];
962 u8 log_wq_pg_sz[0x5];
963 u8 reserved_at_118[0x3];
966 u8 reserved_at_120[0x4e0];
968 struct mlx5_ifc_cmd_pas_bits pas[0];
971 struct mlx5_ifc_rq_num_bits {
972 u8 reserved_at_0[0x8];
976 struct mlx5_ifc_mac_address_layout_bits {
977 u8 reserved_at_0[0x10];
978 u8 mac_addr_47_32[0x10];
980 u8 mac_addr_31_0[0x20];
983 struct mlx5_ifc_vlan_layout_bits {
984 u8 reserved_at_0[0x14];
987 u8 reserved_at_20[0x20];
990 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
991 u8 reserved_at_0[0xa0];
993 u8 min_time_between_cnps[0x20];
995 u8 reserved_at_c0[0x12];
997 u8 reserved_at_d8[0x5];
998 u8 cnp_802p_prio[0x3];
1000 u8 reserved_at_e0[0x720];
1003 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1004 u8 reserved_at_0[0x60];
1006 u8 reserved_at_60[0x4];
1007 u8 clamp_tgt_rate[0x1];
1008 u8 reserved_at_65[0x3];
1009 u8 clamp_tgt_rate_after_time_inc[0x1];
1010 u8 reserved_at_69[0x17];
1012 u8 reserved_at_80[0x20];
1014 u8 rpg_time_reset[0x20];
1016 u8 rpg_byte_reset[0x20];
1018 u8 rpg_threshold[0x20];
1020 u8 rpg_max_rate[0x20];
1022 u8 rpg_ai_rate[0x20];
1024 u8 rpg_hai_rate[0x20];
1028 u8 rpg_min_dec_fac[0x20];
1030 u8 rpg_min_rate[0x20];
1032 u8 reserved_at_1c0[0xe0];
1034 u8 rate_to_set_on_first_cnp[0x20];
1038 u8 dce_tcp_rtt[0x20];
1040 u8 rate_reduce_monitor_period[0x20];
1042 u8 reserved_at_320[0x20];
1044 u8 initial_alpha_value[0x20];
1046 u8 reserved_at_360[0x4a0];
1049 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1050 u8 reserved_at_0[0x80];
1052 u8 rppp_max_rps[0x20];
1054 u8 rpg_time_reset[0x20];
1056 u8 rpg_byte_reset[0x20];
1058 u8 rpg_threshold[0x20];
1060 u8 rpg_max_rate[0x20];
1062 u8 rpg_ai_rate[0x20];
1064 u8 rpg_hai_rate[0x20];
1068 u8 rpg_min_dec_fac[0x20];
1070 u8 rpg_min_rate[0x20];
1072 u8 reserved_at_1c0[0x640];
1076 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1077 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1078 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1081 struct mlx5_ifc_resize_field_select_bits {
1082 u8 resize_field_select[0x20];
1086 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1087 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1088 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1089 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1092 struct mlx5_ifc_modify_field_select_bits {
1093 u8 modify_field_select[0x20];
1096 struct mlx5_ifc_field_select_r_roce_np_bits {
1097 u8 field_select_r_roce_np[0x20];
1100 struct mlx5_ifc_field_select_r_roce_rp_bits {
1101 u8 field_select_r_roce_rp[0x20];
1105 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1106 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1107 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1108 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1109 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1110 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1111 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1112 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1113 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1114 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1117 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1118 u8 field_select_8021qaurp[0x20];
1121 struct mlx5_ifc_phys_layer_cntrs_bits {
1122 u8 time_since_last_clear_high[0x20];
1124 u8 time_since_last_clear_low[0x20];
1126 u8 symbol_errors_high[0x20];
1128 u8 symbol_errors_low[0x20];
1130 u8 sync_headers_errors_high[0x20];
1132 u8 sync_headers_errors_low[0x20];
1134 u8 edpl_bip_errors_lane0_high[0x20];
1136 u8 edpl_bip_errors_lane0_low[0x20];
1138 u8 edpl_bip_errors_lane1_high[0x20];
1140 u8 edpl_bip_errors_lane1_low[0x20];
1142 u8 edpl_bip_errors_lane2_high[0x20];
1144 u8 edpl_bip_errors_lane2_low[0x20];
1146 u8 edpl_bip_errors_lane3_high[0x20];
1148 u8 edpl_bip_errors_lane3_low[0x20];
1150 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1152 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1154 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1156 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1158 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1160 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1162 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1164 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1166 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1168 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1170 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1172 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1174 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1176 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1178 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1180 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1182 u8 rs_fec_corrected_blocks_high[0x20];
1184 u8 rs_fec_corrected_blocks_low[0x20];
1186 u8 rs_fec_uncorrectable_blocks_high[0x20];
1188 u8 rs_fec_uncorrectable_blocks_low[0x20];
1190 u8 rs_fec_no_errors_blocks_high[0x20];
1192 u8 rs_fec_no_errors_blocks_low[0x20];
1194 u8 rs_fec_single_error_blocks_high[0x20];
1196 u8 rs_fec_single_error_blocks_low[0x20];
1198 u8 rs_fec_corrected_symbols_total_high[0x20];
1200 u8 rs_fec_corrected_symbols_total_low[0x20];
1202 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1204 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1206 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1208 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1210 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1212 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1214 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1216 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1218 u8 link_down_events[0x20];
1220 u8 successful_recovery_events[0x20];
1222 u8 reserved_at_640[0x180];
1225 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1226 u8 transmit_queue_high[0x20];
1228 u8 transmit_queue_low[0x20];
1230 u8 reserved_at_40[0x780];
1233 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1234 u8 rx_octets_high[0x20];
1236 u8 rx_octets_low[0x20];
1238 u8 reserved_at_40[0xc0];
1240 u8 rx_frames_high[0x20];
1242 u8 rx_frames_low[0x20];
1244 u8 tx_octets_high[0x20];
1246 u8 tx_octets_low[0x20];
1248 u8 reserved_at_180[0xc0];
1250 u8 tx_frames_high[0x20];
1252 u8 tx_frames_low[0x20];
1254 u8 rx_pause_high[0x20];
1256 u8 rx_pause_low[0x20];
1258 u8 rx_pause_duration_high[0x20];
1260 u8 rx_pause_duration_low[0x20];
1262 u8 tx_pause_high[0x20];
1264 u8 tx_pause_low[0x20];
1266 u8 tx_pause_duration_high[0x20];
1268 u8 tx_pause_duration_low[0x20];
1270 u8 rx_pause_transition_high[0x20];
1272 u8 rx_pause_transition_low[0x20];
1274 u8 reserved_at_3c0[0x400];
1277 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1278 u8 port_transmit_wait_high[0x20];
1280 u8 port_transmit_wait_low[0x20];
1282 u8 reserved_at_40[0x780];
1285 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1286 u8 dot3stats_alignment_errors_high[0x20];
1288 u8 dot3stats_alignment_errors_low[0x20];
1290 u8 dot3stats_fcs_errors_high[0x20];
1292 u8 dot3stats_fcs_errors_low[0x20];
1294 u8 dot3stats_single_collision_frames_high[0x20];
1296 u8 dot3stats_single_collision_frames_low[0x20];
1298 u8 dot3stats_multiple_collision_frames_high[0x20];
1300 u8 dot3stats_multiple_collision_frames_low[0x20];
1302 u8 dot3stats_sqe_test_errors_high[0x20];
1304 u8 dot3stats_sqe_test_errors_low[0x20];
1306 u8 dot3stats_deferred_transmissions_high[0x20];
1308 u8 dot3stats_deferred_transmissions_low[0x20];
1310 u8 dot3stats_late_collisions_high[0x20];
1312 u8 dot3stats_late_collisions_low[0x20];
1314 u8 dot3stats_excessive_collisions_high[0x20];
1316 u8 dot3stats_excessive_collisions_low[0x20];
1318 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1320 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1322 u8 dot3stats_carrier_sense_errors_high[0x20];
1324 u8 dot3stats_carrier_sense_errors_low[0x20];
1326 u8 dot3stats_frame_too_longs_high[0x20];
1328 u8 dot3stats_frame_too_longs_low[0x20];
1330 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1332 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1334 u8 dot3stats_symbol_errors_high[0x20];
1336 u8 dot3stats_symbol_errors_low[0x20];
1338 u8 dot3control_in_unknown_opcodes_high[0x20];
1340 u8 dot3control_in_unknown_opcodes_low[0x20];
1342 u8 dot3in_pause_frames_high[0x20];
1344 u8 dot3in_pause_frames_low[0x20];
1346 u8 dot3out_pause_frames_high[0x20];
1348 u8 dot3out_pause_frames_low[0x20];
1350 u8 reserved_at_400[0x3c0];
1353 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1354 u8 ether_stats_drop_events_high[0x20];
1356 u8 ether_stats_drop_events_low[0x20];
1358 u8 ether_stats_octets_high[0x20];
1360 u8 ether_stats_octets_low[0x20];
1362 u8 ether_stats_pkts_high[0x20];
1364 u8 ether_stats_pkts_low[0x20];
1366 u8 ether_stats_broadcast_pkts_high[0x20];
1368 u8 ether_stats_broadcast_pkts_low[0x20];
1370 u8 ether_stats_multicast_pkts_high[0x20];
1372 u8 ether_stats_multicast_pkts_low[0x20];
1374 u8 ether_stats_crc_align_errors_high[0x20];
1376 u8 ether_stats_crc_align_errors_low[0x20];
1378 u8 ether_stats_undersize_pkts_high[0x20];
1380 u8 ether_stats_undersize_pkts_low[0x20];
1382 u8 ether_stats_oversize_pkts_high[0x20];
1384 u8 ether_stats_oversize_pkts_low[0x20];
1386 u8 ether_stats_fragments_high[0x20];
1388 u8 ether_stats_fragments_low[0x20];
1390 u8 ether_stats_jabbers_high[0x20];
1392 u8 ether_stats_jabbers_low[0x20];
1394 u8 ether_stats_collisions_high[0x20];
1396 u8 ether_stats_collisions_low[0x20];
1398 u8 ether_stats_pkts64octets_high[0x20];
1400 u8 ether_stats_pkts64octets_low[0x20];
1402 u8 ether_stats_pkts65to127octets_high[0x20];
1404 u8 ether_stats_pkts65to127octets_low[0x20];
1406 u8 ether_stats_pkts128to255octets_high[0x20];
1408 u8 ether_stats_pkts128to255octets_low[0x20];
1410 u8 ether_stats_pkts256to511octets_high[0x20];
1412 u8 ether_stats_pkts256to511octets_low[0x20];
1414 u8 ether_stats_pkts512to1023octets_high[0x20];
1416 u8 ether_stats_pkts512to1023octets_low[0x20];
1418 u8 ether_stats_pkts1024to1518octets_high[0x20];
1420 u8 ether_stats_pkts1024to1518octets_low[0x20];
1422 u8 ether_stats_pkts1519to2047octets_high[0x20];
1424 u8 ether_stats_pkts1519to2047octets_low[0x20];
1426 u8 ether_stats_pkts2048to4095octets_high[0x20];
1428 u8 ether_stats_pkts2048to4095octets_low[0x20];
1430 u8 ether_stats_pkts4096to8191octets_high[0x20];
1432 u8 ether_stats_pkts4096to8191octets_low[0x20];
1434 u8 ether_stats_pkts8192to10239octets_high[0x20];
1436 u8 ether_stats_pkts8192to10239octets_low[0x20];
1438 u8 reserved_at_540[0x280];
1441 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1442 u8 if_in_octets_high[0x20];
1444 u8 if_in_octets_low[0x20];
1446 u8 if_in_ucast_pkts_high[0x20];
1448 u8 if_in_ucast_pkts_low[0x20];
1450 u8 if_in_discards_high[0x20];
1452 u8 if_in_discards_low[0x20];
1454 u8 if_in_errors_high[0x20];
1456 u8 if_in_errors_low[0x20];
1458 u8 if_in_unknown_protos_high[0x20];
1460 u8 if_in_unknown_protos_low[0x20];
1462 u8 if_out_octets_high[0x20];
1464 u8 if_out_octets_low[0x20];
1466 u8 if_out_ucast_pkts_high[0x20];
1468 u8 if_out_ucast_pkts_low[0x20];
1470 u8 if_out_discards_high[0x20];
1472 u8 if_out_discards_low[0x20];
1474 u8 if_out_errors_high[0x20];
1476 u8 if_out_errors_low[0x20];
1478 u8 if_in_multicast_pkts_high[0x20];
1480 u8 if_in_multicast_pkts_low[0x20];
1482 u8 if_in_broadcast_pkts_high[0x20];
1484 u8 if_in_broadcast_pkts_low[0x20];
1486 u8 if_out_multicast_pkts_high[0x20];
1488 u8 if_out_multicast_pkts_low[0x20];
1490 u8 if_out_broadcast_pkts_high[0x20];
1492 u8 if_out_broadcast_pkts_low[0x20];
1494 u8 reserved_at_340[0x480];
1497 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1498 u8 a_frames_transmitted_ok_high[0x20];
1500 u8 a_frames_transmitted_ok_low[0x20];
1502 u8 a_frames_received_ok_high[0x20];
1504 u8 a_frames_received_ok_low[0x20];
1506 u8 a_frame_check_sequence_errors_high[0x20];
1508 u8 a_frame_check_sequence_errors_low[0x20];
1510 u8 a_alignment_errors_high[0x20];
1512 u8 a_alignment_errors_low[0x20];
1514 u8 a_octets_transmitted_ok_high[0x20];
1516 u8 a_octets_transmitted_ok_low[0x20];
1518 u8 a_octets_received_ok_high[0x20];
1520 u8 a_octets_received_ok_low[0x20];
1522 u8 a_multicast_frames_xmitted_ok_high[0x20];
1524 u8 a_multicast_frames_xmitted_ok_low[0x20];
1526 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1528 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1530 u8 a_multicast_frames_received_ok_high[0x20];
1532 u8 a_multicast_frames_received_ok_low[0x20];
1534 u8 a_broadcast_frames_received_ok_high[0x20];
1536 u8 a_broadcast_frames_received_ok_low[0x20];
1538 u8 a_in_range_length_errors_high[0x20];
1540 u8 a_in_range_length_errors_low[0x20];
1542 u8 a_out_of_range_length_field_high[0x20];
1544 u8 a_out_of_range_length_field_low[0x20];
1546 u8 a_frame_too_long_errors_high[0x20];
1548 u8 a_frame_too_long_errors_low[0x20];
1550 u8 a_symbol_error_during_carrier_high[0x20];
1552 u8 a_symbol_error_during_carrier_low[0x20];
1554 u8 a_mac_control_frames_transmitted_high[0x20];
1556 u8 a_mac_control_frames_transmitted_low[0x20];
1558 u8 a_mac_control_frames_received_high[0x20];
1560 u8 a_mac_control_frames_received_low[0x20];
1562 u8 a_unsupported_opcodes_received_high[0x20];
1564 u8 a_unsupported_opcodes_received_low[0x20];
1566 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1568 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1570 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1572 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1574 u8 reserved_at_4c0[0x300];
1577 struct mlx5_ifc_cmd_inter_comp_event_bits {
1578 u8 command_completion_vector[0x20];
1580 u8 reserved_at_20[0xc0];
1583 struct mlx5_ifc_stall_vl_event_bits {
1584 u8 reserved_at_0[0x18];
1586 u8 reserved_at_19[0x3];
1589 u8 reserved_at_20[0xa0];
1592 struct mlx5_ifc_db_bf_congestion_event_bits {
1593 u8 event_subtype[0x8];
1594 u8 reserved_at_8[0x8];
1595 u8 congestion_level[0x8];
1596 u8 reserved_at_18[0x8];
1598 u8 reserved_at_20[0xa0];
1601 struct mlx5_ifc_gpio_event_bits {
1602 u8 reserved_at_0[0x60];
1604 u8 gpio_event_hi[0x20];
1606 u8 gpio_event_lo[0x20];
1608 u8 reserved_at_a0[0x40];
1611 struct mlx5_ifc_port_state_change_event_bits {
1612 u8 reserved_at_0[0x40];
1615 u8 reserved_at_44[0x1c];
1617 u8 reserved_at_60[0x80];
1620 struct mlx5_ifc_dropped_packet_logged_bits {
1621 u8 reserved_at_0[0xe0];
1625 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1626 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1629 struct mlx5_ifc_cq_error_bits {
1630 u8 reserved_at_0[0x8];
1633 u8 reserved_at_20[0x20];
1635 u8 reserved_at_40[0x18];
1638 u8 reserved_at_60[0x80];
1641 struct mlx5_ifc_rdma_page_fault_event_bits {
1642 u8 bytes_committed[0x20];
1646 u8 reserved_at_40[0x10];
1647 u8 packet_len[0x10];
1649 u8 rdma_op_len[0x20];
1653 u8 reserved_at_c0[0x5];
1660 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1661 u8 bytes_committed[0x20];
1663 u8 reserved_at_20[0x10];
1666 u8 reserved_at_40[0x10];
1669 u8 reserved_at_60[0x60];
1671 u8 reserved_at_c0[0x5];
1678 struct mlx5_ifc_qp_events_bits {
1679 u8 reserved_at_0[0xa0];
1682 u8 reserved_at_a8[0x18];
1684 u8 reserved_at_c0[0x8];
1685 u8 qpn_rqn_sqn[0x18];
1688 struct mlx5_ifc_dct_events_bits {
1689 u8 reserved_at_0[0xc0];
1691 u8 reserved_at_c0[0x8];
1692 u8 dct_number[0x18];
1695 struct mlx5_ifc_comp_event_bits {
1696 u8 reserved_at_0[0xc0];
1698 u8 reserved_at_c0[0x8];
1703 MLX5_QPC_STATE_RST = 0x0,
1704 MLX5_QPC_STATE_INIT = 0x1,
1705 MLX5_QPC_STATE_RTR = 0x2,
1706 MLX5_QPC_STATE_RTS = 0x3,
1707 MLX5_QPC_STATE_SQER = 0x4,
1708 MLX5_QPC_STATE_ERR = 0x6,
1709 MLX5_QPC_STATE_SQD = 0x7,
1710 MLX5_QPC_STATE_SUSPENDED = 0x9,
1714 MLX5_QPC_ST_RC = 0x0,
1715 MLX5_QPC_ST_UC = 0x1,
1716 MLX5_QPC_ST_UD = 0x2,
1717 MLX5_QPC_ST_XRC = 0x3,
1718 MLX5_QPC_ST_DCI = 0x5,
1719 MLX5_QPC_ST_QP0 = 0x7,
1720 MLX5_QPC_ST_QP1 = 0x8,
1721 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1722 MLX5_QPC_ST_REG_UMR = 0xc,
1726 MLX5_QPC_PM_STATE_ARMED = 0x0,
1727 MLX5_QPC_PM_STATE_REARM = 0x1,
1728 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1729 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1733 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1734 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1738 MLX5_QPC_MTU_256_BYTES = 0x1,
1739 MLX5_QPC_MTU_512_BYTES = 0x2,
1740 MLX5_QPC_MTU_1K_BYTES = 0x3,
1741 MLX5_QPC_MTU_2K_BYTES = 0x4,
1742 MLX5_QPC_MTU_4K_BYTES = 0x5,
1743 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1747 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1748 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1749 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1750 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1751 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1752 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1753 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1754 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1758 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1759 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1760 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1764 MLX5_QPC_CS_RES_DISABLE = 0x0,
1765 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1766 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1769 struct mlx5_ifc_qpc_bits {
1771 u8 reserved_at_4[0x4];
1773 u8 reserved_at_10[0x3];
1775 u8 reserved_at_15[0x7];
1776 u8 end_padding_mode[0x2];
1777 u8 reserved_at_1e[0x2];
1779 u8 wq_signature[0x1];
1780 u8 block_lb_mc[0x1];
1781 u8 atomic_like_write_en[0x1];
1782 u8 latency_sensitive[0x1];
1783 u8 reserved_at_24[0x1];
1784 u8 drain_sigerr[0x1];
1785 u8 reserved_at_26[0x2];
1789 u8 log_msg_max[0x5];
1790 u8 reserved_at_48[0x1];
1791 u8 log_rq_size[0x4];
1792 u8 log_rq_stride[0x3];
1794 u8 log_sq_size[0x4];
1795 u8 reserved_at_55[0x6];
1797 u8 reserved_at_5c[0x4];
1799 u8 counter_set_id[0x8];
1802 u8 reserved_at_80[0x8];
1803 u8 user_index[0x18];
1805 u8 reserved_at_a0[0x3];
1806 u8 log_page_size[0x5];
1807 u8 remote_qpn[0x18];
1809 struct mlx5_ifc_ads_bits primary_address_path;
1811 struct mlx5_ifc_ads_bits secondary_address_path;
1813 u8 log_ack_req_freq[0x4];
1814 u8 reserved_at_384[0x4];
1815 u8 log_sra_max[0x3];
1816 u8 reserved_at_38b[0x2];
1817 u8 retry_count[0x3];
1819 u8 reserved_at_393[0x1];
1821 u8 cur_rnr_retry[0x3];
1822 u8 cur_retry_count[0x3];
1823 u8 reserved_at_39b[0x5];
1825 u8 reserved_at_3a0[0x20];
1827 u8 reserved_at_3c0[0x8];
1828 u8 next_send_psn[0x18];
1830 u8 reserved_at_3e0[0x8];
1833 u8 reserved_at_400[0x40];
1835 u8 reserved_at_440[0x8];
1836 u8 last_acked_psn[0x18];
1838 u8 reserved_at_460[0x8];
1841 u8 reserved_at_480[0x8];
1842 u8 log_rra_max[0x3];
1843 u8 reserved_at_48b[0x1];
1844 u8 atomic_mode[0x4];
1848 u8 reserved_at_493[0x1];
1849 u8 page_offset[0x6];
1850 u8 reserved_at_49a[0x3];
1851 u8 cd_slave_receive[0x1];
1852 u8 cd_slave_send[0x1];
1855 u8 reserved_at_4a0[0x3];
1856 u8 min_rnr_nak[0x5];
1857 u8 next_rcv_psn[0x18];
1859 u8 reserved_at_4c0[0x8];
1862 u8 reserved_at_4e0[0x8];
1869 u8 reserved_at_560[0x5];
1873 u8 reserved_at_580[0x8];
1876 u8 hw_sq_wqebb_counter[0x10];
1877 u8 sw_sq_wqebb_counter[0x10];
1879 u8 hw_rq_counter[0x20];
1881 u8 sw_rq_counter[0x20];
1883 u8 reserved_at_600[0x20];
1885 u8 reserved_at_620[0xf];
1890 u8 dc_access_key[0x40];
1892 u8 reserved_at_680[0xc0];
1895 struct mlx5_ifc_roce_addr_layout_bits {
1896 u8 source_l3_address[16][0x8];
1898 u8 reserved_at_80[0x3];
1901 u8 source_mac_47_32[0x10];
1903 u8 source_mac_31_0[0x20];
1905 u8 reserved_at_c0[0x14];
1906 u8 roce_l3_type[0x4];
1907 u8 roce_version[0x8];
1909 u8 reserved_at_e0[0x20];
1912 union mlx5_ifc_hca_cap_union_bits {
1913 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1914 struct mlx5_ifc_odp_cap_bits odp_cap;
1915 struct mlx5_ifc_atomic_caps_bits atomic_caps;
1916 struct mlx5_ifc_roce_cap_bits roce_cap;
1917 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1918 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1919 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
1920 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
1921 u8 reserved_at_0[0x8000];
1925 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
1926 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
1927 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
1930 struct mlx5_ifc_flow_context_bits {
1931 u8 reserved_at_0[0x20];
1935 u8 reserved_at_40[0x8];
1938 u8 reserved_at_60[0x10];
1941 u8 reserved_at_80[0x8];
1942 u8 destination_list_size[0x18];
1944 u8 reserved_at_a0[0x160];
1946 struct mlx5_ifc_fte_match_param_bits match_value;
1948 u8 reserved_at_1200[0x600];
1950 struct mlx5_ifc_dest_format_struct_bits destination[0];
1954 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
1955 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
1958 struct mlx5_ifc_xrc_srqc_bits {
1960 u8 log_xrc_srq_size[0x4];
1961 u8 reserved_at_8[0x18];
1963 u8 wq_signature[0x1];
1965 u8 reserved_at_22[0x1];
1967 u8 basic_cyclic_rcv_wqe[0x1];
1968 u8 log_rq_stride[0x3];
1971 u8 page_offset[0x6];
1972 u8 reserved_at_46[0x2];
1975 u8 reserved_at_60[0x20];
1977 u8 user_index_equal_xrc_srqn[0x1];
1978 u8 reserved_at_81[0x1];
1979 u8 log_page_size[0x6];
1980 u8 user_index[0x18];
1982 u8 reserved_at_a0[0x20];
1984 u8 reserved_at_c0[0x8];
1990 u8 reserved_at_100[0x40];
1992 u8 db_record_addr_h[0x20];
1994 u8 db_record_addr_l[0x1e];
1995 u8 reserved_at_17e[0x2];
1997 u8 reserved_at_180[0x80];
2000 struct mlx5_ifc_traffic_counter_bits {
2006 struct mlx5_ifc_tisc_bits {
2007 u8 reserved_at_0[0xc];
2009 u8 reserved_at_10[0x10];
2011 u8 reserved_at_20[0x100];
2013 u8 reserved_at_120[0x8];
2014 u8 transport_domain[0x18];
2016 u8 reserved_at_140[0x3c0];
2020 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2021 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2025 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2026 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2030 MLX5_RX_HASH_FN_NONE = 0x0,
2031 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2032 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2036 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2037 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2040 struct mlx5_ifc_tirc_bits {
2041 u8 reserved_at_0[0x20];
2044 u8 reserved_at_24[0x1c];
2046 u8 reserved_at_40[0x40];
2048 u8 reserved_at_80[0x4];
2049 u8 lro_timeout_period_usecs[0x10];
2050 u8 lro_enable_mask[0x4];
2051 u8 lro_max_ip_payload_size[0x8];
2053 u8 reserved_at_a0[0x40];
2055 u8 reserved_at_e0[0x8];
2056 u8 inline_rqn[0x18];
2058 u8 rx_hash_symmetric[0x1];
2059 u8 reserved_at_101[0x1];
2060 u8 tunneled_offload_en[0x1];
2061 u8 reserved_at_103[0x5];
2062 u8 indirect_table[0x18];
2065 u8 reserved_at_124[0x2];
2066 u8 self_lb_block[0x2];
2067 u8 transport_domain[0x18];
2069 u8 rx_hash_toeplitz_key[10][0x20];
2071 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2073 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2075 u8 reserved_at_2c0[0x4c0];
2079 MLX5_SRQC_STATE_GOOD = 0x0,
2080 MLX5_SRQC_STATE_ERROR = 0x1,
2083 struct mlx5_ifc_srqc_bits {
2085 u8 log_srq_size[0x4];
2086 u8 reserved_at_8[0x18];
2088 u8 wq_signature[0x1];
2090 u8 reserved_at_22[0x1];
2092 u8 reserved_at_24[0x1];
2093 u8 log_rq_stride[0x3];
2096 u8 page_offset[0x6];
2097 u8 reserved_at_46[0x2];
2100 u8 reserved_at_60[0x20];
2102 u8 reserved_at_80[0x2];
2103 u8 log_page_size[0x6];
2104 u8 reserved_at_88[0x18];
2106 u8 reserved_at_a0[0x20];
2108 u8 reserved_at_c0[0x8];
2114 u8 reserved_at_100[0x40];
2118 u8 reserved_at_180[0x80];
2122 MLX5_SQC_STATE_RST = 0x0,
2123 MLX5_SQC_STATE_RDY = 0x1,
2124 MLX5_SQC_STATE_ERR = 0x3,
2127 struct mlx5_ifc_sqc_bits {
2131 u8 flush_in_error_en[0x1];
2132 u8 reserved_at_4[0x4];
2134 u8 reserved_at_c[0x14];
2136 u8 reserved_at_20[0x8];
2137 u8 user_index[0x18];
2139 u8 reserved_at_40[0x8];
2142 u8 reserved_at_60[0xa0];
2144 u8 tis_lst_sz[0x10];
2145 u8 reserved_at_110[0x10];
2147 u8 reserved_at_120[0x40];
2149 u8 reserved_at_160[0x8];
2152 struct mlx5_ifc_wq_bits wq;
2155 struct mlx5_ifc_rqtc_bits {
2156 u8 reserved_at_0[0xa0];
2158 u8 reserved_at_a0[0x10];
2159 u8 rqt_max_size[0x10];
2161 u8 reserved_at_c0[0x10];
2162 u8 rqt_actual_size[0x10];
2164 u8 reserved_at_e0[0x6a0];
2166 struct mlx5_ifc_rq_num_bits rq_num[0];
2170 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2171 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2175 MLX5_RQC_STATE_RST = 0x0,
2176 MLX5_RQC_STATE_RDY = 0x1,
2177 MLX5_RQC_STATE_ERR = 0x3,
2180 struct mlx5_ifc_rqc_bits {
2182 u8 reserved_at_1[0x2];
2184 u8 mem_rq_type[0x4];
2186 u8 reserved_at_c[0x1];
2187 u8 flush_in_error_en[0x1];
2188 u8 reserved_at_e[0x12];
2190 u8 reserved_at_20[0x8];
2191 u8 user_index[0x18];
2193 u8 reserved_at_40[0x8];
2196 u8 counter_set_id[0x8];
2197 u8 reserved_at_68[0x18];
2199 u8 reserved_at_80[0x8];
2202 u8 reserved_at_a0[0xe0];
2204 struct mlx5_ifc_wq_bits wq;
2208 MLX5_RMPC_STATE_RDY = 0x1,
2209 MLX5_RMPC_STATE_ERR = 0x3,
2212 struct mlx5_ifc_rmpc_bits {
2213 u8 reserved_at_0[0x8];
2215 u8 reserved_at_c[0x14];
2217 u8 basic_cyclic_rcv_wqe[0x1];
2218 u8 reserved_at_21[0x1f];
2220 u8 reserved_at_40[0x140];
2222 struct mlx5_ifc_wq_bits wq;
2225 struct mlx5_ifc_nic_vport_context_bits {
2226 u8 reserved_at_0[0x1f];
2229 u8 arm_change_event[0x1];
2230 u8 reserved_at_21[0x1a];
2231 u8 event_on_mtu[0x1];
2232 u8 event_on_promisc_change[0x1];
2233 u8 event_on_vlan_change[0x1];
2234 u8 event_on_mc_address_change[0x1];
2235 u8 event_on_uc_address_change[0x1];
2237 u8 reserved_at_40[0xf0];
2241 u8 system_image_guid[0x40];
2245 u8 reserved_at_200[0x140];
2246 u8 qkey_violation_counter[0x10];
2247 u8 reserved_at_350[0x430];
2251 u8 promisc_all[0x1];
2252 u8 reserved_at_783[0x2];
2253 u8 allowed_list_type[0x3];
2254 u8 reserved_at_788[0xc];
2255 u8 allowed_list_size[0xc];
2257 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2259 u8 reserved_at_7e0[0x20];
2261 u8 current_uc_mac_address[0][0x40];
2265 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2266 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2267 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2270 struct mlx5_ifc_mkc_bits {
2271 u8 reserved_at_0[0x1];
2273 u8 reserved_at_2[0xd];
2274 u8 small_fence_on_rdma_read_response[0x1];
2281 u8 access_mode[0x2];
2282 u8 reserved_at_18[0x8];
2287 u8 reserved_at_40[0x20];
2292 u8 reserved_at_63[0x2];
2293 u8 expected_sigerr_count[0x1];
2294 u8 reserved_at_66[0x1];
2298 u8 start_addr[0x40];
2302 u8 bsf_octword_size[0x20];
2304 u8 reserved_at_120[0x80];
2306 u8 translations_octword_size[0x20];
2308 u8 reserved_at_1c0[0x1b];
2309 u8 log_page_size[0x5];
2311 u8 reserved_at_1e0[0x20];
2314 struct mlx5_ifc_pkey_bits {
2315 u8 reserved_at_0[0x10];
2319 struct mlx5_ifc_array128_auto_bits {
2320 u8 array128_auto[16][0x8];
2323 struct mlx5_ifc_hca_vport_context_bits {
2324 u8 field_select[0x20];
2326 u8 reserved_at_20[0xe0];
2328 u8 sm_virt_aware[0x1];
2331 u8 grh_required[0x1];
2332 u8 reserved_at_104[0xc];
2333 u8 port_physical_state[0x4];
2334 u8 vport_state_policy[0x4];
2336 u8 vport_state[0x4];
2338 u8 reserved_at_120[0x20];
2340 u8 system_image_guid[0x40];
2348 u8 cap_mask1_field_select[0x20];
2352 u8 cap_mask2_field_select[0x20];
2354 u8 reserved_at_280[0x80];
2357 u8 reserved_at_310[0x4];
2358 u8 init_type_reply[0x4];
2360 u8 subnet_timeout[0x5];
2364 u8 reserved_at_334[0xc];
2366 u8 qkey_violation_counter[0x10];
2367 u8 pkey_violation_counter[0x10];
2369 u8 reserved_at_360[0xca0];
2372 struct mlx5_ifc_esw_vport_context_bits {
2373 u8 reserved_at_0[0x3];
2374 u8 vport_svlan_strip[0x1];
2375 u8 vport_cvlan_strip[0x1];
2376 u8 vport_svlan_insert[0x1];
2377 u8 vport_cvlan_insert[0x2];
2378 u8 reserved_at_8[0x18];
2380 u8 reserved_at_20[0x20];
2389 u8 reserved_at_60[0x7a0];
2393 MLX5_EQC_STATUS_OK = 0x0,
2394 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2398 MLX5_EQC_ST_ARMED = 0x9,
2399 MLX5_EQC_ST_FIRED = 0xa,
2402 struct mlx5_ifc_eqc_bits {
2404 u8 reserved_at_4[0x9];
2407 u8 reserved_at_f[0x5];
2409 u8 reserved_at_18[0x8];
2411 u8 reserved_at_20[0x20];
2413 u8 reserved_at_40[0x14];
2414 u8 page_offset[0x6];
2415 u8 reserved_at_5a[0x6];
2417 u8 reserved_at_60[0x3];
2418 u8 log_eq_size[0x5];
2421 u8 reserved_at_80[0x20];
2423 u8 reserved_at_a0[0x18];
2426 u8 reserved_at_c0[0x3];
2427 u8 log_page_size[0x5];
2428 u8 reserved_at_c8[0x18];
2430 u8 reserved_at_e0[0x60];
2432 u8 reserved_at_140[0x8];
2433 u8 consumer_counter[0x18];
2435 u8 reserved_at_160[0x8];
2436 u8 producer_counter[0x18];
2438 u8 reserved_at_180[0x80];
2442 MLX5_DCTC_STATE_ACTIVE = 0x0,
2443 MLX5_DCTC_STATE_DRAINING = 0x1,
2444 MLX5_DCTC_STATE_DRAINED = 0x2,
2448 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2449 MLX5_DCTC_CS_RES_NA = 0x1,
2450 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2454 MLX5_DCTC_MTU_256_BYTES = 0x1,
2455 MLX5_DCTC_MTU_512_BYTES = 0x2,
2456 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2457 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2458 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2461 struct mlx5_ifc_dctc_bits {
2462 u8 reserved_at_0[0x4];
2464 u8 reserved_at_8[0x18];
2466 u8 reserved_at_20[0x8];
2467 u8 user_index[0x18];
2469 u8 reserved_at_40[0x8];
2472 u8 counter_set_id[0x8];
2473 u8 atomic_mode[0x4];
2477 u8 atomic_like_write_en[0x1];
2478 u8 latency_sensitive[0x1];
2481 u8 reserved_at_73[0xd];
2483 u8 reserved_at_80[0x8];
2485 u8 reserved_at_90[0x3];
2486 u8 min_rnr_nak[0x5];
2487 u8 reserved_at_98[0x8];
2489 u8 reserved_at_a0[0x8];
2492 u8 reserved_at_c0[0x8];
2496 u8 reserved_at_e8[0x4];
2497 u8 flow_label[0x14];
2499 u8 dc_access_key[0x40];
2501 u8 reserved_at_140[0x5];
2504 u8 pkey_index[0x10];
2506 u8 reserved_at_160[0x8];
2507 u8 my_addr_index[0x8];
2508 u8 reserved_at_170[0x8];
2511 u8 dc_access_key_violation_count[0x20];
2513 u8 reserved_at_1a0[0x14];
2519 u8 reserved_at_1c0[0x40];
2523 MLX5_CQC_STATUS_OK = 0x0,
2524 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2525 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2529 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2530 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2534 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2535 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2536 MLX5_CQC_ST_FIRED = 0xa,
2539 struct mlx5_ifc_cqc_bits {
2541 u8 reserved_at_4[0x4];
2544 u8 reserved_at_c[0x1];
2545 u8 scqe_break_moderation_en[0x1];
2547 u8 reserved_at_f[0x2];
2549 u8 mini_cqe_res_format[0x2];
2551 u8 reserved_at_18[0x8];
2553 u8 reserved_at_20[0x20];
2555 u8 reserved_at_40[0x14];
2556 u8 page_offset[0x6];
2557 u8 reserved_at_5a[0x6];
2559 u8 reserved_at_60[0x3];
2560 u8 log_cq_size[0x5];
2563 u8 reserved_at_80[0x4];
2565 u8 cq_max_count[0x10];
2567 u8 reserved_at_a0[0x18];
2570 u8 reserved_at_c0[0x3];
2571 u8 log_page_size[0x5];
2572 u8 reserved_at_c8[0x18];
2574 u8 reserved_at_e0[0x20];
2576 u8 reserved_at_100[0x8];
2577 u8 last_notified_index[0x18];
2579 u8 reserved_at_120[0x8];
2580 u8 last_solicit_index[0x18];
2582 u8 reserved_at_140[0x8];
2583 u8 consumer_counter[0x18];
2585 u8 reserved_at_160[0x8];
2586 u8 producer_counter[0x18];
2588 u8 reserved_at_180[0x40];
2593 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2594 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2595 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2596 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2597 u8 reserved_at_0[0x800];
2600 struct mlx5_ifc_query_adapter_param_block_bits {
2601 u8 reserved_at_0[0xc0];
2603 u8 reserved_at_c0[0x8];
2604 u8 ieee_vendor_id[0x18];
2606 u8 reserved_at_e0[0x10];
2607 u8 vsd_vendor_id[0x10];
2611 u8 vsd_contd_psid[16][0x8];
2614 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2615 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2616 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2617 u8 reserved_at_0[0x20];
2620 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2621 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2622 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2623 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2624 u8 reserved_at_0[0x20];
2627 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2628 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2629 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2630 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2631 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2632 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2633 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2634 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2635 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2636 u8 reserved_at_0[0x7c0];
2639 union mlx5_ifc_event_auto_bits {
2640 struct mlx5_ifc_comp_event_bits comp_event;
2641 struct mlx5_ifc_dct_events_bits dct_events;
2642 struct mlx5_ifc_qp_events_bits qp_events;
2643 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2644 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2645 struct mlx5_ifc_cq_error_bits cq_error;
2646 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2647 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2648 struct mlx5_ifc_gpio_event_bits gpio_event;
2649 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2650 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2651 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2652 u8 reserved_at_0[0xe0];
2655 struct mlx5_ifc_health_buffer_bits {
2656 u8 reserved_at_0[0x100];
2658 u8 assert_existptr[0x20];
2660 u8 assert_callra[0x20];
2662 u8 reserved_at_140[0x40];
2664 u8 fw_version[0x20];
2668 u8 reserved_at_1c0[0x20];
2670 u8 irisc_index[0x8];
2675 struct mlx5_ifc_register_loopback_control_bits {
2677 u8 reserved_at_1[0x7];
2679 u8 reserved_at_10[0x10];
2681 u8 reserved_at_20[0x60];
2684 struct mlx5_ifc_teardown_hca_out_bits {
2686 u8 reserved_at_8[0x18];
2690 u8 reserved_at_40[0x40];
2694 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2695 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2698 struct mlx5_ifc_teardown_hca_in_bits {
2700 u8 reserved_at_10[0x10];
2702 u8 reserved_at_20[0x10];
2705 u8 reserved_at_40[0x10];
2708 u8 reserved_at_60[0x20];
2711 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2713 u8 reserved_at_8[0x18];
2717 u8 reserved_at_40[0x40];
2720 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2722 u8 reserved_at_10[0x10];
2724 u8 reserved_at_20[0x10];
2727 u8 reserved_at_40[0x8];
2730 u8 reserved_at_60[0x20];
2732 u8 opt_param_mask[0x20];
2734 u8 reserved_at_a0[0x20];
2736 struct mlx5_ifc_qpc_bits qpc;
2738 u8 reserved_at_800[0x80];
2741 struct mlx5_ifc_sqd2rts_qp_out_bits {
2743 u8 reserved_at_8[0x18];
2747 u8 reserved_at_40[0x40];
2750 struct mlx5_ifc_sqd2rts_qp_in_bits {
2752 u8 reserved_at_10[0x10];
2754 u8 reserved_at_20[0x10];
2757 u8 reserved_at_40[0x8];
2760 u8 reserved_at_60[0x20];
2762 u8 opt_param_mask[0x20];
2764 u8 reserved_at_a0[0x20];
2766 struct mlx5_ifc_qpc_bits qpc;
2768 u8 reserved_at_800[0x80];
2771 struct mlx5_ifc_set_roce_address_out_bits {
2773 u8 reserved_at_8[0x18];
2777 u8 reserved_at_40[0x40];
2780 struct mlx5_ifc_set_roce_address_in_bits {
2782 u8 reserved_at_10[0x10];
2784 u8 reserved_at_20[0x10];
2787 u8 roce_address_index[0x10];
2788 u8 reserved_at_50[0x10];
2790 u8 reserved_at_60[0x20];
2792 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2795 struct mlx5_ifc_set_mad_demux_out_bits {
2797 u8 reserved_at_8[0x18];
2801 u8 reserved_at_40[0x40];
2805 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
2806 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
2809 struct mlx5_ifc_set_mad_demux_in_bits {
2811 u8 reserved_at_10[0x10];
2813 u8 reserved_at_20[0x10];
2816 u8 reserved_at_40[0x20];
2818 u8 reserved_at_60[0x6];
2820 u8 reserved_at_68[0x18];
2823 struct mlx5_ifc_set_l2_table_entry_out_bits {
2825 u8 reserved_at_8[0x18];
2829 u8 reserved_at_40[0x40];
2832 struct mlx5_ifc_set_l2_table_entry_in_bits {
2834 u8 reserved_at_10[0x10];
2836 u8 reserved_at_20[0x10];
2839 u8 reserved_at_40[0x60];
2841 u8 reserved_at_a0[0x8];
2842 u8 table_index[0x18];
2844 u8 reserved_at_c0[0x20];
2846 u8 reserved_at_e0[0x13];
2850 struct mlx5_ifc_mac_address_layout_bits mac_address;
2852 u8 reserved_at_140[0xc0];
2855 struct mlx5_ifc_set_issi_out_bits {
2857 u8 reserved_at_8[0x18];
2861 u8 reserved_at_40[0x40];
2864 struct mlx5_ifc_set_issi_in_bits {
2866 u8 reserved_at_10[0x10];
2868 u8 reserved_at_20[0x10];
2871 u8 reserved_at_40[0x10];
2872 u8 current_issi[0x10];
2874 u8 reserved_at_60[0x20];
2877 struct mlx5_ifc_set_hca_cap_out_bits {
2879 u8 reserved_at_8[0x18];
2883 u8 reserved_at_40[0x40];
2886 struct mlx5_ifc_set_hca_cap_in_bits {
2888 u8 reserved_at_10[0x10];
2890 u8 reserved_at_20[0x10];
2893 u8 reserved_at_40[0x40];
2895 union mlx5_ifc_hca_cap_union_bits capability;
2899 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
2900 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
2901 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
2902 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
2905 struct mlx5_ifc_set_fte_out_bits {
2907 u8 reserved_at_8[0x18];
2911 u8 reserved_at_40[0x40];
2914 struct mlx5_ifc_set_fte_in_bits {
2916 u8 reserved_at_10[0x10];
2918 u8 reserved_at_20[0x10];
2921 u8 reserved_at_40[0x40];
2924 u8 reserved_at_88[0x18];
2926 u8 reserved_at_a0[0x8];
2929 u8 reserved_at_c0[0x18];
2930 u8 modify_enable_mask[0x8];
2932 u8 reserved_at_e0[0x20];
2934 u8 flow_index[0x20];
2936 u8 reserved_at_120[0xe0];
2938 struct mlx5_ifc_flow_context_bits flow_context;
2941 struct mlx5_ifc_rts2rts_qp_out_bits {
2943 u8 reserved_at_8[0x18];
2947 u8 reserved_at_40[0x40];
2950 struct mlx5_ifc_rts2rts_qp_in_bits {
2952 u8 reserved_at_10[0x10];
2954 u8 reserved_at_20[0x10];
2957 u8 reserved_at_40[0x8];
2960 u8 reserved_at_60[0x20];
2962 u8 opt_param_mask[0x20];
2964 u8 reserved_at_a0[0x20];
2966 struct mlx5_ifc_qpc_bits qpc;
2968 u8 reserved_at_800[0x80];
2971 struct mlx5_ifc_rtr2rts_qp_out_bits {
2973 u8 reserved_at_8[0x18];
2977 u8 reserved_at_40[0x40];
2980 struct mlx5_ifc_rtr2rts_qp_in_bits {
2982 u8 reserved_at_10[0x10];
2984 u8 reserved_at_20[0x10];
2987 u8 reserved_at_40[0x8];
2990 u8 reserved_at_60[0x20];
2992 u8 opt_param_mask[0x20];
2994 u8 reserved_at_a0[0x20];
2996 struct mlx5_ifc_qpc_bits qpc;
2998 u8 reserved_at_800[0x80];
3001 struct mlx5_ifc_rst2init_qp_out_bits {
3003 u8 reserved_at_8[0x18];
3007 u8 reserved_at_40[0x40];
3010 struct mlx5_ifc_rst2init_qp_in_bits {
3012 u8 reserved_at_10[0x10];
3014 u8 reserved_at_20[0x10];
3017 u8 reserved_at_40[0x8];
3020 u8 reserved_at_60[0x20];
3022 u8 opt_param_mask[0x20];
3024 u8 reserved_at_a0[0x20];
3026 struct mlx5_ifc_qpc_bits qpc;
3028 u8 reserved_at_800[0x80];
3031 struct mlx5_ifc_query_xrc_srq_out_bits {
3033 u8 reserved_at_8[0x18];
3037 u8 reserved_at_40[0x40];
3039 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3041 u8 reserved_at_280[0x600];
3046 struct mlx5_ifc_query_xrc_srq_in_bits {
3048 u8 reserved_at_10[0x10];
3050 u8 reserved_at_20[0x10];
3053 u8 reserved_at_40[0x8];
3056 u8 reserved_at_60[0x20];
3060 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3061 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3064 struct mlx5_ifc_query_vport_state_out_bits {
3066 u8 reserved_at_8[0x18];
3070 u8 reserved_at_40[0x20];
3072 u8 reserved_at_60[0x18];
3073 u8 admin_state[0x4];
3078 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3079 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3082 struct mlx5_ifc_query_vport_state_in_bits {
3084 u8 reserved_at_10[0x10];
3086 u8 reserved_at_20[0x10];
3089 u8 other_vport[0x1];
3090 u8 reserved_at_41[0xf];
3091 u8 vport_number[0x10];
3093 u8 reserved_at_60[0x20];
3096 struct mlx5_ifc_query_vport_counter_out_bits {
3098 u8 reserved_at_8[0x18];
3102 u8 reserved_at_40[0x40];
3104 struct mlx5_ifc_traffic_counter_bits received_errors;
3106 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3108 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3110 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3112 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3114 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3116 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3118 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3120 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3122 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3124 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3126 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3128 u8 reserved_at_680[0xa00];
3132 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3135 struct mlx5_ifc_query_vport_counter_in_bits {
3137 u8 reserved_at_10[0x10];
3139 u8 reserved_at_20[0x10];
3142 u8 other_vport[0x1];
3143 u8 reserved_at_41[0xf];
3144 u8 vport_number[0x10];
3146 u8 reserved_at_60[0x60];
3149 u8 reserved_at_c1[0x1f];
3151 u8 reserved_at_e0[0x20];
3154 struct mlx5_ifc_query_tis_out_bits {
3156 u8 reserved_at_8[0x18];
3160 u8 reserved_at_40[0x40];
3162 struct mlx5_ifc_tisc_bits tis_context;
3165 struct mlx5_ifc_query_tis_in_bits {
3167 u8 reserved_at_10[0x10];
3169 u8 reserved_at_20[0x10];
3172 u8 reserved_at_40[0x8];
3175 u8 reserved_at_60[0x20];
3178 struct mlx5_ifc_query_tir_out_bits {
3180 u8 reserved_at_8[0x18];
3184 u8 reserved_at_40[0xc0];
3186 struct mlx5_ifc_tirc_bits tir_context;
3189 struct mlx5_ifc_query_tir_in_bits {
3191 u8 reserved_at_10[0x10];
3193 u8 reserved_at_20[0x10];
3196 u8 reserved_at_40[0x8];
3199 u8 reserved_at_60[0x20];
3202 struct mlx5_ifc_query_srq_out_bits {
3204 u8 reserved_at_8[0x18];
3208 u8 reserved_at_40[0x40];
3210 struct mlx5_ifc_srqc_bits srq_context_entry;
3212 u8 reserved_at_280[0x600];
3217 struct mlx5_ifc_query_srq_in_bits {
3219 u8 reserved_at_10[0x10];
3221 u8 reserved_at_20[0x10];
3224 u8 reserved_at_40[0x8];
3227 u8 reserved_at_60[0x20];
3230 struct mlx5_ifc_query_sq_out_bits {
3232 u8 reserved_at_8[0x18];
3236 u8 reserved_at_40[0xc0];
3238 struct mlx5_ifc_sqc_bits sq_context;
3241 struct mlx5_ifc_query_sq_in_bits {
3243 u8 reserved_at_10[0x10];
3245 u8 reserved_at_20[0x10];
3248 u8 reserved_at_40[0x8];
3251 u8 reserved_at_60[0x20];
3254 struct mlx5_ifc_query_special_contexts_out_bits {
3256 u8 reserved_at_8[0x18];
3260 u8 reserved_at_40[0x20];
3265 struct mlx5_ifc_query_special_contexts_in_bits {
3267 u8 reserved_at_10[0x10];
3269 u8 reserved_at_20[0x10];
3272 u8 reserved_at_40[0x40];
3275 struct mlx5_ifc_query_rqt_out_bits {
3277 u8 reserved_at_8[0x18];
3281 u8 reserved_at_40[0xc0];
3283 struct mlx5_ifc_rqtc_bits rqt_context;
3286 struct mlx5_ifc_query_rqt_in_bits {
3288 u8 reserved_at_10[0x10];
3290 u8 reserved_at_20[0x10];
3293 u8 reserved_at_40[0x8];
3296 u8 reserved_at_60[0x20];
3299 struct mlx5_ifc_query_rq_out_bits {
3301 u8 reserved_at_8[0x18];
3305 u8 reserved_at_40[0xc0];
3307 struct mlx5_ifc_rqc_bits rq_context;
3310 struct mlx5_ifc_query_rq_in_bits {
3312 u8 reserved_at_10[0x10];
3314 u8 reserved_at_20[0x10];
3317 u8 reserved_at_40[0x8];
3320 u8 reserved_at_60[0x20];
3323 struct mlx5_ifc_query_roce_address_out_bits {
3325 u8 reserved_at_8[0x18];
3329 u8 reserved_at_40[0x40];
3331 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3334 struct mlx5_ifc_query_roce_address_in_bits {
3336 u8 reserved_at_10[0x10];
3338 u8 reserved_at_20[0x10];
3341 u8 roce_address_index[0x10];
3342 u8 reserved_at_50[0x10];
3344 u8 reserved_at_60[0x20];
3347 struct mlx5_ifc_query_rmp_out_bits {
3349 u8 reserved_at_8[0x18];
3353 u8 reserved_at_40[0xc0];
3355 struct mlx5_ifc_rmpc_bits rmp_context;
3358 struct mlx5_ifc_query_rmp_in_bits {
3360 u8 reserved_at_10[0x10];
3362 u8 reserved_at_20[0x10];
3365 u8 reserved_at_40[0x8];
3368 u8 reserved_at_60[0x20];
3371 struct mlx5_ifc_query_qp_out_bits {
3373 u8 reserved_at_8[0x18];
3377 u8 reserved_at_40[0x40];
3379 u8 opt_param_mask[0x20];
3381 u8 reserved_at_a0[0x20];
3383 struct mlx5_ifc_qpc_bits qpc;
3385 u8 reserved_at_800[0x80];
3390 struct mlx5_ifc_query_qp_in_bits {
3392 u8 reserved_at_10[0x10];
3394 u8 reserved_at_20[0x10];
3397 u8 reserved_at_40[0x8];
3400 u8 reserved_at_60[0x20];
3403 struct mlx5_ifc_query_q_counter_out_bits {
3405 u8 reserved_at_8[0x18];
3409 u8 reserved_at_40[0x40];
3411 u8 rx_write_requests[0x20];
3413 u8 reserved_at_a0[0x20];
3415 u8 rx_read_requests[0x20];
3417 u8 reserved_at_e0[0x20];
3419 u8 rx_atomic_requests[0x20];
3421 u8 reserved_at_120[0x20];
3423 u8 rx_dct_connect[0x20];
3425 u8 reserved_at_160[0x20];
3427 u8 out_of_buffer[0x20];
3429 u8 reserved_at_1a0[0x20];
3431 u8 out_of_sequence[0x20];
3433 u8 reserved_at_1e0[0x620];
3436 struct mlx5_ifc_query_q_counter_in_bits {
3438 u8 reserved_at_10[0x10];
3440 u8 reserved_at_20[0x10];
3443 u8 reserved_at_40[0x80];
3446 u8 reserved_at_c1[0x1f];
3448 u8 reserved_at_e0[0x18];
3449 u8 counter_set_id[0x8];
3452 struct mlx5_ifc_query_pages_out_bits {
3454 u8 reserved_at_8[0x18];
3458 u8 reserved_at_40[0x10];
3459 u8 function_id[0x10];
3465 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3466 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3467 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3470 struct mlx5_ifc_query_pages_in_bits {
3472 u8 reserved_at_10[0x10];
3474 u8 reserved_at_20[0x10];
3477 u8 reserved_at_40[0x10];
3478 u8 function_id[0x10];
3480 u8 reserved_at_60[0x20];
3483 struct mlx5_ifc_query_nic_vport_context_out_bits {
3485 u8 reserved_at_8[0x18];
3489 u8 reserved_at_40[0x40];
3491 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3494 struct mlx5_ifc_query_nic_vport_context_in_bits {
3496 u8 reserved_at_10[0x10];
3498 u8 reserved_at_20[0x10];
3501 u8 other_vport[0x1];
3502 u8 reserved_at_41[0xf];
3503 u8 vport_number[0x10];
3505 u8 reserved_at_60[0x5];
3506 u8 allowed_list_type[0x3];
3507 u8 reserved_at_68[0x18];
3510 struct mlx5_ifc_query_mkey_out_bits {
3512 u8 reserved_at_8[0x18];
3516 u8 reserved_at_40[0x40];
3518 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3520 u8 reserved_at_280[0x600];
3522 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3524 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3527 struct mlx5_ifc_query_mkey_in_bits {
3529 u8 reserved_at_10[0x10];
3531 u8 reserved_at_20[0x10];
3534 u8 reserved_at_40[0x8];
3535 u8 mkey_index[0x18];
3538 u8 reserved_at_61[0x1f];
3541 struct mlx5_ifc_query_mad_demux_out_bits {
3543 u8 reserved_at_8[0x18];
3547 u8 reserved_at_40[0x40];
3549 u8 mad_dumux_parameters_block[0x20];
3552 struct mlx5_ifc_query_mad_demux_in_bits {
3554 u8 reserved_at_10[0x10];
3556 u8 reserved_at_20[0x10];
3559 u8 reserved_at_40[0x40];
3562 struct mlx5_ifc_query_l2_table_entry_out_bits {
3564 u8 reserved_at_8[0x18];
3568 u8 reserved_at_40[0xa0];
3570 u8 reserved_at_e0[0x13];
3574 struct mlx5_ifc_mac_address_layout_bits mac_address;
3576 u8 reserved_at_140[0xc0];
3579 struct mlx5_ifc_query_l2_table_entry_in_bits {
3581 u8 reserved_at_10[0x10];
3583 u8 reserved_at_20[0x10];
3586 u8 reserved_at_40[0x60];
3588 u8 reserved_at_a0[0x8];
3589 u8 table_index[0x18];
3591 u8 reserved_at_c0[0x140];
3594 struct mlx5_ifc_query_issi_out_bits {
3596 u8 reserved_at_8[0x18];
3600 u8 reserved_at_40[0x10];
3601 u8 current_issi[0x10];
3603 u8 reserved_at_60[0xa0];
3605 u8 reserved_at_100[76][0x8];
3606 u8 supported_issi_dw0[0x20];
3609 struct mlx5_ifc_query_issi_in_bits {
3611 u8 reserved_at_10[0x10];
3613 u8 reserved_at_20[0x10];
3616 u8 reserved_at_40[0x40];
3619 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3621 u8 reserved_at_8[0x18];
3625 u8 reserved_at_40[0x40];
3627 struct mlx5_ifc_pkey_bits pkey[0];
3630 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3632 u8 reserved_at_10[0x10];
3634 u8 reserved_at_20[0x10];
3637 u8 other_vport[0x1];
3638 u8 reserved_at_41[0xb];
3640 u8 vport_number[0x10];
3642 u8 reserved_at_60[0x10];
3643 u8 pkey_index[0x10];
3646 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3648 u8 reserved_at_8[0x18];
3652 u8 reserved_at_40[0x20];
3655 u8 reserved_at_70[0x10];
3657 struct mlx5_ifc_array128_auto_bits gid[0];
3660 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3662 u8 reserved_at_10[0x10];
3664 u8 reserved_at_20[0x10];
3667 u8 other_vport[0x1];
3668 u8 reserved_at_41[0xb];
3670 u8 vport_number[0x10];
3672 u8 reserved_at_60[0x10];
3676 struct mlx5_ifc_query_hca_vport_context_out_bits {
3678 u8 reserved_at_8[0x18];
3682 u8 reserved_at_40[0x40];
3684 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3687 struct mlx5_ifc_query_hca_vport_context_in_bits {
3689 u8 reserved_at_10[0x10];
3691 u8 reserved_at_20[0x10];
3694 u8 other_vport[0x1];
3695 u8 reserved_at_41[0xb];
3697 u8 vport_number[0x10];
3699 u8 reserved_at_60[0x20];
3702 struct mlx5_ifc_query_hca_cap_out_bits {
3704 u8 reserved_at_8[0x18];
3708 u8 reserved_at_40[0x40];
3710 union mlx5_ifc_hca_cap_union_bits capability;
3713 struct mlx5_ifc_query_hca_cap_in_bits {
3715 u8 reserved_at_10[0x10];
3717 u8 reserved_at_20[0x10];
3720 u8 reserved_at_40[0x40];
3723 struct mlx5_ifc_query_flow_table_out_bits {
3725 u8 reserved_at_8[0x18];
3729 u8 reserved_at_40[0x80];
3731 u8 reserved_at_c0[0x8];
3733 u8 reserved_at_d0[0x8];
3736 u8 reserved_at_e0[0x120];
3739 struct mlx5_ifc_query_flow_table_in_bits {
3741 u8 reserved_at_10[0x10];
3743 u8 reserved_at_20[0x10];
3746 u8 reserved_at_40[0x40];
3749 u8 reserved_at_88[0x18];
3751 u8 reserved_at_a0[0x8];
3754 u8 reserved_at_c0[0x140];
3757 struct mlx5_ifc_query_fte_out_bits {
3759 u8 reserved_at_8[0x18];
3763 u8 reserved_at_40[0x1c0];
3765 struct mlx5_ifc_flow_context_bits flow_context;
3768 struct mlx5_ifc_query_fte_in_bits {
3770 u8 reserved_at_10[0x10];
3772 u8 reserved_at_20[0x10];
3775 u8 reserved_at_40[0x40];
3778 u8 reserved_at_88[0x18];
3780 u8 reserved_at_a0[0x8];
3783 u8 reserved_at_c0[0x40];
3785 u8 flow_index[0x20];
3787 u8 reserved_at_120[0xe0];
3791 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
3792 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
3793 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
3796 struct mlx5_ifc_query_flow_group_out_bits {
3798 u8 reserved_at_8[0x18];
3802 u8 reserved_at_40[0xa0];
3804 u8 start_flow_index[0x20];
3806 u8 reserved_at_100[0x20];
3808 u8 end_flow_index[0x20];
3810 u8 reserved_at_140[0xa0];
3812 u8 reserved_at_1e0[0x18];
3813 u8 match_criteria_enable[0x8];
3815 struct mlx5_ifc_fte_match_param_bits match_criteria;
3817 u8 reserved_at_1200[0xe00];
3820 struct mlx5_ifc_query_flow_group_in_bits {
3822 u8 reserved_at_10[0x10];
3824 u8 reserved_at_20[0x10];
3827 u8 reserved_at_40[0x40];
3830 u8 reserved_at_88[0x18];
3832 u8 reserved_at_a0[0x8];
3837 u8 reserved_at_e0[0x120];
3840 struct mlx5_ifc_query_esw_vport_context_out_bits {
3842 u8 reserved_at_8[0x18];
3846 u8 reserved_at_40[0x40];
3848 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3851 struct mlx5_ifc_query_esw_vport_context_in_bits {
3853 u8 reserved_at_10[0x10];
3855 u8 reserved_at_20[0x10];
3858 u8 other_vport[0x1];
3859 u8 reserved_at_41[0xf];
3860 u8 vport_number[0x10];
3862 u8 reserved_at_60[0x20];
3865 struct mlx5_ifc_modify_esw_vport_context_out_bits {
3867 u8 reserved_at_8[0x18];
3871 u8 reserved_at_40[0x40];
3874 struct mlx5_ifc_esw_vport_context_fields_select_bits {
3875 u8 reserved_at_0[0x1c];
3876 u8 vport_cvlan_insert[0x1];
3877 u8 vport_svlan_insert[0x1];
3878 u8 vport_cvlan_strip[0x1];
3879 u8 vport_svlan_strip[0x1];
3882 struct mlx5_ifc_modify_esw_vport_context_in_bits {
3884 u8 reserved_at_10[0x10];
3886 u8 reserved_at_20[0x10];
3889 u8 other_vport[0x1];
3890 u8 reserved_at_41[0xf];
3891 u8 vport_number[0x10];
3893 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
3895 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3898 struct mlx5_ifc_query_eq_out_bits {
3900 u8 reserved_at_8[0x18];
3904 u8 reserved_at_40[0x40];
3906 struct mlx5_ifc_eqc_bits eq_context_entry;
3908 u8 reserved_at_280[0x40];
3910 u8 event_bitmask[0x40];
3912 u8 reserved_at_300[0x580];
3917 struct mlx5_ifc_query_eq_in_bits {
3919 u8 reserved_at_10[0x10];
3921 u8 reserved_at_20[0x10];
3924 u8 reserved_at_40[0x18];
3927 u8 reserved_at_60[0x20];
3930 struct mlx5_ifc_query_dct_out_bits {
3932 u8 reserved_at_8[0x18];
3936 u8 reserved_at_40[0x40];
3938 struct mlx5_ifc_dctc_bits dct_context_entry;
3940 u8 reserved_at_280[0x180];
3943 struct mlx5_ifc_query_dct_in_bits {
3945 u8 reserved_at_10[0x10];
3947 u8 reserved_at_20[0x10];
3950 u8 reserved_at_40[0x8];
3953 u8 reserved_at_60[0x20];
3956 struct mlx5_ifc_query_cq_out_bits {
3958 u8 reserved_at_8[0x18];
3962 u8 reserved_at_40[0x40];
3964 struct mlx5_ifc_cqc_bits cq_context;
3966 u8 reserved_at_280[0x600];
3971 struct mlx5_ifc_query_cq_in_bits {
3973 u8 reserved_at_10[0x10];
3975 u8 reserved_at_20[0x10];
3978 u8 reserved_at_40[0x8];
3981 u8 reserved_at_60[0x20];
3984 struct mlx5_ifc_query_cong_status_out_bits {
3986 u8 reserved_at_8[0x18];
3990 u8 reserved_at_40[0x20];
3994 u8 reserved_at_62[0x1e];
3997 struct mlx5_ifc_query_cong_status_in_bits {
3999 u8 reserved_at_10[0x10];
4001 u8 reserved_at_20[0x10];
4004 u8 reserved_at_40[0x18];
4006 u8 cong_protocol[0x4];
4008 u8 reserved_at_60[0x20];
4011 struct mlx5_ifc_query_cong_statistics_out_bits {
4013 u8 reserved_at_8[0x18];
4017 u8 reserved_at_40[0x40];
4023 u8 cnp_ignored_high[0x20];
4025 u8 cnp_ignored_low[0x20];
4027 u8 cnp_handled_high[0x20];
4029 u8 cnp_handled_low[0x20];
4031 u8 reserved_at_140[0x100];
4033 u8 time_stamp_high[0x20];
4035 u8 time_stamp_low[0x20];
4037 u8 accumulators_period[0x20];
4039 u8 ecn_marked_roce_packets_high[0x20];
4041 u8 ecn_marked_roce_packets_low[0x20];
4043 u8 cnps_sent_high[0x20];
4045 u8 cnps_sent_low[0x20];
4047 u8 reserved_at_320[0x560];
4050 struct mlx5_ifc_query_cong_statistics_in_bits {
4052 u8 reserved_at_10[0x10];
4054 u8 reserved_at_20[0x10];
4058 u8 reserved_at_41[0x1f];
4060 u8 reserved_at_60[0x20];
4063 struct mlx5_ifc_query_cong_params_out_bits {
4065 u8 reserved_at_8[0x18];
4069 u8 reserved_at_40[0x40];
4071 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4074 struct mlx5_ifc_query_cong_params_in_bits {
4076 u8 reserved_at_10[0x10];
4078 u8 reserved_at_20[0x10];
4081 u8 reserved_at_40[0x1c];
4082 u8 cong_protocol[0x4];
4084 u8 reserved_at_60[0x20];
4087 struct mlx5_ifc_query_adapter_out_bits {
4089 u8 reserved_at_8[0x18];
4093 u8 reserved_at_40[0x40];
4095 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4098 struct mlx5_ifc_query_adapter_in_bits {
4100 u8 reserved_at_10[0x10];
4102 u8 reserved_at_20[0x10];
4105 u8 reserved_at_40[0x40];
4108 struct mlx5_ifc_qp_2rst_out_bits {
4110 u8 reserved_at_8[0x18];
4114 u8 reserved_at_40[0x40];
4117 struct mlx5_ifc_qp_2rst_in_bits {
4119 u8 reserved_at_10[0x10];
4121 u8 reserved_at_20[0x10];
4124 u8 reserved_at_40[0x8];
4127 u8 reserved_at_60[0x20];
4130 struct mlx5_ifc_qp_2err_out_bits {
4132 u8 reserved_at_8[0x18];
4136 u8 reserved_at_40[0x40];
4139 struct mlx5_ifc_qp_2err_in_bits {
4141 u8 reserved_at_10[0x10];
4143 u8 reserved_at_20[0x10];
4146 u8 reserved_at_40[0x8];
4149 u8 reserved_at_60[0x20];
4152 struct mlx5_ifc_page_fault_resume_out_bits {
4154 u8 reserved_at_8[0x18];
4158 u8 reserved_at_40[0x40];
4161 struct mlx5_ifc_page_fault_resume_in_bits {
4163 u8 reserved_at_10[0x10];
4165 u8 reserved_at_20[0x10];
4169 u8 reserved_at_41[0x4];
4175 u8 reserved_at_60[0x20];
4178 struct mlx5_ifc_nop_out_bits {
4180 u8 reserved_at_8[0x18];
4184 u8 reserved_at_40[0x40];
4187 struct mlx5_ifc_nop_in_bits {
4189 u8 reserved_at_10[0x10];
4191 u8 reserved_at_20[0x10];
4194 u8 reserved_at_40[0x40];
4197 struct mlx5_ifc_modify_vport_state_out_bits {
4199 u8 reserved_at_8[0x18];
4203 u8 reserved_at_40[0x40];
4206 struct mlx5_ifc_modify_vport_state_in_bits {
4208 u8 reserved_at_10[0x10];
4210 u8 reserved_at_20[0x10];
4213 u8 other_vport[0x1];
4214 u8 reserved_at_41[0xf];
4215 u8 vport_number[0x10];
4217 u8 reserved_at_60[0x18];
4218 u8 admin_state[0x4];
4219 u8 reserved_at_7c[0x4];
4222 struct mlx5_ifc_modify_tis_out_bits {
4224 u8 reserved_at_8[0x18];
4228 u8 reserved_at_40[0x40];
4231 struct mlx5_ifc_modify_tis_bitmask_bits {
4232 u8 reserved_at_0[0x20];
4234 u8 reserved_at_20[0x1f];
4238 struct mlx5_ifc_modify_tis_in_bits {
4240 u8 reserved_at_10[0x10];
4242 u8 reserved_at_20[0x10];
4245 u8 reserved_at_40[0x8];
4248 u8 reserved_at_60[0x20];
4250 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4252 u8 reserved_at_c0[0x40];
4254 struct mlx5_ifc_tisc_bits ctx;
4257 struct mlx5_ifc_modify_tir_bitmask_bits {
4258 u8 reserved_at_0[0x20];
4260 u8 reserved_at_20[0x1b];
4262 u8 reserved_at_3c[0x1];
4264 u8 reserved_at_3e[0x1];
4268 struct mlx5_ifc_modify_tir_out_bits {
4270 u8 reserved_at_8[0x18];
4274 u8 reserved_at_40[0x40];
4277 struct mlx5_ifc_modify_tir_in_bits {
4279 u8 reserved_at_10[0x10];
4281 u8 reserved_at_20[0x10];
4284 u8 reserved_at_40[0x8];
4287 u8 reserved_at_60[0x20];
4289 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4291 u8 reserved_at_c0[0x40];
4293 struct mlx5_ifc_tirc_bits ctx;
4296 struct mlx5_ifc_modify_sq_out_bits {
4298 u8 reserved_at_8[0x18];
4302 u8 reserved_at_40[0x40];
4305 struct mlx5_ifc_modify_sq_in_bits {
4307 u8 reserved_at_10[0x10];
4309 u8 reserved_at_20[0x10];
4313 u8 reserved_at_44[0x4];
4316 u8 reserved_at_60[0x20];
4318 u8 modify_bitmask[0x40];
4320 u8 reserved_at_c0[0x40];
4322 struct mlx5_ifc_sqc_bits ctx;
4325 struct mlx5_ifc_modify_rqt_out_bits {
4327 u8 reserved_at_8[0x18];
4331 u8 reserved_at_40[0x40];
4334 struct mlx5_ifc_rqt_bitmask_bits {
4335 u8 reserved_at_0[0x20];
4337 u8 reserved_at_20[0x1f];
4341 struct mlx5_ifc_modify_rqt_in_bits {
4343 u8 reserved_at_10[0x10];
4345 u8 reserved_at_20[0x10];
4348 u8 reserved_at_40[0x8];
4351 u8 reserved_at_60[0x20];
4353 struct mlx5_ifc_rqt_bitmask_bits bitmask;
4355 u8 reserved_at_c0[0x40];
4357 struct mlx5_ifc_rqtc_bits ctx;
4360 struct mlx5_ifc_modify_rq_out_bits {
4362 u8 reserved_at_8[0x18];
4366 u8 reserved_at_40[0x40];
4369 struct mlx5_ifc_modify_rq_in_bits {
4371 u8 reserved_at_10[0x10];
4373 u8 reserved_at_20[0x10];
4377 u8 reserved_at_44[0x4];
4380 u8 reserved_at_60[0x20];
4382 u8 modify_bitmask[0x40];
4384 u8 reserved_at_c0[0x40];
4386 struct mlx5_ifc_rqc_bits ctx;
4389 struct mlx5_ifc_modify_rmp_out_bits {
4391 u8 reserved_at_8[0x18];
4395 u8 reserved_at_40[0x40];
4398 struct mlx5_ifc_rmp_bitmask_bits {
4399 u8 reserved_at_0[0x20];
4401 u8 reserved_at_20[0x1f];
4405 struct mlx5_ifc_modify_rmp_in_bits {
4407 u8 reserved_at_10[0x10];
4409 u8 reserved_at_20[0x10];
4413 u8 reserved_at_44[0x4];
4416 u8 reserved_at_60[0x20];
4418 struct mlx5_ifc_rmp_bitmask_bits bitmask;
4420 u8 reserved_at_c0[0x40];
4422 struct mlx5_ifc_rmpc_bits ctx;
4425 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4427 u8 reserved_at_8[0x18];
4431 u8 reserved_at_40[0x40];
4434 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4435 u8 reserved_at_0[0x19];
4437 u8 change_event[0x1];
4439 u8 permanent_address[0x1];
4440 u8 addresses_list[0x1];
4442 u8 reserved_at_1f[0x1];
4445 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4447 u8 reserved_at_10[0x10];
4449 u8 reserved_at_20[0x10];
4452 u8 other_vport[0x1];
4453 u8 reserved_at_41[0xf];
4454 u8 vport_number[0x10];
4456 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4458 u8 reserved_at_80[0x780];
4460 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4463 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4465 u8 reserved_at_8[0x18];
4469 u8 reserved_at_40[0x40];
4472 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4474 u8 reserved_at_10[0x10];
4476 u8 reserved_at_20[0x10];
4479 u8 other_vport[0x1];
4480 u8 reserved_at_41[0xb];
4482 u8 vport_number[0x10];
4484 u8 reserved_at_60[0x20];
4486 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4489 struct mlx5_ifc_modify_cq_out_bits {
4491 u8 reserved_at_8[0x18];
4495 u8 reserved_at_40[0x40];
4499 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4500 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4503 struct mlx5_ifc_modify_cq_in_bits {
4505 u8 reserved_at_10[0x10];
4507 u8 reserved_at_20[0x10];
4510 u8 reserved_at_40[0x8];
4513 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4515 struct mlx5_ifc_cqc_bits cq_context;
4517 u8 reserved_at_280[0x600];
4522 struct mlx5_ifc_modify_cong_status_out_bits {
4524 u8 reserved_at_8[0x18];
4528 u8 reserved_at_40[0x40];
4531 struct mlx5_ifc_modify_cong_status_in_bits {
4533 u8 reserved_at_10[0x10];
4535 u8 reserved_at_20[0x10];
4538 u8 reserved_at_40[0x18];
4540 u8 cong_protocol[0x4];
4544 u8 reserved_at_62[0x1e];
4547 struct mlx5_ifc_modify_cong_params_out_bits {
4549 u8 reserved_at_8[0x18];
4553 u8 reserved_at_40[0x40];
4556 struct mlx5_ifc_modify_cong_params_in_bits {
4558 u8 reserved_at_10[0x10];
4560 u8 reserved_at_20[0x10];
4563 u8 reserved_at_40[0x1c];
4564 u8 cong_protocol[0x4];
4566 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4568 u8 reserved_at_80[0x80];
4570 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4573 struct mlx5_ifc_manage_pages_out_bits {
4575 u8 reserved_at_8[0x18];
4579 u8 output_num_entries[0x20];
4581 u8 reserved_at_60[0x20];
4587 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4588 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4589 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4592 struct mlx5_ifc_manage_pages_in_bits {
4594 u8 reserved_at_10[0x10];
4596 u8 reserved_at_20[0x10];
4599 u8 reserved_at_40[0x10];
4600 u8 function_id[0x10];
4602 u8 input_num_entries[0x20];
4607 struct mlx5_ifc_mad_ifc_out_bits {
4609 u8 reserved_at_8[0x18];
4613 u8 reserved_at_40[0x40];
4615 u8 response_mad_packet[256][0x8];
4618 struct mlx5_ifc_mad_ifc_in_bits {
4620 u8 reserved_at_10[0x10];
4622 u8 reserved_at_20[0x10];
4625 u8 remote_lid[0x10];
4626 u8 reserved_at_50[0x8];
4629 u8 reserved_at_60[0x20];
4634 struct mlx5_ifc_init_hca_out_bits {
4636 u8 reserved_at_8[0x18];
4640 u8 reserved_at_40[0x40];
4643 struct mlx5_ifc_init_hca_in_bits {
4645 u8 reserved_at_10[0x10];
4647 u8 reserved_at_20[0x10];
4650 u8 reserved_at_40[0x40];
4653 struct mlx5_ifc_init2rtr_qp_out_bits {
4655 u8 reserved_at_8[0x18];
4659 u8 reserved_at_40[0x40];
4662 struct mlx5_ifc_init2rtr_qp_in_bits {
4664 u8 reserved_at_10[0x10];
4666 u8 reserved_at_20[0x10];
4669 u8 reserved_at_40[0x8];
4672 u8 reserved_at_60[0x20];
4674 u8 opt_param_mask[0x20];
4676 u8 reserved_at_a0[0x20];
4678 struct mlx5_ifc_qpc_bits qpc;
4680 u8 reserved_at_800[0x80];
4683 struct mlx5_ifc_init2init_qp_out_bits {
4685 u8 reserved_at_8[0x18];
4689 u8 reserved_at_40[0x40];
4692 struct mlx5_ifc_init2init_qp_in_bits {
4694 u8 reserved_at_10[0x10];
4696 u8 reserved_at_20[0x10];
4699 u8 reserved_at_40[0x8];
4702 u8 reserved_at_60[0x20];
4704 u8 opt_param_mask[0x20];
4706 u8 reserved_at_a0[0x20];
4708 struct mlx5_ifc_qpc_bits qpc;
4710 u8 reserved_at_800[0x80];
4713 struct mlx5_ifc_get_dropped_packet_log_out_bits {
4715 u8 reserved_at_8[0x18];
4719 u8 reserved_at_40[0x40];
4721 u8 packet_headers_log[128][0x8];
4723 u8 packet_syndrome[64][0x8];
4726 struct mlx5_ifc_get_dropped_packet_log_in_bits {
4728 u8 reserved_at_10[0x10];
4730 u8 reserved_at_20[0x10];
4733 u8 reserved_at_40[0x40];
4736 struct mlx5_ifc_gen_eqe_in_bits {
4738 u8 reserved_at_10[0x10];
4740 u8 reserved_at_20[0x10];
4743 u8 reserved_at_40[0x18];
4746 u8 reserved_at_60[0x20];
4751 struct mlx5_ifc_gen_eq_out_bits {
4753 u8 reserved_at_8[0x18];
4757 u8 reserved_at_40[0x40];
4760 struct mlx5_ifc_enable_hca_out_bits {
4762 u8 reserved_at_8[0x18];
4766 u8 reserved_at_40[0x20];
4769 struct mlx5_ifc_enable_hca_in_bits {
4771 u8 reserved_at_10[0x10];
4773 u8 reserved_at_20[0x10];
4776 u8 reserved_at_40[0x10];
4777 u8 function_id[0x10];
4779 u8 reserved_at_60[0x20];
4782 struct mlx5_ifc_drain_dct_out_bits {
4784 u8 reserved_at_8[0x18];
4788 u8 reserved_at_40[0x40];
4791 struct mlx5_ifc_drain_dct_in_bits {
4793 u8 reserved_at_10[0x10];
4795 u8 reserved_at_20[0x10];
4798 u8 reserved_at_40[0x8];
4801 u8 reserved_at_60[0x20];
4804 struct mlx5_ifc_disable_hca_out_bits {
4806 u8 reserved_at_8[0x18];
4810 u8 reserved_at_40[0x20];
4813 struct mlx5_ifc_disable_hca_in_bits {
4815 u8 reserved_at_10[0x10];
4817 u8 reserved_at_20[0x10];
4820 u8 reserved_at_40[0x10];
4821 u8 function_id[0x10];
4823 u8 reserved_at_60[0x20];
4826 struct mlx5_ifc_detach_from_mcg_out_bits {
4828 u8 reserved_at_8[0x18];
4832 u8 reserved_at_40[0x40];
4835 struct mlx5_ifc_detach_from_mcg_in_bits {
4837 u8 reserved_at_10[0x10];
4839 u8 reserved_at_20[0x10];
4842 u8 reserved_at_40[0x8];
4845 u8 reserved_at_60[0x20];
4847 u8 multicast_gid[16][0x8];
4850 struct mlx5_ifc_destroy_xrc_srq_out_bits {
4852 u8 reserved_at_8[0x18];
4856 u8 reserved_at_40[0x40];
4859 struct mlx5_ifc_destroy_xrc_srq_in_bits {
4861 u8 reserved_at_10[0x10];
4863 u8 reserved_at_20[0x10];
4866 u8 reserved_at_40[0x8];
4869 u8 reserved_at_60[0x20];
4872 struct mlx5_ifc_destroy_tis_out_bits {
4874 u8 reserved_at_8[0x18];
4878 u8 reserved_at_40[0x40];
4881 struct mlx5_ifc_destroy_tis_in_bits {
4883 u8 reserved_at_10[0x10];
4885 u8 reserved_at_20[0x10];
4888 u8 reserved_at_40[0x8];
4891 u8 reserved_at_60[0x20];
4894 struct mlx5_ifc_destroy_tir_out_bits {
4896 u8 reserved_at_8[0x18];
4900 u8 reserved_at_40[0x40];
4903 struct mlx5_ifc_destroy_tir_in_bits {
4905 u8 reserved_at_10[0x10];
4907 u8 reserved_at_20[0x10];
4910 u8 reserved_at_40[0x8];
4913 u8 reserved_at_60[0x20];
4916 struct mlx5_ifc_destroy_srq_out_bits {
4918 u8 reserved_at_8[0x18];
4922 u8 reserved_at_40[0x40];
4925 struct mlx5_ifc_destroy_srq_in_bits {
4927 u8 reserved_at_10[0x10];
4929 u8 reserved_at_20[0x10];
4932 u8 reserved_at_40[0x8];
4935 u8 reserved_at_60[0x20];
4938 struct mlx5_ifc_destroy_sq_out_bits {
4940 u8 reserved_at_8[0x18];
4944 u8 reserved_at_40[0x40];
4947 struct mlx5_ifc_destroy_sq_in_bits {
4949 u8 reserved_at_10[0x10];
4951 u8 reserved_at_20[0x10];
4954 u8 reserved_at_40[0x8];
4957 u8 reserved_at_60[0x20];
4960 struct mlx5_ifc_destroy_rqt_out_bits {
4962 u8 reserved_at_8[0x18];
4966 u8 reserved_at_40[0x40];
4969 struct mlx5_ifc_destroy_rqt_in_bits {
4971 u8 reserved_at_10[0x10];
4973 u8 reserved_at_20[0x10];
4976 u8 reserved_at_40[0x8];
4979 u8 reserved_at_60[0x20];
4982 struct mlx5_ifc_destroy_rq_out_bits {
4984 u8 reserved_at_8[0x18];
4988 u8 reserved_at_40[0x40];
4991 struct mlx5_ifc_destroy_rq_in_bits {
4993 u8 reserved_at_10[0x10];
4995 u8 reserved_at_20[0x10];
4998 u8 reserved_at_40[0x8];
5001 u8 reserved_at_60[0x20];
5004 struct mlx5_ifc_destroy_rmp_out_bits {
5006 u8 reserved_at_8[0x18];
5010 u8 reserved_at_40[0x40];
5013 struct mlx5_ifc_destroy_rmp_in_bits {
5015 u8 reserved_at_10[0x10];
5017 u8 reserved_at_20[0x10];
5020 u8 reserved_at_40[0x8];
5023 u8 reserved_at_60[0x20];
5026 struct mlx5_ifc_destroy_qp_out_bits {
5028 u8 reserved_at_8[0x18];
5032 u8 reserved_at_40[0x40];
5035 struct mlx5_ifc_destroy_qp_in_bits {
5037 u8 reserved_at_10[0x10];
5039 u8 reserved_at_20[0x10];
5042 u8 reserved_at_40[0x8];
5045 u8 reserved_at_60[0x20];
5048 struct mlx5_ifc_destroy_psv_out_bits {
5050 u8 reserved_at_8[0x18];
5054 u8 reserved_at_40[0x40];
5057 struct mlx5_ifc_destroy_psv_in_bits {
5059 u8 reserved_at_10[0x10];
5061 u8 reserved_at_20[0x10];
5064 u8 reserved_at_40[0x8];
5067 u8 reserved_at_60[0x20];
5070 struct mlx5_ifc_destroy_mkey_out_bits {
5072 u8 reserved_at_8[0x18];
5076 u8 reserved_at_40[0x40];
5079 struct mlx5_ifc_destroy_mkey_in_bits {
5081 u8 reserved_at_10[0x10];
5083 u8 reserved_at_20[0x10];
5086 u8 reserved_at_40[0x8];
5087 u8 mkey_index[0x18];
5089 u8 reserved_at_60[0x20];
5092 struct mlx5_ifc_destroy_flow_table_out_bits {
5094 u8 reserved_at_8[0x18];
5098 u8 reserved_at_40[0x40];
5101 struct mlx5_ifc_destroy_flow_table_in_bits {
5103 u8 reserved_at_10[0x10];
5105 u8 reserved_at_20[0x10];
5108 u8 reserved_at_40[0x40];
5111 u8 reserved_at_88[0x18];
5113 u8 reserved_at_a0[0x8];
5116 u8 reserved_at_c0[0x140];
5119 struct mlx5_ifc_destroy_flow_group_out_bits {
5121 u8 reserved_at_8[0x18];
5125 u8 reserved_at_40[0x40];
5128 struct mlx5_ifc_destroy_flow_group_in_bits {
5130 u8 reserved_at_10[0x10];
5132 u8 reserved_at_20[0x10];
5135 u8 reserved_at_40[0x40];
5138 u8 reserved_at_88[0x18];
5140 u8 reserved_at_a0[0x8];
5145 u8 reserved_at_e0[0x120];
5148 struct mlx5_ifc_destroy_eq_out_bits {
5150 u8 reserved_at_8[0x18];
5154 u8 reserved_at_40[0x40];
5157 struct mlx5_ifc_destroy_eq_in_bits {
5159 u8 reserved_at_10[0x10];
5161 u8 reserved_at_20[0x10];
5164 u8 reserved_at_40[0x18];
5167 u8 reserved_at_60[0x20];
5170 struct mlx5_ifc_destroy_dct_out_bits {
5172 u8 reserved_at_8[0x18];
5176 u8 reserved_at_40[0x40];
5179 struct mlx5_ifc_destroy_dct_in_bits {
5181 u8 reserved_at_10[0x10];
5183 u8 reserved_at_20[0x10];
5186 u8 reserved_at_40[0x8];
5189 u8 reserved_at_60[0x20];
5192 struct mlx5_ifc_destroy_cq_out_bits {
5194 u8 reserved_at_8[0x18];
5198 u8 reserved_at_40[0x40];
5201 struct mlx5_ifc_destroy_cq_in_bits {
5203 u8 reserved_at_10[0x10];
5205 u8 reserved_at_20[0x10];
5208 u8 reserved_at_40[0x8];
5211 u8 reserved_at_60[0x20];
5214 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5216 u8 reserved_at_8[0x18];
5220 u8 reserved_at_40[0x40];
5223 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5225 u8 reserved_at_10[0x10];
5227 u8 reserved_at_20[0x10];
5230 u8 reserved_at_40[0x20];
5232 u8 reserved_at_60[0x10];
5233 u8 vxlan_udp_port[0x10];
5236 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5238 u8 reserved_at_8[0x18];
5242 u8 reserved_at_40[0x40];
5245 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5247 u8 reserved_at_10[0x10];
5249 u8 reserved_at_20[0x10];
5252 u8 reserved_at_40[0x60];
5254 u8 reserved_at_a0[0x8];
5255 u8 table_index[0x18];
5257 u8 reserved_at_c0[0x140];
5260 struct mlx5_ifc_delete_fte_out_bits {
5262 u8 reserved_at_8[0x18];
5266 u8 reserved_at_40[0x40];
5269 struct mlx5_ifc_delete_fte_in_bits {
5271 u8 reserved_at_10[0x10];
5273 u8 reserved_at_20[0x10];
5276 u8 reserved_at_40[0x40];
5279 u8 reserved_at_88[0x18];
5281 u8 reserved_at_a0[0x8];
5284 u8 reserved_at_c0[0x40];
5286 u8 flow_index[0x20];
5288 u8 reserved_at_120[0xe0];
5291 struct mlx5_ifc_dealloc_xrcd_out_bits {
5293 u8 reserved_at_8[0x18];
5297 u8 reserved_at_40[0x40];
5300 struct mlx5_ifc_dealloc_xrcd_in_bits {
5302 u8 reserved_at_10[0x10];
5304 u8 reserved_at_20[0x10];
5307 u8 reserved_at_40[0x8];
5310 u8 reserved_at_60[0x20];
5313 struct mlx5_ifc_dealloc_uar_out_bits {
5315 u8 reserved_at_8[0x18];
5319 u8 reserved_at_40[0x40];
5322 struct mlx5_ifc_dealloc_uar_in_bits {
5324 u8 reserved_at_10[0x10];
5326 u8 reserved_at_20[0x10];
5329 u8 reserved_at_40[0x8];
5332 u8 reserved_at_60[0x20];
5335 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5337 u8 reserved_at_8[0x18];
5341 u8 reserved_at_40[0x40];
5344 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5346 u8 reserved_at_10[0x10];
5348 u8 reserved_at_20[0x10];
5351 u8 reserved_at_40[0x8];
5352 u8 transport_domain[0x18];
5354 u8 reserved_at_60[0x20];
5357 struct mlx5_ifc_dealloc_q_counter_out_bits {
5359 u8 reserved_at_8[0x18];
5363 u8 reserved_at_40[0x40];
5366 struct mlx5_ifc_dealloc_q_counter_in_bits {
5368 u8 reserved_at_10[0x10];
5370 u8 reserved_at_20[0x10];
5373 u8 reserved_at_40[0x18];
5374 u8 counter_set_id[0x8];
5376 u8 reserved_at_60[0x20];
5379 struct mlx5_ifc_dealloc_pd_out_bits {
5381 u8 reserved_at_8[0x18];
5385 u8 reserved_at_40[0x40];
5388 struct mlx5_ifc_dealloc_pd_in_bits {
5390 u8 reserved_at_10[0x10];
5392 u8 reserved_at_20[0x10];
5395 u8 reserved_at_40[0x8];
5398 u8 reserved_at_60[0x20];
5401 struct mlx5_ifc_create_xrc_srq_out_bits {
5403 u8 reserved_at_8[0x18];
5407 u8 reserved_at_40[0x8];
5410 u8 reserved_at_60[0x20];
5413 struct mlx5_ifc_create_xrc_srq_in_bits {
5415 u8 reserved_at_10[0x10];
5417 u8 reserved_at_20[0x10];
5420 u8 reserved_at_40[0x40];
5422 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5424 u8 reserved_at_280[0x600];
5429 struct mlx5_ifc_create_tis_out_bits {
5431 u8 reserved_at_8[0x18];
5435 u8 reserved_at_40[0x8];
5438 u8 reserved_at_60[0x20];
5441 struct mlx5_ifc_create_tis_in_bits {
5443 u8 reserved_at_10[0x10];
5445 u8 reserved_at_20[0x10];
5448 u8 reserved_at_40[0xc0];
5450 struct mlx5_ifc_tisc_bits ctx;
5453 struct mlx5_ifc_create_tir_out_bits {
5455 u8 reserved_at_8[0x18];
5459 u8 reserved_at_40[0x8];
5462 u8 reserved_at_60[0x20];
5465 struct mlx5_ifc_create_tir_in_bits {
5467 u8 reserved_at_10[0x10];
5469 u8 reserved_at_20[0x10];
5472 u8 reserved_at_40[0xc0];
5474 struct mlx5_ifc_tirc_bits ctx;
5477 struct mlx5_ifc_create_srq_out_bits {
5479 u8 reserved_at_8[0x18];
5483 u8 reserved_at_40[0x8];
5486 u8 reserved_at_60[0x20];
5489 struct mlx5_ifc_create_srq_in_bits {
5491 u8 reserved_at_10[0x10];
5493 u8 reserved_at_20[0x10];
5496 u8 reserved_at_40[0x40];
5498 struct mlx5_ifc_srqc_bits srq_context_entry;
5500 u8 reserved_at_280[0x600];
5505 struct mlx5_ifc_create_sq_out_bits {
5507 u8 reserved_at_8[0x18];
5511 u8 reserved_at_40[0x8];
5514 u8 reserved_at_60[0x20];
5517 struct mlx5_ifc_create_sq_in_bits {
5519 u8 reserved_at_10[0x10];
5521 u8 reserved_at_20[0x10];
5524 u8 reserved_at_40[0xc0];
5526 struct mlx5_ifc_sqc_bits ctx;
5529 struct mlx5_ifc_create_rqt_out_bits {
5531 u8 reserved_at_8[0x18];
5535 u8 reserved_at_40[0x8];
5538 u8 reserved_at_60[0x20];
5541 struct mlx5_ifc_create_rqt_in_bits {
5543 u8 reserved_at_10[0x10];
5545 u8 reserved_at_20[0x10];
5548 u8 reserved_at_40[0xc0];
5550 struct mlx5_ifc_rqtc_bits rqt_context;
5553 struct mlx5_ifc_create_rq_out_bits {
5555 u8 reserved_at_8[0x18];
5559 u8 reserved_at_40[0x8];
5562 u8 reserved_at_60[0x20];
5565 struct mlx5_ifc_create_rq_in_bits {
5567 u8 reserved_at_10[0x10];
5569 u8 reserved_at_20[0x10];
5572 u8 reserved_at_40[0xc0];
5574 struct mlx5_ifc_rqc_bits ctx;
5577 struct mlx5_ifc_create_rmp_out_bits {
5579 u8 reserved_at_8[0x18];
5583 u8 reserved_at_40[0x8];
5586 u8 reserved_at_60[0x20];
5589 struct mlx5_ifc_create_rmp_in_bits {
5591 u8 reserved_at_10[0x10];
5593 u8 reserved_at_20[0x10];
5596 u8 reserved_at_40[0xc0];
5598 struct mlx5_ifc_rmpc_bits ctx;
5601 struct mlx5_ifc_create_qp_out_bits {
5603 u8 reserved_at_8[0x18];
5607 u8 reserved_at_40[0x8];
5610 u8 reserved_at_60[0x20];
5613 struct mlx5_ifc_create_qp_in_bits {
5615 u8 reserved_at_10[0x10];
5617 u8 reserved_at_20[0x10];
5620 u8 reserved_at_40[0x40];
5622 u8 opt_param_mask[0x20];
5624 u8 reserved_at_a0[0x20];
5626 struct mlx5_ifc_qpc_bits qpc;
5628 u8 reserved_at_800[0x80];
5633 struct mlx5_ifc_create_psv_out_bits {
5635 u8 reserved_at_8[0x18];
5639 u8 reserved_at_40[0x40];
5641 u8 reserved_at_80[0x8];
5642 u8 psv0_index[0x18];
5644 u8 reserved_at_a0[0x8];
5645 u8 psv1_index[0x18];
5647 u8 reserved_at_c0[0x8];
5648 u8 psv2_index[0x18];
5650 u8 reserved_at_e0[0x8];
5651 u8 psv3_index[0x18];
5654 struct mlx5_ifc_create_psv_in_bits {
5656 u8 reserved_at_10[0x10];
5658 u8 reserved_at_20[0x10];
5662 u8 reserved_at_44[0x4];
5665 u8 reserved_at_60[0x20];
5668 struct mlx5_ifc_create_mkey_out_bits {
5670 u8 reserved_at_8[0x18];
5674 u8 reserved_at_40[0x8];
5675 u8 mkey_index[0x18];
5677 u8 reserved_at_60[0x20];
5680 struct mlx5_ifc_create_mkey_in_bits {
5682 u8 reserved_at_10[0x10];
5684 u8 reserved_at_20[0x10];
5687 u8 reserved_at_40[0x20];
5690 u8 reserved_at_61[0x1f];
5692 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5694 u8 reserved_at_280[0x80];
5696 u8 translations_octword_actual_size[0x20];
5698 u8 reserved_at_320[0x560];
5700 u8 klm_pas_mtt[0][0x20];
5703 struct mlx5_ifc_create_flow_table_out_bits {
5705 u8 reserved_at_8[0x18];
5709 u8 reserved_at_40[0x8];
5712 u8 reserved_at_60[0x20];
5715 struct mlx5_ifc_create_flow_table_in_bits {
5717 u8 reserved_at_10[0x10];
5719 u8 reserved_at_20[0x10];
5722 u8 reserved_at_40[0x40];
5725 u8 reserved_at_88[0x18];
5727 u8 reserved_at_a0[0x20];
5729 u8 reserved_at_c0[0x4];
5730 u8 table_miss_mode[0x4];
5732 u8 reserved_at_d0[0x8];
5735 u8 reserved_at_e0[0x8];
5736 u8 table_miss_id[0x18];
5738 u8 reserved_at_100[0x100];
5741 struct mlx5_ifc_create_flow_group_out_bits {
5743 u8 reserved_at_8[0x18];
5747 u8 reserved_at_40[0x8];
5750 u8 reserved_at_60[0x20];
5754 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5755 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5756 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5759 struct mlx5_ifc_create_flow_group_in_bits {
5761 u8 reserved_at_10[0x10];
5763 u8 reserved_at_20[0x10];
5766 u8 reserved_at_40[0x40];
5769 u8 reserved_at_88[0x18];
5771 u8 reserved_at_a0[0x8];
5774 u8 reserved_at_c0[0x20];
5776 u8 start_flow_index[0x20];
5778 u8 reserved_at_100[0x20];
5780 u8 end_flow_index[0x20];
5782 u8 reserved_at_140[0xa0];
5784 u8 reserved_at_1e0[0x18];
5785 u8 match_criteria_enable[0x8];
5787 struct mlx5_ifc_fte_match_param_bits match_criteria;
5789 u8 reserved_at_1200[0xe00];
5792 struct mlx5_ifc_create_eq_out_bits {
5794 u8 reserved_at_8[0x18];
5798 u8 reserved_at_40[0x18];
5801 u8 reserved_at_60[0x20];
5804 struct mlx5_ifc_create_eq_in_bits {
5806 u8 reserved_at_10[0x10];
5808 u8 reserved_at_20[0x10];
5811 u8 reserved_at_40[0x40];
5813 struct mlx5_ifc_eqc_bits eq_context_entry;
5815 u8 reserved_at_280[0x40];
5817 u8 event_bitmask[0x40];
5819 u8 reserved_at_300[0x580];
5824 struct mlx5_ifc_create_dct_out_bits {
5826 u8 reserved_at_8[0x18];
5830 u8 reserved_at_40[0x8];
5833 u8 reserved_at_60[0x20];
5836 struct mlx5_ifc_create_dct_in_bits {
5838 u8 reserved_at_10[0x10];
5840 u8 reserved_at_20[0x10];
5843 u8 reserved_at_40[0x40];
5845 struct mlx5_ifc_dctc_bits dct_context_entry;
5847 u8 reserved_at_280[0x180];
5850 struct mlx5_ifc_create_cq_out_bits {
5852 u8 reserved_at_8[0x18];
5856 u8 reserved_at_40[0x8];
5859 u8 reserved_at_60[0x20];
5862 struct mlx5_ifc_create_cq_in_bits {
5864 u8 reserved_at_10[0x10];
5866 u8 reserved_at_20[0x10];
5869 u8 reserved_at_40[0x40];
5871 struct mlx5_ifc_cqc_bits cq_context;
5873 u8 reserved_at_280[0x600];
5878 struct mlx5_ifc_config_int_moderation_out_bits {
5880 u8 reserved_at_8[0x18];
5884 u8 reserved_at_40[0x4];
5886 u8 int_vector[0x10];
5888 u8 reserved_at_60[0x20];
5892 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
5893 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
5896 struct mlx5_ifc_config_int_moderation_in_bits {
5898 u8 reserved_at_10[0x10];
5900 u8 reserved_at_20[0x10];
5903 u8 reserved_at_40[0x4];
5905 u8 int_vector[0x10];
5907 u8 reserved_at_60[0x20];
5910 struct mlx5_ifc_attach_to_mcg_out_bits {
5912 u8 reserved_at_8[0x18];
5916 u8 reserved_at_40[0x40];
5919 struct mlx5_ifc_attach_to_mcg_in_bits {
5921 u8 reserved_at_10[0x10];
5923 u8 reserved_at_20[0x10];
5926 u8 reserved_at_40[0x8];
5929 u8 reserved_at_60[0x20];
5931 u8 multicast_gid[16][0x8];
5934 struct mlx5_ifc_arm_xrc_srq_out_bits {
5936 u8 reserved_at_8[0x18];
5940 u8 reserved_at_40[0x40];
5944 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
5947 struct mlx5_ifc_arm_xrc_srq_in_bits {
5949 u8 reserved_at_10[0x10];
5951 u8 reserved_at_20[0x10];
5954 u8 reserved_at_40[0x8];
5957 u8 reserved_at_60[0x10];
5961 struct mlx5_ifc_arm_rq_out_bits {
5963 u8 reserved_at_8[0x18];
5967 u8 reserved_at_40[0x40];
5971 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1,
5974 struct mlx5_ifc_arm_rq_in_bits {
5976 u8 reserved_at_10[0x10];
5978 u8 reserved_at_20[0x10];
5981 u8 reserved_at_40[0x8];
5982 u8 srq_number[0x18];
5984 u8 reserved_at_60[0x10];
5988 struct mlx5_ifc_arm_dct_out_bits {
5990 u8 reserved_at_8[0x18];
5994 u8 reserved_at_40[0x40];
5997 struct mlx5_ifc_arm_dct_in_bits {
5999 u8 reserved_at_10[0x10];
6001 u8 reserved_at_20[0x10];
6004 u8 reserved_at_40[0x8];
6005 u8 dct_number[0x18];
6007 u8 reserved_at_60[0x20];
6010 struct mlx5_ifc_alloc_xrcd_out_bits {
6012 u8 reserved_at_8[0x18];
6016 u8 reserved_at_40[0x8];
6019 u8 reserved_at_60[0x20];
6022 struct mlx5_ifc_alloc_xrcd_in_bits {
6024 u8 reserved_at_10[0x10];
6026 u8 reserved_at_20[0x10];
6029 u8 reserved_at_40[0x40];
6032 struct mlx5_ifc_alloc_uar_out_bits {
6034 u8 reserved_at_8[0x18];
6038 u8 reserved_at_40[0x8];
6041 u8 reserved_at_60[0x20];
6044 struct mlx5_ifc_alloc_uar_in_bits {
6046 u8 reserved_at_10[0x10];
6048 u8 reserved_at_20[0x10];
6051 u8 reserved_at_40[0x40];
6054 struct mlx5_ifc_alloc_transport_domain_out_bits {
6056 u8 reserved_at_8[0x18];
6060 u8 reserved_at_40[0x8];
6061 u8 transport_domain[0x18];
6063 u8 reserved_at_60[0x20];
6066 struct mlx5_ifc_alloc_transport_domain_in_bits {
6068 u8 reserved_at_10[0x10];
6070 u8 reserved_at_20[0x10];
6073 u8 reserved_at_40[0x40];
6076 struct mlx5_ifc_alloc_q_counter_out_bits {
6078 u8 reserved_at_8[0x18];
6082 u8 reserved_at_40[0x18];
6083 u8 counter_set_id[0x8];
6085 u8 reserved_at_60[0x20];
6088 struct mlx5_ifc_alloc_q_counter_in_bits {
6090 u8 reserved_at_10[0x10];
6092 u8 reserved_at_20[0x10];
6095 u8 reserved_at_40[0x40];
6098 struct mlx5_ifc_alloc_pd_out_bits {
6100 u8 reserved_at_8[0x18];
6104 u8 reserved_at_40[0x8];
6107 u8 reserved_at_60[0x20];
6110 struct mlx5_ifc_alloc_pd_in_bits {
6112 u8 reserved_at_10[0x10];
6114 u8 reserved_at_20[0x10];
6117 u8 reserved_at_40[0x40];
6120 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6122 u8 reserved_at_8[0x18];
6126 u8 reserved_at_40[0x40];
6129 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6131 u8 reserved_at_10[0x10];
6133 u8 reserved_at_20[0x10];
6136 u8 reserved_at_40[0x20];
6138 u8 reserved_at_60[0x10];
6139 u8 vxlan_udp_port[0x10];
6142 struct mlx5_ifc_access_register_out_bits {
6144 u8 reserved_at_8[0x18];
6148 u8 reserved_at_40[0x40];
6150 u8 register_data[0][0x20];
6154 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
6155 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
6158 struct mlx5_ifc_access_register_in_bits {
6160 u8 reserved_at_10[0x10];
6162 u8 reserved_at_20[0x10];
6165 u8 reserved_at_40[0x10];
6166 u8 register_id[0x10];
6170 u8 register_data[0][0x20];
6173 struct mlx5_ifc_sltp_reg_bits {
6178 u8 reserved_at_12[0x2];
6180 u8 reserved_at_18[0x8];
6182 u8 reserved_at_20[0x20];
6184 u8 reserved_at_40[0x7];
6190 u8 reserved_at_60[0xc];
6191 u8 ob_preemp_mode[0x4];
6195 u8 reserved_at_80[0x20];
6198 struct mlx5_ifc_slrg_reg_bits {
6203 u8 reserved_at_12[0x2];
6205 u8 reserved_at_18[0x8];
6207 u8 time_to_link_up[0x10];
6208 u8 reserved_at_30[0xc];
6209 u8 grade_lane_speed[0x4];
6211 u8 grade_version[0x8];
6214 u8 reserved_at_60[0x4];
6215 u8 height_grade_type[0x4];
6216 u8 height_grade[0x18];
6221 u8 reserved_at_a0[0x10];
6222 u8 height_sigma[0x10];
6224 u8 reserved_at_c0[0x20];
6226 u8 reserved_at_e0[0x4];
6227 u8 phase_grade_type[0x4];
6228 u8 phase_grade[0x18];
6230 u8 reserved_at_100[0x8];
6231 u8 phase_eo_pos[0x8];
6232 u8 reserved_at_110[0x8];
6233 u8 phase_eo_neg[0x8];
6235 u8 ffe_set_tested[0x10];
6236 u8 test_errors_per_lane[0x10];
6239 struct mlx5_ifc_pvlc_reg_bits {
6240 u8 reserved_at_0[0x8];
6242 u8 reserved_at_10[0x10];
6244 u8 reserved_at_20[0x1c];
6247 u8 reserved_at_40[0x1c];
6250 u8 reserved_at_60[0x1c];
6251 u8 vl_operational[0x4];
6254 struct mlx5_ifc_pude_reg_bits {
6257 u8 reserved_at_10[0x4];
6258 u8 admin_status[0x4];
6259 u8 reserved_at_18[0x4];
6260 u8 oper_status[0x4];
6262 u8 reserved_at_20[0x60];
6265 struct mlx5_ifc_ptys_reg_bits {
6266 u8 reserved_at_0[0x8];
6268 u8 reserved_at_10[0xd];
6271 u8 reserved_at_20[0x40];
6273 u8 eth_proto_capability[0x20];
6275 u8 ib_link_width_capability[0x10];
6276 u8 ib_proto_capability[0x10];
6278 u8 reserved_at_a0[0x20];
6280 u8 eth_proto_admin[0x20];
6282 u8 ib_link_width_admin[0x10];
6283 u8 ib_proto_admin[0x10];
6285 u8 reserved_at_100[0x20];
6287 u8 eth_proto_oper[0x20];
6289 u8 ib_link_width_oper[0x10];
6290 u8 ib_proto_oper[0x10];
6292 u8 reserved_at_160[0x20];
6294 u8 eth_proto_lp_advertise[0x20];
6296 u8 reserved_at_1a0[0x60];
6299 struct mlx5_ifc_ptas_reg_bits {
6300 u8 reserved_at_0[0x20];
6302 u8 algorithm_options[0x10];
6303 u8 reserved_at_30[0x4];
6304 u8 repetitions_mode[0x4];
6305 u8 num_of_repetitions[0x8];
6307 u8 grade_version[0x8];
6308 u8 height_grade_type[0x4];
6309 u8 phase_grade_type[0x4];
6310 u8 height_grade_weight[0x8];
6311 u8 phase_grade_weight[0x8];
6313 u8 gisim_measure_bits[0x10];
6314 u8 adaptive_tap_measure_bits[0x10];
6316 u8 ber_bath_high_error_threshold[0x10];
6317 u8 ber_bath_mid_error_threshold[0x10];
6319 u8 ber_bath_low_error_threshold[0x10];
6320 u8 one_ratio_high_threshold[0x10];
6322 u8 one_ratio_high_mid_threshold[0x10];
6323 u8 one_ratio_low_mid_threshold[0x10];
6325 u8 one_ratio_low_threshold[0x10];
6326 u8 ndeo_error_threshold[0x10];
6328 u8 mixer_offset_step_size[0x10];
6329 u8 reserved_at_110[0x8];
6330 u8 mix90_phase_for_voltage_bath[0x8];
6332 u8 mixer_offset_start[0x10];
6333 u8 mixer_offset_end[0x10];
6335 u8 reserved_at_140[0x15];
6336 u8 ber_test_time[0xb];
6339 struct mlx5_ifc_pspa_reg_bits {
6343 u8 reserved_at_18[0x8];
6345 u8 reserved_at_20[0x20];
6348 struct mlx5_ifc_pqdr_reg_bits {
6349 u8 reserved_at_0[0x8];
6351 u8 reserved_at_10[0x5];
6353 u8 reserved_at_18[0x6];
6356 u8 reserved_at_20[0x20];
6358 u8 reserved_at_40[0x10];
6359 u8 min_threshold[0x10];
6361 u8 reserved_at_60[0x10];
6362 u8 max_threshold[0x10];
6364 u8 reserved_at_80[0x10];
6365 u8 mark_probability_denominator[0x10];
6367 u8 reserved_at_a0[0x60];
6370 struct mlx5_ifc_ppsc_reg_bits {
6371 u8 reserved_at_0[0x8];
6373 u8 reserved_at_10[0x10];
6375 u8 reserved_at_20[0x60];
6377 u8 reserved_at_80[0x1c];
6380 u8 reserved_at_a0[0x1c];
6381 u8 wrps_status[0x4];
6383 u8 reserved_at_c0[0x8];
6384 u8 up_threshold[0x8];
6385 u8 reserved_at_d0[0x8];
6386 u8 down_threshold[0x8];
6388 u8 reserved_at_e0[0x20];
6390 u8 reserved_at_100[0x1c];
6393 u8 reserved_at_120[0x1c];
6394 u8 srps_status[0x4];
6396 u8 reserved_at_140[0x40];
6399 struct mlx5_ifc_pplr_reg_bits {
6400 u8 reserved_at_0[0x8];
6402 u8 reserved_at_10[0x10];
6404 u8 reserved_at_20[0x8];
6406 u8 reserved_at_30[0x8];
6410 struct mlx5_ifc_pplm_reg_bits {
6411 u8 reserved_at_0[0x8];
6413 u8 reserved_at_10[0x10];
6415 u8 reserved_at_20[0x20];
6417 u8 port_profile_mode[0x8];
6418 u8 static_port_profile[0x8];
6419 u8 active_port_profile[0x8];
6420 u8 reserved_at_58[0x8];
6422 u8 retransmission_active[0x8];
6423 u8 fec_mode_active[0x18];
6425 u8 reserved_at_80[0x20];
6428 struct mlx5_ifc_ppcnt_reg_bits {
6432 u8 reserved_at_12[0x8];
6436 u8 reserved_at_21[0x1c];
6439 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6442 struct mlx5_ifc_ppad_reg_bits {
6443 u8 reserved_at_0[0x3];
6445 u8 reserved_at_4[0x4];
6451 u8 reserved_at_40[0x40];
6454 struct mlx5_ifc_pmtu_reg_bits {
6455 u8 reserved_at_0[0x8];
6457 u8 reserved_at_10[0x10];
6460 u8 reserved_at_30[0x10];
6463 u8 reserved_at_50[0x10];
6466 u8 reserved_at_70[0x10];
6469 struct mlx5_ifc_pmpr_reg_bits {
6470 u8 reserved_at_0[0x8];
6472 u8 reserved_at_10[0x10];
6474 u8 reserved_at_20[0x18];
6475 u8 attenuation_5g[0x8];
6477 u8 reserved_at_40[0x18];
6478 u8 attenuation_7g[0x8];
6480 u8 reserved_at_60[0x18];
6481 u8 attenuation_12g[0x8];
6484 struct mlx5_ifc_pmpe_reg_bits {
6485 u8 reserved_at_0[0x8];
6487 u8 reserved_at_10[0xc];
6488 u8 module_status[0x4];
6490 u8 reserved_at_20[0x60];
6493 struct mlx5_ifc_pmpc_reg_bits {
6494 u8 module_state_updated[32][0x8];
6497 struct mlx5_ifc_pmlpn_reg_bits {
6498 u8 reserved_at_0[0x4];
6499 u8 mlpn_status[0x4];
6501 u8 reserved_at_10[0x10];
6504 u8 reserved_at_21[0x1f];
6507 struct mlx5_ifc_pmlp_reg_bits {
6509 u8 reserved_at_1[0x7];
6511 u8 reserved_at_10[0x8];
6514 u8 lane0_module_mapping[0x20];
6516 u8 lane1_module_mapping[0x20];
6518 u8 lane2_module_mapping[0x20];
6520 u8 lane3_module_mapping[0x20];
6522 u8 reserved_at_a0[0x160];
6525 struct mlx5_ifc_pmaos_reg_bits {
6526 u8 reserved_at_0[0x8];
6528 u8 reserved_at_10[0x4];
6529 u8 admin_status[0x4];
6530 u8 reserved_at_18[0x4];
6531 u8 oper_status[0x4];
6535 u8 reserved_at_22[0x1c];
6538 u8 reserved_at_40[0x40];
6541 struct mlx5_ifc_plpc_reg_bits {
6542 u8 reserved_at_0[0x4];
6544 u8 reserved_at_10[0x4];
6546 u8 reserved_at_18[0x8];
6548 u8 reserved_at_20[0x10];
6549 u8 lane_speed[0x10];
6551 u8 reserved_at_40[0x17];
6553 u8 fec_mode_policy[0x8];
6555 u8 retransmission_capability[0x8];
6556 u8 fec_mode_capability[0x18];
6558 u8 retransmission_support_admin[0x8];
6559 u8 fec_mode_support_admin[0x18];
6561 u8 retransmission_request_admin[0x8];
6562 u8 fec_mode_request_admin[0x18];
6564 u8 reserved_at_c0[0x80];
6567 struct mlx5_ifc_plib_reg_bits {
6568 u8 reserved_at_0[0x8];
6570 u8 reserved_at_10[0x8];
6573 u8 reserved_at_20[0x60];
6576 struct mlx5_ifc_plbf_reg_bits {
6577 u8 reserved_at_0[0x8];
6579 u8 reserved_at_10[0xd];
6582 u8 reserved_at_20[0x20];
6585 struct mlx5_ifc_pipg_reg_bits {
6586 u8 reserved_at_0[0x8];
6588 u8 reserved_at_10[0x10];
6591 u8 reserved_at_21[0x19];
6593 u8 reserved_at_3e[0x2];
6596 struct mlx5_ifc_pifr_reg_bits {
6597 u8 reserved_at_0[0x8];
6599 u8 reserved_at_10[0x10];
6601 u8 reserved_at_20[0xe0];
6603 u8 port_filter[8][0x20];
6605 u8 port_filter_update_en[8][0x20];
6608 struct mlx5_ifc_pfcc_reg_bits {
6609 u8 reserved_at_0[0x8];
6611 u8 reserved_at_10[0x10];
6614 u8 reserved_at_24[0x4];
6615 u8 prio_mask_tx[0x8];
6616 u8 reserved_at_30[0x8];
6617 u8 prio_mask_rx[0x8];
6621 u8 reserved_at_42[0x6];
6623 u8 reserved_at_50[0x10];
6627 u8 reserved_at_62[0x6];
6629 u8 reserved_at_70[0x10];
6631 u8 reserved_at_80[0x80];
6634 struct mlx5_ifc_pelc_reg_bits {
6636 u8 reserved_at_4[0x4];
6638 u8 reserved_at_10[0x10];
6641 u8 op_capability[0x8];
6647 u8 capability[0x40];
6653 u8 reserved_at_140[0x80];
6656 struct mlx5_ifc_peir_reg_bits {
6657 u8 reserved_at_0[0x8];
6659 u8 reserved_at_10[0x10];
6661 u8 reserved_at_20[0xc];
6662 u8 error_count[0x4];
6663 u8 reserved_at_30[0x10];
6665 u8 reserved_at_40[0xc];
6667 u8 reserved_at_50[0x8];
6671 struct mlx5_ifc_pcap_reg_bits {
6672 u8 reserved_at_0[0x8];
6674 u8 reserved_at_10[0x10];
6676 u8 port_capability_mask[4][0x20];
6679 struct mlx5_ifc_paos_reg_bits {
6682 u8 reserved_at_10[0x4];
6683 u8 admin_status[0x4];
6684 u8 reserved_at_18[0x4];
6685 u8 oper_status[0x4];
6689 u8 reserved_at_22[0x1c];
6692 u8 reserved_at_40[0x40];
6695 struct mlx5_ifc_pamp_reg_bits {
6696 u8 reserved_at_0[0x8];
6697 u8 opamp_group[0x8];
6698 u8 reserved_at_10[0xc];
6699 u8 opamp_group_type[0x4];
6701 u8 start_index[0x10];
6702 u8 reserved_at_30[0x4];
6703 u8 num_of_indices[0xc];
6705 u8 index_data[18][0x10];
6708 struct mlx5_ifc_lane_2_module_mapping_bits {
6709 u8 reserved_at_0[0x6];
6711 u8 reserved_at_8[0x6];
6713 u8 reserved_at_10[0x8];
6717 struct mlx5_ifc_bufferx_reg_bits {
6718 u8 reserved_at_0[0x6];
6721 u8 reserved_at_8[0xc];
6724 u8 xoff_threshold[0x10];
6725 u8 xon_threshold[0x10];
6728 struct mlx5_ifc_set_node_in_bits {
6729 u8 node_description[64][0x8];
6732 struct mlx5_ifc_register_power_settings_bits {
6733 u8 reserved_at_0[0x18];
6734 u8 power_settings_level[0x8];
6736 u8 reserved_at_20[0x60];
6739 struct mlx5_ifc_register_host_endianness_bits {
6741 u8 reserved_at_1[0x1f];
6743 u8 reserved_at_20[0x60];
6746 struct mlx5_ifc_umr_pointer_desc_argument_bits {
6747 u8 reserved_at_0[0x20];
6751 u8 addressh_63_32[0x20];
6753 u8 addressl_31_0[0x20];
6756 struct mlx5_ifc_ud_adrs_vector_bits {
6760 u8 reserved_at_41[0x7];
6761 u8 destination_qp_dct[0x18];
6763 u8 static_rate[0x4];
6764 u8 sl_eth_prio[0x4];
6767 u8 rlid_udp_sport[0x10];
6769 u8 reserved_at_80[0x20];
6771 u8 rmac_47_16[0x20];
6777 u8 reserved_at_e0[0x1];
6779 u8 reserved_at_e2[0x2];
6780 u8 src_addr_index[0x8];
6781 u8 flow_label[0x14];
6783 u8 rgid_rip[16][0x8];
6786 struct mlx5_ifc_pages_req_event_bits {
6787 u8 reserved_at_0[0x10];
6788 u8 function_id[0x10];
6792 u8 reserved_at_40[0xa0];
6795 struct mlx5_ifc_eqe_bits {
6796 u8 reserved_at_0[0x8];
6798 u8 reserved_at_10[0x8];
6799 u8 event_sub_type[0x8];
6801 u8 reserved_at_20[0xe0];
6803 union mlx5_ifc_event_auto_bits event_data;
6805 u8 reserved_at_1e0[0x10];
6807 u8 reserved_at_1f8[0x7];
6812 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
6815 struct mlx5_ifc_cmd_queue_entry_bits {
6817 u8 reserved_at_8[0x18];
6819 u8 input_length[0x20];
6821 u8 input_mailbox_pointer_63_32[0x20];
6823 u8 input_mailbox_pointer_31_9[0x17];
6824 u8 reserved_at_77[0x9];
6826 u8 command_input_inline_data[16][0x8];
6828 u8 command_output_inline_data[16][0x8];
6830 u8 output_mailbox_pointer_63_32[0x20];
6832 u8 output_mailbox_pointer_31_9[0x17];
6833 u8 reserved_at_1b7[0x9];
6835 u8 output_length[0x20];
6839 u8 reserved_at_1f0[0x8];
6844 struct mlx5_ifc_cmd_out_bits {
6846 u8 reserved_at_8[0x18];
6850 u8 command_output[0x20];
6853 struct mlx5_ifc_cmd_in_bits {
6855 u8 reserved_at_10[0x10];
6857 u8 reserved_at_20[0x10];
6860 u8 command[0][0x20];
6863 struct mlx5_ifc_cmd_if_box_bits {
6864 u8 mailbox_data[512][0x8];
6866 u8 reserved_at_1000[0x180];
6868 u8 next_pointer_63_32[0x20];
6870 u8 next_pointer_31_10[0x16];
6871 u8 reserved_at_11b6[0xa];
6873 u8 block_number[0x20];
6875 u8 reserved_at_11e0[0x8];
6877 u8 ctrl_signature[0x8];
6881 struct mlx5_ifc_mtt_bits {
6882 u8 ptag_63_32[0x20];
6885 u8 reserved_at_38[0x6];
6890 struct mlx5_ifc_query_wol_rol_out_bits {
6892 u8 reserved_at_8[0x18];
6896 u8 reserved_at_40[0x10];
6900 u8 reserved_at_60[0x20];
6903 struct mlx5_ifc_query_wol_rol_in_bits {
6905 u8 reserved_at_10[0x10];
6907 u8 reserved_at_20[0x10];
6910 u8 reserved_at_40[0x40];
6913 struct mlx5_ifc_set_wol_rol_out_bits {
6915 u8 reserved_at_8[0x18];
6919 u8 reserved_at_40[0x40];
6922 struct mlx5_ifc_set_wol_rol_in_bits {
6924 u8 reserved_at_10[0x10];
6926 u8 reserved_at_20[0x10];
6929 u8 rol_mode_valid[0x1];
6930 u8 wol_mode_valid[0x1];
6931 u8 reserved_at_42[0xe];
6935 u8 reserved_at_60[0x20];
6939 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
6940 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
6941 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
6945 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
6946 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
6947 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
6951 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
6952 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
6953 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
6954 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
6955 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
6956 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
6957 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
6958 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
6959 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
6960 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
6961 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
6964 struct mlx5_ifc_initial_seg_bits {
6965 u8 fw_rev_minor[0x10];
6966 u8 fw_rev_major[0x10];
6968 u8 cmd_interface_rev[0x10];
6969 u8 fw_rev_subminor[0x10];
6971 u8 reserved_at_40[0x40];
6973 u8 cmdq_phy_addr_63_32[0x20];
6975 u8 cmdq_phy_addr_31_12[0x14];
6976 u8 reserved_at_b4[0x2];
6977 u8 nic_interface[0x2];
6978 u8 log_cmdq_size[0x4];
6979 u8 log_cmdq_stride[0x4];
6981 u8 command_doorbell_vector[0x20];
6983 u8 reserved_at_e0[0xf00];
6985 u8 initializing[0x1];
6986 u8 reserved_at_fe1[0x4];
6987 u8 nic_interface_supported[0x3];
6988 u8 reserved_at_fe8[0x18];
6990 struct mlx5_ifc_health_buffer_bits health_buffer;
6992 u8 no_dram_nic_offset[0x20];
6994 u8 reserved_at_1220[0x6e40];
6996 u8 reserved_at_8060[0x1f];
6999 u8 health_syndrome[0x8];
7000 u8 health_counter[0x18];
7002 u8 reserved_at_80a0[0x17fc0];
7005 union mlx5_ifc_ports_control_registers_document_bits {
7006 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7007 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7008 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7009 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7010 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7011 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7012 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7013 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7014 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7015 struct mlx5_ifc_pamp_reg_bits pamp_reg;
7016 struct mlx5_ifc_paos_reg_bits paos_reg;
7017 struct mlx5_ifc_pcap_reg_bits pcap_reg;
7018 struct mlx5_ifc_peir_reg_bits peir_reg;
7019 struct mlx5_ifc_pelc_reg_bits pelc_reg;
7020 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
7021 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7022 struct mlx5_ifc_pifr_reg_bits pifr_reg;
7023 struct mlx5_ifc_pipg_reg_bits pipg_reg;
7024 struct mlx5_ifc_plbf_reg_bits plbf_reg;
7025 struct mlx5_ifc_plib_reg_bits plib_reg;
7026 struct mlx5_ifc_plpc_reg_bits plpc_reg;
7027 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7028 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7029 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7030 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7031 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7032 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7033 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7034 struct mlx5_ifc_ppad_reg_bits ppad_reg;
7035 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7036 struct mlx5_ifc_pplm_reg_bits pplm_reg;
7037 struct mlx5_ifc_pplr_reg_bits pplr_reg;
7038 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7039 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7040 struct mlx5_ifc_pspa_reg_bits pspa_reg;
7041 struct mlx5_ifc_ptas_reg_bits ptas_reg;
7042 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7043 struct mlx5_ifc_pude_reg_bits pude_reg;
7044 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7045 struct mlx5_ifc_slrg_reg_bits slrg_reg;
7046 struct mlx5_ifc_sltp_reg_bits sltp_reg;
7047 u8 reserved_at_0[0x60e0];
7050 union mlx5_ifc_debug_enhancements_document_bits {
7051 struct mlx5_ifc_health_buffer_bits health_buffer;
7052 u8 reserved_at_0[0x200];
7055 union mlx5_ifc_uplink_pci_interface_document_bits {
7056 struct mlx5_ifc_initial_seg_bits initial_seg;
7057 u8 reserved_at_0[0x20060];
7060 struct mlx5_ifc_set_flow_table_root_out_bits {
7062 u8 reserved_at_8[0x18];
7066 u8 reserved_at_40[0x40];
7069 struct mlx5_ifc_set_flow_table_root_in_bits {
7071 u8 reserved_at_10[0x10];
7073 u8 reserved_at_20[0x10];
7076 u8 reserved_at_40[0x40];
7079 u8 reserved_at_88[0x18];
7081 u8 reserved_at_a0[0x8];
7084 u8 reserved_at_c0[0x140];
7088 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7091 struct mlx5_ifc_modify_flow_table_out_bits {
7093 u8 reserved_at_8[0x18];
7097 u8 reserved_at_40[0x40];
7100 struct mlx5_ifc_modify_flow_table_in_bits {
7102 u8 reserved_at_10[0x10];
7104 u8 reserved_at_20[0x10];
7107 u8 reserved_at_40[0x20];
7109 u8 reserved_at_60[0x10];
7110 u8 modify_field_select[0x10];
7113 u8 reserved_at_88[0x18];
7115 u8 reserved_at_a0[0x8];
7118 u8 reserved_at_c0[0x4];
7119 u8 table_miss_mode[0x4];
7120 u8 reserved_at_c8[0x18];
7122 u8 reserved_at_e0[0x8];
7123 u8 table_miss_id[0x18];
7125 u8 reserved_at_100[0x100];
7128 struct mlx5_ifc_ets_tcn_config_reg_bits {
7132 u8 reserved_at_3[0x9];
7134 u8 reserved_at_10[0x9];
7135 u8 bw_allocation[0x7];
7137 u8 reserved_at_20[0xc];
7138 u8 max_bw_units[0x4];
7139 u8 reserved_at_30[0x8];
7140 u8 max_bw_value[0x8];
7143 struct mlx5_ifc_ets_global_config_reg_bits {
7144 u8 reserved_at_0[0x2];
7146 u8 reserved_at_3[0x1d];
7148 u8 reserved_at_20[0xc];
7149 u8 max_bw_units[0x4];
7150 u8 reserved_at_30[0x8];
7151 u8 max_bw_value[0x8];
7154 struct mlx5_ifc_qetc_reg_bits {
7155 u8 reserved_at_0[0x8];
7156 u8 port_number[0x8];
7157 u8 reserved_at_10[0x30];
7159 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
7160 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7163 struct mlx5_ifc_qtct_reg_bits {
7164 u8 reserved_at_0[0x8];
7165 u8 port_number[0x8];
7166 u8 reserved_at_10[0xd];
7169 u8 reserved_at_20[0x1d];
7173 #endif /* MLX5_IFC_H */