include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63 };
  64
  65 enum {
  66         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  67         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  68         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  69         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  70 };
  71
  72 enum {
  73         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  74         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  75 };
  76
  77 enum {
  78         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  79         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  80         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  81         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  82         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  83         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  84         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  85         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  86         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  87         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  88         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  89         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  90         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  91         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  92         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  93         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  94         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  95         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  96         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  97         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  98         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  99         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 100         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 101         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 102         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 103         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 104         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 105         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 106         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 107         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 108         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 109         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 110         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 111         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 112         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 113         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 114         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 115         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 116         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 117         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 118         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 119         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 120         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 121         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 122         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 123         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 124         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 125         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 126         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 127         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 128         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 129         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 130         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 131         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 132         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 133         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 134         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 135         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 136         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 137         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 138         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 139         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 140         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 141         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 142         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 143         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 144         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 145         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 146         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 147         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 148         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 149         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 150         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 151         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 152         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 153         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 154         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 155         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 156         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 157         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 158         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 159         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 160         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 161         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 162         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 163         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 164         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 165         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 166         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 167         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 168         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 169         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 170         MLX5_CMD_OP_NOP                           = 0x80d,
 171         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 172         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 173         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 174         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 175         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 176         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 177         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 178         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 179         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 180         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 181         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 182         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 183         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 184         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 185         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 186         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 187         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 188         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 189         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 190         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 191         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 192         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 193         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 194         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 195         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 196         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 197         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 198         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 199         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 200         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 201         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 202         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 203         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 204         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 205         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 206         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 207         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 208         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 209         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 210         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 211         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 212         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 213         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 214         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 215         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 216         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 217         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 218         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 219         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 220         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 221         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 222         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 223         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 224         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 225         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 226         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 227         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 228         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 229         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 230         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 231         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 232         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 233         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 234         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 235         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 236         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 237         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 238         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 239         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 240         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 241         MLX5_CMD_OP_MAX
 242 };
 243
 244 struct mlx5_ifc_flow_table_fields_supported_bits {
 245         u8         outer_dmac[0x1];
 246         u8         outer_smac[0x1];
 247         u8         outer_ether_type[0x1];
 248         u8         outer_ip_version[0x1];
 249         u8         outer_first_prio[0x1];
 250         u8         outer_first_cfi[0x1];
 251         u8         outer_first_vid[0x1];
 252         u8         outer_ipv4_ttl[0x1];
 253         u8         outer_second_prio[0x1];
 254         u8         outer_second_cfi[0x1];
 255         u8         outer_second_vid[0x1];
 256         u8         reserved_at_b[0x1];
 257         u8         outer_sip[0x1];
 258         u8         outer_dip[0x1];
 259         u8         outer_frag[0x1];
 260         u8         outer_ip_protocol[0x1];
 261         u8         outer_ip_ecn[0x1];
 262         u8         outer_ip_dscp[0x1];
 263         u8         outer_udp_sport[0x1];
 264         u8         outer_udp_dport[0x1];
 265         u8         outer_tcp_sport[0x1];
 266         u8         outer_tcp_dport[0x1];
 267         u8         outer_tcp_flags[0x1];
 268         u8         outer_gre_protocol[0x1];
 269         u8         outer_gre_key[0x1];
 270         u8         outer_vxlan_vni[0x1];
 271         u8         reserved_at_1a[0x5];
 272         u8         source_eswitch_port[0x1];
 273
 274         u8         inner_dmac[0x1];
 275         u8         inner_smac[0x1];
 276         u8         inner_ether_type[0x1];
 277         u8         inner_ip_version[0x1];
 278         u8         inner_first_prio[0x1];
 279         u8         inner_first_cfi[0x1];
 280         u8         inner_first_vid[0x1];
 281         u8         reserved_at_27[0x1];
 282         u8         inner_second_prio[0x1];
 283         u8         inner_second_cfi[0x1];
 284         u8         inner_second_vid[0x1];
 285         u8         reserved_at_2b[0x1];
 286         u8         inner_sip[0x1];
 287         u8         inner_dip[0x1];
 288         u8         inner_frag[0x1];
 289         u8         inner_ip_protocol[0x1];
 290         u8         inner_ip_ecn[0x1];
 291         u8         inner_ip_dscp[0x1];
 292         u8         inner_udp_sport[0x1];
 293         u8         inner_udp_dport[0x1];
 294         u8         inner_tcp_sport[0x1];
 295         u8         inner_tcp_dport[0x1];
 296         u8         inner_tcp_flags[0x1];
 297         u8         reserved_at_37[0x9];
 298         u8         reserved_at_40[0x1a];
 299         u8         bth_dst_qp[0x1];
 300
 301         u8         reserved_at_5b[0x25];
 302 };
 303
 304 struct mlx5_ifc_flow_table_prop_layout_bits {
 305         u8         ft_support[0x1];
 306         u8         reserved_at_1[0x1];
 307         u8         flow_counter[0x1];
 308         u8         flow_modify_en[0x1];
 309         u8         modify_root[0x1];
 310         u8         identified_miss_table_mode[0x1];
 311         u8         flow_table_modify[0x1];
 312         u8         encap[0x1];
 313         u8         decap[0x1];
 314         u8         reserved_at_9[0x17];
 315
 316         u8         reserved_at_20[0x2];
 317         u8         log_max_ft_size[0x6];
 318         u8         log_max_modify_header_context[0x8];
 319         u8         max_modify_header_actions[0x8];
 320         u8         max_ft_level[0x8];
 321
 322         u8         reserved_at_40[0x20];
 323
 324         u8         reserved_at_60[0x18];
 325         u8         log_max_ft_num[0x8];
 326
 327         u8         reserved_at_80[0x18];
 328         u8         log_max_destination[0x8];
 329
 330         u8         log_max_flow_counter[0x8];
 331         u8         reserved_at_a8[0x10];
 332         u8         log_max_flow[0x8];
 333
 334         u8         reserved_at_c0[0x40];
 335
 336         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 337
 338         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 339 };
 340
 341 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 342         u8         send[0x1];
 343         u8         receive[0x1];
 344         u8         write[0x1];
 345         u8         read[0x1];
 346         u8         atomic[0x1];
 347         u8         srq_receive[0x1];
 348         u8         reserved_at_6[0x1a];
 349 };
 350
 351 struct mlx5_ifc_ipv4_layout_bits {
 352         u8         reserved_at_0[0x60];
 353
 354         u8         ipv4[0x20];
 355 };
 356
 357 struct mlx5_ifc_ipv6_layout_bits {
 358         u8         ipv6[16][0x8];
 359 };
 360
 361 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 362         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 363         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 364         u8         reserved_at_0[0x80];
 365 };
 366
 367 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 368         u8         smac_47_16[0x20];
 369
 370         u8         smac_15_0[0x10];
 371         u8         ethertype[0x10];
 372
 373         u8         dmac_47_16[0x20];
 374
 375         u8         dmac_15_0[0x10];
 376         u8         first_prio[0x3];
 377         u8         first_cfi[0x1];
 378         u8         first_vid[0xc];
 379
 380         u8         ip_protocol[0x8];
 381         u8         ip_dscp[0x6];
 382         u8         ip_ecn[0x2];
 383         u8         cvlan_tag[0x1];
 384         u8         svlan_tag[0x1];
 385         u8         frag[0x1];
 386         u8         ip_version[0x4];
 387         u8         tcp_flags[0x9];
 388
 389         u8         tcp_sport[0x10];
 390         u8         tcp_dport[0x10];
 391
 392         u8         reserved_at_c0[0x18];
 393         u8         ttl_hoplimit[0x8];
 394
 395         u8         udp_sport[0x10];
 396         u8         udp_dport[0x10];
 397
 398         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 399
 400         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 401 };
 402
 403 struct mlx5_ifc_fte_match_set_misc_bits {
 404         u8         reserved_at_0[0x8];
 405         u8         source_sqn[0x18];
 406
 407         u8         reserved_at_20[0x10];
 408         u8         source_port[0x10];
 409
 410         u8         outer_second_prio[0x3];
 411         u8         outer_second_cfi[0x1];
 412         u8         outer_second_vid[0xc];
 413         u8         inner_second_prio[0x3];
 414         u8         inner_second_cfi[0x1];
 415         u8         inner_second_vid[0xc];
 416
 417         u8         outer_second_cvlan_tag[0x1];
 418         u8         inner_second_cvlan_tag[0x1];
 419         u8         outer_second_svlan_tag[0x1];
 420         u8         inner_second_svlan_tag[0x1];
 421         u8         reserved_at_64[0xc];
 422         u8         gre_protocol[0x10];
 423
 424         u8         gre_key_h[0x18];
 425         u8         gre_key_l[0x8];
 426
 427         u8         vxlan_vni[0x18];
 428         u8         reserved_at_b8[0x8];
 429
 430         u8         reserved_at_c0[0x20];
 431
 432         u8         reserved_at_e0[0xc];
 433         u8         outer_ipv6_flow_label[0x14];
 434
 435         u8         reserved_at_100[0xc];
 436         u8         inner_ipv6_flow_label[0x14];
 437
 438         u8         reserved_at_120[0x28];
 439         u8         bth_dst_qp[0x18];
 440         u8         reserved_at_160[0xa0];
 441 };
 442
 443 struct mlx5_ifc_cmd_pas_bits {
 444         u8         pa_h[0x20];
 445
 446         u8         pa_l[0x14];
 447         u8         reserved_at_34[0xc];
 448 };
 449
 450 struct mlx5_ifc_uint64_bits {
 451         u8         hi[0x20];
 452
 453         u8         lo[0x20];
 454 };
 455
 456 enum {
 457         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 458         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 459         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 460         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 461         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 462         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 463         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 464         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 465         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 466         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 467 };
 468
 469 struct mlx5_ifc_ads_bits {
 470         u8         fl[0x1];
 471         u8         free_ar[0x1];
 472         u8         reserved_at_2[0xe];
 473         u8         pkey_index[0x10];
 474
 475         u8         reserved_at_20[0x8];
 476         u8         grh[0x1];
 477         u8         mlid[0x7];
 478         u8         rlid[0x10];
 479
 480         u8         ack_timeout[0x5];
 481         u8         reserved_at_45[0x3];
 482         u8         src_addr_index[0x8];
 483         u8         reserved_at_50[0x4];
 484         u8         stat_rate[0x4];
 485         u8         hop_limit[0x8];
 486
 487         u8         reserved_at_60[0x4];
 488         u8         tclass[0x8];
 489         u8         flow_label[0x14];
 490
 491         u8         rgid_rip[16][0x8];
 492
 493         u8         reserved_at_100[0x4];
 494         u8         f_dscp[0x1];
 495         u8         f_ecn[0x1];
 496         u8         reserved_at_106[0x1];
 497         u8         f_eth_prio[0x1];
 498         u8         ecn[0x2];
 499         u8         dscp[0x6];
 500         u8         udp_sport[0x10];
 501
 502         u8         dei_cfi[0x1];
 503         u8         eth_prio[0x3];
 504         u8         sl[0x4];
 505         u8         vhca_port_num[0x8];
 506         u8         rmac_47_32[0x10];
 507
 508         u8         rmac_31_0[0x20];
 509 };
 510
 511 struct mlx5_ifc_flow_table_nic_cap_bits {
 512         u8         nic_rx_multi_path_tirs[0x1];
 513         u8         nic_rx_multi_path_tirs_fts[0x1];
 514         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 515         u8         reserved_at_3[0x1fd];
 516
 517         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 518
 519         u8         reserved_at_400[0x200];
 520
 521         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 522
 523         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 524
 525         u8         reserved_at_a00[0x200];
 526
 527         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 528
 529         u8         reserved_at_e00[0x7200];
 530 };
 531
 532 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 533         u8     reserved_at_0[0x200];
 534
 535         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 536
 537         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 538
 539         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 540
 541         u8      reserved_at_800[0x7800];
 542 };
 543
 544 struct mlx5_ifc_e_switch_cap_bits {
 545         u8         vport_svlan_strip[0x1];
 546         u8         vport_cvlan_strip[0x1];
 547         u8         vport_svlan_insert[0x1];
 548         u8         vport_cvlan_insert_if_not_exist[0x1];
 549         u8         vport_cvlan_insert_overwrite[0x1];
 550         u8         reserved_at_5[0x19];
 551         u8         nic_vport_node_guid_modify[0x1];
 552         u8         nic_vport_port_guid_modify[0x1];
 553
 554         u8         vxlan_encap_decap[0x1];
 555         u8         nvgre_encap_decap[0x1];
 556         u8         reserved_at_22[0x9];
 557         u8         log_max_encap_headers[0x5];
 558         u8         reserved_2b[0x6];
 559         u8         max_encap_header_size[0xa];
 560
 561         u8         reserved_40[0x7c0];
 562
 563 };
 564
 565 struct mlx5_ifc_qos_cap_bits {
 566         u8         packet_pacing[0x1];
 567         u8         esw_scheduling[0x1];
 568         u8         esw_bw_share[0x1];
 569         u8         esw_rate_limit[0x1];
 570         u8         reserved_at_4[0x1c];
 571
 572         u8         reserved_at_20[0x20];
 573
 574         u8         packet_pacing_max_rate[0x20];
 575
 576         u8         packet_pacing_min_rate[0x20];
 577
 578         u8         reserved_at_80[0x10];
 579         u8         packet_pacing_rate_table_size[0x10];
 580
 581         u8         esw_element_type[0x10];
 582         u8         esw_tsar_type[0x10];
 583
 584         u8         reserved_at_c0[0x10];
 585         u8         max_qos_para_vport[0x10];
 586
 587         u8         max_tsar_bw_share[0x20];
 588
 589         u8         reserved_at_100[0x700];
 590 };
 591
 592 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 593         u8         csum_cap[0x1];
 594         u8         vlan_cap[0x1];
 595         u8         lro_cap[0x1];
 596         u8         lro_psh_flag[0x1];
 597         u8         lro_time_stamp[0x1];
 598         u8         reserved_at_5[0x2];
 599         u8         wqe_vlan_insert[0x1];
 600         u8         self_lb_en_modifiable[0x1];
 601         u8         reserved_at_9[0x2];
 602         u8         max_lso_cap[0x5];
 603         u8         multi_pkt_send_wqe[0x2];
 604         u8         wqe_inline_mode[0x2];
 605         u8         rss_ind_tbl_cap[0x4];
 606         u8         reg_umr_sq[0x1];
 607         u8         scatter_fcs[0x1];
 608         u8         enhanced_multi_pkt_send_wqe[0x1];
 609         u8         tunnel_lso_const_out_ip_id[0x1];
 610         u8         reserved_at_1c[0x2];
 611         u8         tunnel_stateless_gre[0x1];
 612         u8         tunnel_stateless_vxlan[0x1];
 613
 614         u8         swp[0x1];
 615         u8         swp_csum[0x1];
 616         u8         swp_lso[0x1];
 617         u8         reserved_at_23[0x1b];
 618         u8         max_geneve_opt_len[0x1];
 619         u8         tunnel_stateless_geneve_rx[0x1];
 620
 621         u8         reserved_at_40[0x10];
 622         u8         lro_min_mss_size[0x10];
 623
 624         u8         reserved_at_60[0x120];
 625
 626         u8         lro_timer_supported_periods[4][0x20];
 627
 628         u8         reserved_at_200[0x600];
 629 };
 630
 631 struct mlx5_ifc_roce_cap_bits {
 632         u8         roce_apm[0x1];
 633         u8         reserved_at_1[0x1f];
 634
 635         u8         reserved_at_20[0x60];
 636
 637         u8         reserved_at_80[0xc];
 638         u8         l3_type[0x4];
 639         u8         reserved_at_90[0x8];
 640         u8         roce_version[0x8];
 641
 642         u8         reserved_at_a0[0x10];
 643         u8         r_roce_dest_udp_port[0x10];
 644
 645         u8         r_roce_max_src_udp_port[0x10];
 646         u8         r_roce_min_src_udp_port[0x10];
 647
 648         u8         reserved_at_e0[0x10];
 649         u8         roce_address_table_size[0x10];
 650
 651         u8         reserved_at_100[0x700];
 652 };
 653
 654 enum {
 655         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 656         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 657         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 658         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 659         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 660         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 661         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 662         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 663         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 664 };
 665
 666 enum {
 667         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 668         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 669         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 670         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 671         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 672         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 673         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 674         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 675         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 676 };
 677
 678 struct mlx5_ifc_atomic_caps_bits {
 679         u8         reserved_at_0[0x40];
 680
 681         u8         atomic_req_8B_endianness_mode[0x2];
 682         u8         reserved_at_42[0x4];
 683         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 684
 685         u8         reserved_at_47[0x19];
 686
 687         u8         reserved_at_60[0x20];
 688
 689         u8         reserved_at_80[0x10];
 690         u8         atomic_operations[0x10];
 691
 692         u8         reserved_at_a0[0x10];
 693         u8         atomic_size_qp[0x10];
 694
 695         u8         reserved_at_c0[0x10];
 696         u8         atomic_size_dc[0x10];
 697
 698         u8         reserved_at_e0[0x720];
 699 };
 700
 701 struct mlx5_ifc_odp_cap_bits {
 702         u8         reserved_at_0[0x40];
 703
 704         u8         sig[0x1];
 705         u8         reserved_at_41[0x1f];
 706
 707         u8         reserved_at_60[0x20];
 708
 709         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 710
 711         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 712
 713         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 714
 715         u8         reserved_at_e0[0x720];
 716 };
 717
 718 struct mlx5_ifc_calc_op {
 719         u8        reserved_at_0[0x10];
 720         u8        reserved_at_10[0x9];
 721         u8        op_swap_endianness[0x1];
 722         u8        op_min[0x1];
 723         u8        op_xor[0x1];
 724         u8        op_or[0x1];
 725         u8        op_and[0x1];
 726         u8        op_max[0x1];
 727         u8        op_add[0x1];
 728 };
 729
 730 struct mlx5_ifc_vector_calc_cap_bits {
 731         u8         calc_matrix[0x1];
 732         u8         reserved_at_1[0x1f];
 733         u8         reserved_at_20[0x8];
 734         u8         max_vec_count[0x8];
 735         u8         reserved_at_30[0xd];
 736         u8         max_chunk_size[0x3];
 737         struct mlx5_ifc_calc_op calc0;
 738         struct mlx5_ifc_calc_op calc1;
 739         struct mlx5_ifc_calc_op calc2;
 740         struct mlx5_ifc_calc_op calc3;
 741
 742         u8         reserved_at_e0[0x720];
 743 };
 744
 745 enum {
 746         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 747         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 748         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 749         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
 750 };
 751
 752 enum {
 753         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 754         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 755 };
 756
 757 enum {
 758         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 759         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 760         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 761         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 762         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 763 };
 764
 765 enum {
 766         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 767         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 768         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 769         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 770         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 771         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 772 };
 773
 774 enum {
 775         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 776         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 777 };
 778
 779 enum {
 780         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 781         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 782         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 783 };
 784
 785 enum {
 786         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 787         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 788 };
 789
 790 enum {
 791         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
 792         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
 793         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
 794 };
 795
 796 struct mlx5_ifc_cmd_hca_cap_bits {
 797         u8         reserved_at_0[0x30];
 798         u8         vhca_id[0x10];
 799
 800         u8         reserved_at_40[0x40];
 801
 802         u8         log_max_srq_sz[0x8];
 803         u8         log_max_qp_sz[0x8];
 804         u8         reserved_at_90[0xb];
 805         u8         log_max_qp[0x5];
 806
 807         u8         reserved_at_a0[0xb];
 808         u8         log_max_srq[0x5];
 809         u8         reserved_at_b0[0x10];
 810
 811         u8         reserved_at_c0[0x8];
 812         u8         log_max_cq_sz[0x8];
 813         u8         reserved_at_d0[0xb];
 814         u8         log_max_cq[0x5];
 815
 816         u8         log_max_eq_sz[0x8];
 817         u8         reserved_at_e8[0x2];
 818         u8         log_max_mkey[0x6];
 819         u8         reserved_at_f0[0xc];
 820         u8         log_max_eq[0x4];
 821
 822         u8         max_indirection[0x8];
 823         u8         fixed_buffer_size[0x1];
 824         u8         log_max_mrw_sz[0x7];
 825         u8         force_teardown[0x1];
 826         u8         reserved_at_111[0x1];
 827         u8         log_max_bsf_list_size[0x6];
 828         u8         umr_extended_translation_offset[0x1];
 829         u8         null_mkey[0x1];
 830         u8         log_max_klm_list_size[0x6];
 831
 832         u8         reserved_at_120[0xa];
 833         u8         log_max_ra_req_dc[0x6];
 834         u8         reserved_at_130[0xa];
 835         u8         log_max_ra_res_dc[0x6];
 836
 837         u8         reserved_at_140[0xa];
 838         u8         log_max_ra_req_qp[0x6];
 839         u8         reserved_at_150[0xa];
 840         u8         log_max_ra_res_qp[0x6];
 841
 842         u8         end_pad[0x1];
 843         u8         cc_query_allowed[0x1];
 844         u8         cc_modify_allowed[0x1];
 845         u8         start_pad[0x1];
 846         u8         cache_line_128byte[0x1];
 847         u8         reserved_at_165[0xa];
 848         u8         qcam_reg[0x1];
 849         u8         gid_table_size[0x10];
 850
 851         u8         out_of_seq_cnt[0x1];
 852         u8         vport_counters[0x1];
 853         u8         retransmission_q_counters[0x1];
 854         u8         reserved_at_183[0x1];
 855         u8         modify_rq_counter_set_id[0x1];
 856         u8         rq_delay_drop[0x1];
 857         u8         max_qp_cnt[0xa];
 858         u8         pkey_table_size[0x10];
 859
 860         u8         vport_group_manager[0x1];
 861         u8         vhca_group_manager[0x1];
 862         u8         ib_virt[0x1];
 863         u8         eth_virt[0x1];
 864         u8         reserved_at_1a4[0x1];
 865         u8         ets[0x1];
 866         u8         nic_flow_table[0x1];
 867         u8         eswitch_flow_table[0x1];
 868         u8         early_vf_enable[0x1];
 869         u8         mcam_reg[0x1];
 870         u8         pcam_reg[0x1];
 871         u8         local_ca_ack_delay[0x5];
 872         u8         port_module_event[0x1];
 873         u8         enhanced_error_q_counters[0x1];
 874         u8         ports_check[0x1];
 875         u8         reserved_at_1b3[0x1];
 876         u8         disable_link_up[0x1];
 877         u8         beacon_led[0x1];
 878         u8         port_type[0x2];
 879         u8         num_ports[0x8];
 880
 881         u8         reserved_at_1c0[0x1];
 882         u8         pps[0x1];
 883         u8         pps_modify[0x1];
 884         u8         log_max_msg[0x5];
 885         u8         reserved_at_1c8[0x4];
 886         u8         max_tc[0x4];
 887         u8         reserved_at_1d0[0x1];
 888         u8         dcbx[0x1];
 889         u8         general_notification_event[0x1];
 890         u8         reserved_at_1d3[0x2];
 891         u8         fpga[0x1];
 892         u8         rol_s[0x1];
 893         u8         rol_g[0x1];
 894         u8         reserved_at_1d8[0x1];
 895         u8         wol_s[0x1];
 896         u8         wol_g[0x1];
 897         u8         wol_a[0x1];
 898         u8         wol_b[0x1];
 899         u8         wol_m[0x1];
 900         u8         wol_u[0x1];
 901         u8         wol_p[0x1];
 902
 903         u8         stat_rate_support[0x10];
 904         u8         reserved_at_1f0[0xc];
 905         u8         cqe_version[0x4];
 906
 907         u8         compact_address_vector[0x1];
 908         u8         striding_rq[0x1];
 909         u8         reserved_at_202[0x1];
 910         u8         ipoib_enhanced_offloads[0x1];
 911         u8         ipoib_basic_offloads[0x1];
 912         u8         reserved_at_205[0x5];
 913         u8         umr_fence[0x2];
 914         u8         reserved_at_20c[0x3];
 915         u8         drain_sigerr[0x1];
 916         u8         cmdif_checksum[0x2];
 917         u8         sigerr_cqe[0x1];
 918         u8         reserved_at_213[0x1];
 919         u8         wq_signature[0x1];
 920         u8         sctr_data_cqe[0x1];
 921         u8         reserved_at_216[0x1];
 922         u8         sho[0x1];
 923         u8         tph[0x1];
 924         u8         rf[0x1];
 925         u8         dct[0x1];
 926         u8         qos[0x1];
 927         u8         eth_net_offloads[0x1];
 928         u8         roce[0x1];
 929         u8         atomic[0x1];
 930         u8         reserved_at_21f[0x1];
 931
 932         u8         cq_oi[0x1];
 933         u8         cq_resize[0x1];
 934         u8         cq_moderation[0x1];
 935         u8         reserved_at_223[0x3];
 936         u8         cq_eq_remap[0x1];
 937         u8         pg[0x1];
 938         u8         block_lb_mc[0x1];
 939         u8         reserved_at_229[0x1];
 940         u8         scqe_break_moderation[0x1];
 941         u8         cq_period_start_from_cqe[0x1];
 942         u8         cd[0x1];
 943         u8         reserved_at_22d[0x1];
 944         u8         apm[0x1];
 945         u8         vector_calc[0x1];
 946         u8         umr_ptr_rlky[0x1];
 947         u8         imaicl[0x1];
 948         u8         reserved_at_232[0x4];
 949         u8         qkv[0x1];
 950         u8         pkv[0x1];
 951         u8         set_deth_sqpn[0x1];
 952         u8         reserved_at_239[0x3];
 953         u8         xrc[0x1];
 954         u8         ud[0x1];
 955         u8         uc[0x1];
 956         u8         rc[0x1];
 957
 958         u8         uar_4k[0x1];
 959         u8         reserved_at_241[0x9];
 960         u8         uar_sz[0x6];
 961         u8         reserved_at_250[0x8];
 962         u8         log_pg_sz[0x8];
 963
 964         u8         bf[0x1];
 965         u8         driver_version[0x1];
 966         u8         pad_tx_eth_packet[0x1];
 967         u8         reserved_at_263[0x8];
 968         u8         log_bf_reg_size[0x5];
 969
 970         u8         reserved_at_270[0xb];
 971         u8         lag_master[0x1];
 972         u8         num_lag_ports[0x4];
 973
 974         u8         reserved_at_280[0x10];
 975         u8         max_wqe_sz_sq[0x10];
 976
 977         u8         reserved_at_2a0[0x10];
 978         u8         max_wqe_sz_rq[0x10];
 979
 980         u8         max_flow_counter_31_16[0x10];
 981         u8         max_wqe_sz_sq_dc[0x10];
 982
 983         u8         reserved_at_2e0[0x7];
 984         u8         max_qp_mcg[0x19];
 985
 986         u8         reserved_at_300[0x18];
 987         u8         log_max_mcg[0x8];
 988
 989         u8         reserved_at_320[0x3];
 990         u8         log_max_transport_domain[0x5];
 991         u8         reserved_at_328[0x3];
 992         u8         log_max_pd[0x5];
 993         u8         reserved_at_330[0xb];
 994         u8         log_max_xrcd[0x5];
 995
 996         u8         reserved_at_340[0x8];
 997         u8         log_max_flow_counter_bulk[0x8];
 998         u8         max_flow_counter_15_0[0x10];
 999
1000
1001         u8         reserved_at_360[0x3];
1002         u8         log_max_rq[0x5];
1003         u8         reserved_at_368[0x3];
1004         u8         log_max_sq[0x5];
1005         u8         reserved_at_370[0x3];
1006         u8         log_max_tir[0x5];
1007         u8         reserved_at_378[0x3];
1008         u8         log_max_tis[0x5];
1009
1010         u8         basic_cyclic_rcv_wqe[0x1];
1011         u8         reserved_at_381[0x2];
1012         u8         log_max_rmp[0x5];
1013         u8         reserved_at_388[0x3];
1014         u8         log_max_rqt[0x5];
1015         u8         reserved_at_390[0x3];
1016         u8         log_max_rqt_size[0x5];
1017         u8         reserved_at_398[0x3];
1018         u8         log_max_tis_per_sq[0x5];
1019
1020         u8         reserved_at_3a0[0x3];
1021         u8         log_max_stride_sz_rq[0x5];
1022         u8         reserved_at_3a8[0x3];
1023         u8         log_min_stride_sz_rq[0x5];
1024         u8         reserved_at_3b0[0x3];
1025         u8         log_max_stride_sz_sq[0x5];
1026         u8         reserved_at_3b8[0x3];
1027         u8         log_min_stride_sz_sq[0x5];
1028
1029         u8         reserved_at_3c0[0x1b];
1030         u8         log_max_wq_sz[0x5];
1031
1032         u8         nic_vport_change_event[0x1];
1033         u8         disable_local_lb[0x1];
1034         u8         reserved_at_3e2[0x9];
1035         u8         log_max_vlan_list[0x5];
1036         u8         reserved_at_3f0[0x3];
1037         u8         log_max_current_mc_list[0x5];
1038         u8         reserved_at_3f8[0x3];
1039         u8         log_max_current_uc_list[0x5];
1040
1041         u8         reserved_at_400[0x80];
1042
1043         u8         reserved_at_480[0x3];
1044         u8         log_max_l2_table[0x5];
1045         u8         reserved_at_488[0x8];
1046         u8         log_uar_page_sz[0x10];
1047
1048         u8         reserved_at_4a0[0x20];
1049         u8         device_frequency_mhz[0x20];
1050         u8         device_frequency_khz[0x20];
1051
1052         u8         reserved_at_500[0x20];
1053         u8         num_of_uars_per_page[0x20];
1054         u8         reserved_at_540[0x40];
1055
1056         u8         reserved_at_580[0x3d];
1057         u8         cqe_128_always[0x1];
1058         u8         cqe_compression_128[0x1];
1059         u8         cqe_compression[0x1];
1060
1061         u8         cqe_compression_timeout[0x10];
1062         u8         cqe_compression_max_num[0x10];
1063
1064         u8         reserved_at_5e0[0x10];
1065         u8         tag_matching[0x1];
1066         u8         rndv_offload_rc[0x1];
1067         u8         rndv_offload_dc[0x1];
1068         u8         log_tag_matching_list_sz[0x5];
1069         u8         reserved_at_5f8[0x3];
1070         u8         log_max_xrq[0x5];
1071
1072         u8         affiliate_nic_vport_criteria[0x8];
1073         u8         native_port_num[0x8];
1074         u8         num_vhca_ports[0x8];
1075         u8         reserved_at_618[0x6];
1076         u8         sw_owner_id[0x1];
1077         u8         reserved_at_61f[0x1e1];
1078 };
1079
1080 enum mlx5_flow_destination_type {
1081         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1082         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1083         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1084
1085         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1086 };
1087
1088 struct mlx5_ifc_dest_format_struct_bits {
1089         u8         destination_type[0x8];
1090         u8         destination_id[0x18];
1091
1092         u8         reserved_at_20[0x20];
1093 };
1094
1095 struct mlx5_ifc_flow_counter_list_bits {
1096         u8         flow_counter_id[0x20];
1097
1098         u8         reserved_at_20[0x20];
1099 };
1100
1101 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1102         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1103         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1104         u8         reserved_at_0[0x40];
1105 };
1106
1107 struct mlx5_ifc_fte_match_param_bits {
1108         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1109
1110         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1111
1112         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1113
1114         u8         reserved_at_600[0xa00];
1115 };
1116
1117 enum {
1118         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1119         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1120         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1121         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1122         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1123 };
1124
1125 struct mlx5_ifc_rx_hash_field_select_bits {
1126         u8         l3_prot_type[0x1];
1127         u8         l4_prot_type[0x1];
1128         u8         selected_fields[0x1e];
1129 };
1130
1131 enum {
1132         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1133         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1134 };
1135
1136 enum {
1137         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1138         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1139 };
1140
1141 struct mlx5_ifc_wq_bits {
1142         u8         wq_type[0x4];
1143         u8         wq_signature[0x1];
1144         u8         end_padding_mode[0x2];
1145         u8         cd_slave[0x1];
1146         u8         reserved_at_8[0x18];
1147
1148         u8         hds_skip_first_sge[0x1];
1149         u8         log2_hds_buf_size[0x3];
1150         u8         reserved_at_24[0x7];
1151         u8         page_offset[0x5];
1152         u8         lwm[0x10];
1153
1154         u8         reserved_at_40[0x8];
1155         u8         pd[0x18];
1156
1157         u8         reserved_at_60[0x8];
1158         u8         uar_page[0x18];
1159
1160         u8         dbr_addr[0x40];
1161
1162         u8         hw_counter[0x20];
1163
1164         u8         sw_counter[0x20];
1165
1166         u8         reserved_at_100[0xc];
1167         u8         log_wq_stride[0x4];
1168         u8         reserved_at_110[0x3];
1169         u8         log_wq_pg_sz[0x5];
1170         u8         reserved_at_118[0x3];
1171         u8         log_wq_sz[0x5];
1172
1173         u8         reserved_at_120[0x15];
1174         u8         log_wqe_num_of_strides[0x3];
1175         u8         two_byte_shift_en[0x1];
1176         u8         reserved_at_139[0x4];
1177         u8         log_wqe_stride_size[0x3];
1178
1179         u8         reserved_at_140[0x4c0];
1180
1181         struct mlx5_ifc_cmd_pas_bits pas[0];
1182 };
1183
1184 struct mlx5_ifc_rq_num_bits {
1185         u8         reserved_at_0[0x8];
1186         u8         rq_num[0x18];
1187 };
1188
1189 struct mlx5_ifc_mac_address_layout_bits {
1190         u8         reserved_at_0[0x10];
1191         u8         mac_addr_47_32[0x10];
1192
1193         u8         mac_addr_31_0[0x20];
1194 };
1195
1196 struct mlx5_ifc_vlan_layout_bits {
1197         u8         reserved_at_0[0x14];
1198         u8         vlan[0x0c];
1199
1200         u8         reserved_at_20[0x20];
1201 };
1202
1203 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1204         u8         reserved_at_0[0xa0];
1205
1206         u8         min_time_between_cnps[0x20];
1207
1208         u8         reserved_at_c0[0x12];
1209         u8         cnp_dscp[0x6];
1210         u8         reserved_at_d8[0x4];
1211         u8         cnp_prio_mode[0x1];
1212         u8         cnp_802p_prio[0x3];
1213
1214         u8         reserved_at_e0[0x720];
1215 };
1216
1217 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1218         u8         reserved_at_0[0x60];
1219
1220         u8         reserved_at_60[0x4];
1221         u8         clamp_tgt_rate[0x1];
1222         u8         reserved_at_65[0x3];
1223         u8         clamp_tgt_rate_after_time_inc[0x1];
1224         u8         reserved_at_69[0x17];
1225
1226         u8         reserved_at_80[0x20];
1227
1228         u8         rpg_time_reset[0x20];
1229
1230         u8         rpg_byte_reset[0x20];
1231
1232         u8         rpg_threshold[0x20];
1233
1234         u8         rpg_max_rate[0x20];
1235
1236         u8         rpg_ai_rate[0x20];
1237
1238         u8         rpg_hai_rate[0x20];
1239
1240         u8         rpg_gd[0x20];
1241
1242         u8         rpg_min_dec_fac[0x20];
1243
1244         u8         rpg_min_rate[0x20];
1245
1246         u8         reserved_at_1c0[0xe0];
1247
1248         u8         rate_to_set_on_first_cnp[0x20];
1249
1250         u8         dce_tcp_g[0x20];
1251
1252         u8         dce_tcp_rtt[0x20];
1253
1254         u8         rate_reduce_monitor_period[0x20];
1255
1256         u8         reserved_at_320[0x20];
1257
1258         u8         initial_alpha_value[0x20];
1259
1260         u8         reserved_at_360[0x4a0];
1261 };
1262
1263 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1264         u8         reserved_at_0[0x80];
1265
1266         u8         rppp_max_rps[0x20];
1267
1268         u8         rpg_time_reset[0x20];
1269
1270         u8         rpg_byte_reset[0x20];
1271
1272         u8         rpg_threshold[0x20];
1273
1274         u8         rpg_max_rate[0x20];
1275
1276         u8         rpg_ai_rate[0x20];
1277
1278         u8         rpg_hai_rate[0x20];
1279
1280         u8         rpg_gd[0x20];
1281
1282         u8         rpg_min_dec_fac[0x20];
1283
1284         u8         rpg_min_rate[0x20];
1285
1286         u8         reserved_at_1c0[0x640];
1287 };
1288
1289 enum {
1290         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1291         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1292         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1293 };
1294
1295 struct mlx5_ifc_resize_field_select_bits {
1296         u8         resize_field_select[0x20];
1297 };
1298
1299 enum {
1300         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1301         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1302         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1303         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1304 };
1305
1306 struct mlx5_ifc_modify_field_select_bits {
1307         u8         modify_field_select[0x20];
1308 };
1309
1310 struct mlx5_ifc_field_select_r_roce_np_bits {
1311         u8         field_select_r_roce_np[0x20];
1312 };
1313
1314 struct mlx5_ifc_field_select_r_roce_rp_bits {
1315         u8         field_select_r_roce_rp[0x20];
1316 };
1317
1318 enum {
1319         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1320         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1321         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1322         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1323         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1324         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1325         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1326         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1327         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1328         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1329 };
1330
1331 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1332         u8         field_select_8021qaurp[0x20];
1333 };
1334
1335 struct mlx5_ifc_phys_layer_cntrs_bits {
1336         u8         time_since_last_clear_high[0x20];
1337
1338         u8         time_since_last_clear_low[0x20];
1339
1340         u8         symbol_errors_high[0x20];
1341
1342         u8         symbol_errors_low[0x20];
1343
1344         u8         sync_headers_errors_high[0x20];
1345
1346         u8         sync_headers_errors_low[0x20];
1347
1348         u8         edpl_bip_errors_lane0_high[0x20];
1349
1350         u8         edpl_bip_errors_lane0_low[0x20];
1351
1352         u8         edpl_bip_errors_lane1_high[0x20];
1353
1354         u8         edpl_bip_errors_lane1_low[0x20];
1355
1356         u8         edpl_bip_errors_lane2_high[0x20];
1357
1358         u8         edpl_bip_errors_lane2_low[0x20];
1359
1360         u8         edpl_bip_errors_lane3_high[0x20];
1361
1362         u8         edpl_bip_errors_lane3_low[0x20];
1363
1364         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1365
1366         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1367
1368         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1369
1370         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1371
1372         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1373
1374         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1375
1376         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1377
1378         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1379
1380         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1381
1382         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1383
1384         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1385
1386         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1387
1388         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1389
1390         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1391
1392         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1393
1394         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1395
1396         u8         rs_fec_corrected_blocks_high[0x20];
1397
1398         u8         rs_fec_corrected_blocks_low[0x20];
1399
1400         u8         rs_fec_uncorrectable_blocks_high[0x20];
1401
1402         u8         rs_fec_uncorrectable_blocks_low[0x20];
1403
1404         u8         rs_fec_no_errors_blocks_high[0x20];
1405
1406         u8         rs_fec_no_errors_blocks_low[0x20];
1407
1408         u8         rs_fec_single_error_blocks_high[0x20];
1409
1410         u8         rs_fec_single_error_blocks_low[0x20];
1411
1412         u8         rs_fec_corrected_symbols_total_high[0x20];
1413
1414         u8         rs_fec_corrected_symbols_total_low[0x20];
1415
1416         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1417
1418         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1419
1420         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1421
1422         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1423
1424         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1425
1426         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1427
1428         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1429
1430         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1431
1432         u8         link_down_events[0x20];
1433
1434         u8         successful_recovery_events[0x20];
1435
1436         u8         reserved_at_640[0x180];
1437 };
1438
1439 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1440         u8         time_since_last_clear_high[0x20];
1441
1442         u8         time_since_last_clear_low[0x20];
1443
1444         u8         phy_received_bits_high[0x20];
1445
1446         u8         phy_received_bits_low[0x20];
1447
1448         u8         phy_symbol_errors_high[0x20];
1449
1450         u8         phy_symbol_errors_low[0x20];
1451
1452         u8         phy_corrected_bits_high[0x20];
1453
1454         u8         phy_corrected_bits_low[0x20];
1455
1456         u8         phy_corrected_bits_lane0_high[0x20];
1457
1458         u8         phy_corrected_bits_lane0_low[0x20];
1459
1460         u8         phy_corrected_bits_lane1_high[0x20];
1461
1462         u8         phy_corrected_bits_lane1_low[0x20];
1463
1464         u8         phy_corrected_bits_lane2_high[0x20];
1465
1466         u8         phy_corrected_bits_lane2_low[0x20];
1467
1468         u8         phy_corrected_bits_lane3_high[0x20];
1469
1470         u8         phy_corrected_bits_lane3_low[0x20];
1471
1472         u8         reserved_at_200[0x5c0];
1473 };
1474
1475 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1476         u8         symbol_error_counter[0x10];
1477
1478         u8         link_error_recovery_counter[0x8];
1479
1480         u8         link_downed_counter[0x8];
1481
1482         u8         port_rcv_errors[0x10];
1483
1484         u8         port_rcv_remote_physical_errors[0x10];
1485
1486         u8         port_rcv_switch_relay_errors[0x10];
1487
1488         u8         port_xmit_discards[0x10];
1489
1490         u8         port_xmit_constraint_errors[0x8];
1491
1492         u8         port_rcv_constraint_errors[0x8];
1493
1494         u8         reserved_at_70[0x8];
1495
1496         u8         link_overrun_errors[0x8];
1497
1498         u8         reserved_at_80[0x10];
1499
1500         u8         vl_15_dropped[0x10];
1501
1502         u8         reserved_at_a0[0x80];
1503
1504         u8         port_xmit_wait[0x20];
1505 };
1506
1507 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1508         u8         transmit_queue_high[0x20];
1509
1510         u8         transmit_queue_low[0x20];
1511
1512         u8         reserved_at_40[0x780];
1513 };
1514
1515 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1516         u8         rx_octets_high[0x20];
1517
1518         u8         rx_octets_low[0x20];
1519
1520         u8         reserved_at_40[0xc0];
1521
1522         u8         rx_frames_high[0x20];
1523
1524         u8         rx_frames_low[0x20];
1525
1526         u8         tx_octets_high[0x20];
1527
1528         u8         tx_octets_low[0x20];
1529
1530         u8         reserved_at_180[0xc0];
1531
1532         u8         tx_frames_high[0x20];
1533
1534         u8         tx_frames_low[0x20];
1535
1536         u8         rx_pause_high[0x20];
1537
1538         u8         rx_pause_low[0x20];
1539
1540         u8         rx_pause_duration_high[0x20];
1541
1542         u8         rx_pause_duration_low[0x20];
1543
1544         u8         tx_pause_high[0x20];
1545
1546         u8         tx_pause_low[0x20];
1547
1548         u8         tx_pause_duration_high[0x20];
1549
1550         u8         tx_pause_duration_low[0x20];
1551
1552         u8         rx_pause_transition_high[0x20];
1553
1554         u8         rx_pause_transition_low[0x20];
1555
1556         u8         reserved_at_3c0[0x400];
1557 };
1558
1559 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1560         u8         port_transmit_wait_high[0x20];
1561
1562         u8         port_transmit_wait_low[0x20];
1563
1564         u8         reserved_at_40[0x100];
1565
1566         u8         rx_buffer_almost_full_high[0x20];
1567
1568         u8         rx_buffer_almost_full_low[0x20];
1569
1570         u8         rx_buffer_full_high[0x20];
1571
1572         u8         rx_buffer_full_low[0x20];
1573
1574         u8         reserved_at_1c0[0x600];
1575 };
1576
1577 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1578         u8         dot3stats_alignment_errors_high[0x20];
1579
1580         u8         dot3stats_alignment_errors_low[0x20];
1581
1582         u8         dot3stats_fcs_errors_high[0x20];
1583
1584         u8         dot3stats_fcs_errors_low[0x20];
1585
1586         u8         dot3stats_single_collision_frames_high[0x20];
1587
1588         u8         dot3stats_single_collision_frames_low[0x20];
1589
1590         u8         dot3stats_multiple_collision_frames_high[0x20];
1591
1592         u8         dot3stats_multiple_collision_frames_low[0x20];
1593
1594         u8         dot3stats_sqe_test_errors_high[0x20];
1595
1596         u8         dot3stats_sqe_test_errors_low[0x20];
1597
1598         u8         dot3stats_deferred_transmissions_high[0x20];
1599
1600         u8         dot3stats_deferred_transmissions_low[0x20];
1601
1602         u8         dot3stats_late_collisions_high[0x20];
1603
1604         u8         dot3stats_late_collisions_low[0x20];
1605
1606         u8         dot3stats_excessive_collisions_high[0x20];
1607
1608         u8         dot3stats_excessive_collisions_low[0x20];
1609
1610         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1611
1612         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1613
1614         u8         dot3stats_carrier_sense_errors_high[0x20];
1615
1616         u8         dot3stats_carrier_sense_errors_low[0x20];
1617
1618         u8         dot3stats_frame_too_longs_high[0x20];
1619
1620         u8         dot3stats_frame_too_longs_low[0x20];
1621
1622         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1623
1624         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1625
1626         u8         dot3stats_symbol_errors_high[0x20];
1627
1628         u8         dot3stats_symbol_errors_low[0x20];
1629
1630         u8         dot3control_in_unknown_opcodes_high[0x20];
1631
1632         u8         dot3control_in_unknown_opcodes_low[0x20];
1633
1634         u8         dot3in_pause_frames_high[0x20];
1635
1636         u8         dot3in_pause_frames_low[0x20];
1637
1638         u8         dot3out_pause_frames_high[0x20];
1639
1640         u8         dot3out_pause_frames_low[0x20];
1641
1642         u8         reserved_at_400[0x3c0];
1643 };
1644
1645 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1646         u8         ether_stats_drop_events_high[0x20];
1647
1648         u8         ether_stats_drop_events_low[0x20];
1649
1650         u8         ether_stats_octets_high[0x20];
1651
1652         u8         ether_stats_octets_low[0x20];
1653
1654         u8         ether_stats_pkts_high[0x20];
1655
1656         u8         ether_stats_pkts_low[0x20];
1657
1658         u8         ether_stats_broadcast_pkts_high[0x20];
1659
1660         u8         ether_stats_broadcast_pkts_low[0x20];
1661
1662         u8         ether_stats_multicast_pkts_high[0x20];
1663
1664         u8         ether_stats_multicast_pkts_low[0x20];
1665
1666         u8         ether_stats_crc_align_errors_high[0x20];
1667
1668         u8         ether_stats_crc_align_errors_low[0x20];
1669
1670         u8         ether_stats_undersize_pkts_high[0x20];
1671
1672         u8         ether_stats_undersize_pkts_low[0x20];
1673
1674         u8         ether_stats_oversize_pkts_high[0x20];
1675
1676         u8         ether_stats_oversize_pkts_low[0x20];
1677
1678         u8         ether_stats_fragments_high[0x20];
1679
1680         u8         ether_stats_fragments_low[0x20];
1681
1682         u8         ether_stats_jabbers_high[0x20];
1683
1684         u8         ether_stats_jabbers_low[0x20];
1685
1686         u8         ether_stats_collisions_high[0x20];
1687
1688         u8         ether_stats_collisions_low[0x20];
1689
1690         u8         ether_stats_pkts64octets_high[0x20];
1691
1692         u8         ether_stats_pkts64octets_low[0x20];
1693
1694         u8         ether_stats_pkts65to127octets_high[0x20];
1695
1696         u8         ether_stats_pkts65to127octets_low[0x20];
1697
1698         u8         ether_stats_pkts128to255octets_high[0x20];
1699
1700         u8         ether_stats_pkts128to255octets_low[0x20];
1701
1702         u8         ether_stats_pkts256to511octets_high[0x20];
1703
1704         u8         ether_stats_pkts256to511octets_low[0x20];
1705
1706         u8         ether_stats_pkts512to1023octets_high[0x20];
1707
1708         u8         ether_stats_pkts512to1023octets_low[0x20];
1709
1710         u8         ether_stats_pkts1024to1518octets_high[0x20];
1711
1712         u8         ether_stats_pkts1024to1518octets_low[0x20];
1713
1714         u8         ether_stats_pkts1519to2047octets_high[0x20];
1715
1716         u8         ether_stats_pkts1519to2047octets_low[0x20];
1717
1718         u8         ether_stats_pkts2048to4095octets_high[0x20];
1719
1720         u8         ether_stats_pkts2048to4095octets_low[0x20];
1721
1722         u8         ether_stats_pkts4096to8191octets_high[0x20];
1723
1724         u8         ether_stats_pkts4096to8191octets_low[0x20];
1725
1726         u8         ether_stats_pkts8192to10239octets_high[0x20];
1727
1728         u8         ether_stats_pkts8192to10239octets_low[0x20];
1729
1730         u8         reserved_at_540[0x280];
1731 };
1732
1733 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1734         u8         if_in_octets_high[0x20];
1735
1736         u8         if_in_octets_low[0x20];
1737
1738         u8         if_in_ucast_pkts_high[0x20];
1739
1740         u8         if_in_ucast_pkts_low[0x20];
1741
1742         u8         if_in_discards_high[0x20];
1743
1744         u8         if_in_discards_low[0x20];
1745
1746         u8         if_in_errors_high[0x20];
1747
1748         u8         if_in_errors_low[0x20];
1749
1750         u8         if_in_unknown_protos_high[0x20];
1751
1752         u8         if_in_unknown_protos_low[0x20];
1753
1754         u8         if_out_octets_high[0x20];
1755
1756         u8         if_out_octets_low[0x20];
1757
1758         u8         if_out_ucast_pkts_high[0x20];
1759
1760         u8         if_out_ucast_pkts_low[0x20];
1761
1762         u8         if_out_discards_high[0x20];
1763
1764         u8         if_out_discards_low[0x20];
1765
1766         u8         if_out_errors_high[0x20];
1767
1768         u8         if_out_errors_low[0x20];
1769
1770         u8         if_in_multicast_pkts_high[0x20];
1771
1772         u8         if_in_multicast_pkts_low[0x20];
1773
1774         u8         if_in_broadcast_pkts_high[0x20];
1775
1776         u8         if_in_broadcast_pkts_low[0x20];
1777
1778         u8         if_out_multicast_pkts_high[0x20];
1779
1780         u8         if_out_multicast_pkts_low[0x20];
1781
1782         u8         if_out_broadcast_pkts_high[0x20];
1783
1784         u8         if_out_broadcast_pkts_low[0x20];
1785
1786         u8         reserved_at_340[0x480];
1787 };
1788
1789 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1790         u8         a_frames_transmitted_ok_high[0x20];
1791
1792         u8         a_frames_transmitted_ok_low[0x20];
1793
1794         u8         a_frames_received_ok_high[0x20];
1795
1796         u8         a_frames_received_ok_low[0x20];
1797
1798         u8         a_frame_check_sequence_errors_high[0x20];
1799
1800         u8         a_frame_check_sequence_errors_low[0x20];
1801
1802         u8         a_alignment_errors_high[0x20];
1803
1804         u8         a_alignment_errors_low[0x20];
1805
1806         u8         a_octets_transmitted_ok_high[0x20];
1807
1808         u8         a_octets_transmitted_ok_low[0x20];
1809
1810         u8         a_octets_received_ok_high[0x20];
1811
1812         u8         a_octets_received_ok_low[0x20];
1813
1814         u8         a_multicast_frames_xmitted_ok_high[0x20];
1815
1816         u8         a_multicast_frames_xmitted_ok_low[0x20];
1817
1818         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1819
1820         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1821
1822         u8         a_multicast_frames_received_ok_high[0x20];
1823
1824         u8         a_multicast_frames_received_ok_low[0x20];
1825
1826         u8         a_broadcast_frames_received_ok_high[0x20];
1827
1828         u8         a_broadcast_frames_received_ok_low[0x20];
1829
1830         u8         a_in_range_length_errors_high[0x20];
1831
1832         u8         a_in_range_length_errors_low[0x20];
1833
1834         u8         a_out_of_range_length_field_high[0x20];
1835
1836         u8         a_out_of_range_length_field_low[0x20];
1837
1838         u8         a_frame_too_long_errors_high[0x20];
1839
1840         u8         a_frame_too_long_errors_low[0x20];
1841
1842         u8         a_symbol_error_during_carrier_high[0x20];
1843
1844         u8         a_symbol_error_during_carrier_low[0x20];
1845
1846         u8         a_mac_control_frames_transmitted_high[0x20];
1847
1848         u8         a_mac_control_frames_transmitted_low[0x20];
1849
1850         u8         a_mac_control_frames_received_high[0x20];
1851
1852         u8         a_mac_control_frames_received_low[0x20];
1853
1854         u8         a_unsupported_opcodes_received_high[0x20];
1855
1856         u8         a_unsupported_opcodes_received_low[0x20];
1857
1858         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1859
1860         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1861
1862         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1863
1864         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1865
1866         u8         reserved_at_4c0[0x300];
1867 };
1868
1869 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1870         u8         life_time_counter_high[0x20];
1871
1872         u8         life_time_counter_low[0x20];
1873
1874         u8         rx_errors[0x20];
1875
1876         u8         tx_errors[0x20];
1877
1878         u8         l0_to_recovery_eieos[0x20];
1879
1880         u8         l0_to_recovery_ts[0x20];
1881
1882         u8         l0_to_recovery_framing[0x20];
1883
1884         u8         l0_to_recovery_retrain[0x20];
1885
1886         u8         crc_error_dllp[0x20];
1887
1888         u8         crc_error_tlp[0x20];
1889
1890         u8         tx_overflow_buffer_pkt_high[0x20];
1891
1892         u8         tx_overflow_buffer_pkt_low[0x20];
1893
1894         u8         outbound_stalled_reads[0x20];
1895
1896         u8         outbound_stalled_writes[0x20];
1897
1898         u8         outbound_stalled_reads_events[0x20];
1899
1900         u8         outbound_stalled_writes_events[0x20];
1901
1902         u8         reserved_at_200[0x5c0];
1903 };
1904
1905 struct mlx5_ifc_cmd_inter_comp_event_bits {
1906         u8         command_completion_vector[0x20];
1907
1908         u8         reserved_at_20[0xc0];
1909 };
1910
1911 struct mlx5_ifc_stall_vl_event_bits {
1912         u8         reserved_at_0[0x18];
1913         u8         port_num[0x1];
1914         u8         reserved_at_19[0x3];
1915         u8         vl[0x4];
1916
1917         u8         reserved_at_20[0xa0];
1918 };
1919
1920 struct mlx5_ifc_db_bf_congestion_event_bits {
1921         u8         event_subtype[0x8];
1922         u8         reserved_at_8[0x8];
1923         u8         congestion_level[0x8];
1924         u8         reserved_at_18[0x8];
1925
1926         u8         reserved_at_20[0xa0];
1927 };
1928
1929 struct mlx5_ifc_gpio_event_bits {
1930         u8         reserved_at_0[0x60];
1931
1932         u8         gpio_event_hi[0x20];
1933
1934         u8         gpio_event_lo[0x20];
1935
1936         u8         reserved_at_a0[0x40];
1937 };
1938
1939 struct mlx5_ifc_port_state_change_event_bits {
1940         u8         reserved_at_0[0x40];
1941
1942         u8         port_num[0x4];
1943         u8         reserved_at_44[0x1c];
1944
1945         u8         reserved_at_60[0x80];
1946 };
1947
1948 struct mlx5_ifc_dropped_packet_logged_bits {
1949         u8         reserved_at_0[0xe0];
1950 };
1951
1952 enum {
1953         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1954         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1955 };
1956
1957 struct mlx5_ifc_cq_error_bits {
1958         u8         reserved_at_0[0x8];
1959         u8         cqn[0x18];
1960
1961         u8         reserved_at_20[0x20];
1962
1963         u8         reserved_at_40[0x18];
1964         u8         syndrome[0x8];
1965
1966         u8         reserved_at_60[0x80];
1967 };
1968
1969 struct mlx5_ifc_rdma_page_fault_event_bits {
1970         u8         bytes_committed[0x20];
1971
1972         u8         r_key[0x20];
1973
1974         u8         reserved_at_40[0x10];
1975         u8         packet_len[0x10];
1976
1977         u8         rdma_op_len[0x20];
1978
1979         u8         rdma_va[0x40];
1980
1981         u8         reserved_at_c0[0x5];
1982         u8         rdma[0x1];
1983         u8         write[0x1];
1984         u8         requestor[0x1];
1985         u8         qp_number[0x18];
1986 };
1987
1988 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1989         u8         bytes_committed[0x20];
1990
1991         u8         reserved_at_20[0x10];
1992         u8         wqe_index[0x10];
1993
1994         u8         reserved_at_40[0x10];
1995         u8         len[0x10];
1996
1997         u8         reserved_at_60[0x60];
1998
1999         u8         reserved_at_c0[0x5];
2000         u8         rdma[0x1];
2001         u8         write_read[0x1];
2002         u8         requestor[0x1];
2003         u8         qpn[0x18];
2004 };
2005
2006 struct mlx5_ifc_qp_events_bits {
2007         u8         reserved_at_0[0xa0];
2008
2009         u8         type[0x8];
2010         u8         reserved_at_a8[0x18];
2011
2012         u8         reserved_at_c0[0x8];
2013         u8         qpn_rqn_sqn[0x18];
2014 };
2015
2016 struct mlx5_ifc_dct_events_bits {
2017         u8         reserved_at_0[0xc0];
2018
2019         u8         reserved_at_c0[0x8];
2020         u8         dct_number[0x18];
2021 };
2022
2023 struct mlx5_ifc_comp_event_bits {
2024         u8         reserved_at_0[0xc0];
2025
2026         u8         reserved_at_c0[0x8];
2027         u8         cq_number[0x18];
2028 };
2029
2030 enum {
2031         MLX5_QPC_STATE_RST        = 0x0,
2032         MLX5_QPC_STATE_INIT       = 0x1,
2033         MLX5_QPC_STATE_RTR        = 0x2,
2034         MLX5_QPC_STATE_RTS        = 0x3,
2035         MLX5_QPC_STATE_SQER       = 0x4,
2036         MLX5_QPC_STATE_ERR        = 0x6,
2037         MLX5_QPC_STATE_SQD        = 0x7,
2038         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2039 };
2040
2041 enum {
2042         MLX5_QPC_ST_RC            = 0x0,
2043         MLX5_QPC_ST_UC            = 0x1,
2044         MLX5_QPC_ST_UD            = 0x2,
2045         MLX5_QPC_ST_XRC           = 0x3,
2046         MLX5_QPC_ST_DCI           = 0x5,
2047         MLX5_QPC_ST_QP0           = 0x7,
2048         MLX5_QPC_ST_QP1           = 0x8,
2049         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2050         MLX5_QPC_ST_REG_UMR       = 0xc,
2051 };
2052
2053 enum {
2054         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2055         MLX5_QPC_PM_STATE_REARM     = 0x1,
2056         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2057         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2058 };
2059
2060 enum {
2061         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2062 };
2063
2064 enum {
2065         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2066         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2067 };
2068
2069 enum {
2070         MLX5_QPC_MTU_256_BYTES        = 0x1,
2071         MLX5_QPC_MTU_512_BYTES        = 0x2,
2072         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2073         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2074         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2075         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2076 };
2077
2078 enum {
2079         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2080         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2081         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2082         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2083         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2084         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2085         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2086         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2087 };
2088
2089 enum {
2090         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2091         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2092         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2093 };
2094
2095 enum {
2096         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2097         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2098         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2099 };
2100
2101 struct mlx5_ifc_qpc_bits {
2102         u8         state[0x4];
2103         u8         lag_tx_port_affinity[0x4];
2104         u8         st[0x8];
2105         u8         reserved_at_10[0x3];
2106         u8         pm_state[0x2];
2107         u8         reserved_at_15[0x3];
2108         u8         offload_type[0x4];
2109         u8         end_padding_mode[0x2];
2110         u8         reserved_at_1e[0x2];
2111
2112         u8         wq_signature[0x1];
2113         u8         block_lb_mc[0x1];
2114         u8         atomic_like_write_en[0x1];
2115         u8         latency_sensitive[0x1];
2116         u8         reserved_at_24[0x1];
2117         u8         drain_sigerr[0x1];
2118         u8         reserved_at_26[0x2];
2119         u8         pd[0x18];
2120
2121         u8         mtu[0x3];
2122         u8         log_msg_max[0x5];
2123         u8         reserved_at_48[0x1];
2124         u8         log_rq_size[0x4];
2125         u8         log_rq_stride[0x3];
2126         u8         no_sq[0x1];
2127         u8         log_sq_size[0x4];
2128         u8         reserved_at_55[0x6];
2129         u8         rlky[0x1];
2130         u8         ulp_stateless_offload_mode[0x4];
2131
2132         u8         counter_set_id[0x8];
2133         u8         uar_page[0x18];
2134
2135         u8         reserved_at_80[0x8];
2136         u8         user_index[0x18];
2137
2138         u8         reserved_at_a0[0x3];
2139         u8         log_page_size[0x5];
2140         u8         remote_qpn[0x18];
2141
2142         struct mlx5_ifc_ads_bits primary_address_path;
2143
2144         struct mlx5_ifc_ads_bits secondary_address_path;
2145
2146         u8         log_ack_req_freq[0x4];
2147         u8         reserved_at_384[0x4];
2148         u8         log_sra_max[0x3];
2149         u8         reserved_at_38b[0x2];
2150         u8         retry_count[0x3];
2151         u8         rnr_retry[0x3];
2152         u8         reserved_at_393[0x1];
2153         u8         fre[0x1];
2154         u8         cur_rnr_retry[0x3];
2155         u8         cur_retry_count[0x3];
2156         u8         reserved_at_39b[0x5];
2157
2158         u8         reserved_at_3a0[0x20];
2159
2160         u8         reserved_at_3c0[0x8];
2161         u8         next_send_psn[0x18];
2162
2163         u8         reserved_at_3e0[0x8];
2164         u8         cqn_snd[0x18];
2165
2166         u8         reserved_at_400[0x8];
2167         u8         deth_sqpn[0x18];
2168
2169         u8         reserved_at_420[0x20];
2170
2171         u8         reserved_at_440[0x8];
2172         u8         last_acked_psn[0x18];
2173
2174         u8         reserved_at_460[0x8];
2175         u8         ssn[0x18];
2176
2177         u8         reserved_at_480[0x8];
2178         u8         log_rra_max[0x3];
2179         u8         reserved_at_48b[0x1];
2180         u8         atomic_mode[0x4];
2181         u8         rre[0x1];
2182         u8         rwe[0x1];
2183         u8         rae[0x1];
2184         u8         reserved_at_493[0x1];
2185         u8         page_offset[0x6];
2186         u8         reserved_at_49a[0x3];
2187         u8         cd_slave_receive[0x1];
2188         u8         cd_slave_send[0x1];
2189         u8         cd_master[0x1];
2190
2191         u8         reserved_at_4a0[0x3];
2192         u8         min_rnr_nak[0x5];
2193         u8         next_rcv_psn[0x18];
2194
2195         u8         reserved_at_4c0[0x8];
2196         u8         xrcd[0x18];
2197
2198         u8         reserved_at_4e0[0x8];
2199         u8         cqn_rcv[0x18];
2200
2201         u8         dbr_addr[0x40];
2202
2203         u8         q_key[0x20];
2204
2205         u8         reserved_at_560[0x5];
2206         u8         rq_type[0x3];
2207         u8         srqn_rmpn_xrqn[0x18];
2208
2209         u8         reserved_at_580[0x8];
2210         u8         rmsn[0x18];
2211
2212         u8         hw_sq_wqebb_counter[0x10];
2213         u8         sw_sq_wqebb_counter[0x10];
2214
2215         u8         hw_rq_counter[0x20];
2216
2217         u8         sw_rq_counter[0x20];
2218
2219         u8         reserved_at_600[0x20];
2220
2221         u8         reserved_at_620[0xf];
2222         u8         cgs[0x1];
2223         u8         cs_req[0x8];
2224         u8         cs_res[0x8];
2225
2226         u8         dc_access_key[0x40];
2227
2228         u8         reserved_at_680[0xc0];
2229 };
2230
2231 struct mlx5_ifc_roce_addr_layout_bits {
2232         u8         source_l3_address[16][0x8];
2233
2234         u8         reserved_at_80[0x3];
2235         u8         vlan_valid[0x1];
2236         u8         vlan_id[0xc];
2237         u8         source_mac_47_32[0x10];
2238
2239         u8         source_mac_31_0[0x20];
2240
2241         u8         reserved_at_c0[0x14];
2242         u8         roce_l3_type[0x4];
2243         u8         roce_version[0x8];
2244
2245         u8         reserved_at_e0[0x20];
2246 };
2247
2248 union mlx5_ifc_hca_cap_union_bits {
2249         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2250         struct mlx5_ifc_odp_cap_bits odp_cap;
2251         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2252         struct mlx5_ifc_roce_cap_bits roce_cap;
2253         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2254         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2255         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2256         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2257         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2258         struct mlx5_ifc_qos_cap_bits qos_cap;
2259         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2260         u8         reserved_at_0[0x8000];
2261 };
2262
2263 enum {
2264         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2265         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2266         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2267         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2268         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2269         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2270         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2271 };
2272
2273 struct mlx5_ifc_flow_context_bits {
2274         u8         reserved_at_0[0x20];
2275
2276         u8         group_id[0x20];
2277
2278         u8         reserved_at_40[0x8];
2279         u8         flow_tag[0x18];
2280
2281         u8         reserved_at_60[0x10];
2282         u8         action[0x10];
2283
2284         u8         reserved_at_80[0x8];
2285         u8         destination_list_size[0x18];
2286
2287         u8         reserved_at_a0[0x8];
2288         u8         flow_counter_list_size[0x18];
2289
2290         u8         encap_id[0x20];
2291
2292         u8         modify_header_id[0x20];
2293
2294         u8         reserved_at_100[0x100];
2295
2296         struct mlx5_ifc_fte_match_param_bits match_value;
2297
2298         u8         reserved_at_1200[0x600];
2299
2300         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2301 };
2302
2303 enum {
2304         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2305         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2306 };
2307
2308 struct mlx5_ifc_xrc_srqc_bits {
2309         u8         state[0x4];
2310         u8         log_xrc_srq_size[0x4];
2311         u8         reserved_at_8[0x18];
2312
2313         u8         wq_signature[0x1];
2314         u8         cont_srq[0x1];
2315         u8         reserved_at_22[0x1];
2316         u8         rlky[0x1];
2317         u8         basic_cyclic_rcv_wqe[0x1];
2318         u8         log_rq_stride[0x3];
2319         u8         xrcd[0x18];
2320
2321         u8         page_offset[0x6];
2322         u8         reserved_at_46[0x2];
2323         u8         cqn[0x18];
2324
2325         u8         reserved_at_60[0x20];
2326
2327         u8         user_index_equal_xrc_srqn[0x1];
2328         u8         reserved_at_81[0x1];
2329         u8         log_page_size[0x6];
2330         u8         user_index[0x18];
2331
2332         u8         reserved_at_a0[0x20];
2333
2334         u8         reserved_at_c0[0x8];
2335         u8         pd[0x18];
2336
2337         u8         lwm[0x10];
2338         u8         wqe_cnt[0x10];
2339
2340         u8         reserved_at_100[0x40];
2341
2342         u8         db_record_addr_h[0x20];
2343
2344         u8         db_record_addr_l[0x1e];
2345         u8         reserved_at_17e[0x2];
2346
2347         u8         reserved_at_180[0x80];
2348 };
2349
2350 struct mlx5_ifc_traffic_counter_bits {
2351         u8         packets[0x40];
2352
2353         u8         octets[0x40];
2354 };
2355
2356 struct mlx5_ifc_tisc_bits {
2357         u8         strict_lag_tx_port_affinity[0x1];
2358         u8         reserved_at_1[0x3];
2359         u8         lag_tx_port_affinity[0x04];
2360
2361         u8         reserved_at_8[0x4];
2362         u8         prio[0x4];
2363         u8         reserved_at_10[0x10];
2364
2365         u8         reserved_at_20[0x100];
2366
2367         u8         reserved_at_120[0x8];
2368         u8         transport_domain[0x18];
2369
2370         u8         reserved_at_140[0x8];
2371         u8         underlay_qpn[0x18];
2372         u8         reserved_at_160[0x3a0];
2373 };
2374
2375 enum {
2376         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2377         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2378 };
2379
2380 enum {
2381         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2382         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2383 };
2384
2385 enum {
2386         MLX5_RX_HASH_FN_NONE           = 0x0,
2387         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2388         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2389 };
2390
2391 enum {
2392         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2393         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2394 };
2395
2396 struct mlx5_ifc_tirc_bits {
2397         u8         reserved_at_0[0x20];
2398
2399         u8         disp_type[0x4];
2400         u8         reserved_at_24[0x1c];
2401
2402         u8         reserved_at_40[0x40];
2403
2404         u8         reserved_at_80[0x4];
2405         u8         lro_timeout_period_usecs[0x10];
2406         u8         lro_enable_mask[0x4];
2407         u8         lro_max_ip_payload_size[0x8];
2408
2409         u8         reserved_at_a0[0x40];
2410
2411         u8         reserved_at_e0[0x8];
2412         u8         inline_rqn[0x18];
2413
2414         u8         rx_hash_symmetric[0x1];
2415         u8         reserved_at_101[0x1];
2416         u8         tunneled_offload_en[0x1];
2417         u8         reserved_at_103[0x5];
2418         u8         indirect_table[0x18];
2419
2420         u8         rx_hash_fn[0x4];
2421         u8         reserved_at_124[0x2];
2422         u8         self_lb_block[0x2];
2423         u8         transport_domain[0x18];
2424
2425         u8         rx_hash_toeplitz_key[10][0x20];
2426
2427         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2428
2429         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2430
2431         u8         reserved_at_2c0[0x4c0];
2432 };
2433
2434 enum {
2435         MLX5_SRQC_STATE_GOOD   = 0x0,
2436         MLX5_SRQC_STATE_ERROR  = 0x1,
2437 };
2438
2439 struct mlx5_ifc_srqc_bits {
2440         u8         state[0x4];
2441         u8         log_srq_size[0x4];
2442         u8         reserved_at_8[0x18];
2443
2444         u8         wq_signature[0x1];
2445         u8         cont_srq[0x1];
2446         u8         reserved_at_22[0x1];
2447         u8         rlky[0x1];
2448         u8         reserved_at_24[0x1];
2449         u8         log_rq_stride[0x3];
2450         u8         xrcd[0x18];
2451
2452         u8         page_offset[0x6];
2453         u8         reserved_at_46[0x2];
2454         u8         cqn[0x18];
2455
2456         u8         reserved_at_60[0x20];
2457
2458         u8         reserved_at_80[0x2];
2459         u8         log_page_size[0x6];
2460         u8         reserved_at_88[0x18];
2461
2462         u8         reserved_at_a0[0x20];
2463
2464         u8         reserved_at_c0[0x8];
2465         u8         pd[0x18];
2466
2467         u8         lwm[0x10];
2468         u8         wqe_cnt[0x10];
2469
2470         u8         reserved_at_100[0x40];
2471
2472         u8         dbr_addr[0x40];
2473
2474         u8         reserved_at_180[0x80];
2475 };
2476
2477 enum {
2478         MLX5_SQC_STATE_RST  = 0x0,
2479         MLX5_SQC_STATE_RDY  = 0x1,
2480         MLX5_SQC_STATE_ERR  = 0x3,
2481 };
2482
2483 struct mlx5_ifc_sqc_bits {
2484         u8         rlky[0x1];
2485         u8         cd_master[0x1];
2486         u8         fre[0x1];
2487         u8         flush_in_error_en[0x1];
2488         u8         allow_multi_pkt_send_wqe[0x1];
2489         u8         min_wqe_inline_mode[0x3];
2490         u8         state[0x4];
2491         u8         reg_umr[0x1];
2492         u8         allow_swp[0x1];
2493         u8         reserved_at_e[0x12];
2494
2495         u8         reserved_at_20[0x8];
2496         u8         user_index[0x18];
2497
2498         u8         reserved_at_40[0x8];
2499         u8         cqn[0x18];
2500
2501         u8         reserved_at_60[0x90];
2502
2503         u8         packet_pacing_rate_limit_index[0x10];
2504         u8         tis_lst_sz[0x10];
2505         u8         reserved_at_110[0x10];
2506
2507         u8         reserved_at_120[0x40];
2508
2509         u8         reserved_at_160[0x8];
2510         u8         tis_num_0[0x18];
2511
2512         struct mlx5_ifc_wq_bits wq;
2513 };
2514
2515 enum {
2516         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2517         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2518         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2519         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2520 };
2521
2522 struct mlx5_ifc_scheduling_context_bits {
2523         u8         element_type[0x8];
2524         u8         reserved_at_8[0x18];
2525
2526         u8         element_attributes[0x20];
2527
2528         u8         parent_element_id[0x20];
2529
2530         u8         reserved_at_60[0x40];
2531
2532         u8         bw_share[0x20];
2533
2534         u8         max_average_bw[0x20];
2535
2536         u8         reserved_at_e0[0x120];
2537 };
2538
2539 struct mlx5_ifc_rqtc_bits {
2540         u8         reserved_at_0[0xa0];
2541
2542         u8         reserved_at_a0[0x10];
2543         u8         rqt_max_size[0x10];
2544
2545         u8         reserved_at_c0[0x10];
2546         u8         rqt_actual_size[0x10];
2547
2548         u8         reserved_at_e0[0x6a0];
2549
2550         struct mlx5_ifc_rq_num_bits rq_num[0];
2551 };
2552
2553 enum {
2554         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2555         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2556 };
2557
2558 enum {
2559         MLX5_RQC_STATE_RST  = 0x0,
2560         MLX5_RQC_STATE_RDY  = 0x1,
2561         MLX5_RQC_STATE_ERR  = 0x3,
2562 };
2563
2564 struct mlx5_ifc_rqc_bits {
2565         u8         rlky[0x1];
2566         u8         delay_drop_en[0x1];
2567         u8         scatter_fcs[0x1];
2568         u8         vsd[0x1];
2569         u8         mem_rq_type[0x4];
2570         u8         state[0x4];
2571         u8         reserved_at_c[0x1];
2572         u8         flush_in_error_en[0x1];
2573         u8         reserved_at_e[0x12];
2574
2575         u8         reserved_at_20[0x8];
2576         u8         user_index[0x18];
2577
2578         u8         reserved_at_40[0x8];
2579         u8         cqn[0x18];
2580
2581         u8         counter_set_id[0x8];
2582         u8         reserved_at_68[0x18];
2583
2584         u8         reserved_at_80[0x8];
2585         u8         rmpn[0x18];
2586
2587         u8         reserved_at_a0[0xe0];
2588
2589         struct mlx5_ifc_wq_bits wq;
2590 };
2591
2592 enum {
2593         MLX5_RMPC_STATE_RDY  = 0x1,
2594         MLX5_RMPC_STATE_ERR  = 0x3,
2595 };
2596
2597 struct mlx5_ifc_rmpc_bits {
2598         u8         reserved_at_0[0x8];
2599         u8         state[0x4];
2600         u8         reserved_at_c[0x14];
2601
2602         u8         basic_cyclic_rcv_wqe[0x1];
2603         u8         reserved_at_21[0x1f];
2604
2605         u8         reserved_at_40[0x140];
2606
2607         struct mlx5_ifc_wq_bits wq;
2608 };
2609
2610 struct mlx5_ifc_nic_vport_context_bits {
2611         u8         reserved_at_0[0x5];
2612         u8         min_wqe_inline_mode[0x3];
2613         u8         reserved_at_8[0x15];
2614         u8         disable_mc_local_lb[0x1];
2615         u8         disable_uc_local_lb[0x1];
2616         u8         roce_en[0x1];
2617
2618         u8         arm_change_event[0x1];
2619         u8         reserved_at_21[0x1a];
2620         u8         event_on_mtu[0x1];
2621         u8         event_on_promisc_change[0x1];
2622         u8         event_on_vlan_change[0x1];
2623         u8         event_on_mc_address_change[0x1];
2624         u8         event_on_uc_address_change[0x1];
2625
2626         u8         reserved_at_40[0xc];
2627
2628         u8         affiliation_criteria[0x4];
2629         u8         affiliated_vhca_id[0x10];
2630
2631         u8         reserved_at_60[0xd0];
2632
2633         u8         mtu[0x10];
2634
2635         u8         system_image_guid[0x40];
2636         u8         port_guid[0x40];
2637         u8         node_guid[0x40];
2638
2639         u8         reserved_at_200[0x140];
2640         u8         qkey_violation_counter[0x10];
2641         u8         reserved_at_350[0x430];
2642
2643         u8         promisc_uc[0x1];
2644         u8         promisc_mc[0x1];
2645         u8         promisc_all[0x1];
2646         u8         reserved_at_783[0x2];
2647         u8         allowed_list_type[0x3];
2648         u8         reserved_at_788[0xc];
2649         u8         allowed_list_size[0xc];
2650
2651         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2652
2653         u8         reserved_at_7e0[0x20];
2654
2655         u8         current_uc_mac_address[0][0x40];
2656 };
2657
2658 enum {
2659         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2660         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2661         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2662         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2663 };
2664
2665 struct mlx5_ifc_mkc_bits {
2666         u8         reserved_at_0[0x1];
2667         u8         free[0x1];
2668         u8         reserved_at_2[0xd];
2669         u8         small_fence_on_rdma_read_response[0x1];
2670         u8         umr_en[0x1];
2671         u8         a[0x1];
2672         u8         rw[0x1];
2673         u8         rr[0x1];
2674         u8         lw[0x1];
2675         u8         lr[0x1];
2676         u8         access_mode[0x2];
2677         u8         reserved_at_18[0x8];
2678
2679         u8         qpn[0x18];
2680         u8         mkey_7_0[0x8];
2681
2682         u8         reserved_at_40[0x20];
2683
2684         u8         length64[0x1];
2685         u8         bsf_en[0x1];
2686         u8         sync_umr[0x1];
2687         u8         reserved_at_63[0x2];
2688         u8         expected_sigerr_count[0x1];
2689         u8         reserved_at_66[0x1];
2690         u8         en_rinval[0x1];
2691         u8         pd[0x18];
2692
2693         u8         start_addr[0x40];
2694
2695         u8         len[0x40];
2696
2697         u8         bsf_octword_size[0x20];
2698
2699         u8         reserved_at_120[0x80];
2700
2701         u8         translations_octword_size[0x20];
2702
2703         u8         reserved_at_1c0[0x1b];
2704         u8         log_page_size[0x5];
2705
2706         u8         reserved_at_1e0[0x20];
2707 };
2708
2709 struct mlx5_ifc_pkey_bits {
2710         u8         reserved_at_0[0x10];
2711         u8         pkey[0x10];
2712 };
2713
2714 struct mlx5_ifc_array128_auto_bits {
2715         u8         array128_auto[16][0x8];
2716 };
2717
2718 struct mlx5_ifc_hca_vport_context_bits {
2719         u8         field_select[0x20];
2720
2721         u8         reserved_at_20[0xe0];
2722
2723         u8         sm_virt_aware[0x1];
2724         u8         has_smi[0x1];
2725         u8         has_raw[0x1];
2726         u8         grh_required[0x1];
2727         u8         reserved_at_104[0xc];
2728         u8         port_physical_state[0x4];
2729         u8         vport_state_policy[0x4];
2730         u8         port_state[0x4];
2731         u8         vport_state[0x4];
2732
2733         u8         reserved_at_120[0x20];
2734
2735         u8         system_image_guid[0x40];
2736
2737         u8         port_guid[0x40];
2738
2739         u8         node_guid[0x40];
2740
2741         u8         cap_mask1[0x20];
2742
2743         u8         cap_mask1_field_select[0x20];
2744
2745         u8         cap_mask2[0x20];
2746
2747         u8         cap_mask2_field_select[0x20];
2748
2749         u8         reserved_at_280[0x80];
2750
2751         u8         lid[0x10];
2752         u8         reserved_at_310[0x4];
2753         u8         init_type_reply[0x4];
2754         u8         lmc[0x3];
2755         u8         subnet_timeout[0x5];
2756
2757         u8         sm_lid[0x10];
2758         u8         sm_sl[0x4];
2759         u8         reserved_at_334[0xc];
2760
2761         u8         qkey_violation_counter[0x10];
2762         u8         pkey_violation_counter[0x10];
2763
2764         u8         reserved_at_360[0xca0];
2765 };
2766
2767 struct mlx5_ifc_esw_vport_context_bits {
2768         u8         reserved_at_0[0x3];
2769         u8         vport_svlan_strip[0x1];
2770         u8         vport_cvlan_strip[0x1];
2771         u8         vport_svlan_insert[0x1];
2772         u8         vport_cvlan_insert[0x2];
2773         u8         reserved_at_8[0x18];
2774
2775         u8         reserved_at_20[0x20];
2776
2777         u8         svlan_cfi[0x1];
2778         u8         svlan_pcp[0x3];
2779         u8         svlan_id[0xc];
2780         u8         cvlan_cfi[0x1];
2781         u8         cvlan_pcp[0x3];
2782         u8         cvlan_id[0xc];
2783
2784         u8         reserved_at_60[0x7a0];
2785 };
2786
2787 enum {
2788         MLX5_EQC_STATUS_OK                = 0x0,
2789         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2790 };
2791
2792 enum {
2793         MLX5_EQC_ST_ARMED  = 0x9,
2794         MLX5_EQC_ST_FIRED  = 0xa,
2795 };
2796
2797 struct mlx5_ifc_eqc_bits {
2798         u8         status[0x4];
2799         u8         reserved_at_4[0x9];
2800         u8         ec[0x1];
2801         u8         oi[0x1];
2802         u8         reserved_at_f[0x5];
2803         u8         st[0x4];
2804         u8         reserved_at_18[0x8];
2805
2806         u8         reserved_at_20[0x20];
2807
2808         u8         reserved_at_40[0x14];
2809         u8         page_offset[0x6];
2810         u8         reserved_at_5a[0x6];
2811
2812         u8         reserved_at_60[0x3];
2813         u8         log_eq_size[0x5];
2814         u8         uar_page[0x18];
2815
2816         u8         reserved_at_80[0x20];
2817
2818         u8         reserved_at_a0[0x18];
2819         u8         intr[0x8];
2820
2821         u8         reserved_at_c0[0x3];
2822         u8         log_page_size[0x5];
2823         u8         reserved_at_c8[0x18];
2824
2825         u8         reserved_at_e0[0x60];
2826
2827         u8         reserved_at_140[0x8];
2828         u8         consumer_counter[0x18];
2829
2830         u8         reserved_at_160[0x8];
2831         u8         producer_counter[0x18];
2832
2833         u8         reserved_at_180[0x80];
2834 };
2835
2836 enum {
2837         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2838         MLX5_DCTC_STATE_DRAINING  = 0x1,
2839         MLX5_DCTC_STATE_DRAINED   = 0x2,
2840 };
2841
2842 enum {
2843         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2844         MLX5_DCTC_CS_RES_NA         = 0x1,
2845         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2846 };
2847
2848 enum {
2849         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2850         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2851         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2852         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2853         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2854 };
2855
2856 struct mlx5_ifc_dctc_bits {
2857         u8         reserved_at_0[0x4];
2858         u8         state[0x4];
2859         u8         reserved_at_8[0x18];
2860
2861         u8         reserved_at_20[0x8];
2862         u8         user_index[0x18];
2863
2864         u8         reserved_at_40[0x8];
2865         u8         cqn[0x18];
2866
2867         u8         counter_set_id[0x8];
2868         u8         atomic_mode[0x4];
2869         u8         rre[0x1];
2870         u8         rwe[0x1];
2871         u8         rae[0x1];
2872         u8         atomic_like_write_en[0x1];
2873         u8         latency_sensitive[0x1];
2874         u8         rlky[0x1];
2875         u8         free_ar[0x1];
2876         u8         reserved_at_73[0xd];
2877
2878         u8         reserved_at_80[0x8];
2879         u8         cs_res[0x8];
2880         u8         reserved_at_90[0x3];
2881         u8         min_rnr_nak[0x5];
2882         u8         reserved_at_98[0x8];
2883
2884         u8         reserved_at_a0[0x8];
2885         u8         srqn_xrqn[0x18];
2886
2887         u8         reserved_at_c0[0x8];
2888         u8         pd[0x18];
2889
2890         u8         tclass[0x8];
2891         u8         reserved_at_e8[0x4];
2892         u8         flow_label[0x14];
2893
2894         u8         dc_access_key[0x40];
2895
2896         u8         reserved_at_140[0x5];
2897         u8         mtu[0x3];
2898         u8         port[0x8];
2899         u8         pkey_index[0x10];
2900
2901         u8         reserved_at_160[0x8];
2902         u8         my_addr_index[0x8];
2903         u8         reserved_at_170[0x8];
2904         u8         hop_limit[0x8];
2905
2906         u8         dc_access_key_violation_count[0x20];
2907
2908         u8         reserved_at_1a0[0x14];
2909         u8         dei_cfi[0x1];
2910         u8         eth_prio[0x3];
2911         u8         ecn[0x2];
2912         u8         dscp[0x6];
2913
2914         u8         reserved_at_1c0[0x40];
2915 };
2916
2917 enum {
2918         MLX5_CQC_STATUS_OK             = 0x0,
2919         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2920         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2921 };
2922
2923 enum {
2924         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2925         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2926 };
2927
2928 enum {
2929         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2930         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2931         MLX5_CQC_ST_FIRED                                 = 0xa,
2932 };
2933
2934 enum {
2935         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2936         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2937         MLX5_CQ_PERIOD_NUM_MODES
2938 };
2939
2940 struct mlx5_ifc_cqc_bits {
2941         u8         status[0x4];
2942         u8         reserved_at_4[0x4];
2943         u8         cqe_sz[0x3];
2944         u8         cc[0x1];
2945         u8         reserved_at_c[0x1];
2946         u8         scqe_break_moderation_en[0x1];
2947         u8         oi[0x1];
2948         u8         cq_period_mode[0x2];
2949         u8         cqe_comp_en[0x1];
2950         u8         mini_cqe_res_format[0x2];
2951         u8         st[0x4];
2952         u8         reserved_at_18[0x8];
2953
2954         u8         reserved_at_20[0x20];
2955
2956         u8         reserved_at_40[0x14];
2957         u8         page_offset[0x6];
2958         u8         reserved_at_5a[0x6];
2959
2960         u8         reserved_at_60[0x3];
2961         u8         log_cq_size[0x5];
2962         u8         uar_page[0x18];
2963
2964         u8         reserved_at_80[0x4];
2965         u8         cq_period[0xc];
2966         u8         cq_max_count[0x10];
2967
2968         u8         reserved_at_a0[0x18];
2969         u8         c_eqn[0x8];
2970
2971         u8         reserved_at_c0[0x3];
2972         u8         log_page_size[0x5];
2973         u8         reserved_at_c8[0x18];
2974
2975         u8         reserved_at_e0[0x20];
2976
2977         u8         reserved_at_100[0x8];
2978         u8         last_notified_index[0x18];
2979
2980         u8         reserved_at_120[0x8];
2981         u8         last_solicit_index[0x18];
2982
2983         u8         reserved_at_140[0x8];
2984         u8         consumer_counter[0x18];
2985
2986         u8         reserved_at_160[0x8];
2987         u8         producer_counter[0x18];
2988
2989         u8         reserved_at_180[0x40];
2990
2991         u8         dbr_addr[0x40];
2992 };
2993
2994 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2995         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2996         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2997         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2998         u8         reserved_at_0[0x800];
2999 };
3000
3001 struct mlx5_ifc_query_adapter_param_block_bits {
3002         u8         reserved_at_0[0xc0];
3003
3004         u8         reserved_at_c0[0x8];
3005         u8         ieee_vendor_id[0x18];
3006
3007         u8         reserved_at_e0[0x10];
3008         u8         vsd_vendor_id[0x10];
3009
3010         u8         vsd[208][0x8];
3011
3012         u8         vsd_contd_psid[16][0x8];
3013 };
3014
3015 enum {
3016         MLX5_XRQC_STATE_GOOD   = 0x0,
3017         MLX5_XRQC_STATE_ERROR  = 0x1,
3018 };
3019
3020 enum {
3021         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3022         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3023 };
3024
3025 enum {
3026         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3027 };
3028
3029 struct mlx5_ifc_tag_matching_topology_context_bits {
3030         u8         log_matching_list_sz[0x4];
3031         u8         reserved_at_4[0xc];
3032         u8         append_next_index[0x10];
3033
3034         u8         sw_phase_cnt[0x10];
3035         u8         hw_phase_cnt[0x10];
3036
3037         u8         reserved_at_40[0x40];
3038 };
3039
3040 struct mlx5_ifc_xrqc_bits {
3041         u8         state[0x4];
3042         u8         rlkey[0x1];
3043         u8         reserved_at_5[0xf];
3044         u8         topology[0x4];
3045         u8         reserved_at_18[0x4];
3046         u8         offload[0x4];
3047
3048         u8         reserved_at_20[0x8];
3049         u8         user_index[0x18];
3050
3051         u8         reserved_at_40[0x8];
3052         u8         cqn[0x18];
3053
3054         u8         reserved_at_60[0xa0];
3055
3056         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3057
3058         u8         reserved_at_180[0x280];
3059
3060         struct mlx5_ifc_wq_bits wq;
3061 };
3062
3063 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3064         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3065         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3066         u8         reserved_at_0[0x20];
3067 };
3068
3069 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3070         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3071         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3072         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3073         u8         reserved_at_0[0x20];
3074 };
3075
3076 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3077         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3078         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3079         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3080         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3081         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3082         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3083         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3084         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3085         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3086         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3087         u8         reserved_at_0[0x7c0];
3088 };
3089
3090 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3091         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3092         u8         reserved_at_0[0x7c0];
3093 };
3094
3095 union mlx5_ifc_event_auto_bits {
3096         struct mlx5_ifc_comp_event_bits comp_event;
3097         struct mlx5_ifc_dct_events_bits dct_events;
3098         struct mlx5_ifc_qp_events_bits qp_events;
3099         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3100         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3101         struct mlx5_ifc_cq_error_bits cq_error;
3102         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3103         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3104         struct mlx5_ifc_gpio_event_bits gpio_event;
3105         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3106         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3107         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3108         u8         reserved_at_0[0xe0];
3109 };
3110
3111 struct mlx5_ifc_health_buffer_bits {
3112         u8         reserved_at_0[0x100];
3113
3114         u8         assert_existptr[0x20];
3115
3116         u8         assert_callra[0x20];
3117
3118         u8         reserved_at_140[0x40];
3119
3120         u8         fw_version[0x20];
3121
3122         u8         hw_id[0x20];
3123
3124         u8         reserved_at_1c0[0x20];
3125
3126         u8         irisc_index[0x8];
3127         u8         synd[0x8];
3128         u8         ext_synd[0x10];
3129 };
3130
3131 struct mlx5_ifc_register_loopback_control_bits {
3132         u8         no_lb[0x1];
3133         u8         reserved_at_1[0x7];
3134         u8         port[0x8];
3135         u8         reserved_at_10[0x10];
3136
3137         u8         reserved_at_20[0x60];
3138 };
3139
3140 struct mlx5_ifc_vport_tc_element_bits {
3141         u8         traffic_class[0x4];
3142         u8         reserved_at_4[0xc];
3143         u8         vport_number[0x10];
3144 };
3145
3146 struct mlx5_ifc_vport_element_bits {
3147         u8         reserved_at_0[0x10];
3148         u8         vport_number[0x10];
3149 };
3150
3151 enum {
3152         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3153         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3154         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3155 };
3156
3157 struct mlx5_ifc_tsar_element_bits {
3158         u8         reserved_at_0[0x8];
3159         u8         tsar_type[0x8];
3160         u8         reserved_at_10[0x10];
3161 };
3162
3163 enum {
3164         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3165         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3166 };
3167
3168 struct mlx5_ifc_teardown_hca_out_bits {
3169         u8         status[0x8];
3170         u8         reserved_at_8[0x18];
3171
3172         u8         syndrome[0x20];
3173
3174         u8         reserved_at_40[0x3f];
3175
3176         u8         force_state[0x1];
3177 };
3178
3179 enum {
3180         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3181         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3182 };
3183
3184 struct mlx5_ifc_teardown_hca_in_bits {
3185         u8         opcode[0x10];
3186         u8         reserved_at_10[0x10];
3187
3188         u8         reserved_at_20[0x10];
3189         u8         op_mod[0x10];
3190
3191         u8         reserved_at_40[0x10];
3192         u8         profile[0x10];
3193
3194         u8         reserved_at_60[0x20];
3195 };
3196
3197 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3198         u8         status[0x8];
3199         u8         reserved_at_8[0x18];
3200
3201         u8         syndrome[0x20];
3202
3203         u8         reserved_at_40[0x40];
3204 };
3205
3206 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3207         u8         opcode[0x10];
3208         u8         reserved_at_10[0x10];
3209
3210         u8         reserved_at_20[0x10];
3211         u8         op_mod[0x10];
3212
3213         u8         reserved_at_40[0x8];
3214         u8         qpn[0x18];
3215
3216         u8         reserved_at_60[0x20];
3217
3218         u8         opt_param_mask[0x20];
3219
3220         u8         reserved_at_a0[0x20];
3221
3222         struct mlx5_ifc_qpc_bits qpc;
3223
3224         u8         reserved_at_800[0x80];
3225 };
3226
3227 struct mlx5_ifc_sqd2rts_qp_out_bits {
3228         u8         status[0x8];
3229         u8         reserved_at_8[0x18];
3230
3231         u8         syndrome[0x20];
3232
3233         u8         reserved_at_40[0x40];
3234 };
3235
3236 struct mlx5_ifc_sqd2rts_qp_in_bits {
3237         u8         opcode[0x10];
3238         u8         reserved_at_10[0x10];
3239
3240         u8         reserved_at_20[0x10];
3241         u8         op_mod[0x10];
3242
3243         u8         reserved_at_40[0x8];
3244         u8         qpn[0x18];
3245
3246         u8         reserved_at_60[0x20];
3247
3248         u8         opt_param_mask[0x20];
3249
3250         u8         reserved_at_a0[0x20];
3251
3252         struct mlx5_ifc_qpc_bits qpc;
3253
3254         u8         reserved_at_800[0x80];
3255 };
3256
3257 struct mlx5_ifc_set_roce_address_out_bits {
3258         u8         status[0x8];
3259         u8         reserved_at_8[0x18];
3260
3261         u8         syndrome[0x20];
3262
3263         u8         reserved_at_40[0x40];
3264 };
3265
3266 struct mlx5_ifc_set_roce_address_in_bits {
3267         u8         opcode[0x10];
3268         u8         reserved_at_10[0x10];
3269
3270         u8         reserved_at_20[0x10];
3271         u8         op_mod[0x10];
3272
3273         u8         roce_address_index[0x10];
3274         u8         reserved_at_50[0xc];
3275         u8         vhca_port_num[0x4];
3276
3277         u8         reserved_at_60[0x20];
3278
3279         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3280 };
3281
3282 struct mlx5_ifc_set_mad_demux_out_bits {
3283         u8         status[0x8];
3284         u8         reserved_at_8[0x18];
3285
3286         u8         syndrome[0x20];
3287
3288         u8         reserved_at_40[0x40];
3289 };
3290
3291 enum {
3292         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3293         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3294 };
3295
3296 struct mlx5_ifc_set_mad_demux_in_bits {
3297         u8         opcode[0x10];
3298         u8         reserved_at_10[0x10];
3299
3300         u8         reserved_at_20[0x10];
3301         u8         op_mod[0x10];
3302
3303         u8         reserved_at_40[0x20];
3304
3305         u8         reserved_at_60[0x6];
3306         u8         demux_mode[0x2];
3307         u8         reserved_at_68[0x18];
3308 };
3309
3310 struct mlx5_ifc_set_l2_table_entry_out_bits {
3311         u8         status[0x8];
3312         u8         reserved_at_8[0x18];
3313
3314         u8         syndrome[0x20];
3315
3316         u8         reserved_at_40[0x40];
3317 };
3318
3319 struct mlx5_ifc_set_l2_table_entry_in_bits {
3320         u8         opcode[0x10];
3321         u8         reserved_at_10[0x10];
3322
3323         u8         reserved_at_20[0x10];
3324         u8         op_mod[0x10];
3325
3326         u8         reserved_at_40[0x60];
3327
3328         u8         reserved_at_a0[0x8];
3329         u8         table_index[0x18];
3330
3331         u8         reserved_at_c0[0x20];
3332
3333         u8         reserved_at_e0[0x13];
3334         u8         vlan_valid[0x1];
3335         u8         vlan[0xc];
3336
3337         struct mlx5_ifc_mac_address_layout_bits mac_address;
3338
3339         u8         reserved_at_140[0xc0];
3340 };
3341
3342 struct mlx5_ifc_set_issi_out_bits {
3343         u8         status[0x8];
3344         u8         reserved_at_8[0x18];
3345
3346         u8         syndrome[0x20];
3347
3348         u8         reserved_at_40[0x40];
3349 };
3350
3351 struct mlx5_ifc_set_issi_in_bits {
3352         u8         opcode[0x10];
3353         u8         reserved_at_10[0x10];
3354
3355         u8         reserved_at_20[0x10];
3356         u8         op_mod[0x10];
3357
3358         u8         reserved_at_40[0x10];
3359         u8         current_issi[0x10];
3360
3361         u8         reserved_at_60[0x20];
3362 };
3363
3364 struct mlx5_ifc_set_hca_cap_out_bits {
3365         u8         status[0x8];
3366         u8         reserved_at_8[0x18];
3367
3368         u8         syndrome[0x20];
3369
3370         u8         reserved_at_40[0x40];
3371 };
3372
3373 struct mlx5_ifc_set_hca_cap_in_bits {
3374         u8         opcode[0x10];
3375         u8         reserved_at_10[0x10];
3376
3377         u8         reserved_at_20[0x10];
3378         u8         op_mod[0x10];
3379
3380         u8         reserved_at_40[0x40];
3381
3382         union mlx5_ifc_hca_cap_union_bits capability;
3383 };
3384
3385 enum {
3386         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3387         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3388         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3389         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3390 };
3391
3392 struct mlx5_ifc_set_fte_out_bits {
3393         u8         status[0x8];
3394         u8         reserved_at_8[0x18];
3395
3396         u8         syndrome[0x20];
3397
3398         u8         reserved_at_40[0x40];
3399 };
3400
3401 struct mlx5_ifc_set_fte_in_bits {
3402         u8         opcode[0x10];
3403         u8         reserved_at_10[0x10];
3404
3405         u8         reserved_at_20[0x10];
3406         u8         op_mod[0x10];
3407
3408         u8         other_vport[0x1];
3409         u8         reserved_at_41[0xf];
3410         u8         vport_number[0x10];
3411
3412         u8         reserved_at_60[0x20];
3413
3414         u8         table_type[0x8];
3415         u8         reserved_at_88[0x18];
3416
3417         u8         reserved_at_a0[0x8];
3418         u8         table_id[0x18];
3419
3420         u8         reserved_at_c0[0x18];
3421         u8         modify_enable_mask[0x8];
3422
3423         u8         reserved_at_e0[0x20];
3424
3425         u8         flow_index[0x20];
3426
3427         u8         reserved_at_120[0xe0];
3428
3429         struct mlx5_ifc_flow_context_bits flow_context;
3430 };
3431
3432 struct mlx5_ifc_rts2rts_qp_out_bits {
3433         u8         status[0x8];
3434         u8         reserved_at_8[0x18];
3435
3436         u8         syndrome[0x20];
3437
3438         u8         reserved_at_40[0x40];
3439 };
3440
3441 struct mlx5_ifc_rts2rts_qp_in_bits {
3442         u8         opcode[0x10];
3443         u8         reserved_at_10[0x10];
3444
3445         u8         reserved_at_20[0x10];
3446         u8         op_mod[0x10];
3447
3448         u8         reserved_at_40[0x8];
3449         u8         qpn[0x18];
3450
3451         u8         reserved_at_60[0x20];
3452
3453         u8         opt_param_mask[0x20];
3454
3455         u8         reserved_at_a0[0x20];
3456
3457         struct mlx5_ifc_qpc_bits qpc;
3458
3459         u8         reserved_at_800[0x80];
3460 };
3461
3462 struct mlx5_ifc_rtr2rts_qp_out_bits {
3463         u8         status[0x8];
3464         u8         reserved_at_8[0x18];
3465
3466         u8         syndrome[0x20];
3467
3468         u8         reserved_at_40[0x40];
3469 };
3470
3471 struct mlx5_ifc_rtr2rts_qp_in_bits {
3472         u8         opcode[0x10];
3473         u8         reserved_at_10[0x10];
3474
3475         u8         reserved_at_20[0x10];
3476         u8         op_mod[0x10];
3477
3478         u8         reserved_at_40[0x8];
3479         u8         qpn[0x18];
3480
3481         u8         reserved_at_60[0x20];
3482
3483         u8         opt_param_mask[0x20];
3484
3485         u8         reserved_at_a0[0x20];
3486
3487         struct mlx5_ifc_qpc_bits qpc;
3488
3489         u8         reserved_at_800[0x80];
3490 };
3491
3492 struct mlx5_ifc_rst2init_qp_out_bits {
3493         u8         status[0x8];
3494         u8         reserved_at_8[0x18];
3495
3496         u8         syndrome[0x20];
3497
3498         u8         reserved_at_40[0x40];
3499 };
3500
3501 struct mlx5_ifc_rst2init_qp_in_bits {
3502         u8         opcode[0x10];
3503         u8         reserved_at_10[0x10];
3504
3505         u8         reserved_at_20[0x10];
3506         u8         op_mod[0x10];
3507
3508         u8         reserved_at_40[0x8];
3509         u8         qpn[0x18];
3510
3511         u8         reserved_at_60[0x20];
3512
3513         u8         opt_param_mask[0x20];
3514
3515         u8         reserved_at_a0[0x20];
3516
3517         struct mlx5_ifc_qpc_bits qpc;
3518
3519         u8         reserved_at_800[0x80];
3520 };
3521
3522 struct mlx5_ifc_query_xrq_out_bits {
3523         u8         status[0x8];
3524         u8         reserved_at_8[0x18];
3525
3526         u8         syndrome[0x20];
3527
3528         u8         reserved_at_40[0x40];
3529
3530         struct mlx5_ifc_xrqc_bits xrq_context;
3531 };
3532
3533 struct mlx5_ifc_query_xrq_in_bits {
3534         u8         opcode[0x10];
3535         u8         reserved_at_10[0x10];
3536
3537         u8         reserved_at_20[0x10];
3538         u8         op_mod[0x10];
3539
3540         u8         reserved_at_40[0x8];
3541         u8         xrqn[0x18];
3542
3543         u8         reserved_at_60[0x20];
3544 };
3545
3546 struct mlx5_ifc_query_xrc_srq_out_bits {
3547         u8         status[0x8];
3548         u8         reserved_at_8[0x18];
3549
3550         u8         syndrome[0x20];
3551
3552         u8         reserved_at_40[0x40];
3553
3554         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3555
3556         u8         reserved_at_280[0x600];
3557
3558         u8         pas[0][0x40];
3559 };
3560
3561 struct mlx5_ifc_query_xrc_srq_in_bits {
3562         u8         opcode[0x10];
3563         u8         reserved_at_10[0x10];
3564
3565         u8         reserved_at_20[0x10];
3566         u8         op_mod[0x10];
3567
3568         u8         reserved_at_40[0x8];
3569         u8         xrc_srqn[0x18];
3570
3571         u8         reserved_at_60[0x20];
3572 };
3573
3574 enum {
3575         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3576         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3577 };
3578
3579 struct mlx5_ifc_query_vport_state_out_bits {
3580         u8         status[0x8];
3581         u8         reserved_at_8[0x18];
3582
3583         u8         syndrome[0x20];
3584
3585         u8         reserved_at_40[0x20];
3586
3587         u8         reserved_at_60[0x18];
3588         u8         admin_state[0x4];
3589         u8         state[0x4];
3590 };
3591
3592 enum {
3593         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3594         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3595 };
3596
3597 struct mlx5_ifc_query_vport_state_in_bits {
3598         u8         opcode[0x10];
3599         u8         reserved_at_10[0x10];
3600
3601         u8         reserved_at_20[0x10];
3602         u8         op_mod[0x10];
3603
3604         u8         other_vport[0x1];
3605         u8         reserved_at_41[0xf];
3606         u8         vport_number[0x10];
3607
3608         u8         reserved_at_60[0x20];
3609 };
3610
3611 struct mlx5_ifc_query_vport_counter_out_bits {
3612         u8         status[0x8];
3613         u8         reserved_at_8[0x18];
3614
3615         u8         syndrome[0x20];
3616
3617         u8         reserved_at_40[0x40];
3618
3619         struct mlx5_ifc_traffic_counter_bits received_errors;
3620
3621         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3622
3623         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3624
3625         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3626
3627         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3628
3629         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3630
3631         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3632
3633         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3634
3635         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3636
3637         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3638
3639         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3640
3641         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3642
3643         u8         reserved_at_680[0xa00];
3644 };
3645
3646 enum {
3647         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3648 };
3649
3650 struct mlx5_ifc_query_vport_counter_in_bits {
3651         u8         opcode[0x10];
3652         u8         reserved_at_10[0x10];
3653
3654         u8         reserved_at_20[0x10];
3655         u8         op_mod[0x10];
3656
3657         u8         other_vport[0x1];
3658         u8         reserved_at_41[0xb];
3659         u8         port_num[0x4];
3660         u8         vport_number[0x10];
3661
3662         u8         reserved_at_60[0x60];
3663
3664         u8         clear[0x1];
3665         u8         reserved_at_c1[0x1f];
3666
3667         u8         reserved_at_e0[0x20];
3668 };
3669
3670 struct mlx5_ifc_query_tis_out_bits {
3671         u8         status[0x8];
3672         u8         reserved_at_8[0x18];
3673
3674         u8         syndrome[0x20];
3675
3676         u8         reserved_at_40[0x40];
3677
3678         struct mlx5_ifc_tisc_bits tis_context;
3679 };
3680
3681 struct mlx5_ifc_query_tis_in_bits {
3682         u8         opcode[0x10];
3683         u8         reserved_at_10[0x10];
3684
3685         u8         reserved_at_20[0x10];
3686         u8         op_mod[0x10];
3687
3688         u8         reserved_at_40[0x8];
3689         u8         tisn[0x18];
3690
3691         u8         reserved_at_60[0x20];
3692 };
3693
3694 struct mlx5_ifc_query_tir_out_bits {
3695         u8         status[0x8];
3696         u8         reserved_at_8[0x18];
3697
3698         u8         syndrome[0x20];
3699
3700         u8         reserved_at_40[0xc0];
3701
3702         struct mlx5_ifc_tirc_bits tir_context;
3703 };
3704
3705 struct mlx5_ifc_query_tir_in_bits {
3706         u8         opcode[0x10];
3707         u8         reserved_at_10[0x10];
3708
3709         u8         reserved_at_20[0x10];
3710         u8         op_mod[0x10];
3711
3712         u8         reserved_at_40[0x8];
3713         u8         tirn[0x18];
3714
3715         u8         reserved_at_60[0x20];
3716 };
3717
3718 struct mlx5_ifc_query_srq_out_bits {
3719         u8         status[0x8];
3720         u8         reserved_at_8[0x18];
3721
3722         u8         syndrome[0x20];
3723
3724         u8         reserved_at_40[0x40];
3725
3726         struct mlx5_ifc_srqc_bits srq_context_entry;
3727
3728         u8         reserved_at_280[0x600];
3729
3730         u8         pas[0][0x40];
3731 };
3732
3733 struct mlx5_ifc_query_srq_in_bits {
3734         u8         opcode[0x10];
3735         u8         reserved_at_10[0x10];
3736
3737         u8         reserved_at_20[0x10];
3738         u8         op_mod[0x10];
3739
3740         u8         reserved_at_40[0x8];
3741         u8         srqn[0x18];
3742
3743         u8         reserved_at_60[0x20];
3744 };
3745
3746 struct mlx5_ifc_query_sq_out_bits {
3747         u8         status[0x8];
3748         u8         reserved_at_8[0x18];
3749
3750         u8         syndrome[0x20];
3751
3752         u8         reserved_at_40[0xc0];
3753
3754         struct mlx5_ifc_sqc_bits sq_context;
3755 };
3756
3757 struct mlx5_ifc_query_sq_in_bits {
3758         u8         opcode[0x10];
3759         u8         reserved_at_10[0x10];
3760
3761         u8         reserved_at_20[0x10];
3762         u8         op_mod[0x10];
3763
3764         u8         reserved_at_40[0x8];
3765         u8         sqn[0x18];
3766
3767         u8         reserved_at_60[0x20];
3768 };
3769
3770 struct mlx5_ifc_query_special_contexts_out_bits {
3771         u8         status[0x8];
3772         u8         reserved_at_8[0x18];
3773
3774         u8         syndrome[0x20];
3775
3776         u8         dump_fill_mkey[0x20];
3777
3778         u8         resd_lkey[0x20];
3779
3780         u8         null_mkey[0x20];
3781
3782         u8         reserved_at_a0[0x60];
3783 };
3784
3785 struct mlx5_ifc_query_special_contexts_in_bits {
3786         u8         opcode[0x10];
3787         u8         reserved_at_10[0x10];
3788
3789         u8         reserved_at_20[0x10];
3790         u8         op_mod[0x10];
3791
3792         u8         reserved_at_40[0x40];
3793 };
3794
3795 struct mlx5_ifc_query_scheduling_element_out_bits {
3796         u8         opcode[0x10];
3797         u8         reserved_at_10[0x10];
3798
3799         u8         reserved_at_20[0x10];
3800         u8         op_mod[0x10];
3801
3802         u8         reserved_at_40[0xc0];
3803
3804         struct mlx5_ifc_scheduling_context_bits scheduling_context;
3805
3806         u8         reserved_at_300[0x100];
3807 };
3808
3809 enum {
3810         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3811 };
3812
3813 struct mlx5_ifc_query_scheduling_element_in_bits {
3814         u8         opcode[0x10];
3815         u8         reserved_at_10[0x10];
3816
3817         u8         reserved_at_20[0x10];
3818         u8         op_mod[0x10];
3819
3820         u8         scheduling_hierarchy[0x8];
3821         u8         reserved_at_48[0x18];
3822
3823         u8         scheduling_element_id[0x20];
3824
3825         u8         reserved_at_80[0x180];
3826 };
3827
3828 struct mlx5_ifc_query_rqt_out_bits {
3829         u8         status[0x8];
3830         u8         reserved_at_8[0x18];
3831
3832         u8         syndrome[0x20];
3833
3834         u8         reserved_at_40[0xc0];
3835
3836         struct mlx5_ifc_rqtc_bits rqt_context;
3837 };
3838
3839 struct mlx5_ifc_query_rqt_in_bits {
3840         u8         opcode[0x10];
3841         u8         reserved_at_10[0x10];
3842
3843         u8         reserved_at_20[0x10];
3844         u8         op_mod[0x10];
3845
3846         u8         reserved_at_40[0x8];
3847         u8         rqtn[0x18];
3848
3849         u8         reserved_at_60[0x20];
3850 };
3851
3852 struct mlx5_ifc_query_rq_out_bits {
3853         u8         status[0x8];
3854         u8         reserved_at_8[0x18];
3855
3856         u8         syndrome[0x20];
3857
3858         u8         reserved_at_40[0xc0];
3859
3860         struct mlx5_ifc_rqc_bits rq_context;
3861 };
3862
3863 struct mlx5_ifc_query_rq_in_bits {
3864         u8         opcode[0x10];
3865         u8         reserved_at_10[0x10];
3866
3867         u8         reserved_at_20[0x10];
3868         u8         op_mod[0x10];
3869
3870         u8         reserved_at_40[0x8];
3871         u8         rqn[0x18];
3872
3873         u8         reserved_at_60[0x20];
3874 };
3875
3876 struct mlx5_ifc_query_roce_address_out_bits {
3877         u8         status[0x8];
3878         u8         reserved_at_8[0x18];
3879
3880         u8         syndrome[0x20];
3881
3882         u8         reserved_at_40[0x40];
3883
3884         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3885 };
3886
3887 struct mlx5_ifc_query_roce_address_in_bits {
3888         u8         opcode[0x10];
3889         u8         reserved_at_10[0x10];
3890
3891         u8         reserved_at_20[0x10];
3892         u8         op_mod[0x10];
3893
3894         u8         roce_address_index[0x10];
3895         u8         reserved_at_50[0xc];
3896         u8         vhca_port_num[0x4];
3897
3898         u8         reserved_at_60[0x20];
3899 };
3900
3901 struct mlx5_ifc_query_rmp_out_bits {
3902         u8         status[0x8];
3903         u8         reserved_at_8[0x18];
3904
3905         u8         syndrome[0x20];
3906
3907         u8         reserved_at_40[0xc0];
3908
3909         struct mlx5_ifc_rmpc_bits rmp_context;
3910 };
3911
3912 struct mlx5_ifc_query_rmp_in_bits {
3913         u8         opcode[0x10];
3914         u8         reserved_at_10[0x10];
3915
3916         u8         reserved_at_20[0x10];
3917         u8         op_mod[0x10];
3918
3919         u8         reserved_at_40[0x8];
3920         u8         rmpn[0x18];
3921
3922         u8         reserved_at_60[0x20];
3923 };
3924
3925 struct mlx5_ifc_query_qp_out_bits {
3926         u8         status[0x8];
3927         u8         reserved_at_8[0x18];
3928
3929         u8         syndrome[0x20];
3930
3931         u8         reserved_at_40[0x40];
3932
3933         u8         opt_param_mask[0x20];
3934
3935         u8         reserved_at_a0[0x20];
3936
3937         struct mlx5_ifc_qpc_bits qpc;
3938
3939         u8         reserved_at_800[0x80];
3940
3941         u8         pas[0][0x40];
3942 };
3943
3944 struct mlx5_ifc_query_qp_in_bits {
3945         u8         opcode[0x10];
3946         u8         reserved_at_10[0x10];
3947
3948         u8         reserved_at_20[0x10];
3949         u8         op_mod[0x10];
3950
3951         u8         reserved_at_40[0x8];
3952         u8         qpn[0x18];
3953
3954         u8         reserved_at_60[0x20];
3955 };
3956
3957 struct mlx5_ifc_query_q_counter_out_bits {
3958         u8         status[0x8];
3959         u8         reserved_at_8[0x18];
3960
3961         u8         syndrome[0x20];
3962
3963         u8         reserved_at_40[0x40];
3964
3965         u8         rx_write_requests[0x20];
3966
3967         u8         reserved_at_a0[0x20];
3968
3969         u8         rx_read_requests[0x20];
3970
3971         u8         reserved_at_e0[0x20];
3972
3973         u8         rx_atomic_requests[0x20];
3974
3975         u8         reserved_at_120[0x20];
3976
3977         u8         rx_dct_connect[0x20];
3978
3979         u8         reserved_at_160[0x20];
3980
3981         u8         out_of_buffer[0x20];
3982
3983         u8         reserved_at_1a0[0x20];
3984
3985         u8         out_of_sequence[0x20];
3986
3987         u8         reserved_at_1e0[0x20];
3988
3989         u8         duplicate_request[0x20];
3990
3991         u8         reserved_at_220[0x20];
3992
3993         u8         rnr_nak_retry_err[0x20];
3994
3995         u8         reserved_at_260[0x20];
3996
3997         u8         packet_seq_err[0x20];
3998
3999         u8         reserved_at_2a0[0x20];
4000
4001         u8         implied_nak_seq_err[0x20];
4002
4003         u8         reserved_at_2e0[0x20];
4004
4005         u8         local_ack_timeout_err[0x20];
4006
4007         u8         reserved_at_320[0xa0];
4008
4009         u8         resp_local_length_error[0x20];
4010
4011         u8         req_local_length_error[0x20];
4012
4013         u8         resp_local_qp_error[0x20];
4014
4015         u8         local_operation_error[0x20];
4016
4017         u8         resp_local_protection[0x20];
4018
4019         u8         req_local_protection[0x20];
4020
4021         u8         resp_cqe_error[0x20];
4022
4023         u8         req_cqe_error[0x20];
4024
4025         u8         req_mw_binding[0x20];
4026
4027         u8         req_bad_response[0x20];
4028
4029         u8         req_remote_invalid_request[0x20];
4030
4031         u8         resp_remote_invalid_request[0x20];
4032
4033         u8         req_remote_access_errors[0x20];
4034
4035         u8         resp_remote_access_errors[0x20];
4036
4037         u8         req_remote_operation_errors[0x20];
4038
4039         u8         req_transport_retries_exceeded[0x20];
4040
4041         u8         cq_overflow[0x20];
4042
4043         u8         resp_cqe_flush_error[0x20];
4044
4045         u8         req_cqe_flush_error[0x20];
4046
4047         u8         reserved_at_620[0x1e0];
4048 };
4049
4050 struct mlx5_ifc_query_q_counter_in_bits {
4051         u8         opcode[0x10];
4052         u8         reserved_at_10[0x10];
4053
4054         u8         reserved_at_20[0x10];
4055         u8         op_mod[0x10];
4056
4057         u8         reserved_at_40[0x80];
4058
4059         u8         clear[0x1];
4060         u8         reserved_at_c1[0x1f];
4061
4062         u8         reserved_at_e0[0x18];
4063         u8         counter_set_id[0x8];
4064 };
4065
4066 struct mlx5_ifc_query_pages_out_bits {
4067         u8         status[0x8];
4068         u8         reserved_at_8[0x18];
4069
4070         u8         syndrome[0x20];
4071
4072         u8         reserved_at_40[0x10];
4073         u8         function_id[0x10];
4074
4075         u8         num_pages[0x20];
4076 };
4077
4078 enum {
4079         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4080         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4081         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4082 };
4083
4084 struct mlx5_ifc_query_pages_in_bits {
4085         u8         opcode[0x10];
4086         u8         reserved_at_10[0x10];
4087
4088         u8         reserved_at_20[0x10];
4089         u8         op_mod[0x10];
4090
4091         u8         reserved_at_40[0x10];
4092         u8         function_id[0x10];
4093
4094         u8         reserved_at_60[0x20];
4095 };
4096
4097 struct mlx5_ifc_query_nic_vport_context_out_bits {
4098         u8         status[0x8];
4099         u8         reserved_at_8[0x18];
4100
4101         u8         syndrome[0x20];
4102
4103         u8         reserved_at_40[0x40];
4104
4105         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4106 };
4107
4108 struct mlx5_ifc_query_nic_vport_context_in_bits {
4109         u8         opcode[0x10];
4110         u8         reserved_at_10[0x10];
4111
4112         u8         reserved_at_20[0x10];
4113         u8         op_mod[0x10];
4114
4115         u8         other_vport[0x1];
4116         u8         reserved_at_41[0xf];
4117         u8         vport_number[0x10];
4118
4119         u8         reserved_at_60[0x5];
4120         u8         allowed_list_type[0x3];
4121         u8         reserved_at_68[0x18];
4122 };
4123
4124 struct mlx5_ifc_query_mkey_out_bits {
4125         u8         status[0x8];
4126         u8         reserved_at_8[0x18];
4127
4128         u8         syndrome[0x20];
4129
4130         u8         reserved_at_40[0x40];
4131
4132         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4133
4134         u8         reserved_at_280[0x600];
4135
4136         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4137
4138         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4139 };
4140
4141 struct mlx5_ifc_query_mkey_in_bits {
4142         u8         opcode[0x10];
4143         u8         reserved_at_10[0x10];
4144
4145         u8         reserved_at_20[0x10];
4146         u8         op_mod[0x10];
4147
4148         u8         reserved_at_40[0x8];
4149         u8         mkey_index[0x18];
4150
4151         u8         pg_access[0x1];
4152         u8         reserved_at_61[0x1f];
4153 };
4154
4155 struct mlx5_ifc_query_mad_demux_out_bits {
4156         u8         status[0x8];
4157         u8         reserved_at_8[0x18];
4158
4159         u8         syndrome[0x20];
4160
4161         u8         reserved_at_40[0x40];
4162
4163         u8         mad_dumux_parameters_block[0x20];
4164 };
4165
4166 struct mlx5_ifc_query_mad_demux_in_bits {
4167         u8         opcode[0x10];
4168         u8         reserved_at_10[0x10];
4169
4170         u8         reserved_at_20[0x10];
4171         u8         op_mod[0x10];
4172
4173         u8         reserved_at_40[0x40];
4174 };
4175
4176 struct mlx5_ifc_query_l2_table_entry_out_bits {
4177         u8         status[0x8];
4178         u8         reserved_at_8[0x18];
4179
4180         u8         syndrome[0x20];
4181
4182         u8         reserved_at_40[0xa0];
4183
4184         u8         reserved_at_e0[0x13];
4185         u8         vlan_valid[0x1];
4186         u8         vlan[0xc];
4187
4188         struct mlx5_ifc_mac_address_layout_bits mac_address;
4189
4190         u8         reserved_at_140[0xc0];
4191 };
4192
4193 struct mlx5_ifc_query_l2_table_entry_in_bits {
4194         u8         opcode[0x10];
4195         u8         reserved_at_10[0x10];
4196
4197         u8         reserved_at_20[0x10];
4198         u8         op_mod[0x10];
4199
4200         u8         reserved_at_40[0x60];
4201
4202         u8         reserved_at_a0[0x8];
4203         u8         table_index[0x18];
4204
4205         u8         reserved_at_c0[0x140];
4206 };
4207
4208 struct mlx5_ifc_query_issi_out_bits {
4209         u8         status[0x8];
4210         u8         reserved_at_8[0x18];
4211
4212         u8         syndrome[0x20];
4213
4214         u8         reserved_at_40[0x10];
4215         u8         current_issi[0x10];
4216
4217         u8         reserved_at_60[0xa0];
4218
4219         u8         reserved_at_100[76][0x8];
4220         u8         supported_issi_dw0[0x20];
4221 };
4222
4223 struct mlx5_ifc_query_issi_in_bits {
4224         u8         opcode[0x10];
4225         u8         reserved_at_10[0x10];
4226
4227         u8         reserved_at_20[0x10];
4228         u8         op_mod[0x10];
4229
4230         u8         reserved_at_40[0x40];
4231 };
4232
4233 struct mlx5_ifc_set_driver_version_out_bits {
4234         u8         status[0x8];
4235         u8         reserved_0[0x18];
4236
4237         u8         syndrome[0x20];
4238         u8         reserved_1[0x40];
4239 };
4240
4241 struct mlx5_ifc_set_driver_version_in_bits {
4242         u8         opcode[0x10];
4243         u8         reserved_0[0x10];
4244
4245         u8         reserved_1[0x10];
4246         u8         op_mod[0x10];
4247
4248         u8         reserved_2[0x40];
4249         u8         driver_version[64][0x8];
4250 };
4251
4252 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4253         u8         status[0x8];
4254         u8         reserved_at_8[0x18];
4255
4256         u8         syndrome[0x20];
4257
4258         u8         reserved_at_40[0x40];
4259
4260         struct mlx5_ifc_pkey_bits pkey[0];
4261 };
4262
4263 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4264         u8         opcode[0x10];
4265         u8         reserved_at_10[0x10];
4266
4267         u8         reserved_at_20[0x10];
4268         u8         op_mod[0x10];
4269
4270         u8         other_vport[0x1];
4271         u8         reserved_at_41[0xb];
4272         u8         port_num[0x4];
4273         u8         vport_number[0x10];
4274
4275         u8         reserved_at_60[0x10];
4276         u8         pkey_index[0x10];
4277 };
4278
4279 enum {
4280         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4281         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4282         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4283 };
4284
4285 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4286         u8         status[0x8];
4287         u8         reserved_at_8[0x18];
4288
4289         u8         syndrome[0x20];
4290
4291         u8         reserved_at_40[0x20];
4292
4293         u8         gids_num[0x10];
4294         u8         reserved_at_70[0x10];
4295
4296         struct mlx5_ifc_array128_auto_bits gid[0];
4297 };
4298
4299 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4300         u8         opcode[0x10];
4301         u8         reserved_at_10[0x10];
4302
4303         u8         reserved_at_20[0x10];
4304         u8         op_mod[0x10];
4305
4306         u8         other_vport[0x1];
4307         u8         reserved_at_41[0xb];
4308         u8         port_num[0x4];
4309         u8         vport_number[0x10];
4310
4311         u8         reserved_at_60[0x10];
4312         u8         gid_index[0x10];
4313 };
4314
4315 struct mlx5_ifc_query_hca_vport_context_out_bits {
4316         u8         status[0x8];
4317         u8         reserved_at_8[0x18];
4318
4319         u8         syndrome[0x20];
4320
4321         u8         reserved_at_40[0x40];
4322
4323         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4324 };
4325
4326 struct mlx5_ifc_query_hca_vport_context_in_bits {
4327         u8         opcode[0x10];
4328         u8         reserved_at_10[0x10];
4329
4330         u8         reserved_at_20[0x10];
4331         u8         op_mod[0x10];
4332
4333         u8         other_vport[0x1];
4334         u8         reserved_at_41[0xb];
4335         u8         port_num[0x4];
4336         u8         vport_number[0x10];
4337
4338         u8         reserved_at_60[0x20];
4339 };
4340
4341 struct mlx5_ifc_query_hca_cap_out_bits {
4342         u8         status[0x8];
4343         u8         reserved_at_8[0x18];
4344
4345         u8         syndrome[0x20];
4346
4347         u8         reserved_at_40[0x40];
4348
4349         union mlx5_ifc_hca_cap_union_bits capability;
4350 };
4351
4352 struct mlx5_ifc_query_hca_cap_in_bits {
4353         u8         opcode[0x10];
4354         u8         reserved_at_10[0x10];
4355
4356         u8         reserved_at_20[0x10];
4357         u8         op_mod[0x10];
4358
4359         u8         reserved_at_40[0x40];
4360 };
4361
4362 struct mlx5_ifc_query_flow_table_out_bits {
4363         u8         status[0x8];
4364         u8         reserved_at_8[0x18];
4365
4366         u8         syndrome[0x20];
4367
4368         u8         reserved_at_40[0x80];
4369
4370         u8         reserved_at_c0[0x8];
4371         u8         level[0x8];
4372         u8         reserved_at_d0[0x8];
4373         u8         log_size[0x8];
4374
4375         u8         reserved_at_e0[0x120];
4376 };
4377
4378 struct mlx5_ifc_query_flow_table_in_bits {
4379         u8         opcode[0x10];
4380         u8         reserved_at_10[0x10];
4381
4382         u8         reserved_at_20[0x10];
4383         u8         op_mod[0x10];
4384
4385         u8         reserved_at_40[0x40];
4386
4387         u8         table_type[0x8];
4388         u8         reserved_at_88[0x18];
4389
4390         u8         reserved_at_a0[0x8];
4391         u8         table_id[0x18];
4392
4393         u8         reserved_at_c0[0x140];
4394 };
4395
4396 struct mlx5_ifc_query_fte_out_bits {
4397         u8         status[0x8];
4398         u8         reserved_at_8[0x18];
4399
4400         u8         syndrome[0x20];
4401
4402         u8         reserved_at_40[0x1c0];
4403
4404         struct mlx5_ifc_flow_context_bits flow_context;
4405 };
4406
4407 struct mlx5_ifc_query_fte_in_bits {
4408         u8         opcode[0x10];
4409         u8         reserved_at_10[0x10];
4410
4411         u8         reserved_at_20[0x10];
4412         u8         op_mod[0x10];
4413
4414         u8         reserved_at_40[0x40];
4415
4416         u8         table_type[0x8];
4417         u8         reserved_at_88[0x18];
4418
4419         u8         reserved_at_a0[0x8];
4420         u8         table_id[0x18];
4421
4422         u8         reserved_at_c0[0x40];
4423
4424         u8         flow_index[0x20];
4425
4426         u8         reserved_at_120[0xe0];
4427 };
4428
4429 enum {
4430         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4431         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4432         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4433 };
4434
4435 struct mlx5_ifc_query_flow_group_out_bits {
4436         u8         status[0x8];
4437         u8         reserved_at_8[0x18];
4438
4439         u8         syndrome[0x20];
4440
4441         u8         reserved_at_40[0xa0];
4442
4443         u8         start_flow_index[0x20];
4444
4445         u8         reserved_at_100[0x20];
4446
4447         u8         end_flow_index[0x20];
4448
4449         u8         reserved_at_140[0xa0];
4450
4451         u8         reserved_at_1e0[0x18];
4452         u8         match_criteria_enable[0x8];
4453
4454         struct mlx5_ifc_fte_match_param_bits match_criteria;
4455
4456         u8         reserved_at_1200[0xe00];
4457 };
4458
4459 struct mlx5_ifc_query_flow_group_in_bits {
4460         u8         opcode[0x10];
4461         u8         reserved_at_10[0x10];
4462
4463         u8         reserved_at_20[0x10];
4464         u8         op_mod[0x10];
4465
4466         u8         reserved_at_40[0x40];
4467
4468         u8         table_type[0x8];
4469         u8         reserved_at_88[0x18];
4470
4471         u8         reserved_at_a0[0x8];
4472         u8         table_id[0x18];
4473
4474         u8         group_id[0x20];
4475
4476         u8         reserved_at_e0[0x120];
4477 };
4478
4479 struct mlx5_ifc_query_flow_counter_out_bits {
4480         u8         status[0x8];
4481         u8         reserved_at_8[0x18];
4482
4483         u8         syndrome[0x20];
4484
4485         u8         reserved_at_40[0x40];
4486
4487         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4488 };
4489
4490 struct mlx5_ifc_query_flow_counter_in_bits {
4491         u8         opcode[0x10];
4492         u8         reserved_at_10[0x10];
4493
4494         u8         reserved_at_20[0x10];
4495         u8         op_mod[0x10];
4496
4497         u8         reserved_at_40[0x80];
4498
4499         u8         clear[0x1];
4500         u8         reserved_at_c1[0xf];
4501         u8         num_of_counters[0x10];
4502
4503         u8         flow_counter_id[0x20];
4504 };
4505
4506 struct mlx5_ifc_query_esw_vport_context_out_bits {
4507         u8         status[0x8];
4508         u8         reserved_at_8[0x18];
4509
4510         u8         syndrome[0x20];
4511
4512         u8         reserved_at_40[0x40];
4513
4514         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4515 };
4516
4517 struct mlx5_ifc_query_esw_vport_context_in_bits {
4518         u8         opcode[0x10];
4519         u8         reserved_at_10[0x10];
4520
4521         u8         reserved_at_20[0x10];
4522         u8         op_mod[0x10];
4523
4524         u8         other_vport[0x1];
4525         u8         reserved_at_41[0xf];
4526         u8         vport_number[0x10];
4527
4528         u8         reserved_at_60[0x20];
4529 };
4530
4531 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4532         u8         status[0x8];
4533         u8         reserved_at_8[0x18];
4534
4535         u8         syndrome[0x20];
4536
4537         u8         reserved_at_40[0x40];
4538 };
4539
4540 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4541         u8         reserved_at_0[0x1c];
4542         u8         vport_cvlan_insert[0x1];
4543         u8         vport_svlan_insert[0x1];
4544         u8         vport_cvlan_strip[0x1];
4545         u8         vport_svlan_strip[0x1];
4546 };
4547
4548 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4549         u8         opcode[0x10];
4550         u8         reserved_at_10[0x10];
4551
4552         u8         reserved_at_20[0x10];
4553         u8         op_mod[0x10];
4554
4555         u8         other_vport[0x1];
4556         u8         reserved_at_41[0xf];
4557         u8         vport_number[0x10];
4558
4559         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4560
4561         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4562 };
4563
4564 struct mlx5_ifc_query_eq_out_bits {
4565         u8         status[0x8];
4566         u8         reserved_at_8[0x18];
4567
4568         u8         syndrome[0x20];
4569
4570         u8         reserved_at_40[0x40];
4571
4572         struct mlx5_ifc_eqc_bits eq_context_entry;
4573
4574         u8         reserved_at_280[0x40];
4575
4576         u8         event_bitmask[0x40];
4577
4578         u8         reserved_at_300[0x580];
4579
4580         u8         pas[0][0x40];
4581 };
4582
4583 struct mlx5_ifc_query_eq_in_bits {
4584         u8         opcode[0x10];
4585         u8         reserved_at_10[0x10];
4586
4587         u8         reserved_at_20[0x10];
4588         u8         op_mod[0x10];
4589
4590         u8         reserved_at_40[0x18];
4591         u8         eq_number[0x8];
4592
4593         u8         reserved_at_60[0x20];
4594 };
4595
4596 struct mlx5_ifc_encap_header_in_bits {
4597         u8         reserved_at_0[0x5];
4598         u8         header_type[0x3];
4599         u8         reserved_at_8[0xe];
4600         u8         encap_header_size[0xa];
4601
4602         u8         reserved_at_20[0x10];
4603         u8         encap_header[2][0x8];
4604
4605         u8         more_encap_header[0][0x8];
4606 };
4607
4608 struct mlx5_ifc_query_encap_header_out_bits {
4609         u8         status[0x8];
4610         u8         reserved_at_8[0x18];
4611
4612         u8         syndrome[0x20];
4613
4614         u8         reserved_at_40[0xa0];
4615
4616         struct mlx5_ifc_encap_header_in_bits encap_header[0];
4617 };
4618
4619 struct mlx5_ifc_query_encap_header_in_bits {
4620         u8         opcode[0x10];
4621         u8         reserved_at_10[0x10];
4622
4623         u8         reserved_at_20[0x10];
4624         u8         op_mod[0x10];
4625
4626         u8         encap_id[0x20];
4627
4628         u8         reserved_at_60[0xa0];
4629 };
4630
4631 struct mlx5_ifc_alloc_encap_header_out_bits {
4632         u8         status[0x8];
4633         u8         reserved_at_8[0x18];
4634
4635         u8         syndrome[0x20];
4636
4637         u8         encap_id[0x20];
4638
4639         u8         reserved_at_60[0x20];
4640 };
4641
4642 struct mlx5_ifc_alloc_encap_header_in_bits {
4643         u8         opcode[0x10];
4644         u8         reserved_at_10[0x10];
4645
4646         u8         reserved_at_20[0x10];
4647         u8         op_mod[0x10];
4648
4649         u8         reserved_at_40[0xa0];
4650
4651         struct mlx5_ifc_encap_header_in_bits encap_header;
4652 };
4653
4654 struct mlx5_ifc_dealloc_encap_header_out_bits {
4655         u8         status[0x8];
4656         u8         reserved_at_8[0x18];
4657
4658         u8         syndrome[0x20];
4659
4660         u8         reserved_at_40[0x40];
4661 };
4662
4663 struct mlx5_ifc_dealloc_encap_header_in_bits {
4664         u8         opcode[0x10];
4665         u8         reserved_at_10[0x10];
4666
4667         u8         reserved_20[0x10];
4668         u8         op_mod[0x10];
4669
4670         u8         encap_id[0x20];
4671
4672         u8         reserved_60[0x20];
4673 };
4674
4675 struct mlx5_ifc_set_action_in_bits {
4676         u8         action_type[0x4];
4677         u8         field[0xc];
4678         u8         reserved_at_10[0x3];
4679         u8         offset[0x5];
4680         u8         reserved_at_18[0x3];
4681         u8         length[0x5];
4682
4683         u8         data[0x20];
4684 };
4685
4686 struct mlx5_ifc_add_action_in_bits {
4687         u8         action_type[0x4];
4688         u8         field[0xc];
4689         u8         reserved_at_10[0x10];
4690
4691         u8         data[0x20];
4692 };
4693
4694 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4695         struct mlx5_ifc_set_action_in_bits set_action_in;
4696         struct mlx5_ifc_add_action_in_bits add_action_in;
4697         u8         reserved_at_0[0x40];
4698 };
4699
4700 enum {
4701         MLX5_ACTION_TYPE_SET   = 0x1,
4702         MLX5_ACTION_TYPE_ADD   = 0x2,
4703 };
4704
4705 enum {
4706         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
4707         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
4708         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
4709         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
4710         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
4711         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
4712         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
4713         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
4714         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
4715         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
4716         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
4717         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
4718         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
4719         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
4720         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
4721         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
4722         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
4723         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
4724         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
4725         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
4726         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
4727         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
4728         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4729 };
4730
4731 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4732         u8         status[0x8];
4733         u8         reserved_at_8[0x18];
4734
4735         u8         syndrome[0x20];
4736
4737         u8         modify_header_id[0x20];
4738
4739         u8         reserved_at_60[0x20];
4740 };
4741
4742 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4743         u8         opcode[0x10];
4744         u8         reserved_at_10[0x10];
4745
4746         u8         reserved_at_20[0x10];
4747         u8         op_mod[0x10];
4748
4749         u8         reserved_at_40[0x20];
4750
4751         u8         table_type[0x8];
4752         u8         reserved_at_68[0x10];
4753         u8         num_of_actions[0x8];
4754
4755         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4756 };
4757
4758 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4759         u8         status[0x8];
4760         u8         reserved_at_8[0x18];
4761
4762         u8         syndrome[0x20];
4763
4764         u8         reserved_at_40[0x40];
4765 };
4766
4767 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4768         u8         opcode[0x10];
4769         u8         reserved_at_10[0x10];
4770
4771         u8         reserved_at_20[0x10];
4772         u8         op_mod[0x10];
4773
4774         u8         modify_header_id[0x20];
4775
4776         u8         reserved_at_60[0x20];
4777 };
4778
4779 struct mlx5_ifc_query_dct_out_bits {
4780         u8         status[0x8];
4781         u8         reserved_at_8[0x18];
4782
4783         u8         syndrome[0x20];
4784
4785         u8         reserved_at_40[0x40];
4786
4787         struct mlx5_ifc_dctc_bits dct_context_entry;
4788
4789         u8         reserved_at_280[0x180];
4790 };
4791
4792 struct mlx5_ifc_query_dct_in_bits {
4793         u8         opcode[0x10];
4794         u8         reserved_at_10[0x10];
4795
4796         u8         reserved_at_20[0x10];
4797         u8         op_mod[0x10];
4798
4799         u8         reserved_at_40[0x8];
4800         u8         dctn[0x18];
4801
4802         u8         reserved_at_60[0x20];
4803 };
4804
4805 struct mlx5_ifc_query_cq_out_bits {
4806         u8         status[0x8];
4807         u8         reserved_at_8[0x18];
4808
4809         u8         syndrome[0x20];
4810
4811         u8         reserved_at_40[0x40];
4812
4813         struct mlx5_ifc_cqc_bits cq_context;
4814
4815         u8         reserved_at_280[0x600];
4816
4817         u8         pas[0][0x40];
4818 };
4819
4820 struct mlx5_ifc_query_cq_in_bits {
4821         u8         opcode[0x10];
4822         u8         reserved_at_10[0x10];
4823
4824         u8         reserved_at_20[0x10];
4825         u8         op_mod[0x10];
4826
4827         u8         reserved_at_40[0x8];
4828         u8         cqn[0x18];
4829
4830         u8         reserved_at_60[0x20];
4831 };
4832
4833 struct mlx5_ifc_query_cong_status_out_bits {
4834         u8         status[0x8];
4835         u8         reserved_at_8[0x18];
4836
4837         u8         syndrome[0x20];
4838
4839         u8         reserved_at_40[0x20];
4840
4841         u8         enable[0x1];
4842         u8         tag_enable[0x1];
4843         u8         reserved_at_62[0x1e];
4844 };
4845
4846 struct mlx5_ifc_query_cong_status_in_bits {
4847         u8         opcode[0x10];
4848         u8         reserved_at_10[0x10];
4849
4850         u8         reserved_at_20[0x10];
4851         u8         op_mod[0x10];
4852
4853         u8         reserved_at_40[0x18];
4854         u8         priority[0x4];
4855         u8         cong_protocol[0x4];
4856
4857         u8         reserved_at_60[0x20];
4858 };
4859
4860 struct mlx5_ifc_query_cong_statistics_out_bits {
4861         u8         status[0x8];
4862         u8         reserved_at_8[0x18];
4863
4864         u8         syndrome[0x20];
4865
4866         u8         reserved_at_40[0x40];
4867
4868         u8         rp_cur_flows[0x20];
4869
4870         u8         sum_flows[0x20];
4871
4872         u8         rp_cnp_ignored_high[0x20];
4873
4874         u8         rp_cnp_ignored_low[0x20];
4875
4876         u8         rp_cnp_handled_high[0x20];
4877
4878         u8         rp_cnp_handled_low[0x20];
4879
4880         u8         reserved_at_140[0x100];
4881
4882         u8         time_stamp_high[0x20];
4883
4884         u8         time_stamp_low[0x20];
4885
4886         u8         accumulators_period[0x20];
4887
4888         u8         np_ecn_marked_roce_packets_high[0x20];
4889
4890         u8         np_ecn_marked_roce_packets_low[0x20];
4891
4892         u8         np_cnp_sent_high[0x20];
4893
4894         u8         np_cnp_sent_low[0x20];
4895
4896         u8         reserved_at_320[0x560];
4897 };
4898
4899 struct mlx5_ifc_query_cong_statistics_in_bits {
4900         u8         opcode[0x10];
4901         u8         reserved_at_10[0x10];
4902
4903         u8         reserved_at_20[0x10];
4904         u8         op_mod[0x10];
4905
4906         u8         clear[0x1];
4907         u8         reserved_at_41[0x1f];
4908
4909         u8         reserved_at_60[0x20];
4910 };
4911
4912 struct mlx5_ifc_query_cong_params_out_bits {
4913         u8         status[0x8];
4914         u8         reserved_at_8[0x18];
4915
4916         u8         syndrome[0x20];
4917
4918         u8         reserved_at_40[0x40];
4919
4920         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4921 };
4922
4923 struct mlx5_ifc_query_cong_params_in_bits {
4924         u8         opcode[0x10];
4925         u8         reserved_at_10[0x10];
4926
4927         u8         reserved_at_20[0x10];
4928         u8         op_mod[0x10];
4929
4930         u8         reserved_at_40[0x1c];
4931         u8         cong_protocol[0x4];
4932
4933         u8         reserved_at_60[0x20];
4934 };
4935
4936 struct mlx5_ifc_query_adapter_out_bits {
4937         u8         status[0x8];
4938         u8         reserved_at_8[0x18];
4939
4940         u8         syndrome[0x20];
4941
4942         u8         reserved_at_40[0x40];
4943
4944         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4945 };
4946
4947 struct mlx5_ifc_query_adapter_in_bits {
4948         u8         opcode[0x10];
4949         u8         reserved_at_10[0x10];
4950
4951         u8         reserved_at_20[0x10];
4952         u8         op_mod[0x10];
4953
4954         u8         reserved_at_40[0x40];
4955 };
4956
4957 struct mlx5_ifc_qp_2rst_out_bits {
4958         u8         status[0x8];
4959         u8         reserved_at_8[0x18];
4960
4961         u8         syndrome[0x20];
4962
4963         u8         reserved_at_40[0x40];
4964 };
4965
4966 struct mlx5_ifc_qp_2rst_in_bits {
4967         u8         opcode[0x10];
4968         u8         reserved_at_10[0x10];
4969
4970         u8         reserved_at_20[0x10];
4971         u8         op_mod[0x10];
4972
4973         u8         reserved_at_40[0x8];
4974         u8         qpn[0x18];
4975
4976         u8         reserved_at_60[0x20];
4977 };
4978
4979 struct mlx5_ifc_qp_2err_out_bits {
4980         u8         status[0x8];
4981         u8         reserved_at_8[0x18];
4982
4983         u8         syndrome[0x20];
4984
4985         u8         reserved_at_40[0x40];
4986 };
4987
4988 struct mlx5_ifc_qp_2err_in_bits {
4989         u8         opcode[0x10];
4990         u8         reserved_at_10[0x10];
4991
4992         u8         reserved_at_20[0x10];
4993         u8         op_mod[0x10];
4994
4995         u8         reserved_at_40[0x8];
4996         u8         qpn[0x18];
4997
4998         u8         reserved_at_60[0x20];
4999 };
5000
5001 struct mlx5_ifc_page_fault_resume_out_bits {
5002         u8         status[0x8];
5003         u8         reserved_at_8[0x18];
5004
5005         u8         syndrome[0x20];
5006
5007         u8         reserved_at_40[0x40];
5008 };
5009
5010 struct mlx5_ifc_page_fault_resume_in_bits {
5011         u8         opcode[0x10];
5012         u8         reserved_at_10[0x10];
5013
5014         u8         reserved_at_20[0x10];
5015         u8         op_mod[0x10];
5016
5017         u8         error[0x1];
5018         u8         reserved_at_41[0x4];
5019         u8         page_fault_type[0x3];
5020         u8         wq_number[0x18];
5021
5022         u8         reserved_at_60[0x8];
5023         u8         token[0x18];
5024 };
5025
5026 struct mlx5_ifc_nop_out_bits {
5027         u8         status[0x8];
5028         u8         reserved_at_8[0x18];
5029
5030         u8         syndrome[0x20];
5031
5032         u8         reserved_at_40[0x40];
5033 };
5034
5035 struct mlx5_ifc_nop_in_bits {
5036         u8         opcode[0x10];
5037         u8         reserved_at_10[0x10];
5038
5039         u8         reserved_at_20[0x10];
5040         u8         op_mod[0x10];
5041
5042         u8         reserved_at_40[0x40];
5043 };
5044
5045 struct mlx5_ifc_modify_vport_state_out_bits {
5046         u8         status[0x8];
5047         u8         reserved_at_8[0x18];
5048
5049         u8         syndrome[0x20];
5050
5051         u8         reserved_at_40[0x40];
5052 };
5053
5054 struct mlx5_ifc_modify_vport_state_in_bits {
5055         u8         opcode[0x10];
5056         u8         reserved_at_10[0x10];
5057
5058         u8         reserved_at_20[0x10];
5059         u8         op_mod[0x10];
5060
5061         u8         other_vport[0x1];
5062         u8         reserved_at_41[0xf];
5063         u8         vport_number[0x10];
5064
5065         u8         reserved_at_60[0x18];
5066         u8         admin_state[0x4];
5067         u8         reserved_at_7c[0x4];
5068 };
5069
5070 struct mlx5_ifc_modify_tis_out_bits {
5071         u8         status[0x8];
5072         u8         reserved_at_8[0x18];
5073
5074         u8         syndrome[0x20];
5075
5076         u8         reserved_at_40[0x40];
5077 };
5078
5079 struct mlx5_ifc_modify_tis_bitmask_bits {
5080         u8         reserved_at_0[0x20];
5081
5082         u8         reserved_at_20[0x1d];
5083         u8         lag_tx_port_affinity[0x1];
5084         u8         strict_lag_tx_port_affinity[0x1];
5085         u8         prio[0x1];
5086 };
5087
5088 struct mlx5_ifc_modify_tis_in_bits {
5089         u8         opcode[0x10];
5090         u8         reserved_at_10[0x10];
5091
5092         u8         reserved_at_20[0x10];
5093         u8         op_mod[0x10];
5094
5095         u8         reserved_at_40[0x8];
5096         u8         tisn[0x18];
5097
5098         u8         reserved_at_60[0x20];
5099
5100         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5101
5102         u8         reserved_at_c0[0x40];
5103
5104         struct mlx5_ifc_tisc_bits ctx;
5105 };
5106
5107 struct mlx5_ifc_modify_tir_bitmask_bits {
5108         u8         reserved_at_0[0x20];
5109
5110         u8         reserved_at_20[0x1b];
5111         u8         self_lb_en[0x1];
5112         u8         reserved_at_3c[0x1];
5113         u8         hash[0x1];
5114         u8         reserved_at_3e[0x1];
5115         u8         lro[0x1];
5116 };
5117
5118 struct mlx5_ifc_modify_tir_out_bits {
5119         u8         status[0x8];
5120         u8         reserved_at_8[0x18];
5121
5122         u8         syndrome[0x20];
5123
5124         u8         reserved_at_40[0x40];
5125 };
5126
5127 struct mlx5_ifc_modify_tir_in_bits {
5128         u8         opcode[0x10];
5129         u8         reserved_at_10[0x10];
5130
5131         u8         reserved_at_20[0x10];
5132         u8         op_mod[0x10];
5133
5134         u8         reserved_at_40[0x8];
5135         u8         tirn[0x18];
5136
5137         u8         reserved_at_60[0x20];
5138
5139         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5140
5141         u8         reserved_at_c0[0x40];
5142
5143         struct mlx5_ifc_tirc_bits ctx;
5144 };
5145
5146 struct mlx5_ifc_modify_sq_out_bits {
5147         u8         status[0x8];
5148         u8         reserved_at_8[0x18];
5149
5150         u8         syndrome[0x20];
5151
5152         u8         reserved_at_40[0x40];
5153 };
5154
5155 struct mlx5_ifc_modify_sq_in_bits {
5156         u8         opcode[0x10];
5157         u8         reserved_at_10[0x10];
5158
5159         u8         reserved_at_20[0x10];
5160         u8         op_mod[0x10];
5161
5162         u8         sq_state[0x4];
5163         u8         reserved_at_44[0x4];
5164         u8         sqn[0x18];
5165
5166         u8         reserved_at_60[0x20];
5167
5168         u8         modify_bitmask[0x40];
5169
5170         u8         reserved_at_c0[0x40];
5171
5172         struct mlx5_ifc_sqc_bits ctx;
5173 };
5174
5175 struct mlx5_ifc_modify_scheduling_element_out_bits {
5176         u8         status[0x8];
5177         u8         reserved_at_8[0x18];
5178
5179         u8         syndrome[0x20];
5180
5181         u8         reserved_at_40[0x1c0];
5182 };
5183
5184 enum {
5185         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5186         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5187 };
5188
5189 struct mlx5_ifc_modify_scheduling_element_in_bits {
5190         u8         opcode[0x10];
5191         u8         reserved_at_10[0x10];
5192
5193         u8         reserved_at_20[0x10];
5194         u8         op_mod[0x10];
5195
5196         u8         scheduling_hierarchy[0x8];
5197         u8         reserved_at_48[0x18];
5198
5199         u8         scheduling_element_id[0x20];
5200
5201         u8         reserved_at_80[0x20];
5202
5203         u8         modify_bitmask[0x20];
5204
5205         u8         reserved_at_c0[0x40];
5206
5207         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5208
5209         u8         reserved_at_300[0x100];
5210 };
5211
5212 struct mlx5_ifc_modify_rqt_out_bits {
5213         u8         status[0x8];
5214         u8         reserved_at_8[0x18];
5215
5216         u8         syndrome[0x20];
5217
5218         u8         reserved_at_40[0x40];
5219 };
5220
5221 struct mlx5_ifc_rqt_bitmask_bits {
5222         u8         reserved_at_0[0x20];
5223
5224         u8         reserved_at_20[0x1f];
5225         u8         rqn_list[0x1];
5226 };
5227
5228 struct mlx5_ifc_modify_rqt_in_bits {
5229         u8         opcode[0x10];
5230         u8         reserved_at_10[0x10];
5231
5232         u8         reserved_at_20[0x10];
5233         u8         op_mod[0x10];
5234
5235         u8         reserved_at_40[0x8];
5236         u8         rqtn[0x18];
5237
5238         u8         reserved_at_60[0x20];
5239
5240         struct mlx5_ifc_rqt_bitmask_bits bitmask;
5241
5242         u8         reserved_at_c0[0x40];
5243
5244         struct mlx5_ifc_rqtc_bits ctx;
5245 };
5246
5247 struct mlx5_ifc_modify_rq_out_bits {
5248         u8         status[0x8];
5249         u8         reserved_at_8[0x18];
5250
5251         u8         syndrome[0x20];
5252
5253         u8         reserved_at_40[0x40];
5254 };
5255
5256 enum {
5257         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5258         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5259         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5260 };
5261
5262 struct mlx5_ifc_modify_rq_in_bits {
5263         u8         opcode[0x10];
5264         u8         reserved_at_10[0x10];
5265
5266         u8         reserved_at_20[0x10];
5267         u8         op_mod[0x10];
5268
5269         u8         rq_state[0x4];
5270         u8         reserved_at_44[0x4];
5271         u8         rqn[0x18];
5272
5273         u8         reserved_at_60[0x20];
5274
5275         u8         modify_bitmask[0x40];
5276
5277         u8         reserved_at_c0[0x40];
5278
5279         struct mlx5_ifc_rqc_bits ctx;
5280 };
5281
5282 struct mlx5_ifc_modify_rmp_out_bits {
5283         u8         status[0x8];
5284         u8         reserved_at_8[0x18];
5285
5286         u8         syndrome[0x20];
5287
5288         u8         reserved_at_40[0x40];
5289 };
5290
5291 struct mlx5_ifc_rmp_bitmask_bits {
5292         u8         reserved_at_0[0x20];
5293
5294         u8         reserved_at_20[0x1f];
5295         u8         lwm[0x1];
5296 };
5297
5298 struct mlx5_ifc_modify_rmp_in_bits {
5299         u8         opcode[0x10];
5300         u8         reserved_at_10[0x10];
5301
5302         u8         reserved_at_20[0x10];
5303         u8         op_mod[0x10];
5304
5305         u8         rmp_state[0x4];
5306         u8         reserved_at_44[0x4];
5307         u8         rmpn[0x18];
5308
5309         u8         reserved_at_60[0x20];
5310
5311         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5312
5313         u8         reserved_at_c0[0x40];
5314
5315         struct mlx5_ifc_rmpc_bits ctx;
5316 };
5317
5318 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5319         u8         status[0x8];
5320         u8         reserved_at_8[0x18];
5321
5322         u8         syndrome[0x20];
5323
5324         u8         reserved_at_40[0x40];
5325 };
5326
5327 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5328         u8         reserved_at_0[0x12];
5329         u8         affiliation[0x1];
5330         u8         reserved_at_e[0x1];
5331         u8         disable_uc_local_lb[0x1];
5332         u8         disable_mc_local_lb[0x1];
5333         u8         node_guid[0x1];
5334         u8         port_guid[0x1];
5335         u8         min_inline[0x1];
5336         u8         mtu[0x1];
5337         u8         change_event[0x1];
5338         u8         promisc[0x1];
5339         u8         permanent_address[0x1];
5340         u8         addresses_list[0x1];
5341         u8         roce_en[0x1];
5342         u8         reserved_at_1f[0x1];
5343 };
5344
5345 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5346         u8         opcode[0x10];
5347         u8         reserved_at_10[0x10];
5348
5349         u8         reserved_at_20[0x10];
5350         u8         op_mod[0x10];
5351
5352         u8         other_vport[0x1];
5353         u8         reserved_at_41[0xf];
5354         u8         vport_number[0x10];
5355
5356         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5357
5358         u8         reserved_at_80[0x780];
5359
5360         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5361 };
5362
5363 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5364         u8         status[0x8];
5365         u8         reserved_at_8[0x18];
5366
5367         u8         syndrome[0x20];
5368
5369         u8         reserved_at_40[0x40];
5370 };
5371
5372 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5373         u8         opcode[0x10];
5374         u8         reserved_at_10[0x10];
5375
5376         u8         reserved_at_20[0x10];
5377         u8         op_mod[0x10];
5378
5379         u8         other_vport[0x1];
5380         u8         reserved_at_41[0xb];
5381         u8         port_num[0x4];
5382         u8         vport_number[0x10];
5383
5384         u8         reserved_at_60[0x20];
5385
5386         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5387 };
5388
5389 struct mlx5_ifc_modify_cq_out_bits {
5390         u8         status[0x8];
5391         u8         reserved_at_8[0x18];
5392
5393         u8         syndrome[0x20];
5394
5395         u8         reserved_at_40[0x40];
5396 };
5397
5398 enum {
5399         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5400         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5401 };
5402
5403 struct mlx5_ifc_modify_cq_in_bits {
5404         u8         opcode[0x10];
5405         u8         reserved_at_10[0x10];
5406
5407         u8         reserved_at_20[0x10];
5408         u8         op_mod[0x10];
5409
5410         u8         reserved_at_40[0x8];
5411         u8         cqn[0x18];
5412
5413         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5414
5415         struct mlx5_ifc_cqc_bits cq_context;
5416
5417         u8         reserved_at_280[0x600];
5418
5419         u8         pas[0][0x40];
5420 };
5421
5422 struct mlx5_ifc_modify_cong_status_out_bits {
5423         u8         status[0x8];
5424         u8         reserved_at_8[0x18];
5425
5426         u8         syndrome[0x20];
5427
5428         u8         reserved_at_40[0x40];
5429 };
5430
5431 struct mlx5_ifc_modify_cong_status_in_bits {
5432         u8         opcode[0x10];
5433         u8         reserved_at_10[0x10];
5434
5435         u8         reserved_at_20[0x10];
5436         u8         op_mod[0x10];
5437
5438         u8         reserved_at_40[0x18];
5439         u8         priority[0x4];
5440         u8         cong_protocol[0x4];
5441
5442         u8         enable[0x1];
5443         u8         tag_enable[0x1];
5444         u8         reserved_at_62[0x1e];
5445 };
5446
5447 struct mlx5_ifc_modify_cong_params_out_bits {
5448         u8         status[0x8];
5449         u8         reserved_at_8[0x18];
5450
5451         u8         syndrome[0x20];
5452
5453         u8         reserved_at_40[0x40];
5454 };
5455
5456 struct mlx5_ifc_modify_cong_params_in_bits {
5457         u8         opcode[0x10];
5458         u8         reserved_at_10[0x10];
5459
5460         u8         reserved_at_20[0x10];
5461         u8         op_mod[0x10];
5462
5463         u8         reserved_at_40[0x1c];
5464         u8         cong_protocol[0x4];
5465
5466         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5467
5468         u8         reserved_at_80[0x80];
5469
5470         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5471 };
5472
5473 struct mlx5_ifc_manage_pages_out_bits {
5474         u8         status[0x8];
5475         u8         reserved_at_8[0x18];
5476
5477         u8         syndrome[0x20];
5478
5479         u8         output_num_entries[0x20];
5480
5481         u8         reserved_at_60[0x20];
5482
5483         u8         pas[0][0x40];
5484 };
5485
5486 enum {
5487         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5488         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5489         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5490 };
5491
5492 struct mlx5_ifc_manage_pages_in_bits {
5493         u8         opcode[0x10];
5494         u8         reserved_at_10[0x10];
5495
5496         u8         reserved_at_20[0x10];
5497         u8         op_mod[0x10];
5498
5499         u8         reserved_at_40[0x10];
5500         u8         function_id[0x10];
5501
5502         u8         input_num_entries[0x20];
5503
5504         u8         pas[0][0x40];
5505 };
5506
5507 struct mlx5_ifc_mad_ifc_out_bits {
5508         u8         status[0x8];
5509         u8         reserved_at_8[0x18];
5510
5511         u8         syndrome[0x20];
5512
5513         u8         reserved_at_40[0x40];
5514
5515         u8         response_mad_packet[256][0x8];
5516 };
5517
5518 struct mlx5_ifc_mad_ifc_in_bits {
5519         u8         opcode[0x10];
5520         u8         reserved_at_10[0x10];
5521
5522         u8         reserved_at_20[0x10];
5523         u8         op_mod[0x10];
5524
5525         u8         remote_lid[0x10];
5526         u8         reserved_at_50[0x8];
5527         u8         port[0x8];
5528
5529         u8         reserved_at_60[0x20];
5530
5531         u8         mad[256][0x8];
5532 };
5533
5534 struct mlx5_ifc_init_hca_out_bits {
5535         u8         status[0x8];
5536         u8         reserved_at_8[0x18];
5537
5538         u8         syndrome[0x20];
5539
5540         u8         reserved_at_40[0x40];
5541 };
5542
5543 struct mlx5_ifc_init_hca_in_bits {
5544         u8         opcode[0x10];
5545         u8         reserved_at_10[0x10];
5546
5547         u8         reserved_at_20[0x10];
5548         u8         op_mod[0x10];
5549
5550         u8         reserved_at_40[0x40];
5551         u8         sw_owner_id[4][0x20];
5552 };
5553
5554 struct mlx5_ifc_init2rtr_qp_out_bits {
5555         u8         status[0x8];
5556         u8         reserved_at_8[0x18];
5557
5558         u8         syndrome[0x20];
5559
5560         u8         reserved_at_40[0x40];
5561 };
5562
5563 struct mlx5_ifc_init2rtr_qp_in_bits {
5564         u8         opcode[0x10];
5565         u8         reserved_at_10[0x10];
5566
5567         u8         reserved_at_20[0x10];
5568         u8         op_mod[0x10];
5569
5570         u8         reserved_at_40[0x8];
5571         u8         qpn[0x18];
5572
5573         u8         reserved_at_60[0x20];
5574
5575         u8         opt_param_mask[0x20];
5576
5577         u8         reserved_at_a0[0x20];
5578
5579         struct mlx5_ifc_qpc_bits qpc;
5580
5581         u8         reserved_at_800[0x80];
5582 };
5583
5584 struct mlx5_ifc_init2init_qp_out_bits {
5585         u8         status[0x8];
5586         u8         reserved_at_8[0x18];
5587
5588         u8         syndrome[0x20];
5589
5590         u8         reserved_at_40[0x40];
5591 };
5592
5593 struct mlx5_ifc_init2init_qp_in_bits {
5594         u8         opcode[0x10];
5595         u8         reserved_at_10[0x10];
5596
5597         u8         reserved_at_20[0x10];
5598         u8         op_mod[0x10];
5599
5600         u8         reserved_at_40[0x8];
5601         u8         qpn[0x18];
5602
5603         u8         reserved_at_60[0x20];
5604
5605         u8         opt_param_mask[0x20];
5606
5607         u8         reserved_at_a0[0x20];
5608
5609         struct mlx5_ifc_qpc_bits qpc;
5610
5611         u8         reserved_at_800[0x80];
5612 };
5613
5614 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5615         u8         status[0x8];
5616         u8         reserved_at_8[0x18];
5617
5618         u8         syndrome[0x20];
5619
5620         u8         reserved_at_40[0x40];
5621
5622         u8         packet_headers_log[128][0x8];
5623
5624         u8         packet_syndrome[64][0x8];
5625 };
5626
5627 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5628         u8         opcode[0x10];
5629         u8         reserved_at_10[0x10];
5630
5631         u8         reserved_at_20[0x10];
5632         u8         op_mod[0x10];
5633
5634         u8         reserved_at_40[0x40];
5635 };
5636
5637 struct mlx5_ifc_gen_eqe_in_bits {
5638         u8         opcode[0x10];
5639         u8         reserved_at_10[0x10];
5640
5641         u8         reserved_at_20[0x10];
5642         u8         op_mod[0x10];
5643
5644         u8         reserved_at_40[0x18];
5645         u8         eq_number[0x8];
5646
5647         u8         reserved_at_60[0x20];
5648
5649         u8         eqe[64][0x8];
5650 };
5651
5652 struct mlx5_ifc_gen_eq_out_bits {
5653         u8         status[0x8];
5654         u8         reserved_at_8[0x18];
5655
5656         u8         syndrome[0x20];
5657
5658         u8         reserved_at_40[0x40];
5659 };
5660
5661 struct mlx5_ifc_enable_hca_out_bits {
5662         u8         status[0x8];
5663         u8         reserved_at_8[0x18];
5664
5665         u8         syndrome[0x20];
5666
5667         u8         reserved_at_40[0x20];
5668 };
5669
5670 struct mlx5_ifc_enable_hca_in_bits {
5671         u8         opcode[0x10];
5672         u8         reserved_at_10[0x10];
5673
5674         u8         reserved_at_20[0x10];
5675         u8         op_mod[0x10];
5676
5677         u8         reserved_at_40[0x10];
5678         u8         function_id[0x10];
5679
5680         u8         reserved_at_60[0x20];
5681 };
5682
5683 struct mlx5_ifc_drain_dct_out_bits {
5684         u8         status[0x8];
5685         u8         reserved_at_8[0x18];
5686
5687         u8         syndrome[0x20];
5688
5689         u8         reserved_at_40[0x40];
5690 };
5691
5692 struct mlx5_ifc_drain_dct_in_bits {
5693         u8         opcode[0x10];
5694         u8         reserved_at_10[0x10];
5695
5696         u8         reserved_at_20[0x10];
5697         u8         op_mod[0x10];
5698
5699         u8         reserved_at_40[0x8];
5700         u8         dctn[0x18];
5701
5702         u8         reserved_at_60[0x20];
5703 };
5704
5705 struct mlx5_ifc_disable_hca_out_bits {
5706         u8         status[0x8];
5707         u8         reserved_at_8[0x18];
5708
5709         u8         syndrome[0x20];
5710
5711         u8         reserved_at_40[0x20];
5712 };
5713
5714 struct mlx5_ifc_disable_hca_in_bits {
5715         u8         opcode[0x10];
5716         u8         reserved_at_10[0x10];
5717
5718         u8         reserved_at_20[0x10];
5719         u8         op_mod[0x10];
5720
5721         u8         reserved_at_40[0x10];
5722         u8         function_id[0x10];
5723
5724         u8         reserved_at_60[0x20];
5725 };
5726
5727 struct mlx5_ifc_detach_from_mcg_out_bits {
5728         u8         status[0x8];
5729         u8         reserved_at_8[0x18];
5730
5731         u8         syndrome[0x20];
5732
5733         u8         reserved_at_40[0x40];
5734 };
5735
5736 struct mlx5_ifc_detach_from_mcg_in_bits {
5737         u8         opcode[0x10];
5738         u8         reserved_at_10[0x10];
5739
5740         u8         reserved_at_20[0x10];
5741         u8         op_mod[0x10];
5742
5743         u8         reserved_at_40[0x8];
5744         u8         qpn[0x18];
5745
5746         u8         reserved_at_60[0x20];
5747
5748         u8         multicast_gid[16][0x8];
5749 };
5750
5751 struct mlx5_ifc_destroy_xrq_out_bits {
5752         u8         status[0x8];
5753         u8         reserved_at_8[0x18];
5754
5755         u8         syndrome[0x20];
5756
5757         u8         reserved_at_40[0x40];
5758 };
5759
5760 struct mlx5_ifc_destroy_xrq_in_bits {
5761         u8         opcode[0x10];
5762         u8         reserved_at_10[0x10];
5763
5764         u8         reserved_at_20[0x10];
5765         u8         op_mod[0x10];
5766
5767         u8         reserved_at_40[0x8];
5768         u8         xrqn[0x18];
5769
5770         u8         reserved_at_60[0x20];
5771 };
5772
5773 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5774         u8         status[0x8];
5775         u8         reserved_at_8[0x18];
5776
5777         u8         syndrome[0x20];
5778
5779         u8         reserved_at_40[0x40];
5780 };
5781
5782 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5783         u8         opcode[0x10];
5784         u8         reserved_at_10[0x10];
5785
5786         u8         reserved_at_20[0x10];
5787         u8         op_mod[0x10];
5788
5789         u8         reserved_at_40[0x8];
5790         u8         xrc_srqn[0x18];
5791
5792         u8         reserved_at_60[0x20];
5793 };
5794
5795 struct mlx5_ifc_destroy_tis_out_bits {
5796         u8         status[0x8];
5797         u8         reserved_at_8[0x18];
5798
5799         u8         syndrome[0x20];
5800
5801         u8         reserved_at_40[0x40];
5802 };
5803
5804 struct mlx5_ifc_destroy_tis_in_bits {
5805         u8         opcode[0x10];
5806         u8         reserved_at_10[0x10];
5807
5808         u8         reserved_at_20[0x10];
5809         u8         op_mod[0x10];
5810
5811         u8         reserved_at_40[0x8];
5812         u8         tisn[0x18];
5813
5814         u8         reserved_at_60[0x20];
5815 };
5816
5817 struct mlx5_ifc_destroy_tir_out_bits {
5818         u8         status[0x8];
5819         u8         reserved_at_8[0x18];
5820
5821         u8         syndrome[0x20];
5822
5823         u8         reserved_at_40[0x40];
5824 };
5825
5826 struct mlx5_ifc_destroy_tir_in_bits {
5827         u8         opcode[0x10];
5828         u8         reserved_at_10[0x10];
5829
5830         u8         reserved_at_20[0x10];
5831         u8         op_mod[0x10];
5832
5833         u8         reserved_at_40[0x8];
5834         u8         tirn[0x18];
5835
5836         u8         reserved_at_60[0x20];
5837 };
5838
5839 struct mlx5_ifc_destroy_srq_out_bits {
5840         u8         status[0x8];
5841         u8         reserved_at_8[0x18];
5842
5843         u8         syndrome[0x20];
5844
5845         u8         reserved_at_40[0x40];
5846 };
5847
5848 struct mlx5_ifc_destroy_srq_in_bits {
5849         u8         opcode[0x10];
5850         u8         reserved_at_10[0x10];
5851
5852         u8         reserved_at_20[0x10];
5853         u8         op_mod[0x10];
5854
5855         u8         reserved_at_40[0x8];
5856         u8         srqn[0x18];
5857
5858         u8         reserved_at_60[0x20];
5859 };
5860
5861 struct mlx5_ifc_destroy_sq_out_bits {
5862         u8         status[0x8];
5863         u8         reserved_at_8[0x18];
5864
5865         u8         syndrome[0x20];
5866
5867         u8         reserved_at_40[0x40];
5868 };
5869
5870 struct mlx5_ifc_destroy_sq_in_bits {
5871         u8         opcode[0x10];
5872         u8         reserved_at_10[0x10];
5873
5874         u8         reserved_at_20[0x10];
5875         u8         op_mod[0x10];
5876
5877         u8         reserved_at_40[0x8];
5878         u8         sqn[0x18];
5879
5880         u8         reserved_at_60[0x20];
5881 };
5882
5883 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5884         u8         status[0x8];
5885         u8         reserved_at_8[0x18];
5886
5887         u8         syndrome[0x20];
5888
5889         u8         reserved_at_40[0x1c0];
5890 };
5891
5892 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5893         u8         opcode[0x10];
5894         u8         reserved_at_10[0x10];
5895
5896         u8         reserved_at_20[0x10];
5897         u8         op_mod[0x10];
5898
5899         u8         scheduling_hierarchy[0x8];
5900         u8         reserved_at_48[0x18];
5901
5902         u8         scheduling_element_id[0x20];
5903
5904         u8         reserved_at_80[0x180];
5905 };
5906
5907 struct mlx5_ifc_destroy_rqt_out_bits {
5908         u8         status[0x8];
5909         u8         reserved_at_8[0x18];
5910
5911         u8         syndrome[0x20];
5912
5913         u8         reserved_at_40[0x40];
5914 };
5915
5916 struct mlx5_ifc_destroy_rqt_in_bits {
5917         u8         opcode[0x10];
5918         u8         reserved_at_10[0x10];
5919
5920         u8         reserved_at_20[0x10];
5921         u8         op_mod[0x10];
5922
5923         u8         reserved_at_40[0x8];
5924         u8         rqtn[0x18];
5925
5926         u8         reserved_at_60[0x20];
5927 };
5928
5929 struct mlx5_ifc_destroy_rq_out_bits {
5930         u8         status[0x8];
5931         u8         reserved_at_8[0x18];
5932
5933         u8         syndrome[0x20];
5934
5935         u8         reserved_at_40[0x40];
5936 };
5937
5938 struct mlx5_ifc_destroy_rq_in_bits {
5939         u8         opcode[0x10];
5940         u8         reserved_at_10[0x10];
5941
5942         u8         reserved_at_20[0x10];
5943         u8         op_mod[0x10];
5944
5945         u8         reserved_at_40[0x8];
5946         u8         rqn[0x18];
5947
5948         u8         reserved_at_60[0x20];
5949 };
5950
5951 struct mlx5_ifc_set_delay_drop_params_in_bits {
5952         u8         opcode[0x10];
5953         u8         reserved_at_10[0x10];
5954
5955         u8         reserved_at_20[0x10];
5956         u8         op_mod[0x10];
5957
5958         u8         reserved_at_40[0x20];
5959
5960         u8         reserved_at_60[0x10];
5961         u8         delay_drop_timeout[0x10];
5962 };
5963
5964 struct mlx5_ifc_set_delay_drop_params_out_bits {
5965         u8         status[0x8];
5966         u8         reserved_at_8[0x18];
5967
5968         u8         syndrome[0x20];
5969
5970         u8         reserved_at_40[0x40];
5971 };
5972
5973 struct mlx5_ifc_destroy_rmp_out_bits {
5974         u8         status[0x8];
5975         u8         reserved_at_8[0x18];
5976
5977         u8         syndrome[0x20];
5978
5979         u8         reserved_at_40[0x40];
5980 };
5981
5982 struct mlx5_ifc_destroy_rmp_in_bits {
5983         u8         opcode[0x10];
5984         u8         reserved_at_10[0x10];
5985
5986         u8         reserved_at_20[0x10];
5987         u8         op_mod[0x10];
5988
5989         u8         reserved_at_40[0x8];
5990         u8         rmpn[0x18];
5991
5992         u8         reserved_at_60[0x20];
5993 };
5994
5995 struct mlx5_ifc_destroy_qp_out_bits {
5996         u8         status[0x8];
5997         u8         reserved_at_8[0x18];
5998
5999         u8         syndrome[0x20];
6000
6001         u8         reserved_at_40[0x40];
6002 };
6003
6004 struct mlx5_ifc_destroy_qp_in_bits {
6005         u8         opcode[0x10];
6006         u8         reserved_at_10[0x10];
6007
6008         u8         reserved_at_20[0x10];
6009         u8         op_mod[0x10];
6010
6011         u8         reserved_at_40[0x8];
6012         u8         qpn[0x18];
6013
6014         u8         reserved_at_60[0x20];
6015 };
6016
6017 struct mlx5_ifc_destroy_psv_out_bits {
6018         u8         status[0x8];
6019         u8         reserved_at_8[0x18];
6020
6021         u8         syndrome[0x20];
6022
6023         u8         reserved_at_40[0x40];
6024 };
6025
6026 struct mlx5_ifc_destroy_psv_in_bits {
6027         u8         opcode[0x10];
6028         u8         reserved_at_10[0x10];
6029
6030         u8         reserved_at_20[0x10];
6031         u8         op_mod[0x10];
6032
6033         u8         reserved_at_40[0x8];
6034         u8         psvn[0x18];
6035
6036         u8         reserved_at_60[0x20];
6037 };
6038
6039 struct mlx5_ifc_destroy_mkey_out_bits {
6040         u8         status[0x8];
6041         u8         reserved_at_8[0x18];
6042
6043         u8         syndrome[0x20];
6044
6045         u8         reserved_at_40[0x40];
6046 };
6047
6048 struct mlx5_ifc_destroy_mkey_in_bits {
6049         u8         opcode[0x10];
6050         u8         reserved_at_10[0x10];
6051
6052         u8         reserved_at_20[0x10];
6053         u8         op_mod[0x10];
6054
6055         u8         reserved_at_40[0x8];
6056         u8         mkey_index[0x18];
6057
6058         u8         reserved_at_60[0x20];
6059 };
6060
6061 struct mlx5_ifc_destroy_flow_table_out_bits {
6062         u8         status[0x8];
6063         u8         reserved_at_8[0x18];
6064
6065         u8         syndrome[0x20];
6066
6067         u8         reserved_at_40[0x40];
6068 };
6069
6070 struct mlx5_ifc_destroy_flow_table_in_bits {
6071         u8         opcode[0x10];
6072         u8         reserved_at_10[0x10];
6073
6074         u8         reserved_at_20[0x10];
6075         u8         op_mod[0x10];
6076
6077         u8         other_vport[0x1];
6078         u8         reserved_at_41[0xf];
6079         u8         vport_number[0x10];
6080
6081         u8         reserved_at_60[0x20];
6082
6083         u8         table_type[0x8];
6084         u8         reserved_at_88[0x18];
6085
6086         u8         reserved_at_a0[0x8];
6087         u8         table_id[0x18];
6088
6089         u8         reserved_at_c0[0x140];
6090 };
6091
6092 struct mlx5_ifc_destroy_flow_group_out_bits {
6093         u8         status[0x8];
6094         u8         reserved_at_8[0x18];
6095
6096         u8         syndrome[0x20];
6097
6098         u8         reserved_at_40[0x40];
6099 };
6100
6101 struct mlx5_ifc_destroy_flow_group_in_bits {
6102         u8         opcode[0x10];
6103         u8         reserved_at_10[0x10];
6104
6105         u8         reserved_at_20[0x10];
6106         u8         op_mod[0x10];
6107
6108         u8         other_vport[0x1];
6109         u8         reserved_at_41[0xf];
6110         u8         vport_number[0x10];
6111
6112         u8         reserved_at_60[0x20];
6113
6114         u8         table_type[0x8];
6115         u8         reserved_at_88[0x18];
6116
6117         u8         reserved_at_a0[0x8];
6118         u8         table_id[0x18];
6119
6120         u8         group_id[0x20];
6121
6122         u8         reserved_at_e0[0x120];
6123 };
6124
6125 struct mlx5_ifc_destroy_eq_out_bits {
6126         u8         status[0x8];
6127         u8         reserved_at_8[0x18];
6128
6129         u8         syndrome[0x20];
6130
6131         u8         reserved_at_40[0x40];
6132 };
6133
6134 struct mlx5_ifc_destroy_eq_in_bits {
6135         u8         opcode[0x10];
6136         u8         reserved_at_10[0x10];
6137
6138         u8         reserved_at_20[0x10];
6139         u8         op_mod[0x10];
6140
6141         u8         reserved_at_40[0x18];
6142         u8         eq_number[0x8];
6143
6144         u8         reserved_at_60[0x20];
6145 };
6146
6147 struct mlx5_ifc_destroy_dct_out_bits {
6148         u8         status[0x8];
6149         u8         reserved_at_8[0x18];
6150
6151         u8         syndrome[0x20];
6152
6153         u8         reserved_at_40[0x40];
6154 };
6155
6156 struct mlx5_ifc_destroy_dct_in_bits {
6157         u8         opcode[0x10];
6158         u8         reserved_at_10[0x10];
6159
6160         u8         reserved_at_20[0x10];
6161         u8         op_mod[0x10];
6162
6163         u8         reserved_at_40[0x8];
6164         u8         dctn[0x18];
6165
6166         u8         reserved_at_60[0x20];
6167 };
6168
6169 struct mlx5_ifc_destroy_cq_out_bits {
6170         u8         status[0x8];
6171         u8         reserved_at_8[0x18];
6172
6173         u8         syndrome[0x20];
6174
6175         u8         reserved_at_40[0x40];
6176 };
6177
6178 struct mlx5_ifc_destroy_cq_in_bits {
6179         u8         opcode[0x10];
6180         u8         reserved_at_10[0x10];
6181
6182         u8         reserved_at_20[0x10];
6183         u8         op_mod[0x10];
6184
6185         u8         reserved_at_40[0x8];
6186         u8         cqn[0x18];
6187
6188         u8         reserved_at_60[0x20];
6189 };
6190
6191 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6192         u8         status[0x8];
6193         u8         reserved_at_8[0x18];
6194
6195         u8         syndrome[0x20];
6196
6197         u8         reserved_at_40[0x40];
6198 };
6199
6200 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6201         u8         opcode[0x10];
6202         u8         reserved_at_10[0x10];
6203
6204         u8         reserved_at_20[0x10];
6205         u8         op_mod[0x10];
6206
6207         u8         reserved_at_40[0x20];
6208
6209         u8         reserved_at_60[0x10];
6210         u8         vxlan_udp_port[0x10];
6211 };
6212
6213 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6214         u8         status[0x8];
6215         u8         reserved_at_8[0x18];
6216
6217         u8         syndrome[0x20];
6218
6219         u8         reserved_at_40[0x40];
6220 };
6221
6222 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6223         u8         opcode[0x10];
6224         u8         reserved_at_10[0x10];
6225
6226         u8         reserved_at_20[0x10];
6227         u8         op_mod[0x10];
6228
6229         u8         reserved_at_40[0x60];
6230
6231         u8         reserved_at_a0[0x8];
6232         u8         table_index[0x18];
6233
6234         u8         reserved_at_c0[0x140];
6235 };
6236
6237 struct mlx5_ifc_delete_fte_out_bits {
6238         u8         status[0x8];
6239         u8         reserved_at_8[0x18];
6240
6241         u8         syndrome[0x20];
6242
6243         u8         reserved_at_40[0x40];
6244 };
6245
6246 struct mlx5_ifc_delete_fte_in_bits {
6247         u8         opcode[0x10];
6248         u8         reserved_at_10[0x10];
6249
6250         u8         reserved_at_20[0x10];
6251         u8         op_mod[0x10];
6252
6253         u8         other_vport[0x1];
6254         u8         reserved_at_41[0xf];
6255         u8         vport_number[0x10];
6256
6257         u8         reserved_at_60[0x20];
6258
6259         u8         table_type[0x8];
6260         u8         reserved_at_88[0x18];
6261
6262         u8         reserved_at_a0[0x8];
6263         u8         table_id[0x18];
6264
6265         u8         reserved_at_c0[0x40];
6266
6267         u8         flow_index[0x20];
6268
6269         u8         reserved_at_120[0xe0];
6270 };
6271
6272 struct mlx5_ifc_dealloc_xrcd_out_bits {
6273         u8         status[0x8];
6274         u8         reserved_at_8[0x18];
6275
6276         u8         syndrome[0x20];
6277
6278         u8         reserved_at_40[0x40];
6279 };
6280
6281 struct mlx5_ifc_dealloc_xrcd_in_bits {
6282         u8         opcode[0x10];
6283         u8         reserved_at_10[0x10];
6284
6285         u8         reserved_at_20[0x10];
6286         u8         op_mod[0x10];
6287
6288         u8         reserved_at_40[0x8];
6289         u8         xrcd[0x18];
6290
6291         u8         reserved_at_60[0x20];
6292 };
6293
6294 struct mlx5_ifc_dealloc_uar_out_bits {
6295         u8         status[0x8];
6296         u8         reserved_at_8[0x18];
6297
6298         u8         syndrome[0x20];
6299
6300         u8         reserved_at_40[0x40];
6301 };
6302
6303 struct mlx5_ifc_dealloc_uar_in_bits {
6304         u8         opcode[0x10];
6305         u8         reserved_at_10[0x10];
6306
6307         u8         reserved_at_20[0x10];
6308         u8         op_mod[0x10];
6309
6310         u8         reserved_at_40[0x8];
6311         u8         uar[0x18];
6312
6313         u8         reserved_at_60[0x20];
6314 };
6315
6316 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6317         u8         status[0x8];
6318         u8         reserved_at_8[0x18];
6319
6320         u8         syndrome[0x20];
6321
6322         u8         reserved_at_40[0x40];
6323 };
6324
6325 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6326         u8         opcode[0x10];
6327         u8         reserved_at_10[0x10];
6328
6329         u8         reserved_at_20[0x10];
6330         u8         op_mod[0x10];
6331
6332         u8         reserved_at_40[0x8];
6333         u8         transport_domain[0x18];
6334
6335         u8         reserved_at_60[0x20];
6336 };
6337
6338 struct mlx5_ifc_dealloc_q_counter_out_bits {
6339         u8         status[0x8];
6340         u8         reserved_at_8[0x18];
6341
6342         u8         syndrome[0x20];
6343
6344         u8         reserved_at_40[0x40];
6345 };
6346
6347 struct mlx5_ifc_dealloc_q_counter_in_bits {
6348         u8         opcode[0x10];
6349         u8         reserved_at_10[0x10];
6350
6351         u8         reserved_at_20[0x10];
6352         u8         op_mod[0x10];
6353
6354         u8         reserved_at_40[0x18];
6355         u8         counter_set_id[0x8];
6356
6357         u8         reserved_at_60[0x20];
6358 };
6359
6360 struct mlx5_ifc_dealloc_pd_out_bits {
6361         u8         status[0x8];
6362         u8         reserved_at_8[0x18];
6363
6364         u8         syndrome[0x20];
6365
6366         u8         reserved_at_40[0x40];
6367 };
6368
6369 struct mlx5_ifc_dealloc_pd_in_bits {
6370         u8         opcode[0x10];
6371         u8         reserved_at_10[0x10];
6372
6373         u8         reserved_at_20[0x10];
6374         u8         op_mod[0x10];
6375
6376         u8         reserved_at_40[0x8];
6377         u8         pd[0x18];
6378
6379         u8         reserved_at_60[0x20];
6380 };
6381
6382 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6383         u8         status[0x8];
6384         u8         reserved_at_8[0x18];
6385
6386         u8         syndrome[0x20];
6387
6388         u8         reserved_at_40[0x40];
6389 };
6390
6391 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6392         u8         opcode[0x10];
6393         u8         reserved_at_10[0x10];
6394
6395         u8         reserved_at_20[0x10];
6396         u8         op_mod[0x10];
6397
6398         u8         flow_counter_id[0x20];
6399
6400         u8         reserved_at_60[0x20];
6401 };
6402
6403 struct mlx5_ifc_create_xrq_out_bits {
6404         u8         status[0x8];
6405         u8         reserved_at_8[0x18];
6406
6407         u8         syndrome[0x20];
6408
6409         u8         reserved_at_40[0x8];
6410         u8         xrqn[0x18];
6411
6412         u8         reserved_at_60[0x20];
6413 };
6414
6415 struct mlx5_ifc_create_xrq_in_bits {
6416         u8         opcode[0x10];
6417         u8         reserved_at_10[0x10];
6418
6419         u8         reserved_at_20[0x10];
6420         u8         op_mod[0x10];
6421
6422         u8         reserved_at_40[0x40];
6423
6424         struct mlx5_ifc_xrqc_bits xrq_context;
6425 };
6426
6427 struct mlx5_ifc_create_xrc_srq_out_bits {
6428         u8         status[0x8];
6429         u8         reserved_at_8[0x18];
6430
6431         u8         syndrome[0x20];
6432
6433         u8         reserved_at_40[0x8];
6434         u8         xrc_srqn[0x18];
6435
6436         u8         reserved_at_60[0x20];
6437 };
6438
6439 struct mlx5_ifc_create_xrc_srq_in_bits {
6440         u8         opcode[0x10];
6441         u8         reserved_at_10[0x10];
6442
6443         u8         reserved_at_20[0x10];
6444         u8         op_mod[0x10];
6445
6446         u8         reserved_at_40[0x40];
6447
6448         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6449
6450         u8         reserved_at_280[0x600];
6451
6452         u8         pas[0][0x40];
6453 };
6454
6455 struct mlx5_ifc_create_tis_out_bits {
6456         u8         status[0x8];
6457         u8         reserved_at_8[0x18];
6458
6459         u8         syndrome[0x20];
6460
6461         u8         reserved_at_40[0x8];
6462         u8         tisn[0x18];
6463
6464         u8         reserved_at_60[0x20];
6465 };
6466
6467 struct mlx5_ifc_create_tis_in_bits {
6468         u8         opcode[0x10];
6469         u8         reserved_at_10[0x10];
6470
6471         u8         reserved_at_20[0x10];
6472         u8         op_mod[0x10];
6473
6474         u8         reserved_at_40[0xc0];
6475
6476         struct mlx5_ifc_tisc_bits ctx;
6477 };
6478
6479 struct mlx5_ifc_create_tir_out_bits {
6480         u8         status[0x8];
6481         u8         reserved_at_8[0x18];
6482
6483         u8         syndrome[0x20];
6484
6485         u8         reserved_at_40[0x8];
6486         u8         tirn[0x18];
6487
6488         u8         reserved_at_60[0x20];
6489 };
6490
6491 struct mlx5_ifc_create_tir_in_bits {
6492         u8         opcode[0x10];
6493         u8         reserved_at_10[0x10];
6494
6495         u8         reserved_at_20[0x10];
6496         u8         op_mod[0x10];
6497
6498         u8         reserved_at_40[0xc0];
6499
6500         struct mlx5_ifc_tirc_bits ctx;
6501 };
6502
6503 struct mlx5_ifc_create_srq_out_bits {
6504         u8         status[0x8];
6505         u8         reserved_at_8[0x18];
6506
6507         u8         syndrome[0x20];
6508
6509         u8         reserved_at_40[0x8];
6510         u8         srqn[0x18];
6511
6512         u8         reserved_at_60[0x20];
6513 };
6514
6515 struct mlx5_ifc_create_srq_in_bits {
6516         u8         opcode[0x10];
6517         u8         reserved_at_10[0x10];
6518
6519         u8         reserved_at_20[0x10];
6520         u8         op_mod[0x10];
6521
6522         u8         reserved_at_40[0x40];
6523
6524         struct mlx5_ifc_srqc_bits srq_context_entry;
6525
6526         u8         reserved_at_280[0x600];
6527
6528         u8         pas[0][0x40];
6529 };
6530
6531 struct mlx5_ifc_create_sq_out_bits {
6532         u8         status[0x8];
6533         u8         reserved_at_8[0x18];
6534
6535         u8         syndrome[0x20];
6536
6537         u8         reserved_at_40[0x8];
6538         u8         sqn[0x18];
6539
6540         u8         reserved_at_60[0x20];
6541 };
6542
6543 struct mlx5_ifc_create_sq_in_bits {
6544         u8         opcode[0x10];
6545         u8         reserved_at_10[0x10];
6546
6547         u8         reserved_at_20[0x10];
6548         u8         op_mod[0x10];
6549
6550         u8         reserved_at_40[0xc0];
6551
6552         struct mlx5_ifc_sqc_bits ctx;
6553 };
6554
6555 struct mlx5_ifc_create_scheduling_element_out_bits {
6556         u8         status[0x8];
6557         u8         reserved_at_8[0x18];
6558
6559         u8         syndrome[0x20];
6560
6561         u8         reserved_at_40[0x40];
6562
6563         u8         scheduling_element_id[0x20];
6564
6565         u8         reserved_at_a0[0x160];
6566 };
6567
6568 struct mlx5_ifc_create_scheduling_element_in_bits {
6569         u8         opcode[0x10];
6570         u8         reserved_at_10[0x10];
6571
6572         u8         reserved_at_20[0x10];
6573         u8         op_mod[0x10];
6574
6575         u8         scheduling_hierarchy[0x8];
6576         u8         reserved_at_48[0x18];
6577
6578         u8         reserved_at_60[0xa0];
6579
6580         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6581
6582         u8         reserved_at_300[0x100];
6583 };
6584
6585 struct mlx5_ifc_create_rqt_out_bits {
6586         u8         status[0x8];
6587         u8         reserved_at_8[0x18];
6588
6589         u8         syndrome[0x20];
6590
6591         u8         reserved_at_40[0x8];
6592         u8         rqtn[0x18];
6593
6594         u8         reserved_at_60[0x20];
6595 };
6596
6597 struct mlx5_ifc_create_rqt_in_bits {
6598         u8         opcode[0x10];
6599         u8         reserved_at_10[0x10];
6600
6601         u8         reserved_at_20[0x10];
6602         u8         op_mod[0x10];
6603
6604         u8         reserved_at_40[0xc0];
6605
6606         struct mlx5_ifc_rqtc_bits rqt_context;
6607 };
6608
6609 struct mlx5_ifc_create_rq_out_bits {
6610         u8         status[0x8];
6611         u8         reserved_at_8[0x18];
6612
6613         u8         syndrome[0x20];
6614
6615         u8         reserved_at_40[0x8];
6616         u8         rqn[0x18];
6617
6618         u8         reserved_at_60[0x20];
6619 };
6620
6621 struct mlx5_ifc_create_rq_in_bits {
6622         u8         opcode[0x10];
6623         u8         reserved_at_10[0x10];
6624
6625         u8         reserved_at_20[0x10];
6626         u8         op_mod[0x10];
6627
6628         u8         reserved_at_40[0xc0];
6629
6630         struct mlx5_ifc_rqc_bits ctx;
6631 };
6632
6633 struct mlx5_ifc_create_rmp_out_bits {
6634         u8         status[0x8];
6635         u8         reserved_at_8[0x18];
6636
6637         u8         syndrome[0x20];
6638
6639         u8         reserved_at_40[0x8];
6640         u8         rmpn[0x18];
6641
6642         u8         reserved_at_60[0x20];
6643 };
6644
6645 struct mlx5_ifc_create_rmp_in_bits {
6646         u8         opcode[0x10];
6647         u8         reserved_at_10[0x10];
6648
6649         u8         reserved_at_20[0x10];
6650         u8         op_mod[0x10];
6651
6652         u8         reserved_at_40[0xc0];
6653
6654         struct mlx5_ifc_rmpc_bits ctx;
6655 };
6656
6657 struct mlx5_ifc_create_qp_out_bits {
6658         u8         status[0x8];
6659         u8         reserved_at_8[0x18];
6660
6661         u8         syndrome[0x20];
6662
6663         u8         reserved_at_40[0x8];
6664         u8         qpn[0x18];
6665
6666         u8         reserved_at_60[0x20];
6667 };
6668
6669 struct mlx5_ifc_create_qp_in_bits {
6670         u8         opcode[0x10];
6671         u8         reserved_at_10[0x10];
6672
6673         u8         reserved_at_20[0x10];
6674         u8         op_mod[0x10];
6675
6676         u8         reserved_at_40[0x40];
6677
6678         u8         opt_param_mask[0x20];
6679
6680         u8         reserved_at_a0[0x20];
6681
6682         struct mlx5_ifc_qpc_bits qpc;
6683
6684         u8         reserved_at_800[0x80];
6685
6686         u8         pas[0][0x40];
6687 };
6688
6689 struct mlx5_ifc_create_psv_out_bits {
6690         u8         status[0x8];
6691         u8         reserved_at_8[0x18];
6692
6693         u8         syndrome[0x20];
6694
6695         u8         reserved_at_40[0x40];
6696
6697         u8         reserved_at_80[0x8];
6698         u8         psv0_index[0x18];
6699
6700         u8         reserved_at_a0[0x8];
6701         u8         psv1_index[0x18];
6702
6703         u8         reserved_at_c0[0x8];
6704         u8         psv2_index[0x18];
6705
6706         u8         reserved_at_e0[0x8];
6707         u8         psv3_index[0x18];
6708 };
6709
6710 struct mlx5_ifc_create_psv_in_bits {
6711         u8         opcode[0x10];
6712         u8         reserved_at_10[0x10];
6713
6714         u8         reserved_at_20[0x10];
6715         u8         op_mod[0x10];
6716
6717         u8         num_psv[0x4];
6718         u8         reserved_at_44[0x4];
6719         u8         pd[0x18];
6720
6721         u8         reserved_at_60[0x20];
6722 };
6723
6724 struct mlx5_ifc_create_mkey_out_bits {
6725         u8         status[0x8];
6726         u8         reserved_at_8[0x18];
6727
6728         u8         syndrome[0x20];
6729
6730         u8         reserved_at_40[0x8];
6731         u8         mkey_index[0x18];
6732
6733         u8         reserved_at_60[0x20];
6734 };
6735
6736 struct mlx5_ifc_create_mkey_in_bits {
6737         u8         opcode[0x10];
6738         u8         reserved_at_10[0x10];
6739
6740         u8         reserved_at_20[0x10];
6741         u8         op_mod[0x10];
6742
6743         u8         reserved_at_40[0x20];
6744
6745         u8         pg_access[0x1];
6746         u8         reserved_at_61[0x1f];
6747
6748         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6749
6750         u8         reserved_at_280[0x80];
6751
6752         u8         translations_octword_actual_size[0x20];
6753
6754         u8         reserved_at_320[0x560];
6755
6756         u8         klm_pas_mtt[0][0x20];
6757 };
6758
6759 struct mlx5_ifc_create_flow_table_out_bits {
6760         u8         status[0x8];
6761         u8         reserved_at_8[0x18];
6762
6763         u8         syndrome[0x20];
6764
6765         u8         reserved_at_40[0x8];
6766         u8         table_id[0x18];
6767
6768         u8         reserved_at_60[0x20];
6769 };
6770
6771 struct mlx5_ifc_flow_table_context_bits {
6772         u8         encap_en[0x1];
6773         u8         decap_en[0x1];
6774         u8         reserved_at_2[0x2];
6775         u8         table_miss_action[0x4];
6776         u8         level[0x8];
6777         u8         reserved_at_10[0x8];
6778         u8         log_size[0x8];
6779
6780         u8         reserved_at_20[0x8];
6781         u8         table_miss_id[0x18];
6782
6783         u8         reserved_at_40[0x8];
6784         u8         lag_master_next_table_id[0x18];
6785
6786         u8         reserved_at_60[0xe0];
6787 };
6788
6789 struct mlx5_ifc_create_flow_table_in_bits {
6790         u8         opcode[0x10];
6791         u8         reserved_at_10[0x10];
6792
6793         u8         reserved_at_20[0x10];
6794         u8         op_mod[0x10];
6795
6796         u8         other_vport[0x1];
6797         u8         reserved_at_41[0xf];
6798         u8         vport_number[0x10];
6799
6800         u8         reserved_at_60[0x20];
6801
6802         u8         table_type[0x8];
6803         u8         reserved_at_88[0x18];
6804
6805         u8         reserved_at_a0[0x20];
6806
6807         struct mlx5_ifc_flow_table_context_bits flow_table_context;
6808 };
6809
6810 struct mlx5_ifc_create_flow_group_out_bits {
6811         u8         status[0x8];
6812         u8         reserved_at_8[0x18];
6813
6814         u8         syndrome[0x20];
6815
6816         u8         reserved_at_40[0x8];
6817         u8         group_id[0x18];
6818
6819         u8         reserved_at_60[0x20];
6820 };
6821
6822 enum {
6823         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6824         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6825         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6826 };
6827
6828 struct mlx5_ifc_create_flow_group_in_bits {
6829         u8         opcode[0x10];
6830         u8         reserved_at_10[0x10];
6831
6832         u8         reserved_at_20[0x10];
6833         u8         op_mod[0x10];
6834
6835         u8         other_vport[0x1];
6836         u8         reserved_at_41[0xf];
6837         u8         vport_number[0x10];
6838
6839         u8         reserved_at_60[0x20];
6840
6841         u8         table_type[0x8];
6842         u8         reserved_at_88[0x18];
6843
6844         u8         reserved_at_a0[0x8];
6845         u8         table_id[0x18];
6846
6847         u8         reserved_at_c0[0x20];
6848
6849         u8         start_flow_index[0x20];
6850
6851         u8         reserved_at_100[0x20];
6852
6853         u8         end_flow_index[0x20];
6854
6855         u8         reserved_at_140[0xa0];
6856
6857         u8         reserved_at_1e0[0x18];
6858         u8         match_criteria_enable[0x8];
6859
6860         struct mlx5_ifc_fte_match_param_bits match_criteria;
6861
6862         u8         reserved_at_1200[0xe00];
6863 };
6864
6865 struct mlx5_ifc_create_eq_out_bits {
6866         u8         status[0x8];
6867         u8         reserved_at_8[0x18];
6868
6869         u8         syndrome[0x20];
6870
6871         u8         reserved_at_40[0x18];
6872         u8         eq_number[0x8];
6873
6874         u8         reserved_at_60[0x20];
6875 };
6876
6877 struct mlx5_ifc_create_eq_in_bits {
6878         u8         opcode[0x10];
6879         u8         reserved_at_10[0x10];
6880
6881         u8         reserved_at_20[0x10];
6882         u8         op_mod[0x10];
6883
6884         u8         reserved_at_40[0x40];
6885
6886         struct mlx5_ifc_eqc_bits eq_context_entry;
6887
6888         u8         reserved_at_280[0x40];
6889
6890         u8         event_bitmask[0x40];
6891
6892         u8         reserved_at_300[0x580];
6893
6894         u8         pas[0][0x40];
6895 };
6896
6897 struct mlx5_ifc_create_dct_out_bits {
6898         u8         status[0x8];
6899         u8         reserved_at_8[0x18];
6900
6901         u8         syndrome[0x20];
6902
6903         u8         reserved_at_40[0x8];
6904         u8         dctn[0x18];
6905
6906         u8         reserved_at_60[0x20];
6907 };
6908
6909 struct mlx5_ifc_create_dct_in_bits {
6910         u8         opcode[0x10];
6911         u8         reserved_at_10[0x10];
6912
6913         u8         reserved_at_20[0x10];
6914         u8         op_mod[0x10];
6915
6916         u8         reserved_at_40[0x40];
6917
6918         struct mlx5_ifc_dctc_bits dct_context_entry;
6919
6920         u8         reserved_at_280[0x180];
6921 };
6922
6923 struct mlx5_ifc_create_cq_out_bits {
6924         u8         status[0x8];
6925         u8         reserved_at_8[0x18];
6926
6927         u8         syndrome[0x20];
6928
6929         u8         reserved_at_40[0x8];
6930         u8         cqn[0x18];
6931
6932         u8         reserved_at_60[0x20];
6933 };
6934
6935 struct mlx5_ifc_create_cq_in_bits {
6936         u8         opcode[0x10];
6937         u8         reserved_at_10[0x10];
6938
6939         u8         reserved_at_20[0x10];
6940         u8         op_mod[0x10];
6941
6942         u8         reserved_at_40[0x40];
6943
6944         struct mlx5_ifc_cqc_bits cq_context;
6945
6946         u8         reserved_at_280[0x600];
6947
6948         u8         pas[0][0x40];
6949 };
6950
6951 struct mlx5_ifc_config_int_moderation_out_bits {
6952         u8         status[0x8];
6953         u8         reserved_at_8[0x18];
6954
6955         u8         syndrome[0x20];
6956
6957         u8         reserved_at_40[0x4];
6958         u8         min_delay[0xc];
6959         u8         int_vector[0x10];
6960
6961         u8         reserved_at_60[0x20];
6962 };
6963
6964 enum {
6965         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
6966         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
6967 };
6968
6969 struct mlx5_ifc_config_int_moderation_in_bits {
6970         u8         opcode[0x10];
6971         u8         reserved_at_10[0x10];
6972
6973         u8         reserved_at_20[0x10];
6974         u8         op_mod[0x10];
6975
6976         u8         reserved_at_40[0x4];
6977         u8         min_delay[0xc];
6978         u8         int_vector[0x10];
6979
6980         u8         reserved_at_60[0x20];
6981 };
6982
6983 struct mlx5_ifc_attach_to_mcg_out_bits {
6984         u8         status[0x8];
6985         u8         reserved_at_8[0x18];
6986
6987         u8         syndrome[0x20];
6988
6989         u8         reserved_at_40[0x40];
6990 };
6991
6992 struct mlx5_ifc_attach_to_mcg_in_bits {
6993         u8         opcode[0x10];
6994         u8         reserved_at_10[0x10];
6995
6996         u8         reserved_at_20[0x10];
6997         u8         op_mod[0x10];
6998
6999         u8         reserved_at_40[0x8];
7000         u8         qpn[0x18];
7001
7002         u8         reserved_at_60[0x20];
7003
7004         u8         multicast_gid[16][0x8];
7005 };
7006
7007 struct mlx5_ifc_arm_xrq_out_bits {
7008         u8         status[0x8];
7009         u8         reserved_at_8[0x18];
7010
7011         u8         syndrome[0x20];
7012
7013         u8         reserved_at_40[0x40];
7014 };
7015
7016 struct mlx5_ifc_arm_xrq_in_bits {
7017         u8         opcode[0x10];
7018         u8         reserved_at_10[0x10];
7019
7020         u8         reserved_at_20[0x10];
7021         u8         op_mod[0x10];
7022
7023         u8         reserved_at_40[0x8];
7024         u8         xrqn[0x18];
7025
7026         u8         reserved_at_60[0x10];
7027         u8         lwm[0x10];
7028 };
7029
7030 struct mlx5_ifc_arm_xrc_srq_out_bits {
7031         u8         status[0x8];
7032         u8         reserved_at_8[0x18];
7033
7034         u8         syndrome[0x20];
7035
7036         u8         reserved_at_40[0x40];
7037 };
7038
7039 enum {
7040         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7041 };
7042
7043 struct mlx5_ifc_arm_xrc_srq_in_bits {
7044         u8         opcode[0x10];
7045         u8         reserved_at_10[0x10];
7046
7047         u8         reserved_at_20[0x10];
7048         u8         op_mod[0x10];
7049
7050         u8         reserved_at_40[0x8];
7051         u8         xrc_srqn[0x18];
7052
7053         u8         reserved_at_60[0x10];
7054         u8         lwm[0x10];
7055 };
7056
7057 struct mlx5_ifc_arm_rq_out_bits {
7058         u8         status[0x8];
7059         u8         reserved_at_8[0x18];
7060
7061         u8         syndrome[0x20];
7062
7063         u8         reserved_at_40[0x40];
7064 };
7065
7066 enum {
7067         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7068         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7069 };
7070
7071 struct mlx5_ifc_arm_rq_in_bits {
7072         u8         opcode[0x10];
7073         u8         reserved_at_10[0x10];
7074
7075         u8         reserved_at_20[0x10];
7076         u8         op_mod[0x10];
7077
7078         u8         reserved_at_40[0x8];
7079         u8         srq_number[0x18];
7080
7081         u8         reserved_at_60[0x10];
7082         u8         lwm[0x10];
7083 };
7084
7085 struct mlx5_ifc_arm_dct_out_bits {
7086         u8         status[0x8];
7087         u8         reserved_at_8[0x18];
7088
7089         u8         syndrome[0x20];
7090
7091         u8         reserved_at_40[0x40];
7092 };
7093
7094 struct mlx5_ifc_arm_dct_in_bits {
7095         u8         opcode[0x10];
7096         u8         reserved_at_10[0x10];
7097
7098         u8         reserved_at_20[0x10];
7099         u8         op_mod[0x10];
7100
7101         u8         reserved_at_40[0x8];
7102         u8         dct_number[0x18];
7103
7104         u8         reserved_at_60[0x20];
7105 };
7106
7107 struct mlx5_ifc_alloc_xrcd_out_bits {
7108         u8         status[0x8];
7109         u8         reserved_at_8[0x18];
7110
7111         u8         syndrome[0x20];
7112
7113         u8         reserved_at_40[0x8];
7114         u8         xrcd[0x18];
7115
7116         u8         reserved_at_60[0x20];
7117 };
7118
7119 struct mlx5_ifc_alloc_xrcd_in_bits {
7120         u8         opcode[0x10];
7121         u8         reserved_at_10[0x10];
7122
7123         u8         reserved_at_20[0x10];
7124         u8         op_mod[0x10];
7125
7126         u8         reserved_at_40[0x40];
7127 };
7128
7129 struct mlx5_ifc_alloc_uar_out_bits {
7130         u8         status[0x8];
7131         u8         reserved_at_8[0x18];
7132
7133         u8         syndrome[0x20];
7134
7135         u8         reserved_at_40[0x8];
7136         u8         uar[0x18];
7137
7138         u8         reserved_at_60[0x20];
7139 };
7140
7141 struct mlx5_ifc_alloc_uar_in_bits {
7142         u8         opcode[0x10];
7143         u8         reserved_at_10[0x10];
7144
7145         u8         reserved_at_20[0x10];
7146         u8         op_mod[0x10];
7147
7148         u8         reserved_at_40[0x40];
7149 };
7150
7151 struct mlx5_ifc_alloc_transport_domain_out_bits {
7152         u8         status[0x8];
7153         u8         reserved_at_8[0x18];
7154
7155         u8         syndrome[0x20];
7156
7157         u8         reserved_at_40[0x8];
7158         u8         transport_domain[0x18];
7159
7160         u8         reserved_at_60[0x20];
7161 };
7162
7163 struct mlx5_ifc_alloc_transport_domain_in_bits {
7164         u8         opcode[0x10];
7165         u8         reserved_at_10[0x10];
7166
7167         u8         reserved_at_20[0x10];
7168         u8         op_mod[0x10];
7169
7170         u8         reserved_at_40[0x40];
7171 };
7172
7173 struct mlx5_ifc_alloc_q_counter_out_bits {
7174         u8         status[0x8];
7175         u8         reserved_at_8[0x18];
7176
7177         u8         syndrome[0x20];
7178
7179         u8         reserved_at_40[0x18];
7180         u8         counter_set_id[0x8];
7181
7182         u8         reserved_at_60[0x20];
7183 };
7184
7185 struct mlx5_ifc_alloc_q_counter_in_bits {
7186         u8         opcode[0x10];
7187         u8         reserved_at_10[0x10];
7188
7189         u8         reserved_at_20[0x10];
7190         u8         op_mod[0x10];
7191
7192         u8         reserved_at_40[0x40];
7193 };
7194
7195 struct mlx5_ifc_alloc_pd_out_bits {
7196         u8         status[0x8];
7197         u8         reserved_at_8[0x18];
7198
7199         u8         syndrome[0x20];
7200
7201         u8         reserved_at_40[0x8];
7202         u8         pd[0x18];
7203
7204         u8         reserved_at_60[0x20];
7205 };
7206
7207 struct mlx5_ifc_alloc_pd_in_bits {
7208         u8         opcode[0x10];
7209         u8         reserved_at_10[0x10];
7210
7211         u8         reserved_at_20[0x10];
7212         u8         op_mod[0x10];
7213
7214         u8         reserved_at_40[0x40];
7215 };
7216
7217 struct mlx5_ifc_alloc_flow_counter_out_bits {
7218         u8         status[0x8];
7219         u8         reserved_at_8[0x18];
7220
7221         u8         syndrome[0x20];
7222
7223         u8         flow_counter_id[0x20];
7224
7225         u8         reserved_at_60[0x20];
7226 };
7227
7228 struct mlx5_ifc_alloc_flow_counter_in_bits {
7229         u8         opcode[0x10];
7230         u8         reserved_at_10[0x10];
7231
7232         u8         reserved_at_20[0x10];
7233         u8         op_mod[0x10];
7234
7235         u8         reserved_at_40[0x40];
7236 };
7237
7238 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7239         u8         status[0x8];
7240         u8         reserved_at_8[0x18];
7241
7242         u8         syndrome[0x20];
7243
7244         u8         reserved_at_40[0x40];
7245 };
7246
7247 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7248         u8         opcode[0x10];
7249         u8         reserved_at_10[0x10];
7250
7251         u8         reserved_at_20[0x10];
7252         u8         op_mod[0x10];
7253
7254         u8         reserved_at_40[0x20];
7255
7256         u8         reserved_at_60[0x10];
7257         u8         vxlan_udp_port[0x10];
7258 };
7259
7260 struct mlx5_ifc_set_rate_limit_out_bits {
7261         u8         status[0x8];
7262         u8         reserved_at_8[0x18];
7263
7264         u8         syndrome[0x20];
7265
7266         u8         reserved_at_40[0x40];
7267 };
7268
7269 struct mlx5_ifc_set_rate_limit_in_bits {
7270         u8         opcode[0x10];
7271         u8         reserved_at_10[0x10];
7272
7273         u8         reserved_at_20[0x10];
7274         u8         op_mod[0x10];
7275
7276         u8         reserved_at_40[0x10];
7277         u8         rate_limit_index[0x10];
7278
7279         u8         reserved_at_60[0x20];
7280
7281         u8         rate_limit[0x20];
7282 };
7283
7284 struct mlx5_ifc_access_register_out_bits {
7285         u8         status[0x8];
7286         u8         reserved_at_8[0x18];
7287
7288         u8         syndrome[0x20];
7289
7290         u8         reserved_at_40[0x40];
7291
7292         u8         register_data[0][0x20];
7293 };
7294
7295 enum {
7296         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7297         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7298 };
7299
7300 struct mlx5_ifc_access_register_in_bits {
7301         u8         opcode[0x10];
7302         u8         reserved_at_10[0x10];
7303
7304         u8         reserved_at_20[0x10];
7305         u8         op_mod[0x10];
7306
7307         u8         reserved_at_40[0x10];
7308         u8         register_id[0x10];
7309
7310         u8         argument[0x20];
7311
7312         u8         register_data[0][0x20];
7313 };
7314
7315 struct mlx5_ifc_sltp_reg_bits {
7316         u8         status[0x4];
7317         u8         version[0x4];
7318         u8         local_port[0x8];
7319         u8         pnat[0x2];
7320         u8         reserved_at_12[0x2];
7321         u8         lane[0x4];
7322         u8         reserved_at_18[0x8];
7323
7324         u8         reserved_at_20[0x20];
7325
7326         u8         reserved_at_40[0x7];
7327         u8         polarity[0x1];
7328         u8         ob_tap0[0x8];
7329         u8         ob_tap1[0x8];
7330         u8         ob_tap2[0x8];
7331
7332         u8         reserved_at_60[0xc];
7333         u8         ob_preemp_mode[0x4];
7334         u8         ob_reg[0x8];
7335         u8         ob_bias[0x8];
7336
7337         u8         reserved_at_80[0x20];
7338 };
7339
7340 struct mlx5_ifc_slrg_reg_bits {
7341         u8         status[0x4];
7342         u8         version[0x4];
7343         u8         local_port[0x8];
7344         u8         pnat[0x2];
7345         u8         reserved_at_12[0x2];
7346         u8         lane[0x4];
7347         u8         reserved_at_18[0x8];
7348
7349         u8         time_to_link_up[0x10];
7350         u8         reserved_at_30[0xc];
7351         u8         grade_lane_speed[0x4];
7352
7353         u8         grade_version[0x8];
7354         u8         grade[0x18];
7355
7356         u8         reserved_at_60[0x4];
7357         u8         height_grade_type[0x4];
7358         u8         height_grade[0x18];
7359
7360         u8         height_dz[0x10];
7361         u8         height_dv[0x10];
7362
7363         u8         reserved_at_a0[0x10];
7364         u8         height_sigma[0x10];
7365
7366         u8         reserved_at_c0[0x20];
7367
7368         u8         reserved_at_e0[0x4];
7369         u8         phase_grade_type[0x4];
7370         u8         phase_grade[0x18];
7371
7372         u8         reserved_at_100[0x8];
7373         u8         phase_eo_pos[0x8];
7374         u8         reserved_at_110[0x8];
7375         u8         phase_eo_neg[0x8];
7376
7377         u8         ffe_set_tested[0x10];
7378         u8         test_errors_per_lane[0x10];
7379 };
7380
7381 struct mlx5_ifc_pvlc_reg_bits {
7382         u8         reserved_at_0[0x8];
7383         u8         local_port[0x8];
7384         u8         reserved_at_10[0x10];
7385
7386         u8         reserved_at_20[0x1c];
7387         u8         vl_hw_cap[0x4];
7388
7389         u8         reserved_at_40[0x1c];
7390         u8         vl_admin[0x4];
7391
7392         u8         reserved_at_60[0x1c];
7393         u8         vl_operational[0x4];
7394 };
7395
7396 struct mlx5_ifc_pude_reg_bits {
7397         u8         swid[0x8];
7398         u8         local_port[0x8];
7399         u8         reserved_at_10[0x4];
7400         u8         admin_status[0x4];
7401         u8         reserved_at_18[0x4];
7402         u8         oper_status[0x4];
7403
7404         u8         reserved_at_20[0x60];
7405 };
7406
7407 struct mlx5_ifc_ptys_reg_bits {
7408         u8         reserved_at_0[0x1];
7409         u8         an_disable_admin[0x1];
7410         u8         an_disable_cap[0x1];
7411         u8         reserved_at_3[0x5];
7412         u8         local_port[0x8];
7413         u8         reserved_at_10[0xd];
7414         u8         proto_mask[0x3];
7415
7416         u8         an_status[0x4];
7417         u8         reserved_at_24[0x3c];
7418
7419         u8         eth_proto_capability[0x20];
7420
7421         u8         ib_link_width_capability[0x10];
7422         u8         ib_proto_capability[0x10];
7423
7424         u8         reserved_at_a0[0x20];
7425
7426         u8         eth_proto_admin[0x20];
7427
7428         u8         ib_link_width_admin[0x10];
7429         u8         ib_proto_admin[0x10];
7430
7431         u8         reserved_at_100[0x20];
7432
7433         u8         eth_proto_oper[0x20];
7434
7435         u8         ib_link_width_oper[0x10];
7436         u8         ib_proto_oper[0x10];
7437
7438         u8         reserved_at_160[0x1c];
7439         u8         connector_type[0x4];
7440
7441         u8         eth_proto_lp_advertise[0x20];
7442
7443         u8         reserved_at_1a0[0x60];
7444 };
7445
7446 struct mlx5_ifc_mlcr_reg_bits {
7447         u8         reserved_at_0[0x8];
7448         u8         local_port[0x8];
7449         u8         reserved_at_10[0x20];
7450
7451         u8         beacon_duration[0x10];
7452         u8         reserved_at_40[0x10];
7453
7454         u8         beacon_remain[0x10];
7455 };
7456
7457 struct mlx5_ifc_ptas_reg_bits {
7458         u8         reserved_at_0[0x20];
7459
7460         u8         algorithm_options[0x10];
7461         u8         reserved_at_30[0x4];
7462         u8         repetitions_mode[0x4];
7463         u8         num_of_repetitions[0x8];
7464
7465         u8         grade_version[0x8];
7466         u8         height_grade_type[0x4];
7467         u8         phase_grade_type[0x4];
7468         u8         height_grade_weight[0x8];
7469         u8         phase_grade_weight[0x8];
7470
7471         u8         gisim_measure_bits[0x10];
7472         u8         adaptive_tap_measure_bits[0x10];
7473
7474         u8         ber_bath_high_error_threshold[0x10];
7475         u8         ber_bath_mid_error_threshold[0x10];
7476
7477         u8         ber_bath_low_error_threshold[0x10];
7478         u8         one_ratio_high_threshold[0x10];
7479
7480         u8         one_ratio_high_mid_threshold[0x10];
7481         u8         one_ratio_low_mid_threshold[0x10];
7482
7483         u8         one_ratio_low_threshold[0x10];
7484         u8         ndeo_error_threshold[0x10];
7485
7486         u8         mixer_offset_step_size[0x10];
7487         u8         reserved_at_110[0x8];
7488         u8         mix90_phase_for_voltage_bath[0x8];
7489
7490         u8         mixer_offset_start[0x10];
7491         u8         mixer_offset_end[0x10];
7492
7493         u8         reserved_at_140[0x15];
7494         u8         ber_test_time[0xb];
7495 };
7496
7497 struct mlx5_ifc_pspa_reg_bits {
7498         u8         swid[0x8];
7499         u8         local_port[0x8];
7500         u8         sub_port[0x8];
7501         u8         reserved_at_18[0x8];
7502
7503         u8         reserved_at_20[0x20];
7504 };
7505
7506 struct mlx5_ifc_pqdr_reg_bits {
7507         u8         reserved_at_0[0x8];
7508         u8         local_port[0x8];
7509         u8         reserved_at_10[0x5];
7510         u8         prio[0x3];
7511         u8         reserved_at_18[0x6];
7512         u8         mode[0x2];
7513
7514         u8         reserved_at_20[0x20];
7515
7516         u8         reserved_at_40[0x10];
7517         u8         min_threshold[0x10];
7518
7519         u8         reserved_at_60[0x10];
7520         u8         max_threshold[0x10];
7521
7522         u8         reserved_at_80[0x10];
7523         u8         mark_probability_denominator[0x10];
7524
7525         u8         reserved_at_a0[0x60];
7526 };
7527
7528 struct mlx5_ifc_ppsc_reg_bits {
7529         u8         reserved_at_0[0x8];
7530         u8         local_port[0x8];
7531         u8         reserved_at_10[0x10];
7532
7533         u8         reserved_at_20[0x60];
7534
7535         u8         reserved_at_80[0x1c];
7536         u8         wrps_admin[0x4];
7537
7538         u8         reserved_at_a0[0x1c];
7539         u8         wrps_status[0x4];
7540
7541         u8         reserved_at_c0[0x8];
7542         u8         up_threshold[0x8];
7543         u8         reserved_at_d0[0x8];
7544         u8         down_threshold[0x8];
7545
7546         u8         reserved_at_e0[0x20];
7547
7548         u8         reserved_at_100[0x1c];
7549         u8         srps_admin[0x4];
7550
7551         u8         reserved_at_120[0x1c];
7552         u8         srps_status[0x4];
7553
7554         u8         reserved_at_140[0x40];
7555 };
7556
7557 struct mlx5_ifc_pplr_reg_bits {
7558         u8         reserved_at_0[0x8];
7559         u8         local_port[0x8];
7560         u8         reserved_at_10[0x10];
7561
7562         u8         reserved_at_20[0x8];
7563         u8         lb_cap[0x8];
7564         u8         reserved_at_30[0x8];
7565         u8         lb_en[0x8];
7566 };
7567
7568 struct mlx5_ifc_pplm_reg_bits {
7569         u8         reserved_at_0[0x8];
7570         u8         local_port[0x8];
7571         u8         reserved_at_10[0x10];
7572
7573         u8         reserved_at_20[0x20];
7574
7575         u8         port_profile_mode[0x8];
7576         u8         static_port_profile[0x8];
7577         u8         active_port_profile[0x8];
7578         u8         reserved_at_58[0x8];
7579
7580         u8         retransmission_active[0x8];
7581         u8         fec_mode_active[0x18];
7582
7583         u8         reserved_at_80[0x20];
7584 };
7585
7586 struct mlx5_ifc_ppcnt_reg_bits {
7587         u8         swid[0x8];
7588         u8         local_port[0x8];
7589         u8         pnat[0x2];
7590         u8         reserved_at_12[0x8];
7591         u8         grp[0x6];
7592
7593         u8         clr[0x1];
7594         u8         reserved_at_21[0x1c];
7595         u8         prio_tc[0x3];
7596
7597         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7598 };
7599
7600 struct mlx5_ifc_mpcnt_reg_bits {
7601         u8         reserved_at_0[0x8];
7602         u8         pcie_index[0x8];
7603         u8         reserved_at_10[0xa];
7604         u8         grp[0x6];
7605
7606         u8         clr[0x1];
7607         u8         reserved_at_21[0x1f];
7608
7609         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7610 };
7611
7612 struct mlx5_ifc_ppad_reg_bits {
7613         u8         reserved_at_0[0x3];
7614         u8         single_mac[0x1];
7615         u8         reserved_at_4[0x4];
7616         u8         local_port[0x8];
7617         u8         mac_47_32[0x10];
7618
7619         u8         mac_31_0[0x20];
7620
7621         u8         reserved_at_40[0x40];
7622 };
7623
7624 struct mlx5_ifc_pmtu_reg_bits {
7625         u8         reserved_at_0[0x8];
7626         u8         local_port[0x8];
7627         u8         reserved_at_10[0x10];
7628
7629         u8         max_mtu[0x10];
7630         u8         reserved_at_30[0x10];
7631
7632         u8         admin_mtu[0x10];
7633         u8         reserved_at_50[0x10];
7634
7635         u8         oper_mtu[0x10];
7636         u8         reserved_at_70[0x10];
7637 };
7638
7639 struct mlx5_ifc_pmpr_reg_bits {
7640         u8         reserved_at_0[0x8];
7641         u8         module[0x8];
7642         u8         reserved_at_10[0x10];
7643
7644         u8         reserved_at_20[0x18];
7645         u8         attenuation_5g[0x8];
7646
7647         u8         reserved_at_40[0x18];
7648         u8         attenuation_7g[0x8];
7649
7650         u8         reserved_at_60[0x18];
7651         u8         attenuation_12g[0x8];
7652 };
7653
7654 struct mlx5_ifc_pmpe_reg_bits {
7655         u8         reserved_at_0[0x8];
7656         u8         module[0x8];
7657         u8         reserved_at_10[0xc];
7658         u8         module_status[0x4];
7659
7660         u8         reserved_at_20[0x60];
7661 };
7662
7663 struct mlx5_ifc_pmpc_reg_bits {
7664         u8         module_state_updated[32][0x8];
7665 };
7666
7667 struct mlx5_ifc_pmlpn_reg_bits {
7668         u8         reserved_at_0[0x4];
7669         u8         mlpn_status[0x4];
7670         u8         local_port[0x8];
7671         u8         reserved_at_10[0x10];
7672
7673         u8         e[0x1];
7674         u8         reserved_at_21[0x1f];
7675 };
7676
7677 struct mlx5_ifc_pmlp_reg_bits {
7678         u8         rxtx[0x1];
7679         u8         reserved_at_1[0x7];
7680         u8         local_port[0x8];
7681         u8         reserved_at_10[0x8];
7682         u8         width[0x8];
7683
7684         u8         lane0_module_mapping[0x20];
7685
7686         u8         lane1_module_mapping[0x20];
7687
7688         u8         lane2_module_mapping[0x20];
7689
7690         u8         lane3_module_mapping[0x20];
7691
7692         u8         reserved_at_a0[0x160];
7693 };
7694
7695 struct mlx5_ifc_pmaos_reg_bits {
7696         u8         reserved_at_0[0x8];
7697         u8         module[0x8];
7698         u8         reserved_at_10[0x4];
7699         u8         admin_status[0x4];
7700         u8         reserved_at_18[0x4];
7701         u8         oper_status[0x4];
7702
7703         u8         ase[0x1];
7704         u8         ee[0x1];
7705         u8         reserved_at_22[0x1c];
7706         u8         e[0x2];
7707
7708         u8         reserved_at_40[0x40];
7709 };
7710
7711 struct mlx5_ifc_plpc_reg_bits {
7712         u8         reserved_at_0[0x4];
7713         u8         profile_id[0xc];
7714         u8         reserved_at_10[0x4];
7715         u8         proto_mask[0x4];
7716         u8         reserved_at_18[0x8];
7717
7718         u8         reserved_at_20[0x10];
7719         u8         lane_speed[0x10];
7720
7721         u8         reserved_at_40[0x17];
7722         u8         lpbf[0x1];
7723         u8         fec_mode_policy[0x8];
7724
7725         u8         retransmission_capability[0x8];
7726         u8         fec_mode_capability[0x18];
7727
7728         u8         retransmission_support_admin[0x8];
7729         u8         fec_mode_support_admin[0x18];
7730
7731         u8         retransmission_request_admin[0x8];
7732         u8         fec_mode_request_admin[0x18];
7733
7734         u8         reserved_at_c0[0x80];
7735 };
7736
7737 struct mlx5_ifc_plib_reg_bits {
7738         u8         reserved_at_0[0x8];
7739         u8         local_port[0x8];
7740         u8         reserved_at_10[0x8];
7741         u8         ib_port[0x8];
7742
7743         u8         reserved_at_20[0x60];
7744 };
7745
7746 struct mlx5_ifc_plbf_reg_bits {
7747         u8         reserved_at_0[0x8];
7748         u8         local_port[0x8];
7749         u8         reserved_at_10[0xd];
7750         u8         lbf_mode[0x3];
7751
7752         u8         reserved_at_20[0x20];
7753 };
7754
7755 struct mlx5_ifc_pipg_reg_bits {
7756         u8         reserved_at_0[0x8];
7757         u8         local_port[0x8];
7758         u8         reserved_at_10[0x10];
7759
7760         u8         dic[0x1];
7761         u8         reserved_at_21[0x19];
7762         u8         ipg[0x4];
7763         u8         reserved_at_3e[0x2];
7764 };
7765
7766 struct mlx5_ifc_pifr_reg_bits {
7767         u8         reserved_at_0[0x8];
7768         u8         local_port[0x8];
7769         u8         reserved_at_10[0x10];
7770
7771         u8         reserved_at_20[0xe0];
7772
7773         u8         port_filter[8][0x20];
7774
7775         u8         port_filter_update_en[8][0x20];
7776 };
7777
7778 struct mlx5_ifc_pfcc_reg_bits {
7779         u8         reserved_at_0[0x8];
7780         u8         local_port[0x8];
7781         u8         reserved_at_10[0x10];
7782
7783         u8         ppan[0x4];
7784         u8         reserved_at_24[0x4];
7785         u8         prio_mask_tx[0x8];
7786         u8         reserved_at_30[0x8];
7787         u8         prio_mask_rx[0x8];
7788
7789         u8         pptx[0x1];
7790         u8         aptx[0x1];
7791         u8         reserved_at_42[0x6];
7792         u8         pfctx[0x8];
7793         u8         reserved_at_50[0x10];
7794
7795         u8         pprx[0x1];
7796         u8         aprx[0x1];
7797         u8         reserved_at_62[0x6];
7798         u8         pfcrx[0x8];
7799         u8         reserved_at_70[0x10];
7800
7801         u8         reserved_at_80[0x80];
7802 };
7803
7804 struct mlx5_ifc_pelc_reg_bits {
7805         u8         op[0x4];
7806         u8         reserved_at_4[0x4];
7807         u8         local_port[0x8];
7808         u8         reserved_at_10[0x10];
7809
7810         u8         op_admin[0x8];
7811         u8         op_capability[0x8];
7812         u8         op_request[0x8];
7813         u8         op_active[0x8];
7814
7815         u8         admin[0x40];
7816
7817         u8         capability[0x40];
7818
7819         u8         request[0x40];
7820
7821         u8         active[0x40];
7822
7823         u8         reserved_at_140[0x80];
7824 };
7825
7826 struct mlx5_ifc_peir_reg_bits {
7827         u8         reserved_at_0[0x8];
7828         u8         local_port[0x8];
7829         u8         reserved_at_10[0x10];
7830
7831         u8         reserved_at_20[0xc];
7832         u8         error_count[0x4];
7833         u8         reserved_at_30[0x10];
7834
7835         u8         reserved_at_40[0xc];
7836         u8         lane[0x4];
7837         u8         reserved_at_50[0x8];
7838         u8         error_type[0x8];
7839 };
7840
7841 struct mlx5_ifc_pcam_enhanced_features_bits {
7842         u8         reserved_at_0[0x7b];
7843
7844         u8         rx_buffer_fullness_counters[0x1];
7845         u8         ptys_connector_type[0x1];
7846         u8         reserved_at_7d[0x1];
7847         u8         ppcnt_discard_group[0x1];
7848         u8         ppcnt_statistical_group[0x1];
7849 };
7850
7851 struct mlx5_ifc_pcam_reg_bits {
7852         u8         reserved_at_0[0x8];
7853         u8         feature_group[0x8];
7854         u8         reserved_at_10[0x8];
7855         u8         access_reg_group[0x8];
7856
7857         u8         reserved_at_20[0x20];
7858
7859         union {
7860                 u8         reserved_at_0[0x80];
7861         } port_access_reg_cap_mask;
7862
7863         u8         reserved_at_c0[0x80];
7864
7865         union {
7866                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7867                 u8         reserved_at_0[0x80];
7868         } feature_cap_mask;
7869
7870         u8         reserved_at_1c0[0xc0];
7871 };
7872
7873 struct mlx5_ifc_mcam_enhanced_features_bits {
7874         u8         reserved_at_0[0x7b];
7875         u8         pcie_outbound_stalled[0x1];
7876         u8         tx_overflow_buffer_pkt[0x1];
7877         u8         mtpps_enh_out_per_adj[0x1];
7878         u8         mtpps_fs[0x1];
7879         u8         pcie_performance_group[0x1];
7880 };
7881
7882 struct mlx5_ifc_mcam_access_reg_bits {
7883         u8         reserved_at_0[0x1c];
7884         u8         mcda[0x1];
7885         u8         mcc[0x1];
7886         u8         mcqi[0x1];
7887         u8         reserved_at_1f[0x1];
7888
7889         u8         regs_95_to_64[0x20];
7890         u8         regs_63_to_32[0x20];
7891         u8         regs_31_to_0[0x20];
7892 };
7893
7894 struct mlx5_ifc_mcam_reg_bits {
7895         u8         reserved_at_0[0x8];
7896         u8         feature_group[0x8];
7897         u8         reserved_at_10[0x8];
7898         u8         access_reg_group[0x8];
7899
7900         u8         reserved_at_20[0x20];
7901
7902         union {
7903                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
7904                 u8         reserved_at_0[0x80];
7905         } mng_access_reg_cap_mask;
7906
7907         u8         reserved_at_c0[0x80];
7908
7909         union {
7910                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7911                 u8         reserved_at_0[0x80];
7912         } mng_feature_cap_mask;
7913
7914         u8         reserved_at_1c0[0x80];
7915 };
7916
7917 struct mlx5_ifc_qcam_access_reg_cap_mask {
7918         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
7919         u8         qpdpm[0x1];
7920         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
7921         u8         qdpm[0x1];
7922         u8         qpts[0x1];
7923         u8         qcap[0x1];
7924         u8         qcam_access_reg_cap_mask_0[0x1];
7925 };
7926
7927 struct mlx5_ifc_qcam_qos_feature_cap_mask {
7928         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
7929         u8         qpts_trust_both[0x1];
7930 };
7931
7932 struct mlx5_ifc_qcam_reg_bits {
7933         u8         reserved_at_0[0x8];
7934         u8         feature_group[0x8];
7935         u8         reserved_at_10[0x8];
7936         u8         access_reg_group[0x8];
7937         u8         reserved_at_20[0x20];
7938
7939         union {
7940                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
7941                 u8  reserved_at_0[0x80];
7942         } qos_access_reg_cap_mask;
7943
7944         u8         reserved_at_c0[0x80];
7945
7946         union {
7947                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
7948                 u8  reserved_at_0[0x80];
7949         } qos_feature_cap_mask;
7950
7951         u8         reserved_at_1c0[0x80];
7952 };
7953
7954 struct mlx5_ifc_pcap_reg_bits {
7955         u8         reserved_at_0[0x8];
7956         u8         local_port[0x8];
7957         u8         reserved_at_10[0x10];
7958
7959         u8         port_capability_mask[4][0x20];
7960 };
7961
7962 struct mlx5_ifc_paos_reg_bits {
7963         u8         swid[0x8];
7964         u8         local_port[0x8];
7965         u8         reserved_at_10[0x4];
7966         u8         admin_status[0x4];
7967         u8         reserved_at_18[0x4];
7968         u8         oper_status[0x4];
7969
7970         u8         ase[0x1];
7971         u8         ee[0x1];
7972         u8         reserved_at_22[0x1c];
7973         u8         e[0x2];
7974
7975         u8         reserved_at_40[0x40];
7976 };
7977
7978 struct mlx5_ifc_pamp_reg_bits {
7979         u8         reserved_at_0[0x8];
7980         u8         opamp_group[0x8];
7981         u8         reserved_at_10[0xc];
7982         u8         opamp_group_type[0x4];
7983
7984         u8         start_index[0x10];
7985         u8         reserved_at_30[0x4];
7986         u8         num_of_indices[0xc];
7987
7988         u8         index_data[18][0x10];
7989 };
7990
7991 struct mlx5_ifc_pcmr_reg_bits {
7992         u8         reserved_at_0[0x8];
7993         u8         local_port[0x8];
7994         u8         reserved_at_10[0x2e];
7995         u8         fcs_cap[0x1];
7996         u8         reserved_at_3f[0x1f];
7997         u8         fcs_chk[0x1];
7998         u8         reserved_at_5f[0x1];
7999 };
8000
8001 struct mlx5_ifc_lane_2_module_mapping_bits {
8002         u8         reserved_at_0[0x6];
8003         u8         rx_lane[0x2];
8004         u8         reserved_at_8[0x6];
8005         u8         tx_lane[0x2];
8006         u8         reserved_at_10[0x8];
8007         u8         module[0x8];
8008 };
8009
8010 struct mlx5_ifc_bufferx_reg_bits {
8011         u8         reserved_at_0[0x6];
8012         u8         lossy[0x1];
8013         u8         epsb[0x1];
8014         u8         reserved_at_8[0xc];
8015         u8         size[0xc];
8016
8017         u8         xoff_threshold[0x10];
8018         u8         xon_threshold[0x10];
8019 };
8020
8021 struct mlx5_ifc_set_node_in_bits {
8022         u8         node_description[64][0x8];
8023 };
8024
8025 struct mlx5_ifc_register_power_settings_bits {
8026         u8         reserved_at_0[0x18];
8027         u8         power_settings_level[0x8];
8028
8029         u8         reserved_at_20[0x60];
8030 };
8031
8032 struct mlx5_ifc_register_host_endianness_bits {
8033         u8         he[0x1];
8034         u8         reserved_at_1[0x1f];
8035
8036         u8         reserved_at_20[0x60];
8037 };
8038
8039 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8040         u8         reserved_at_0[0x20];
8041
8042         u8         mkey[0x20];
8043
8044         u8         addressh_63_32[0x20];
8045
8046         u8         addressl_31_0[0x20];
8047 };
8048
8049 struct mlx5_ifc_ud_adrs_vector_bits {
8050         u8         dc_key[0x40];
8051
8052         u8         ext[0x1];
8053         u8         reserved_at_41[0x7];
8054         u8         destination_qp_dct[0x18];
8055
8056         u8         static_rate[0x4];
8057         u8         sl_eth_prio[0x4];
8058         u8         fl[0x1];
8059         u8         mlid[0x7];
8060         u8         rlid_udp_sport[0x10];
8061
8062         u8         reserved_at_80[0x20];
8063
8064         u8         rmac_47_16[0x20];
8065
8066         u8         rmac_15_0[0x10];
8067         u8         tclass[0x8];
8068         u8         hop_limit[0x8];
8069
8070         u8         reserved_at_e0[0x1];
8071         u8         grh[0x1];
8072         u8         reserved_at_e2[0x2];
8073         u8         src_addr_index[0x8];
8074         u8         flow_label[0x14];
8075
8076         u8         rgid_rip[16][0x8];
8077 };
8078
8079 struct mlx5_ifc_pages_req_event_bits {
8080         u8         reserved_at_0[0x10];
8081         u8         function_id[0x10];
8082
8083         u8         num_pages[0x20];
8084
8085         u8         reserved_at_40[0xa0];
8086 };
8087
8088 struct mlx5_ifc_eqe_bits {
8089         u8         reserved_at_0[0x8];
8090         u8         event_type[0x8];
8091         u8         reserved_at_10[0x8];
8092         u8         event_sub_type[0x8];
8093
8094         u8         reserved_at_20[0xe0];
8095
8096         union mlx5_ifc_event_auto_bits event_data;
8097
8098         u8         reserved_at_1e0[0x10];
8099         u8         signature[0x8];
8100         u8         reserved_at_1f8[0x7];
8101         u8         owner[0x1];
8102 };
8103
8104 enum {
8105         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
8106 };
8107
8108 struct mlx5_ifc_cmd_queue_entry_bits {
8109         u8         type[0x8];
8110         u8         reserved_at_8[0x18];
8111
8112         u8         input_length[0x20];
8113
8114         u8         input_mailbox_pointer_63_32[0x20];
8115
8116         u8         input_mailbox_pointer_31_9[0x17];
8117         u8         reserved_at_77[0x9];
8118
8119         u8         command_input_inline_data[16][0x8];
8120
8121         u8         command_output_inline_data[16][0x8];
8122
8123         u8         output_mailbox_pointer_63_32[0x20];
8124
8125         u8         output_mailbox_pointer_31_9[0x17];
8126         u8         reserved_at_1b7[0x9];
8127
8128         u8         output_length[0x20];
8129
8130         u8         token[0x8];
8131         u8         signature[0x8];
8132         u8         reserved_at_1f0[0x8];
8133         u8         status[0x7];
8134         u8         ownership[0x1];
8135 };
8136
8137 struct mlx5_ifc_cmd_out_bits {
8138         u8         status[0x8];
8139         u8         reserved_at_8[0x18];
8140
8141         u8         syndrome[0x20];
8142
8143         u8         command_output[0x20];
8144 };
8145
8146 struct mlx5_ifc_cmd_in_bits {
8147         u8         opcode[0x10];
8148         u8         reserved_at_10[0x10];
8149
8150         u8         reserved_at_20[0x10];
8151         u8         op_mod[0x10];
8152
8153         u8         command[0][0x20];
8154 };
8155
8156 struct mlx5_ifc_cmd_if_box_bits {
8157         u8         mailbox_data[512][0x8];
8158
8159         u8         reserved_at_1000[0x180];
8160
8161         u8         next_pointer_63_32[0x20];
8162
8163         u8         next_pointer_31_10[0x16];
8164         u8         reserved_at_11b6[0xa];
8165
8166         u8         block_number[0x20];
8167
8168         u8         reserved_at_11e0[0x8];
8169         u8         token[0x8];
8170         u8         ctrl_signature[0x8];
8171         u8         signature[0x8];
8172 };
8173
8174 struct mlx5_ifc_mtt_bits {
8175         u8         ptag_63_32[0x20];
8176
8177         u8         ptag_31_8[0x18];
8178         u8         reserved_at_38[0x6];
8179         u8         wr_en[0x1];
8180         u8         rd_en[0x1];
8181 };
8182
8183 struct mlx5_ifc_query_wol_rol_out_bits {
8184         u8         status[0x8];
8185         u8         reserved_at_8[0x18];
8186
8187         u8         syndrome[0x20];
8188
8189         u8         reserved_at_40[0x10];
8190         u8         rol_mode[0x8];
8191         u8         wol_mode[0x8];
8192
8193         u8         reserved_at_60[0x20];
8194 };
8195
8196 struct mlx5_ifc_query_wol_rol_in_bits {
8197         u8         opcode[0x10];
8198         u8         reserved_at_10[0x10];
8199
8200         u8         reserved_at_20[0x10];
8201         u8         op_mod[0x10];
8202
8203         u8         reserved_at_40[0x40];
8204 };
8205
8206 struct mlx5_ifc_set_wol_rol_out_bits {
8207         u8         status[0x8];
8208         u8         reserved_at_8[0x18];
8209
8210         u8         syndrome[0x20];
8211
8212         u8         reserved_at_40[0x40];
8213 };
8214
8215 struct mlx5_ifc_set_wol_rol_in_bits {
8216         u8         opcode[0x10];
8217         u8         reserved_at_10[0x10];
8218
8219         u8         reserved_at_20[0x10];
8220         u8         op_mod[0x10];
8221
8222         u8         rol_mode_valid[0x1];
8223         u8         wol_mode_valid[0x1];
8224         u8         reserved_at_42[0xe];
8225         u8         rol_mode[0x8];
8226         u8         wol_mode[0x8];
8227
8228         u8         reserved_at_60[0x20];
8229 };
8230
8231 enum {
8232         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8233         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8234         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8235 };
8236
8237 enum {
8238         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8239         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8240         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8241 };
8242
8243 enum {
8244         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
8245         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
8246         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
8247         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
8248         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
8249         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
8250         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
8251         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
8252         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
8253         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
8254         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
8255 };
8256
8257 struct mlx5_ifc_initial_seg_bits {
8258         u8         fw_rev_minor[0x10];
8259         u8         fw_rev_major[0x10];
8260
8261         u8         cmd_interface_rev[0x10];
8262         u8         fw_rev_subminor[0x10];
8263
8264         u8         reserved_at_40[0x40];
8265
8266         u8         cmdq_phy_addr_63_32[0x20];
8267
8268         u8         cmdq_phy_addr_31_12[0x14];
8269         u8         reserved_at_b4[0x2];
8270         u8         nic_interface[0x2];
8271         u8         log_cmdq_size[0x4];
8272         u8         log_cmdq_stride[0x4];
8273
8274         u8         command_doorbell_vector[0x20];
8275
8276         u8         reserved_at_e0[0xf00];
8277
8278         u8         initializing[0x1];
8279         u8         reserved_at_fe1[0x4];
8280         u8         nic_interface_supported[0x3];
8281         u8         reserved_at_fe8[0x18];
8282
8283         struct mlx5_ifc_health_buffer_bits health_buffer;
8284
8285         u8         no_dram_nic_offset[0x20];
8286
8287         u8         reserved_at_1220[0x6e40];
8288
8289         u8         reserved_at_8060[0x1f];
8290         u8         clear_int[0x1];
8291
8292         u8         health_syndrome[0x8];
8293         u8         health_counter[0x18];
8294
8295         u8         reserved_at_80a0[0x17fc0];
8296 };
8297
8298 struct mlx5_ifc_mtpps_reg_bits {
8299         u8         reserved_at_0[0xc];
8300         u8         cap_number_of_pps_pins[0x4];
8301         u8         reserved_at_10[0x4];
8302         u8         cap_max_num_of_pps_in_pins[0x4];
8303         u8         reserved_at_18[0x4];
8304         u8         cap_max_num_of_pps_out_pins[0x4];
8305
8306         u8         reserved_at_20[0x24];
8307         u8         cap_pin_3_mode[0x4];
8308         u8         reserved_at_48[0x4];
8309         u8         cap_pin_2_mode[0x4];
8310         u8         reserved_at_50[0x4];
8311         u8         cap_pin_1_mode[0x4];
8312         u8         reserved_at_58[0x4];
8313         u8         cap_pin_0_mode[0x4];
8314
8315         u8         reserved_at_60[0x4];
8316         u8         cap_pin_7_mode[0x4];
8317         u8         reserved_at_68[0x4];
8318         u8         cap_pin_6_mode[0x4];
8319         u8         reserved_at_70[0x4];
8320         u8         cap_pin_5_mode[0x4];
8321         u8         reserved_at_78[0x4];
8322         u8         cap_pin_4_mode[0x4];
8323
8324         u8         field_select[0x20];
8325         u8         reserved_at_a0[0x60];
8326
8327         u8         enable[0x1];
8328         u8         reserved_at_101[0xb];
8329         u8         pattern[0x4];
8330         u8         reserved_at_110[0x4];
8331         u8         pin_mode[0x4];
8332         u8         pin[0x8];
8333
8334         u8         reserved_at_120[0x20];
8335
8336         u8         time_stamp[0x40];
8337
8338         u8         out_pulse_duration[0x10];
8339         u8         out_periodic_adjustment[0x10];
8340         u8         enhanced_out_periodic_adjustment[0x20];
8341
8342         u8         reserved_at_1c0[0x20];
8343 };
8344
8345 struct mlx5_ifc_mtppse_reg_bits {
8346         u8         reserved_at_0[0x18];
8347         u8         pin[0x8];
8348         u8         event_arm[0x1];
8349         u8         reserved_at_21[0x1b];
8350         u8         event_generation_mode[0x4];
8351         u8         reserved_at_40[0x40];
8352 };
8353
8354 struct mlx5_ifc_mcqi_cap_bits {
8355         u8         supported_info_bitmask[0x20];
8356
8357         u8         component_size[0x20];
8358
8359         u8         max_component_size[0x20];
8360
8361         u8         log_mcda_word_size[0x4];
8362         u8         reserved_at_64[0xc];
8363         u8         mcda_max_write_size[0x10];
8364
8365         u8         rd_en[0x1];
8366         u8         reserved_at_81[0x1];
8367         u8         match_chip_id[0x1];
8368         u8         match_psid[0x1];
8369         u8         check_user_timestamp[0x1];
8370         u8         match_base_guid_mac[0x1];
8371         u8         reserved_at_86[0x1a];
8372 };
8373
8374 struct mlx5_ifc_mcqi_reg_bits {
8375         u8         read_pending_component[0x1];
8376         u8         reserved_at_1[0xf];
8377         u8         component_index[0x10];
8378
8379         u8         reserved_at_20[0x20];
8380
8381         u8         reserved_at_40[0x1b];
8382         u8         info_type[0x5];
8383
8384         u8         info_size[0x20];
8385
8386         u8         offset[0x20];
8387
8388         u8         reserved_at_a0[0x10];
8389         u8         data_size[0x10];
8390
8391         u8         data[0][0x20];
8392 };
8393
8394 struct mlx5_ifc_mcc_reg_bits {
8395         u8         reserved_at_0[0x4];
8396         u8         time_elapsed_since_last_cmd[0xc];
8397         u8         reserved_at_10[0x8];
8398         u8         instruction[0x8];
8399
8400         u8         reserved_at_20[0x10];
8401         u8         component_index[0x10];
8402
8403         u8         reserved_at_40[0x8];
8404         u8         update_handle[0x18];
8405
8406         u8         handle_owner_type[0x4];
8407         u8         handle_owner_host_id[0x4];
8408         u8         reserved_at_68[0x1];
8409         u8         control_progress[0x7];
8410         u8         error_code[0x8];
8411         u8         reserved_at_78[0x4];
8412         u8         control_state[0x4];
8413
8414         u8         component_size[0x20];
8415
8416         u8         reserved_at_a0[0x60];
8417 };
8418
8419 struct mlx5_ifc_mcda_reg_bits {
8420         u8         reserved_at_0[0x8];
8421         u8         update_handle[0x18];
8422
8423         u8         offset[0x20];
8424
8425         u8         reserved_at_40[0x10];
8426         u8         size[0x10];
8427
8428         u8         reserved_at_60[0x20];
8429
8430         u8         data[0][0x20];
8431 };
8432
8433 union mlx5_ifc_ports_control_registers_document_bits {
8434         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8435         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8436         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8437         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8438         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8439         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8440         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8441         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8442         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8443         struct mlx5_ifc_pamp_reg_bits pamp_reg;
8444         struct mlx5_ifc_paos_reg_bits paos_reg;
8445         struct mlx5_ifc_pcap_reg_bits pcap_reg;
8446         struct mlx5_ifc_peir_reg_bits peir_reg;
8447         struct mlx5_ifc_pelc_reg_bits pelc_reg;
8448         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8449         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8450         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8451         struct mlx5_ifc_pifr_reg_bits pifr_reg;
8452         struct mlx5_ifc_pipg_reg_bits pipg_reg;
8453         struct mlx5_ifc_plbf_reg_bits plbf_reg;
8454         struct mlx5_ifc_plib_reg_bits plib_reg;
8455         struct mlx5_ifc_plpc_reg_bits plpc_reg;
8456         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8457         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8458         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8459         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8460         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8461         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8462         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8463         struct mlx5_ifc_ppad_reg_bits ppad_reg;
8464         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8465         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8466         struct mlx5_ifc_pplm_reg_bits pplm_reg;
8467         struct mlx5_ifc_pplr_reg_bits pplr_reg;
8468         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8469         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8470         struct mlx5_ifc_pspa_reg_bits pspa_reg;
8471         struct mlx5_ifc_ptas_reg_bits ptas_reg;
8472         struct mlx5_ifc_ptys_reg_bits ptys_reg;
8473         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8474         struct mlx5_ifc_pude_reg_bits pude_reg;
8475         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8476         struct mlx5_ifc_slrg_reg_bits slrg_reg;
8477         struct mlx5_ifc_sltp_reg_bits sltp_reg;
8478         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8479         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8480         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8481         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8482         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8483         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8484         struct mlx5_ifc_mcc_reg_bits mcc_reg;
8485         struct mlx5_ifc_mcda_reg_bits mcda_reg;
8486         u8         reserved_at_0[0x60e0];
8487 };
8488
8489 union mlx5_ifc_debug_enhancements_document_bits {
8490         struct mlx5_ifc_health_buffer_bits health_buffer;
8491         u8         reserved_at_0[0x200];
8492 };
8493
8494 union mlx5_ifc_uplink_pci_interface_document_bits {
8495         struct mlx5_ifc_initial_seg_bits initial_seg;
8496         u8         reserved_at_0[0x20060];
8497 };
8498
8499 struct mlx5_ifc_set_flow_table_root_out_bits {
8500         u8         status[0x8];
8501         u8         reserved_at_8[0x18];
8502
8503         u8         syndrome[0x20];
8504
8505         u8         reserved_at_40[0x40];
8506 };
8507
8508 struct mlx5_ifc_set_flow_table_root_in_bits {
8509         u8         opcode[0x10];
8510         u8         reserved_at_10[0x10];
8511
8512         u8         reserved_at_20[0x10];
8513         u8         op_mod[0x10];
8514
8515         u8         other_vport[0x1];
8516         u8         reserved_at_41[0xf];
8517         u8         vport_number[0x10];
8518
8519         u8         reserved_at_60[0x20];
8520
8521         u8         table_type[0x8];
8522         u8         reserved_at_88[0x18];
8523
8524         u8         reserved_at_a0[0x8];
8525         u8         table_id[0x18];
8526
8527         u8         reserved_at_c0[0x8];
8528         u8         underlay_qpn[0x18];
8529         u8         reserved_at_e0[0x120];
8530 };
8531
8532 enum {
8533         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
8534         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8535 };
8536
8537 struct mlx5_ifc_modify_flow_table_out_bits {
8538         u8         status[0x8];
8539         u8         reserved_at_8[0x18];
8540
8541         u8         syndrome[0x20];
8542
8543         u8         reserved_at_40[0x40];
8544 };
8545
8546 struct mlx5_ifc_modify_flow_table_in_bits {
8547         u8         opcode[0x10];
8548         u8         reserved_at_10[0x10];
8549
8550         u8         reserved_at_20[0x10];
8551         u8         op_mod[0x10];
8552
8553         u8         other_vport[0x1];
8554         u8         reserved_at_41[0xf];
8555         u8         vport_number[0x10];
8556
8557         u8         reserved_at_60[0x10];
8558         u8         modify_field_select[0x10];
8559
8560         u8         table_type[0x8];
8561         u8         reserved_at_88[0x18];
8562
8563         u8         reserved_at_a0[0x8];
8564         u8         table_id[0x18];
8565
8566         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8567 };
8568
8569 struct mlx5_ifc_ets_tcn_config_reg_bits {
8570         u8         g[0x1];
8571         u8         b[0x1];
8572         u8         r[0x1];
8573         u8         reserved_at_3[0x9];
8574         u8         group[0x4];
8575         u8         reserved_at_10[0x9];
8576         u8         bw_allocation[0x7];
8577
8578         u8         reserved_at_20[0xc];
8579         u8         max_bw_units[0x4];
8580         u8         reserved_at_30[0x8];
8581         u8         max_bw_value[0x8];
8582 };
8583
8584 struct mlx5_ifc_ets_global_config_reg_bits {
8585         u8         reserved_at_0[0x2];
8586         u8         r[0x1];
8587         u8         reserved_at_3[0x1d];
8588
8589         u8         reserved_at_20[0xc];
8590         u8         max_bw_units[0x4];
8591         u8         reserved_at_30[0x8];
8592         u8         max_bw_value[0x8];
8593 };
8594
8595 struct mlx5_ifc_qetc_reg_bits {
8596         u8                                         reserved_at_0[0x8];
8597         u8                                         port_number[0x8];
8598         u8                                         reserved_at_10[0x30];
8599
8600         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
8601         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8602 };
8603
8604 struct mlx5_ifc_qpdpm_dscp_reg_bits {
8605         u8         e[0x1];
8606         u8         reserved_at_01[0x0b];
8607         u8         prio[0x04];
8608 };
8609
8610 struct mlx5_ifc_qpdpm_reg_bits {
8611         u8                                     reserved_at_0[0x8];
8612         u8                                     local_port[0x8];
8613         u8                                     reserved_at_10[0x10];
8614         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
8615 };
8616
8617 struct mlx5_ifc_qpts_reg_bits {
8618         u8         reserved_at_0[0x8];
8619         u8         local_port[0x8];
8620         u8         reserved_at_10[0x2d];
8621         u8         trust_state[0x3];
8622 };
8623
8624 struct mlx5_ifc_qtct_reg_bits {
8625         u8         reserved_at_0[0x8];
8626         u8         port_number[0x8];
8627         u8         reserved_at_10[0xd];
8628         u8         prio[0x3];
8629
8630         u8         reserved_at_20[0x1d];
8631         u8         tclass[0x3];
8632 };
8633
8634 struct mlx5_ifc_mcia_reg_bits {
8635         u8         l[0x1];
8636         u8         reserved_at_1[0x7];
8637         u8         module[0x8];
8638         u8         reserved_at_10[0x8];
8639         u8         status[0x8];
8640
8641         u8         i2c_device_address[0x8];
8642         u8         page_number[0x8];
8643         u8         device_address[0x10];
8644
8645         u8         reserved_at_40[0x10];
8646         u8         size[0x10];
8647
8648         u8         reserved_at_60[0x20];
8649
8650         u8         dword_0[0x20];
8651         u8         dword_1[0x20];
8652         u8         dword_2[0x20];
8653         u8         dword_3[0x20];
8654         u8         dword_4[0x20];
8655         u8         dword_5[0x20];
8656         u8         dword_6[0x20];
8657         u8         dword_7[0x20];
8658         u8         dword_8[0x20];
8659         u8         dword_9[0x20];
8660         u8         dword_10[0x20];
8661         u8         dword_11[0x20];
8662 };
8663
8664 struct mlx5_ifc_dcbx_param_bits {
8665         u8         dcbx_cee_cap[0x1];
8666         u8         dcbx_ieee_cap[0x1];
8667         u8         dcbx_standby_cap[0x1];
8668         u8         reserved_at_0[0x5];
8669         u8         port_number[0x8];
8670         u8         reserved_at_10[0xa];
8671         u8         max_application_table_size[6];
8672         u8         reserved_at_20[0x15];
8673         u8         version_oper[0x3];
8674         u8         reserved_at_38[5];
8675         u8         version_admin[0x3];
8676         u8         willing_admin[0x1];
8677         u8         reserved_at_41[0x3];
8678         u8         pfc_cap_oper[0x4];
8679         u8         reserved_at_48[0x4];
8680         u8         pfc_cap_admin[0x4];
8681         u8         reserved_at_50[0x4];
8682         u8         num_of_tc_oper[0x4];
8683         u8         reserved_at_58[0x4];
8684         u8         num_of_tc_admin[0x4];
8685         u8         remote_willing[0x1];
8686         u8         reserved_at_61[3];
8687         u8         remote_pfc_cap[4];
8688         u8         reserved_at_68[0x14];
8689         u8         remote_num_of_tc[0x4];
8690         u8         reserved_at_80[0x18];
8691         u8         error[0x8];
8692         u8         reserved_at_a0[0x160];
8693 };
8694
8695 struct mlx5_ifc_lagc_bits {
8696         u8         reserved_at_0[0x1d];
8697         u8         lag_state[0x3];
8698
8699         u8         reserved_at_20[0x14];
8700         u8         tx_remap_affinity_2[0x4];
8701         u8         reserved_at_38[0x4];
8702         u8         tx_remap_affinity_1[0x4];
8703 };
8704
8705 struct mlx5_ifc_create_lag_out_bits {
8706         u8         status[0x8];
8707         u8         reserved_at_8[0x18];
8708
8709         u8         syndrome[0x20];
8710
8711         u8         reserved_at_40[0x40];
8712 };
8713
8714 struct mlx5_ifc_create_lag_in_bits {
8715         u8         opcode[0x10];
8716         u8         reserved_at_10[0x10];
8717
8718         u8         reserved_at_20[0x10];
8719         u8         op_mod[0x10];
8720
8721         struct mlx5_ifc_lagc_bits ctx;
8722 };
8723
8724 struct mlx5_ifc_modify_lag_out_bits {
8725         u8         status[0x8];
8726         u8         reserved_at_8[0x18];
8727
8728         u8         syndrome[0x20];
8729
8730         u8         reserved_at_40[0x40];
8731 };
8732
8733 struct mlx5_ifc_modify_lag_in_bits {
8734         u8         opcode[0x10];
8735         u8         reserved_at_10[0x10];
8736
8737         u8         reserved_at_20[0x10];
8738         u8         op_mod[0x10];
8739
8740         u8         reserved_at_40[0x20];
8741         u8         field_select[0x20];
8742
8743         struct mlx5_ifc_lagc_bits ctx;
8744 };
8745
8746 struct mlx5_ifc_query_lag_out_bits {
8747         u8         status[0x8];
8748         u8         reserved_at_8[0x18];
8749
8750         u8         syndrome[0x20];
8751
8752         u8         reserved_at_40[0x40];
8753
8754         struct mlx5_ifc_lagc_bits ctx;
8755 };
8756
8757 struct mlx5_ifc_query_lag_in_bits {
8758         u8         opcode[0x10];
8759         u8         reserved_at_10[0x10];
8760
8761         u8         reserved_at_20[0x10];
8762         u8         op_mod[0x10];
8763
8764         u8         reserved_at_40[0x40];
8765 };
8766
8767 struct mlx5_ifc_destroy_lag_out_bits {
8768         u8         status[0x8];
8769         u8         reserved_at_8[0x18];
8770
8771         u8         syndrome[0x20];
8772
8773         u8         reserved_at_40[0x40];
8774 };
8775
8776 struct mlx5_ifc_destroy_lag_in_bits {
8777         u8         opcode[0x10];
8778         u8         reserved_at_10[0x10];
8779
8780         u8         reserved_at_20[0x10];
8781         u8         op_mod[0x10];
8782
8783         u8         reserved_at_40[0x40];
8784 };
8785
8786 struct mlx5_ifc_create_vport_lag_out_bits {
8787         u8         status[0x8];
8788         u8         reserved_at_8[0x18];
8789
8790         u8         syndrome[0x20];
8791
8792         u8         reserved_at_40[0x40];
8793 };
8794
8795 struct mlx5_ifc_create_vport_lag_in_bits {
8796         u8         opcode[0x10];
8797         u8         reserved_at_10[0x10];
8798
8799         u8         reserved_at_20[0x10];
8800         u8         op_mod[0x10];
8801
8802         u8         reserved_at_40[0x40];
8803 };
8804
8805 struct mlx5_ifc_destroy_vport_lag_out_bits {
8806         u8         status[0x8];
8807         u8         reserved_at_8[0x18];
8808
8809         u8         syndrome[0x20];
8810
8811         u8         reserved_at_40[0x40];
8812 };
8813
8814 struct mlx5_ifc_destroy_vport_lag_in_bits {
8815         u8         opcode[0x10];
8816         u8         reserved_at_10[0x10];
8817
8818         u8         reserved_at_20[0x10];
8819         u8         op_mod[0x10];
8820
8821         u8         reserved_at_40[0x40];
8822 };
8823
8824 #endif /* MLX5_IFC_H */