2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
71 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
72 MLX5_CMD_OP_INIT_HCA = 0x102,
73 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
74 MLX5_CMD_OP_ENABLE_HCA = 0x104,
75 MLX5_CMD_OP_DISABLE_HCA = 0x105,
76 MLX5_CMD_OP_QUERY_PAGES = 0x107,
77 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
78 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
79 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
80 MLX5_CMD_OP_SET_ISSI = 0x10b,
81 MLX5_CMD_OP_CREATE_MKEY = 0x200,
82 MLX5_CMD_OP_QUERY_MKEY = 0x201,
83 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
84 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
85 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
86 MLX5_CMD_OP_CREATE_EQ = 0x301,
87 MLX5_CMD_OP_DESTROY_EQ = 0x302,
88 MLX5_CMD_OP_QUERY_EQ = 0x303,
89 MLX5_CMD_OP_GEN_EQE = 0x304,
90 MLX5_CMD_OP_CREATE_CQ = 0x400,
91 MLX5_CMD_OP_DESTROY_CQ = 0x401,
92 MLX5_CMD_OP_QUERY_CQ = 0x402,
93 MLX5_CMD_OP_MODIFY_CQ = 0x403,
94 MLX5_CMD_OP_CREATE_QP = 0x500,
95 MLX5_CMD_OP_DESTROY_QP = 0x501,
96 MLX5_CMD_OP_RST2INIT_QP = 0x502,
97 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
98 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
99 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
100 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
101 MLX5_CMD_OP_2ERR_QP = 0x507,
102 MLX5_CMD_OP_2RST_QP = 0x50a,
103 MLX5_CMD_OP_QUERY_QP = 0x50b,
104 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
105 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
106 MLX5_CMD_OP_CREATE_PSV = 0x600,
107 MLX5_CMD_OP_DESTROY_PSV = 0x601,
108 MLX5_CMD_OP_CREATE_SRQ = 0x700,
109 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
110 MLX5_CMD_OP_QUERY_SRQ = 0x702,
111 MLX5_CMD_OP_ARM_RQ = 0x703,
112 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
113 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
114 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
115 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
116 MLX5_CMD_OP_CREATE_DCT = 0x710,
117 MLX5_CMD_OP_DESTROY_DCT = 0x711,
118 MLX5_CMD_OP_DRAIN_DCT = 0x712,
119 MLX5_CMD_OP_QUERY_DCT = 0x713,
120 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
121 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
122 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
123 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
124 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
125 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
126 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
127 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
128 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
129 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
130 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
131 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
132 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
133 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
134 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
135 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
136 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
137 MLX5_CMD_OP_ALLOC_PD = 0x800,
138 MLX5_CMD_OP_DEALLOC_PD = 0x801,
139 MLX5_CMD_OP_ALLOC_UAR = 0x802,
140 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
141 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
142 MLX5_CMD_OP_ACCESS_REG = 0x805,
143 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
144 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
145 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
146 MLX5_CMD_OP_MAD_IFC = 0x50d,
147 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
148 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
149 MLX5_CMD_OP_NOP = 0x80d,
150 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
151 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
152 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
153 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
154 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
155 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
156 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
157 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
158 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
159 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
160 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
161 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
162 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
163 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
164 MLX5_CMD_OP_CREATE_TIR = 0x900,
165 MLX5_CMD_OP_MODIFY_TIR = 0x901,
166 MLX5_CMD_OP_DESTROY_TIR = 0x902,
167 MLX5_CMD_OP_QUERY_TIR = 0x903,
168 MLX5_CMD_OP_CREATE_SQ = 0x904,
169 MLX5_CMD_OP_MODIFY_SQ = 0x905,
170 MLX5_CMD_OP_DESTROY_SQ = 0x906,
171 MLX5_CMD_OP_QUERY_SQ = 0x907,
172 MLX5_CMD_OP_CREATE_RQ = 0x908,
173 MLX5_CMD_OP_MODIFY_RQ = 0x909,
174 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
175 MLX5_CMD_OP_QUERY_RQ = 0x90b,
176 MLX5_CMD_OP_CREATE_RMP = 0x90c,
177 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
178 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
179 MLX5_CMD_OP_QUERY_RMP = 0x90f,
180 MLX5_CMD_OP_CREATE_TIS = 0x912,
181 MLX5_CMD_OP_MODIFY_TIS = 0x913,
182 MLX5_CMD_OP_DESTROY_TIS = 0x914,
183 MLX5_CMD_OP_QUERY_TIS = 0x915,
184 MLX5_CMD_OP_CREATE_RQT = 0x916,
185 MLX5_CMD_OP_MODIFY_RQT = 0x917,
186 MLX5_CMD_OP_DESTROY_RQT = 0x918,
187 MLX5_CMD_OP_QUERY_RQT = 0x919,
188 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
189 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
190 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
191 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
192 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
193 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
194 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
195 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
196 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
197 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
198 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c
201 struct mlx5_ifc_flow_table_fields_supported_bits {
204 u8 outer_ether_type[0x1];
206 u8 outer_first_prio[0x1];
207 u8 outer_first_cfi[0x1];
208 u8 outer_first_vid[0x1];
210 u8 outer_second_prio[0x1];
211 u8 outer_second_cfi[0x1];
212 u8 outer_second_vid[0x1];
217 u8 outer_ip_protocol[0x1];
218 u8 outer_ip_ecn[0x1];
219 u8 outer_ip_dscp[0x1];
220 u8 outer_udp_sport[0x1];
221 u8 outer_udp_dport[0x1];
222 u8 outer_tcp_sport[0x1];
223 u8 outer_tcp_dport[0x1];
224 u8 outer_tcp_flags[0x1];
225 u8 outer_gre_protocol[0x1];
226 u8 outer_gre_key[0x1];
227 u8 outer_vxlan_vni[0x1];
229 u8 source_eswitch_port[0x1];
233 u8 inner_ether_type[0x1];
235 u8 inner_first_prio[0x1];
236 u8 inner_first_cfi[0x1];
237 u8 inner_first_vid[0x1];
239 u8 inner_second_prio[0x1];
240 u8 inner_second_cfi[0x1];
241 u8 inner_second_vid[0x1];
246 u8 inner_ip_protocol[0x1];
247 u8 inner_ip_ecn[0x1];
248 u8 inner_ip_dscp[0x1];
249 u8 inner_udp_sport[0x1];
250 u8 inner_udp_dport[0x1];
251 u8 inner_tcp_sport[0x1];
252 u8 inner_tcp_dport[0x1];
253 u8 inner_tcp_flags[0x1];
259 struct mlx5_ifc_flow_table_prop_layout_bits {
262 u8 flow_modify_en[0x1];
264 u8 identified_miss_table_mode[0x1];
265 u8 flow_table_modify[0x1];
269 u8 log_max_ft_size[0x6];
271 u8 max_ft_level[0x8];
276 u8 log_max_ft_num[0x8];
279 u8 log_max_destination[0x8];
282 u8 log_max_flow[0x8];
286 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
288 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
291 struct mlx5_ifc_odp_per_transport_service_cap_bits {
301 struct mlx5_ifc_ipv4_layout_bits {
307 struct mlx5_ifc_ipv6_layout_bits {
311 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
312 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
313 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
317 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
347 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
349 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
352 struct mlx5_ifc_fte_match_set_misc_bits {
356 u8 source_port[0x10];
358 u8 outer_second_prio[0x3];
359 u8 outer_second_cfi[0x1];
360 u8 outer_second_vid[0xc];
361 u8 inner_second_prio[0x3];
362 u8 inner_second_cfi[0x1];
363 u8 inner_second_vid[0xc];
365 u8 outer_second_vlan_tag[0x1];
366 u8 inner_second_vlan_tag[0x1];
368 u8 gre_protocol[0x10];
379 u8 outer_ipv6_flow_label[0x14];
382 u8 inner_ipv6_flow_label[0x14];
387 struct mlx5_ifc_cmd_pas_bits {
394 struct mlx5_ifc_uint64_bits {
401 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
402 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
403 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
404 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
405 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
406 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
407 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
408 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
409 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
410 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
413 struct mlx5_ifc_ads_bits {
426 u8 src_addr_index[0x8];
435 u8 rgid_rip[16][0x8];
455 struct mlx5_ifc_flow_table_nic_cap_bits {
456 u8 reserved_0[0x200];
458 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
460 u8 reserved_1[0x200];
462 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
464 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
466 u8 reserved_2[0x200];
468 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
470 u8 reserved_3[0x7200];
473 struct mlx5_ifc_flow_table_eswitch_cap_bits {
474 u8 reserved_0[0x200];
476 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
478 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
480 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
482 u8 reserved_1[0x7800];
485 struct mlx5_ifc_e_switch_cap_bits {
486 u8 vport_svlan_strip[0x1];
487 u8 vport_cvlan_strip[0x1];
488 u8 vport_svlan_insert[0x1];
489 u8 vport_cvlan_insert_if_not_exist[0x1];
490 u8 vport_cvlan_insert_overwrite[0x1];
493 u8 reserved_1[0x7e0];
496 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
500 u8 lro_psh_flag[0x1];
501 u8 lro_time_stamp[0x1];
503 u8 self_lb_en_modifiable[0x1];
507 u8 rss_ind_tbl_cap[0x4];
509 u8 tunnel_lso_const_out_ip_id[0x1];
511 u8 tunnel_statless_gre[0x1];
512 u8 tunnel_stateless_vxlan[0x1];
517 u8 lro_min_mss_size[0x10];
519 u8 reserved_7[0x120];
521 u8 lro_timer_supported_periods[4][0x20];
523 u8 reserved_8[0x600];
526 struct mlx5_ifc_roce_cap_bits {
535 u8 roce_version[0x8];
538 u8 r_roce_dest_udp_port[0x10];
540 u8 r_roce_max_src_udp_port[0x10];
541 u8 r_roce_min_src_udp_port[0x10];
544 u8 roce_address_table_size[0x10];
546 u8 reserved_6[0x700];
550 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
551 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
552 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
553 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
554 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
555 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
556 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
557 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
558 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
562 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
563 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
564 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
565 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
566 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
567 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
568 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
569 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
570 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
573 struct mlx5_ifc_atomic_caps_bits {
576 u8 atomic_req_endianness[0x1];
582 u8 atomic_operations[0x10];
585 u8 atomic_size_qp[0x10];
588 u8 atomic_size_dc[0x10];
590 u8 reserved_6[0x720];
593 struct mlx5_ifc_odp_cap_bits {
601 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
603 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
605 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
607 u8 reserved_3[0x720];
611 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
612 MLX5_WQ_TYPE_CYCLIC = 0x1,
613 MLX5_WQ_TYPE_STRQ = 0x2,
617 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
618 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
622 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
623 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
624 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
625 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
626 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
630 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
631 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
632 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
633 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
634 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
635 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
639 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
640 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
644 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
645 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
646 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
650 MLX5_CAP_PORT_TYPE_IB = 0x0,
651 MLX5_CAP_PORT_TYPE_ETH = 0x1,
654 struct mlx5_ifc_cmd_hca_cap_bits {
657 u8 log_max_srq_sz[0x8];
658 u8 log_max_qp_sz[0x8];
667 u8 log_max_cq_sz[0x8];
671 u8 log_max_eq_sz[0x8];
673 u8 log_max_mkey[0x6];
677 u8 max_indirection[0x8];
679 u8 log_max_mrw_sz[0x7];
681 u8 log_max_bsf_list_size[0x6];
683 u8 log_max_klm_list_size[0x6];
686 u8 log_max_ra_req_dc[0x6];
688 u8 log_max_ra_res_dc[0x6];
691 u8 log_max_ra_req_qp[0x6];
693 u8 log_max_ra_res_qp[0x6];
696 u8 cc_query_allowed[0x1];
697 u8 cc_modify_allowed[0x1];
699 u8 gid_table_size[0x10];
701 u8 out_of_seq_cnt[0x1];
702 u8 vport_counters[0x1];
705 u8 pkey_table_size[0x10];
707 u8 vport_group_manager[0x1];
708 u8 vhca_group_manager[0x1];
713 u8 nic_flow_table[0x1];
714 u8 eswitch_flow_table[0x1];
717 u8 local_ca_ack_delay[0x5];
724 u8 reserved_21[0x18];
726 u8 stat_rate_support[0x10];
730 u8 compact_address_vector[0x1];
732 u8 drain_sigerr[0x1];
733 u8 cmdif_checksum[0x2];
736 u8 wq_signature[0x1];
737 u8 sctr_data_cqe[0x1];
744 u8 eth_net_offloads[0x1];
751 u8 cq_moderation[0x1];
757 u8 scqe_break_moderation[0x1];
778 u8 pad_tx_eth_packet[0x1];
780 u8 log_bf_reg_size[0x5];
781 u8 reserved_38[0x10];
783 u8 reserved_39[0x10];
784 u8 max_wqe_sz_sq[0x10];
786 u8 reserved_40[0x10];
787 u8 max_wqe_sz_rq[0x10];
789 u8 reserved_41[0x10];
790 u8 max_wqe_sz_sq_dc[0x10];
795 u8 reserved_43[0x18];
799 u8 log_max_transport_domain[0x5];
803 u8 log_max_xrcd[0x5];
805 u8 reserved_47[0x20];
816 u8 basic_cyclic_rcv_wqe[0x1];
822 u8 log_max_rqt_size[0x5];
824 u8 log_max_tis_per_sq[0x5];
827 u8 log_max_stride_sz_rq[0x5];
829 u8 log_min_stride_sz_rq[0x5];
831 u8 log_max_stride_sz_sq[0x5];
833 u8 log_min_stride_sz_sq[0x5];
835 u8 reserved_60[0x1b];
836 u8 log_max_wq_sz[0x5];
838 u8 nic_vport_change_event[0x1];
840 u8 log_max_vlan_list[0x5];
842 u8 log_max_current_mc_list[0x5];
844 u8 log_max_current_uc_list[0x5];
846 u8 reserved_64[0x80];
849 u8 log_max_l2_table[0x5];
851 u8 log_uar_page_sz[0x10];
853 u8 reserved_67[0x40];
854 u8 device_frequency_khz[0x20];
855 u8 reserved_68[0x5f];
858 u8 cqe_zip_timeout[0x10];
859 u8 cqe_zip_max_num[0x10];
861 u8 reserved_69[0x220];
864 enum mlx5_flow_destination_type {
865 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
866 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
867 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
870 struct mlx5_ifc_dest_format_struct_bits {
871 u8 destination_type[0x8];
872 u8 destination_id[0x18];
877 struct mlx5_ifc_fte_match_param_bits {
878 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
880 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
882 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
884 u8 reserved_0[0xa00];
888 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
889 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
890 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
891 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
892 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
895 struct mlx5_ifc_rx_hash_field_select_bits {
896 u8 l3_prot_type[0x1];
897 u8 l4_prot_type[0x1];
898 u8 selected_fields[0x1e];
902 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
903 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
907 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
908 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
911 struct mlx5_ifc_wq_bits {
913 u8 wq_signature[0x1];
914 u8 end_padding_mode[0x2];
918 u8 hds_skip_first_sge[0x1];
919 u8 log2_hds_buf_size[0x3];
937 u8 log_wq_stride[0x4];
939 u8 log_wq_pg_sz[0x5];
943 u8 reserved_7[0x4e0];
945 struct mlx5_ifc_cmd_pas_bits pas[0];
948 struct mlx5_ifc_rq_num_bits {
953 struct mlx5_ifc_mac_address_layout_bits {
955 u8 mac_addr_47_32[0x10];
957 u8 mac_addr_31_0[0x20];
960 struct mlx5_ifc_vlan_layout_bits {
967 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
970 u8 min_time_between_cnps[0x20];
975 u8 cnp_802p_prio[0x3];
977 u8 reserved_3[0x720];
980 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
984 u8 clamp_tgt_rate[0x1];
986 u8 clamp_tgt_rate_after_time_inc[0x1];
991 u8 rpg_time_reset[0x20];
993 u8 rpg_byte_reset[0x20];
995 u8 rpg_threshold[0x20];
997 u8 rpg_max_rate[0x20];
999 u8 rpg_ai_rate[0x20];
1001 u8 rpg_hai_rate[0x20];
1005 u8 rpg_min_dec_fac[0x20];
1007 u8 rpg_min_rate[0x20];
1009 u8 reserved_5[0xe0];
1011 u8 rate_to_set_on_first_cnp[0x20];
1015 u8 dce_tcp_rtt[0x20];
1017 u8 rate_reduce_monitor_period[0x20];
1019 u8 reserved_6[0x20];
1021 u8 initial_alpha_value[0x20];
1023 u8 reserved_7[0x4a0];
1026 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1027 u8 reserved_0[0x80];
1029 u8 rppp_max_rps[0x20];
1031 u8 rpg_time_reset[0x20];
1033 u8 rpg_byte_reset[0x20];
1035 u8 rpg_threshold[0x20];
1037 u8 rpg_max_rate[0x20];
1039 u8 rpg_ai_rate[0x20];
1041 u8 rpg_hai_rate[0x20];
1045 u8 rpg_min_dec_fac[0x20];
1047 u8 rpg_min_rate[0x20];
1049 u8 reserved_1[0x640];
1053 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1054 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1055 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1058 struct mlx5_ifc_resize_field_select_bits {
1059 u8 resize_field_select[0x20];
1063 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1064 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1065 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1066 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1069 struct mlx5_ifc_modify_field_select_bits {
1070 u8 modify_field_select[0x20];
1073 struct mlx5_ifc_field_select_r_roce_np_bits {
1074 u8 field_select_r_roce_np[0x20];
1077 struct mlx5_ifc_field_select_r_roce_rp_bits {
1078 u8 field_select_r_roce_rp[0x20];
1082 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1083 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1084 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1085 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1086 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1087 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1088 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1089 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1090 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1091 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1094 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1095 u8 field_select_8021qaurp[0x20];
1098 struct mlx5_ifc_phys_layer_cntrs_bits {
1099 u8 time_since_last_clear_high[0x20];
1101 u8 time_since_last_clear_low[0x20];
1103 u8 symbol_errors_high[0x20];
1105 u8 symbol_errors_low[0x20];
1107 u8 sync_headers_errors_high[0x20];
1109 u8 sync_headers_errors_low[0x20];
1111 u8 edpl_bip_errors_lane0_high[0x20];
1113 u8 edpl_bip_errors_lane0_low[0x20];
1115 u8 edpl_bip_errors_lane1_high[0x20];
1117 u8 edpl_bip_errors_lane1_low[0x20];
1119 u8 edpl_bip_errors_lane2_high[0x20];
1121 u8 edpl_bip_errors_lane2_low[0x20];
1123 u8 edpl_bip_errors_lane3_high[0x20];
1125 u8 edpl_bip_errors_lane3_low[0x20];
1127 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1129 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1131 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1133 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1135 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1137 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1139 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1141 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1143 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1145 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1147 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1149 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1151 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1153 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1155 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1157 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1159 u8 rs_fec_corrected_blocks_high[0x20];
1161 u8 rs_fec_corrected_blocks_low[0x20];
1163 u8 rs_fec_uncorrectable_blocks_high[0x20];
1165 u8 rs_fec_uncorrectable_blocks_low[0x20];
1167 u8 rs_fec_no_errors_blocks_high[0x20];
1169 u8 rs_fec_no_errors_blocks_low[0x20];
1171 u8 rs_fec_single_error_blocks_high[0x20];
1173 u8 rs_fec_single_error_blocks_low[0x20];
1175 u8 rs_fec_corrected_symbols_total_high[0x20];
1177 u8 rs_fec_corrected_symbols_total_low[0x20];
1179 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1181 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1183 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1185 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1187 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1189 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1191 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1193 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1195 u8 link_down_events[0x20];
1197 u8 successful_recovery_events[0x20];
1199 u8 reserved_0[0x180];
1202 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1203 u8 transmit_queue_high[0x20];
1205 u8 transmit_queue_low[0x20];
1207 u8 reserved_0[0x780];
1210 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1211 u8 rx_octets_high[0x20];
1213 u8 rx_octets_low[0x20];
1215 u8 reserved_0[0xc0];
1217 u8 rx_frames_high[0x20];
1219 u8 rx_frames_low[0x20];
1221 u8 tx_octets_high[0x20];
1223 u8 tx_octets_low[0x20];
1225 u8 reserved_1[0xc0];
1227 u8 tx_frames_high[0x20];
1229 u8 tx_frames_low[0x20];
1231 u8 rx_pause_high[0x20];
1233 u8 rx_pause_low[0x20];
1235 u8 rx_pause_duration_high[0x20];
1237 u8 rx_pause_duration_low[0x20];
1239 u8 tx_pause_high[0x20];
1241 u8 tx_pause_low[0x20];
1243 u8 tx_pause_duration_high[0x20];
1245 u8 tx_pause_duration_low[0x20];
1247 u8 rx_pause_transition_high[0x20];
1249 u8 rx_pause_transition_low[0x20];
1251 u8 reserved_2[0x400];
1254 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1255 u8 port_transmit_wait_high[0x20];
1257 u8 port_transmit_wait_low[0x20];
1259 u8 reserved_0[0x780];
1262 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1263 u8 dot3stats_alignment_errors_high[0x20];
1265 u8 dot3stats_alignment_errors_low[0x20];
1267 u8 dot3stats_fcs_errors_high[0x20];
1269 u8 dot3stats_fcs_errors_low[0x20];
1271 u8 dot3stats_single_collision_frames_high[0x20];
1273 u8 dot3stats_single_collision_frames_low[0x20];
1275 u8 dot3stats_multiple_collision_frames_high[0x20];
1277 u8 dot3stats_multiple_collision_frames_low[0x20];
1279 u8 dot3stats_sqe_test_errors_high[0x20];
1281 u8 dot3stats_sqe_test_errors_low[0x20];
1283 u8 dot3stats_deferred_transmissions_high[0x20];
1285 u8 dot3stats_deferred_transmissions_low[0x20];
1287 u8 dot3stats_late_collisions_high[0x20];
1289 u8 dot3stats_late_collisions_low[0x20];
1291 u8 dot3stats_excessive_collisions_high[0x20];
1293 u8 dot3stats_excessive_collisions_low[0x20];
1295 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1297 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1299 u8 dot3stats_carrier_sense_errors_high[0x20];
1301 u8 dot3stats_carrier_sense_errors_low[0x20];
1303 u8 dot3stats_frame_too_longs_high[0x20];
1305 u8 dot3stats_frame_too_longs_low[0x20];
1307 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1309 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1311 u8 dot3stats_symbol_errors_high[0x20];
1313 u8 dot3stats_symbol_errors_low[0x20];
1315 u8 dot3control_in_unknown_opcodes_high[0x20];
1317 u8 dot3control_in_unknown_opcodes_low[0x20];
1319 u8 dot3in_pause_frames_high[0x20];
1321 u8 dot3in_pause_frames_low[0x20];
1323 u8 dot3out_pause_frames_high[0x20];
1325 u8 dot3out_pause_frames_low[0x20];
1327 u8 reserved_0[0x3c0];
1330 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1331 u8 ether_stats_drop_events_high[0x20];
1333 u8 ether_stats_drop_events_low[0x20];
1335 u8 ether_stats_octets_high[0x20];
1337 u8 ether_stats_octets_low[0x20];
1339 u8 ether_stats_pkts_high[0x20];
1341 u8 ether_stats_pkts_low[0x20];
1343 u8 ether_stats_broadcast_pkts_high[0x20];
1345 u8 ether_stats_broadcast_pkts_low[0x20];
1347 u8 ether_stats_multicast_pkts_high[0x20];
1349 u8 ether_stats_multicast_pkts_low[0x20];
1351 u8 ether_stats_crc_align_errors_high[0x20];
1353 u8 ether_stats_crc_align_errors_low[0x20];
1355 u8 ether_stats_undersize_pkts_high[0x20];
1357 u8 ether_stats_undersize_pkts_low[0x20];
1359 u8 ether_stats_oversize_pkts_high[0x20];
1361 u8 ether_stats_oversize_pkts_low[0x20];
1363 u8 ether_stats_fragments_high[0x20];
1365 u8 ether_stats_fragments_low[0x20];
1367 u8 ether_stats_jabbers_high[0x20];
1369 u8 ether_stats_jabbers_low[0x20];
1371 u8 ether_stats_collisions_high[0x20];
1373 u8 ether_stats_collisions_low[0x20];
1375 u8 ether_stats_pkts64octets_high[0x20];
1377 u8 ether_stats_pkts64octets_low[0x20];
1379 u8 ether_stats_pkts65to127octets_high[0x20];
1381 u8 ether_stats_pkts65to127octets_low[0x20];
1383 u8 ether_stats_pkts128to255octets_high[0x20];
1385 u8 ether_stats_pkts128to255octets_low[0x20];
1387 u8 ether_stats_pkts256to511octets_high[0x20];
1389 u8 ether_stats_pkts256to511octets_low[0x20];
1391 u8 ether_stats_pkts512to1023octets_high[0x20];
1393 u8 ether_stats_pkts512to1023octets_low[0x20];
1395 u8 ether_stats_pkts1024to1518octets_high[0x20];
1397 u8 ether_stats_pkts1024to1518octets_low[0x20];
1399 u8 ether_stats_pkts1519to2047octets_high[0x20];
1401 u8 ether_stats_pkts1519to2047octets_low[0x20];
1403 u8 ether_stats_pkts2048to4095octets_high[0x20];
1405 u8 ether_stats_pkts2048to4095octets_low[0x20];
1407 u8 ether_stats_pkts4096to8191octets_high[0x20];
1409 u8 ether_stats_pkts4096to8191octets_low[0x20];
1411 u8 ether_stats_pkts8192to10239octets_high[0x20];
1413 u8 ether_stats_pkts8192to10239octets_low[0x20];
1415 u8 reserved_0[0x280];
1418 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1419 u8 if_in_octets_high[0x20];
1421 u8 if_in_octets_low[0x20];
1423 u8 if_in_ucast_pkts_high[0x20];
1425 u8 if_in_ucast_pkts_low[0x20];
1427 u8 if_in_discards_high[0x20];
1429 u8 if_in_discards_low[0x20];
1431 u8 if_in_errors_high[0x20];
1433 u8 if_in_errors_low[0x20];
1435 u8 if_in_unknown_protos_high[0x20];
1437 u8 if_in_unknown_protos_low[0x20];
1439 u8 if_out_octets_high[0x20];
1441 u8 if_out_octets_low[0x20];
1443 u8 if_out_ucast_pkts_high[0x20];
1445 u8 if_out_ucast_pkts_low[0x20];
1447 u8 if_out_discards_high[0x20];
1449 u8 if_out_discards_low[0x20];
1451 u8 if_out_errors_high[0x20];
1453 u8 if_out_errors_low[0x20];
1455 u8 if_in_multicast_pkts_high[0x20];
1457 u8 if_in_multicast_pkts_low[0x20];
1459 u8 if_in_broadcast_pkts_high[0x20];
1461 u8 if_in_broadcast_pkts_low[0x20];
1463 u8 if_out_multicast_pkts_high[0x20];
1465 u8 if_out_multicast_pkts_low[0x20];
1467 u8 if_out_broadcast_pkts_high[0x20];
1469 u8 if_out_broadcast_pkts_low[0x20];
1471 u8 reserved_0[0x480];
1474 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1475 u8 a_frames_transmitted_ok_high[0x20];
1477 u8 a_frames_transmitted_ok_low[0x20];
1479 u8 a_frames_received_ok_high[0x20];
1481 u8 a_frames_received_ok_low[0x20];
1483 u8 a_frame_check_sequence_errors_high[0x20];
1485 u8 a_frame_check_sequence_errors_low[0x20];
1487 u8 a_alignment_errors_high[0x20];
1489 u8 a_alignment_errors_low[0x20];
1491 u8 a_octets_transmitted_ok_high[0x20];
1493 u8 a_octets_transmitted_ok_low[0x20];
1495 u8 a_octets_received_ok_high[0x20];
1497 u8 a_octets_received_ok_low[0x20];
1499 u8 a_multicast_frames_xmitted_ok_high[0x20];
1501 u8 a_multicast_frames_xmitted_ok_low[0x20];
1503 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1505 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1507 u8 a_multicast_frames_received_ok_high[0x20];
1509 u8 a_multicast_frames_received_ok_low[0x20];
1511 u8 a_broadcast_frames_received_ok_high[0x20];
1513 u8 a_broadcast_frames_received_ok_low[0x20];
1515 u8 a_in_range_length_errors_high[0x20];
1517 u8 a_in_range_length_errors_low[0x20];
1519 u8 a_out_of_range_length_field_high[0x20];
1521 u8 a_out_of_range_length_field_low[0x20];
1523 u8 a_frame_too_long_errors_high[0x20];
1525 u8 a_frame_too_long_errors_low[0x20];
1527 u8 a_symbol_error_during_carrier_high[0x20];
1529 u8 a_symbol_error_during_carrier_low[0x20];
1531 u8 a_mac_control_frames_transmitted_high[0x20];
1533 u8 a_mac_control_frames_transmitted_low[0x20];
1535 u8 a_mac_control_frames_received_high[0x20];
1537 u8 a_mac_control_frames_received_low[0x20];
1539 u8 a_unsupported_opcodes_received_high[0x20];
1541 u8 a_unsupported_opcodes_received_low[0x20];
1543 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1545 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1547 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1549 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1551 u8 reserved_0[0x300];
1554 struct mlx5_ifc_cmd_inter_comp_event_bits {
1555 u8 command_completion_vector[0x20];
1557 u8 reserved_0[0xc0];
1560 struct mlx5_ifc_stall_vl_event_bits {
1561 u8 reserved_0[0x18];
1566 u8 reserved_2[0xa0];
1569 struct mlx5_ifc_db_bf_congestion_event_bits {
1570 u8 event_subtype[0x8];
1572 u8 congestion_level[0x8];
1575 u8 reserved_2[0xa0];
1578 struct mlx5_ifc_gpio_event_bits {
1579 u8 reserved_0[0x60];
1581 u8 gpio_event_hi[0x20];
1583 u8 gpio_event_lo[0x20];
1585 u8 reserved_1[0x40];
1588 struct mlx5_ifc_port_state_change_event_bits {
1589 u8 reserved_0[0x40];
1592 u8 reserved_1[0x1c];
1594 u8 reserved_2[0x80];
1597 struct mlx5_ifc_dropped_packet_logged_bits {
1598 u8 reserved_0[0xe0];
1602 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1603 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1606 struct mlx5_ifc_cq_error_bits {
1610 u8 reserved_1[0x20];
1612 u8 reserved_2[0x18];
1615 u8 reserved_3[0x80];
1618 struct mlx5_ifc_rdma_page_fault_event_bits {
1619 u8 bytes_committed[0x20];
1623 u8 reserved_0[0x10];
1624 u8 packet_len[0x10];
1626 u8 rdma_op_len[0x20];
1637 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1638 u8 bytes_committed[0x20];
1640 u8 reserved_0[0x10];
1643 u8 reserved_1[0x10];
1646 u8 reserved_2[0x60];
1655 struct mlx5_ifc_qp_events_bits {
1656 u8 reserved_0[0xa0];
1659 u8 reserved_1[0x18];
1662 u8 qpn_rqn_sqn[0x18];
1665 struct mlx5_ifc_dct_events_bits {
1666 u8 reserved_0[0xc0];
1669 u8 dct_number[0x18];
1672 struct mlx5_ifc_comp_event_bits {
1673 u8 reserved_0[0xc0];
1680 MLX5_QPC_STATE_RST = 0x0,
1681 MLX5_QPC_STATE_INIT = 0x1,
1682 MLX5_QPC_STATE_RTR = 0x2,
1683 MLX5_QPC_STATE_RTS = 0x3,
1684 MLX5_QPC_STATE_SQER = 0x4,
1685 MLX5_QPC_STATE_ERR = 0x6,
1686 MLX5_QPC_STATE_SQD = 0x7,
1687 MLX5_QPC_STATE_SUSPENDED = 0x9,
1691 MLX5_QPC_ST_RC = 0x0,
1692 MLX5_QPC_ST_UC = 0x1,
1693 MLX5_QPC_ST_UD = 0x2,
1694 MLX5_QPC_ST_XRC = 0x3,
1695 MLX5_QPC_ST_DCI = 0x5,
1696 MLX5_QPC_ST_QP0 = 0x7,
1697 MLX5_QPC_ST_QP1 = 0x8,
1698 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1699 MLX5_QPC_ST_REG_UMR = 0xc,
1703 MLX5_QPC_PM_STATE_ARMED = 0x0,
1704 MLX5_QPC_PM_STATE_REARM = 0x1,
1705 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1706 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1710 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1711 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1715 MLX5_QPC_MTU_256_BYTES = 0x1,
1716 MLX5_QPC_MTU_512_BYTES = 0x2,
1717 MLX5_QPC_MTU_1K_BYTES = 0x3,
1718 MLX5_QPC_MTU_2K_BYTES = 0x4,
1719 MLX5_QPC_MTU_4K_BYTES = 0x5,
1720 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1724 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1725 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1726 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1727 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1728 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1729 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1730 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1731 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1735 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1736 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1737 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1741 MLX5_QPC_CS_RES_DISABLE = 0x0,
1742 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1743 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1746 struct mlx5_ifc_qpc_bits {
1753 u8 end_padding_mode[0x2];
1756 u8 wq_signature[0x1];
1757 u8 block_lb_mc[0x1];
1758 u8 atomic_like_write_en[0x1];
1759 u8 latency_sensitive[0x1];
1761 u8 drain_sigerr[0x1];
1766 u8 log_msg_max[0x5];
1768 u8 log_rq_size[0x4];
1769 u8 log_rq_stride[0x3];
1771 u8 log_sq_size[0x4];
1776 u8 counter_set_id[0x8];
1780 u8 user_index[0x18];
1782 u8 reserved_10[0x3];
1783 u8 log_page_size[0x5];
1784 u8 remote_qpn[0x18];
1786 struct mlx5_ifc_ads_bits primary_address_path;
1788 struct mlx5_ifc_ads_bits secondary_address_path;
1790 u8 log_ack_req_freq[0x4];
1791 u8 reserved_11[0x4];
1792 u8 log_sra_max[0x3];
1793 u8 reserved_12[0x2];
1794 u8 retry_count[0x3];
1796 u8 reserved_13[0x1];
1798 u8 cur_rnr_retry[0x3];
1799 u8 cur_retry_count[0x3];
1800 u8 reserved_14[0x5];
1802 u8 reserved_15[0x20];
1804 u8 reserved_16[0x8];
1805 u8 next_send_psn[0x18];
1807 u8 reserved_17[0x8];
1810 u8 reserved_18[0x40];
1812 u8 reserved_19[0x8];
1813 u8 last_acked_psn[0x18];
1815 u8 reserved_20[0x8];
1818 u8 reserved_21[0x8];
1819 u8 log_rra_max[0x3];
1820 u8 reserved_22[0x1];
1821 u8 atomic_mode[0x4];
1825 u8 reserved_23[0x1];
1826 u8 page_offset[0x6];
1827 u8 reserved_24[0x3];
1828 u8 cd_slave_receive[0x1];
1829 u8 cd_slave_send[0x1];
1832 u8 reserved_25[0x3];
1833 u8 min_rnr_nak[0x5];
1834 u8 next_rcv_psn[0x18];
1836 u8 reserved_26[0x8];
1839 u8 reserved_27[0x8];
1846 u8 reserved_28[0x5];
1850 u8 reserved_29[0x8];
1853 u8 hw_sq_wqebb_counter[0x10];
1854 u8 sw_sq_wqebb_counter[0x10];
1856 u8 hw_rq_counter[0x20];
1858 u8 sw_rq_counter[0x20];
1860 u8 reserved_30[0x20];
1862 u8 reserved_31[0xf];
1867 u8 dc_access_key[0x40];
1869 u8 reserved_32[0xc0];
1872 struct mlx5_ifc_roce_addr_layout_bits {
1873 u8 source_l3_address[16][0x8];
1878 u8 source_mac_47_32[0x10];
1880 u8 source_mac_31_0[0x20];
1882 u8 reserved_1[0x14];
1883 u8 roce_l3_type[0x4];
1884 u8 roce_version[0x8];
1886 u8 reserved_2[0x20];
1889 union mlx5_ifc_hca_cap_union_bits {
1890 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1891 struct mlx5_ifc_odp_cap_bits odp_cap;
1892 struct mlx5_ifc_atomic_caps_bits atomic_caps;
1893 struct mlx5_ifc_roce_cap_bits roce_cap;
1894 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1895 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1896 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
1897 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
1898 u8 reserved_0[0x8000];
1902 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
1903 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
1904 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
1907 struct mlx5_ifc_flow_context_bits {
1908 u8 reserved_0[0x20];
1915 u8 reserved_2[0x10];
1919 u8 destination_list_size[0x18];
1921 u8 reserved_4[0x160];
1923 struct mlx5_ifc_fte_match_param_bits match_value;
1925 u8 reserved_5[0x600];
1927 struct mlx5_ifc_dest_format_struct_bits destination[0];
1931 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
1932 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
1935 struct mlx5_ifc_xrc_srqc_bits {
1937 u8 log_xrc_srq_size[0x4];
1938 u8 reserved_0[0x18];
1940 u8 wq_signature[0x1];
1944 u8 basic_cyclic_rcv_wqe[0x1];
1945 u8 log_rq_stride[0x3];
1948 u8 page_offset[0x6];
1952 u8 reserved_3[0x20];
1954 u8 user_index_equal_xrc_srqn[0x1];
1956 u8 log_page_size[0x6];
1957 u8 user_index[0x18];
1959 u8 reserved_5[0x20];
1967 u8 reserved_7[0x40];
1969 u8 db_record_addr_h[0x20];
1971 u8 db_record_addr_l[0x1e];
1974 u8 reserved_9[0x80];
1977 struct mlx5_ifc_traffic_counter_bits {
1983 struct mlx5_ifc_tisc_bits {
1986 u8 reserved_1[0x10];
1988 u8 reserved_2[0x100];
1991 u8 transport_domain[0x18];
1993 u8 reserved_4[0x3c0];
1997 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
1998 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2002 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2003 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2007 MLX5_RX_HASH_FN_NONE = 0x0,
2008 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2009 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2013 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2014 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2017 struct mlx5_ifc_tirc_bits {
2018 u8 reserved_0[0x20];
2021 u8 reserved_1[0x1c];
2023 u8 reserved_2[0x40];
2026 u8 lro_timeout_period_usecs[0x10];
2027 u8 lro_enable_mask[0x4];
2028 u8 lro_max_ip_payload_size[0x8];
2030 u8 reserved_4[0x40];
2033 u8 inline_rqn[0x18];
2035 u8 rx_hash_symmetric[0x1];
2037 u8 tunneled_offload_en[0x1];
2039 u8 indirect_table[0x18];
2043 u8 self_lb_block[0x2];
2044 u8 transport_domain[0x18];
2046 u8 rx_hash_toeplitz_key[10][0x20];
2048 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2050 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2052 u8 reserved_9[0x4c0];
2056 MLX5_SRQC_STATE_GOOD = 0x0,
2057 MLX5_SRQC_STATE_ERROR = 0x1,
2060 struct mlx5_ifc_srqc_bits {
2062 u8 log_srq_size[0x4];
2063 u8 reserved_0[0x18];
2065 u8 wq_signature[0x1];
2070 u8 log_rq_stride[0x3];
2073 u8 page_offset[0x6];
2077 u8 reserved_4[0x20];
2080 u8 log_page_size[0x6];
2081 u8 reserved_6[0x18];
2083 u8 reserved_7[0x20];
2091 u8 reserved_9[0x40];
2095 u8 reserved_10[0x80];
2099 MLX5_SQC_STATE_RST = 0x0,
2100 MLX5_SQC_STATE_RDY = 0x1,
2101 MLX5_SQC_STATE_ERR = 0x3,
2104 struct mlx5_ifc_sqc_bits {
2108 u8 flush_in_error_en[0x1];
2111 u8 reserved_1[0x14];
2114 u8 user_index[0x18];
2119 u8 reserved_4[0xa0];
2121 u8 tis_lst_sz[0x10];
2122 u8 reserved_5[0x10];
2124 u8 reserved_6[0x40];
2129 struct mlx5_ifc_wq_bits wq;
2132 struct mlx5_ifc_rqtc_bits {
2133 u8 reserved_0[0xa0];
2135 u8 reserved_1[0x10];
2136 u8 rqt_max_size[0x10];
2138 u8 reserved_2[0x10];
2139 u8 rqt_actual_size[0x10];
2141 u8 reserved_3[0x6a0];
2143 struct mlx5_ifc_rq_num_bits rq_num[0];
2147 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2148 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2152 MLX5_RQC_STATE_RST = 0x0,
2153 MLX5_RQC_STATE_RDY = 0x1,
2154 MLX5_RQC_STATE_ERR = 0x3,
2157 struct mlx5_ifc_rqc_bits {
2161 u8 mem_rq_type[0x4];
2164 u8 flush_in_error_en[0x1];
2165 u8 reserved_2[0x12];
2168 u8 user_index[0x18];
2173 u8 counter_set_id[0x8];
2174 u8 reserved_5[0x18];
2179 u8 reserved_7[0xe0];
2181 struct mlx5_ifc_wq_bits wq;
2185 MLX5_RMPC_STATE_RDY = 0x1,
2186 MLX5_RMPC_STATE_ERR = 0x3,
2189 struct mlx5_ifc_rmpc_bits {
2192 u8 reserved_1[0x14];
2194 u8 basic_cyclic_rcv_wqe[0x1];
2195 u8 reserved_2[0x1f];
2197 u8 reserved_3[0x140];
2199 struct mlx5_ifc_wq_bits wq;
2202 struct mlx5_ifc_nic_vport_context_bits {
2203 u8 reserved_0[0x1f];
2206 u8 arm_change_event[0x1];
2207 u8 reserved_1[0x1a];
2208 u8 event_on_mtu[0x1];
2209 u8 event_on_promisc_change[0x1];
2210 u8 event_on_vlan_change[0x1];
2211 u8 event_on_mc_address_change[0x1];
2212 u8 event_on_uc_address_change[0x1];
2214 u8 reserved_2[0xf0];
2218 u8 reserved_3[0x640];
2222 u8 promisc_all[0x1];
2224 u8 allowed_list_type[0x3];
2226 u8 allowed_list_size[0xc];
2228 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2230 u8 reserved_6[0x20];
2232 u8 current_uc_mac_address[0][0x40];
2236 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2237 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2238 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2241 struct mlx5_ifc_mkc_bits {
2245 u8 small_fence_on_rdma_read_response[0x1];
2252 u8 access_mode[0x2];
2258 u8 reserved_3[0x20];
2264 u8 expected_sigerr_count[0x1];
2269 u8 start_addr[0x40];
2273 u8 bsf_octword_size[0x20];
2275 u8 reserved_6[0x80];
2277 u8 translations_octword_size[0x20];
2279 u8 reserved_7[0x1b];
2280 u8 log_page_size[0x5];
2282 u8 reserved_8[0x20];
2285 struct mlx5_ifc_pkey_bits {
2286 u8 reserved_0[0x10];
2290 struct mlx5_ifc_array128_auto_bits {
2291 u8 array128_auto[16][0x8];
2294 struct mlx5_ifc_hca_vport_context_bits {
2295 u8 field_select[0x20];
2297 u8 reserved_0[0xe0];
2299 u8 sm_virt_aware[0x1];
2302 u8 grh_required[0x1];
2304 u8 port_physical_state[0x4];
2305 u8 vport_state_policy[0x4];
2307 u8 vport_state[0x4];
2309 u8 reserved_2[0x20];
2311 u8 system_image_guid[0x40];
2319 u8 cap_mask1_field_select[0x20];
2323 u8 cap_mask2_field_select[0x20];
2325 u8 reserved_3[0x80];
2329 u8 init_type_reply[0x4];
2331 u8 subnet_timeout[0x5];
2337 u8 qkey_violation_counter[0x10];
2338 u8 pkey_violation_counter[0x10];
2340 u8 reserved_6[0xca0];
2343 struct mlx5_ifc_esw_vport_context_bits {
2345 u8 vport_svlan_strip[0x1];
2346 u8 vport_cvlan_strip[0x1];
2347 u8 vport_svlan_insert[0x1];
2348 u8 vport_cvlan_insert[0x2];
2349 u8 reserved_1[0x18];
2351 u8 reserved_2[0x20];
2360 u8 reserved_3[0x7a0];
2364 MLX5_EQC_STATUS_OK = 0x0,
2365 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2369 MLX5_EQC_ST_ARMED = 0x9,
2370 MLX5_EQC_ST_FIRED = 0xa,
2373 struct mlx5_ifc_eqc_bits {
2382 u8 reserved_3[0x20];
2384 u8 reserved_4[0x14];
2385 u8 page_offset[0x6];
2389 u8 log_eq_size[0x5];
2392 u8 reserved_7[0x20];
2394 u8 reserved_8[0x18];
2398 u8 log_page_size[0x5];
2399 u8 reserved_10[0x18];
2401 u8 reserved_11[0x60];
2403 u8 reserved_12[0x8];
2404 u8 consumer_counter[0x18];
2406 u8 reserved_13[0x8];
2407 u8 producer_counter[0x18];
2409 u8 reserved_14[0x80];
2413 MLX5_DCTC_STATE_ACTIVE = 0x0,
2414 MLX5_DCTC_STATE_DRAINING = 0x1,
2415 MLX5_DCTC_STATE_DRAINED = 0x2,
2419 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2420 MLX5_DCTC_CS_RES_NA = 0x1,
2421 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2425 MLX5_DCTC_MTU_256_BYTES = 0x1,
2426 MLX5_DCTC_MTU_512_BYTES = 0x2,
2427 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2428 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2429 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2432 struct mlx5_ifc_dctc_bits {
2435 u8 reserved_1[0x18];
2438 u8 user_index[0x18];
2443 u8 counter_set_id[0x8];
2444 u8 atomic_mode[0x4];
2448 u8 atomic_like_write_en[0x1];
2449 u8 latency_sensitive[0x1];
2457 u8 min_rnr_nak[0x5];
2467 u8 reserved_10[0x4];
2468 u8 flow_label[0x14];
2470 u8 dc_access_key[0x40];
2472 u8 reserved_11[0x5];
2475 u8 pkey_index[0x10];
2477 u8 reserved_12[0x8];
2478 u8 my_addr_index[0x8];
2479 u8 reserved_13[0x8];
2482 u8 dc_access_key_violation_count[0x20];
2484 u8 reserved_14[0x14];
2490 u8 reserved_15[0x40];
2494 MLX5_CQC_STATUS_OK = 0x0,
2495 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2496 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2500 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2501 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2505 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2506 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2507 MLX5_CQC_ST_FIRED = 0xa,
2510 struct mlx5_ifc_cqc_bits {
2516 u8 scqe_break_moderation_en[0x1];
2520 u8 mini_cqe_res_format[0x2];
2524 u8 reserved_4[0x20];
2526 u8 reserved_5[0x14];
2527 u8 page_offset[0x6];
2531 u8 log_cq_size[0x5];
2536 u8 cq_max_count[0x10];
2538 u8 reserved_9[0x18];
2541 u8 reserved_10[0x3];
2542 u8 log_page_size[0x5];
2543 u8 reserved_11[0x18];
2545 u8 reserved_12[0x20];
2547 u8 reserved_13[0x8];
2548 u8 last_notified_index[0x18];
2550 u8 reserved_14[0x8];
2551 u8 last_solicit_index[0x18];
2553 u8 reserved_15[0x8];
2554 u8 consumer_counter[0x18];
2556 u8 reserved_16[0x8];
2557 u8 producer_counter[0x18];
2559 u8 reserved_17[0x40];
2564 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2565 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2566 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2567 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2568 u8 reserved_0[0x800];
2571 struct mlx5_ifc_query_adapter_param_block_bits {
2572 u8 reserved_0[0xc0];
2575 u8 ieee_vendor_id[0x18];
2577 u8 reserved_2[0x10];
2578 u8 vsd_vendor_id[0x10];
2582 u8 vsd_contd_psid[16][0x8];
2585 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2586 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2587 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2588 u8 reserved_0[0x20];
2591 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2592 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2593 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2594 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2595 u8 reserved_0[0x20];
2598 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2599 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2600 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2601 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2602 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2603 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2604 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2605 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2606 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2607 u8 reserved_0[0x7c0];
2610 union mlx5_ifc_event_auto_bits {
2611 struct mlx5_ifc_comp_event_bits comp_event;
2612 struct mlx5_ifc_dct_events_bits dct_events;
2613 struct mlx5_ifc_qp_events_bits qp_events;
2614 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2615 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2616 struct mlx5_ifc_cq_error_bits cq_error;
2617 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2618 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2619 struct mlx5_ifc_gpio_event_bits gpio_event;
2620 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2621 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2622 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2623 u8 reserved_0[0xe0];
2626 struct mlx5_ifc_health_buffer_bits {
2627 u8 reserved_0[0x100];
2629 u8 assert_existptr[0x20];
2631 u8 assert_callra[0x20];
2633 u8 reserved_1[0x40];
2635 u8 fw_version[0x20];
2639 u8 reserved_2[0x20];
2641 u8 irisc_index[0x8];
2646 struct mlx5_ifc_register_loopback_control_bits {
2650 u8 reserved_1[0x10];
2652 u8 reserved_2[0x60];
2655 struct mlx5_ifc_teardown_hca_out_bits {
2657 u8 reserved_0[0x18];
2661 u8 reserved_1[0x40];
2665 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2666 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2669 struct mlx5_ifc_teardown_hca_in_bits {
2671 u8 reserved_0[0x10];
2673 u8 reserved_1[0x10];
2676 u8 reserved_2[0x10];
2679 u8 reserved_3[0x20];
2682 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2684 u8 reserved_0[0x18];
2688 u8 reserved_1[0x40];
2691 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2693 u8 reserved_0[0x10];
2695 u8 reserved_1[0x10];
2701 u8 reserved_3[0x20];
2703 u8 opt_param_mask[0x20];
2705 u8 reserved_4[0x20];
2707 struct mlx5_ifc_qpc_bits qpc;
2709 u8 reserved_5[0x80];
2712 struct mlx5_ifc_sqd2rts_qp_out_bits {
2714 u8 reserved_0[0x18];
2718 u8 reserved_1[0x40];
2721 struct mlx5_ifc_sqd2rts_qp_in_bits {
2723 u8 reserved_0[0x10];
2725 u8 reserved_1[0x10];
2731 u8 reserved_3[0x20];
2733 u8 opt_param_mask[0x20];
2735 u8 reserved_4[0x20];
2737 struct mlx5_ifc_qpc_bits qpc;
2739 u8 reserved_5[0x80];
2742 struct mlx5_ifc_set_roce_address_out_bits {
2744 u8 reserved_0[0x18];
2748 u8 reserved_1[0x40];
2751 struct mlx5_ifc_set_roce_address_in_bits {
2753 u8 reserved_0[0x10];
2755 u8 reserved_1[0x10];
2758 u8 roce_address_index[0x10];
2759 u8 reserved_2[0x10];
2761 u8 reserved_3[0x20];
2763 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2766 struct mlx5_ifc_set_mad_demux_out_bits {
2768 u8 reserved_0[0x18];
2772 u8 reserved_1[0x40];
2776 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
2777 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
2780 struct mlx5_ifc_set_mad_demux_in_bits {
2782 u8 reserved_0[0x10];
2784 u8 reserved_1[0x10];
2787 u8 reserved_2[0x20];
2791 u8 reserved_4[0x18];
2794 struct mlx5_ifc_set_l2_table_entry_out_bits {
2796 u8 reserved_0[0x18];
2800 u8 reserved_1[0x40];
2803 struct mlx5_ifc_set_l2_table_entry_in_bits {
2805 u8 reserved_0[0x10];
2807 u8 reserved_1[0x10];
2810 u8 reserved_2[0x60];
2813 u8 table_index[0x18];
2815 u8 reserved_4[0x20];
2817 u8 reserved_5[0x13];
2821 struct mlx5_ifc_mac_address_layout_bits mac_address;
2823 u8 reserved_6[0xc0];
2826 struct mlx5_ifc_set_issi_out_bits {
2828 u8 reserved_0[0x18];
2832 u8 reserved_1[0x40];
2835 struct mlx5_ifc_set_issi_in_bits {
2837 u8 reserved_0[0x10];
2839 u8 reserved_1[0x10];
2842 u8 reserved_2[0x10];
2843 u8 current_issi[0x10];
2845 u8 reserved_3[0x20];
2848 struct mlx5_ifc_set_hca_cap_out_bits {
2850 u8 reserved_0[0x18];
2854 u8 reserved_1[0x40];
2857 struct mlx5_ifc_set_hca_cap_in_bits {
2859 u8 reserved_0[0x10];
2861 u8 reserved_1[0x10];
2864 u8 reserved_2[0x40];
2866 union mlx5_ifc_hca_cap_union_bits capability;
2870 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
2871 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
2872 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
2873 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
2876 struct mlx5_ifc_set_fte_out_bits {
2878 u8 reserved_0[0x18];
2882 u8 reserved_1[0x40];
2885 struct mlx5_ifc_set_fte_in_bits {
2887 u8 reserved_0[0x10];
2889 u8 reserved_1[0x10];
2892 u8 reserved_2[0x40];
2895 u8 reserved_3[0x18];
2900 u8 reserved_5[0x18];
2901 u8 modify_enable_mask[0x8];
2903 u8 reserved_6[0x20];
2905 u8 flow_index[0x20];
2907 u8 reserved_7[0xe0];
2909 struct mlx5_ifc_flow_context_bits flow_context;
2912 struct mlx5_ifc_rts2rts_qp_out_bits {
2914 u8 reserved_0[0x18];
2918 u8 reserved_1[0x40];
2921 struct mlx5_ifc_rts2rts_qp_in_bits {
2923 u8 reserved_0[0x10];
2925 u8 reserved_1[0x10];
2931 u8 reserved_3[0x20];
2933 u8 opt_param_mask[0x20];
2935 u8 reserved_4[0x20];
2937 struct mlx5_ifc_qpc_bits qpc;
2939 u8 reserved_5[0x80];
2942 struct mlx5_ifc_rtr2rts_qp_out_bits {
2944 u8 reserved_0[0x18];
2948 u8 reserved_1[0x40];
2951 struct mlx5_ifc_rtr2rts_qp_in_bits {
2953 u8 reserved_0[0x10];
2955 u8 reserved_1[0x10];
2961 u8 reserved_3[0x20];
2963 u8 opt_param_mask[0x20];
2965 u8 reserved_4[0x20];
2967 struct mlx5_ifc_qpc_bits qpc;
2969 u8 reserved_5[0x80];
2972 struct mlx5_ifc_rst2init_qp_out_bits {
2974 u8 reserved_0[0x18];
2978 u8 reserved_1[0x40];
2981 struct mlx5_ifc_rst2init_qp_in_bits {
2983 u8 reserved_0[0x10];
2985 u8 reserved_1[0x10];
2991 u8 reserved_3[0x20];
2993 u8 opt_param_mask[0x20];
2995 u8 reserved_4[0x20];
2997 struct mlx5_ifc_qpc_bits qpc;
2999 u8 reserved_5[0x80];
3002 struct mlx5_ifc_query_xrc_srq_out_bits {
3004 u8 reserved_0[0x18];
3008 u8 reserved_1[0x40];
3010 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3012 u8 reserved_2[0x600];
3017 struct mlx5_ifc_query_xrc_srq_in_bits {
3019 u8 reserved_0[0x10];
3021 u8 reserved_1[0x10];
3027 u8 reserved_3[0x20];
3031 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3032 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3035 struct mlx5_ifc_query_vport_state_out_bits {
3037 u8 reserved_0[0x18];
3041 u8 reserved_1[0x20];
3043 u8 reserved_2[0x18];
3044 u8 admin_state[0x4];
3049 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3050 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3053 struct mlx5_ifc_query_vport_state_in_bits {
3055 u8 reserved_0[0x10];
3057 u8 reserved_1[0x10];
3060 u8 other_vport[0x1];
3062 u8 vport_number[0x10];
3064 u8 reserved_3[0x20];
3067 struct mlx5_ifc_query_vport_counter_out_bits {
3069 u8 reserved_0[0x18];
3073 u8 reserved_1[0x40];
3075 struct mlx5_ifc_traffic_counter_bits received_errors;
3077 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3079 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3081 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3083 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3085 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3087 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3089 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3091 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3093 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3095 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3097 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3099 u8 reserved_2[0xa00];
3103 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3106 struct mlx5_ifc_query_vport_counter_in_bits {
3108 u8 reserved_0[0x10];
3110 u8 reserved_1[0x10];
3113 u8 other_vport[0x1];
3115 u8 vport_number[0x10];
3117 u8 reserved_3[0x60];
3120 u8 reserved_4[0x1f];
3122 u8 reserved_5[0x20];
3125 struct mlx5_ifc_query_tis_out_bits {
3127 u8 reserved_0[0x18];
3131 u8 reserved_1[0x40];
3133 struct mlx5_ifc_tisc_bits tis_context;
3136 struct mlx5_ifc_query_tis_in_bits {
3138 u8 reserved_0[0x10];
3140 u8 reserved_1[0x10];
3146 u8 reserved_3[0x20];
3149 struct mlx5_ifc_query_tir_out_bits {
3151 u8 reserved_0[0x18];
3155 u8 reserved_1[0xc0];
3157 struct mlx5_ifc_tirc_bits tir_context;
3160 struct mlx5_ifc_query_tir_in_bits {
3162 u8 reserved_0[0x10];
3164 u8 reserved_1[0x10];
3170 u8 reserved_3[0x20];
3173 struct mlx5_ifc_query_srq_out_bits {
3175 u8 reserved_0[0x18];
3179 u8 reserved_1[0x40];
3181 struct mlx5_ifc_srqc_bits srq_context_entry;
3183 u8 reserved_2[0x600];
3188 struct mlx5_ifc_query_srq_in_bits {
3190 u8 reserved_0[0x10];
3192 u8 reserved_1[0x10];
3198 u8 reserved_3[0x20];
3201 struct mlx5_ifc_query_sq_out_bits {
3203 u8 reserved_0[0x18];
3207 u8 reserved_1[0xc0];
3209 struct mlx5_ifc_sqc_bits sq_context;
3212 struct mlx5_ifc_query_sq_in_bits {
3214 u8 reserved_0[0x10];
3216 u8 reserved_1[0x10];
3222 u8 reserved_3[0x20];
3225 struct mlx5_ifc_query_special_contexts_out_bits {
3227 u8 reserved_0[0x18];
3231 u8 reserved_1[0x20];
3236 struct mlx5_ifc_query_special_contexts_in_bits {
3238 u8 reserved_0[0x10];
3240 u8 reserved_1[0x10];
3243 u8 reserved_2[0x40];
3246 struct mlx5_ifc_query_rqt_out_bits {
3248 u8 reserved_0[0x18];
3252 u8 reserved_1[0xc0];
3254 struct mlx5_ifc_rqtc_bits rqt_context;
3257 struct mlx5_ifc_query_rqt_in_bits {
3259 u8 reserved_0[0x10];
3261 u8 reserved_1[0x10];
3267 u8 reserved_3[0x20];
3270 struct mlx5_ifc_query_rq_out_bits {
3272 u8 reserved_0[0x18];
3276 u8 reserved_1[0xc0];
3278 struct mlx5_ifc_rqc_bits rq_context;
3281 struct mlx5_ifc_query_rq_in_bits {
3283 u8 reserved_0[0x10];
3285 u8 reserved_1[0x10];
3291 u8 reserved_3[0x20];
3294 struct mlx5_ifc_query_roce_address_out_bits {
3296 u8 reserved_0[0x18];
3300 u8 reserved_1[0x40];
3302 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3305 struct mlx5_ifc_query_roce_address_in_bits {
3307 u8 reserved_0[0x10];
3309 u8 reserved_1[0x10];
3312 u8 roce_address_index[0x10];
3313 u8 reserved_2[0x10];
3315 u8 reserved_3[0x20];
3318 struct mlx5_ifc_query_rmp_out_bits {
3320 u8 reserved_0[0x18];
3324 u8 reserved_1[0xc0];
3326 struct mlx5_ifc_rmpc_bits rmp_context;
3329 struct mlx5_ifc_query_rmp_in_bits {
3331 u8 reserved_0[0x10];
3333 u8 reserved_1[0x10];
3339 u8 reserved_3[0x20];
3342 struct mlx5_ifc_query_qp_out_bits {
3344 u8 reserved_0[0x18];
3348 u8 reserved_1[0x40];
3350 u8 opt_param_mask[0x20];
3352 u8 reserved_2[0x20];
3354 struct mlx5_ifc_qpc_bits qpc;
3356 u8 reserved_3[0x80];
3361 struct mlx5_ifc_query_qp_in_bits {
3363 u8 reserved_0[0x10];
3365 u8 reserved_1[0x10];
3371 u8 reserved_3[0x20];
3374 struct mlx5_ifc_query_q_counter_out_bits {
3376 u8 reserved_0[0x18];
3380 u8 reserved_1[0x40];
3382 u8 rx_write_requests[0x20];
3384 u8 reserved_2[0x20];
3386 u8 rx_read_requests[0x20];
3388 u8 reserved_3[0x20];
3390 u8 rx_atomic_requests[0x20];
3392 u8 reserved_4[0x20];
3394 u8 rx_dct_connect[0x20];
3396 u8 reserved_5[0x20];
3398 u8 out_of_buffer[0x20];
3400 u8 reserved_6[0x20];
3402 u8 out_of_sequence[0x20];
3404 u8 reserved_7[0x620];
3407 struct mlx5_ifc_query_q_counter_in_bits {
3409 u8 reserved_0[0x10];
3411 u8 reserved_1[0x10];
3414 u8 reserved_2[0x80];
3417 u8 reserved_3[0x1f];
3419 u8 reserved_4[0x18];
3420 u8 counter_set_id[0x8];
3423 struct mlx5_ifc_query_pages_out_bits {
3425 u8 reserved_0[0x18];
3429 u8 reserved_1[0x10];
3430 u8 function_id[0x10];
3436 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3437 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3438 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3441 struct mlx5_ifc_query_pages_in_bits {
3443 u8 reserved_0[0x10];
3445 u8 reserved_1[0x10];
3448 u8 reserved_2[0x10];
3449 u8 function_id[0x10];
3451 u8 reserved_3[0x20];
3454 struct mlx5_ifc_query_nic_vport_context_out_bits {
3456 u8 reserved_0[0x18];
3460 u8 reserved_1[0x40];
3462 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3465 struct mlx5_ifc_query_nic_vport_context_in_bits {
3467 u8 reserved_0[0x10];
3469 u8 reserved_1[0x10];
3472 u8 other_vport[0x1];
3474 u8 vport_number[0x10];
3477 u8 allowed_list_type[0x3];
3478 u8 reserved_4[0x18];
3481 struct mlx5_ifc_query_mkey_out_bits {
3483 u8 reserved_0[0x18];
3487 u8 reserved_1[0x40];
3489 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3491 u8 reserved_2[0x600];
3493 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3495 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3498 struct mlx5_ifc_query_mkey_in_bits {
3500 u8 reserved_0[0x10];
3502 u8 reserved_1[0x10];
3506 u8 mkey_index[0x18];
3509 u8 reserved_3[0x1f];
3512 struct mlx5_ifc_query_mad_demux_out_bits {
3514 u8 reserved_0[0x18];
3518 u8 reserved_1[0x40];
3520 u8 mad_dumux_parameters_block[0x20];
3523 struct mlx5_ifc_query_mad_demux_in_bits {
3525 u8 reserved_0[0x10];
3527 u8 reserved_1[0x10];
3530 u8 reserved_2[0x40];
3533 struct mlx5_ifc_query_l2_table_entry_out_bits {
3535 u8 reserved_0[0x18];
3539 u8 reserved_1[0xa0];
3541 u8 reserved_2[0x13];
3545 struct mlx5_ifc_mac_address_layout_bits mac_address;
3547 u8 reserved_3[0xc0];
3550 struct mlx5_ifc_query_l2_table_entry_in_bits {
3552 u8 reserved_0[0x10];
3554 u8 reserved_1[0x10];
3557 u8 reserved_2[0x60];
3560 u8 table_index[0x18];
3562 u8 reserved_4[0x140];
3565 struct mlx5_ifc_query_issi_out_bits {
3567 u8 reserved_0[0x18];
3571 u8 reserved_1[0x10];
3572 u8 current_issi[0x10];
3574 u8 reserved_2[0xa0];
3576 u8 supported_issi_reserved[76][0x8];
3577 u8 supported_issi_dw0[0x20];
3580 struct mlx5_ifc_query_issi_in_bits {
3582 u8 reserved_0[0x10];
3584 u8 reserved_1[0x10];
3587 u8 reserved_2[0x40];
3590 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3592 u8 reserved_0[0x18];
3596 u8 reserved_1[0x40];
3598 struct mlx5_ifc_pkey_bits pkey[0];
3601 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3603 u8 reserved_0[0x10];
3605 u8 reserved_1[0x10];
3608 u8 other_vport[0x1];
3611 u8 vport_number[0x10];
3613 u8 reserved_3[0x10];
3614 u8 pkey_index[0x10];
3617 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3619 u8 reserved_0[0x18];
3623 u8 reserved_1[0x20];
3626 u8 reserved_2[0x10];
3628 struct mlx5_ifc_array128_auto_bits gid[0];
3631 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3633 u8 reserved_0[0x10];
3635 u8 reserved_1[0x10];
3638 u8 other_vport[0x1];
3641 u8 vport_number[0x10];
3643 u8 reserved_3[0x10];
3647 struct mlx5_ifc_query_hca_vport_context_out_bits {
3649 u8 reserved_0[0x18];
3653 u8 reserved_1[0x40];
3655 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3658 struct mlx5_ifc_query_hca_vport_context_in_bits {
3660 u8 reserved_0[0x10];
3662 u8 reserved_1[0x10];
3665 u8 other_vport[0x1];
3668 u8 vport_number[0x10];
3670 u8 reserved_3[0x20];
3673 struct mlx5_ifc_query_hca_cap_out_bits {
3675 u8 reserved_0[0x18];
3679 u8 reserved_1[0x40];
3681 union mlx5_ifc_hca_cap_union_bits capability;
3684 struct mlx5_ifc_query_hca_cap_in_bits {
3686 u8 reserved_0[0x10];
3688 u8 reserved_1[0x10];
3691 u8 reserved_2[0x40];
3694 struct mlx5_ifc_query_flow_table_out_bits {
3696 u8 reserved_0[0x18];
3700 u8 reserved_1[0x80];
3707 u8 reserved_4[0x120];
3710 struct mlx5_ifc_query_flow_table_in_bits {
3712 u8 reserved_0[0x10];
3714 u8 reserved_1[0x10];
3717 u8 reserved_2[0x40];
3720 u8 reserved_3[0x18];
3725 u8 reserved_5[0x140];
3728 struct mlx5_ifc_query_fte_out_bits {
3730 u8 reserved_0[0x18];
3734 u8 reserved_1[0x1c0];
3736 struct mlx5_ifc_flow_context_bits flow_context;
3739 struct mlx5_ifc_query_fte_in_bits {
3741 u8 reserved_0[0x10];
3743 u8 reserved_1[0x10];
3746 u8 reserved_2[0x40];
3749 u8 reserved_3[0x18];
3754 u8 reserved_5[0x40];
3756 u8 flow_index[0x20];
3758 u8 reserved_6[0xe0];
3762 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
3763 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
3764 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
3767 struct mlx5_ifc_query_flow_group_out_bits {
3769 u8 reserved_0[0x18];
3773 u8 reserved_1[0xa0];
3775 u8 start_flow_index[0x20];
3777 u8 reserved_2[0x20];
3779 u8 end_flow_index[0x20];
3781 u8 reserved_3[0xa0];
3783 u8 reserved_4[0x18];
3784 u8 match_criteria_enable[0x8];
3786 struct mlx5_ifc_fte_match_param_bits match_criteria;
3788 u8 reserved_5[0xe00];
3791 struct mlx5_ifc_query_flow_group_in_bits {
3793 u8 reserved_0[0x10];
3795 u8 reserved_1[0x10];
3798 u8 reserved_2[0x40];
3801 u8 reserved_3[0x18];
3808 u8 reserved_5[0x120];
3811 struct mlx5_ifc_query_esw_vport_context_out_bits {
3813 u8 reserved_0[0x18];
3817 u8 reserved_1[0x40];
3819 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3822 struct mlx5_ifc_query_esw_vport_context_in_bits {
3824 u8 reserved_0[0x10];
3826 u8 reserved_1[0x10];
3829 u8 other_vport[0x1];
3831 u8 vport_number[0x10];
3833 u8 reserved_3[0x20];
3836 struct mlx5_ifc_modify_esw_vport_context_out_bits {
3838 u8 reserved_0[0x18];
3842 u8 reserved_1[0x40];
3845 struct mlx5_ifc_esw_vport_context_fields_select_bits {
3847 u8 vport_cvlan_insert[0x1];
3848 u8 vport_svlan_insert[0x1];
3849 u8 vport_cvlan_strip[0x1];
3850 u8 vport_svlan_strip[0x1];
3853 struct mlx5_ifc_modify_esw_vport_context_in_bits {
3855 u8 reserved_0[0x10];
3857 u8 reserved_1[0x10];
3860 u8 other_vport[0x1];
3862 u8 vport_number[0x10];
3864 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
3866 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3869 struct mlx5_ifc_query_eq_out_bits {
3871 u8 reserved_0[0x18];
3875 u8 reserved_1[0x40];
3877 struct mlx5_ifc_eqc_bits eq_context_entry;
3879 u8 reserved_2[0x40];
3881 u8 event_bitmask[0x40];
3883 u8 reserved_3[0x580];
3888 struct mlx5_ifc_query_eq_in_bits {
3890 u8 reserved_0[0x10];
3892 u8 reserved_1[0x10];
3895 u8 reserved_2[0x18];
3898 u8 reserved_3[0x20];
3901 struct mlx5_ifc_query_dct_out_bits {
3903 u8 reserved_0[0x18];
3907 u8 reserved_1[0x40];
3909 struct mlx5_ifc_dctc_bits dct_context_entry;
3911 u8 reserved_2[0x180];
3914 struct mlx5_ifc_query_dct_in_bits {
3916 u8 reserved_0[0x10];
3918 u8 reserved_1[0x10];
3924 u8 reserved_3[0x20];
3927 struct mlx5_ifc_query_cq_out_bits {
3929 u8 reserved_0[0x18];
3933 u8 reserved_1[0x40];
3935 struct mlx5_ifc_cqc_bits cq_context;
3937 u8 reserved_2[0x600];
3942 struct mlx5_ifc_query_cq_in_bits {
3944 u8 reserved_0[0x10];
3946 u8 reserved_1[0x10];
3952 u8 reserved_3[0x20];
3955 struct mlx5_ifc_query_cong_status_out_bits {
3957 u8 reserved_0[0x18];
3961 u8 reserved_1[0x20];
3965 u8 reserved_2[0x1e];
3968 struct mlx5_ifc_query_cong_status_in_bits {
3970 u8 reserved_0[0x10];
3972 u8 reserved_1[0x10];
3975 u8 reserved_2[0x18];
3977 u8 cong_protocol[0x4];
3979 u8 reserved_3[0x20];
3982 struct mlx5_ifc_query_cong_statistics_out_bits {
3984 u8 reserved_0[0x18];
3988 u8 reserved_1[0x40];
3994 u8 cnp_ignored_high[0x20];
3996 u8 cnp_ignored_low[0x20];
3998 u8 cnp_handled_high[0x20];
4000 u8 cnp_handled_low[0x20];
4002 u8 reserved_2[0x100];
4004 u8 time_stamp_high[0x20];
4006 u8 time_stamp_low[0x20];
4008 u8 accumulators_period[0x20];
4010 u8 ecn_marked_roce_packets_high[0x20];
4012 u8 ecn_marked_roce_packets_low[0x20];
4014 u8 cnps_sent_high[0x20];
4016 u8 cnps_sent_low[0x20];
4018 u8 reserved_3[0x560];
4021 struct mlx5_ifc_query_cong_statistics_in_bits {
4023 u8 reserved_0[0x10];
4025 u8 reserved_1[0x10];
4029 u8 reserved_2[0x1f];
4031 u8 reserved_3[0x20];
4034 struct mlx5_ifc_query_cong_params_out_bits {
4036 u8 reserved_0[0x18];
4040 u8 reserved_1[0x40];
4042 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4045 struct mlx5_ifc_query_cong_params_in_bits {
4047 u8 reserved_0[0x10];
4049 u8 reserved_1[0x10];
4052 u8 reserved_2[0x1c];
4053 u8 cong_protocol[0x4];
4055 u8 reserved_3[0x20];
4058 struct mlx5_ifc_query_adapter_out_bits {
4060 u8 reserved_0[0x18];
4064 u8 reserved_1[0x40];
4066 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4069 struct mlx5_ifc_query_adapter_in_bits {
4071 u8 reserved_0[0x10];
4073 u8 reserved_1[0x10];
4076 u8 reserved_2[0x40];
4079 struct mlx5_ifc_qp_2rst_out_bits {
4081 u8 reserved_0[0x18];
4085 u8 reserved_1[0x40];
4088 struct mlx5_ifc_qp_2rst_in_bits {
4090 u8 reserved_0[0x10];
4092 u8 reserved_1[0x10];
4098 u8 reserved_3[0x20];
4101 struct mlx5_ifc_qp_2err_out_bits {
4103 u8 reserved_0[0x18];
4107 u8 reserved_1[0x40];
4110 struct mlx5_ifc_qp_2err_in_bits {
4112 u8 reserved_0[0x10];
4114 u8 reserved_1[0x10];
4120 u8 reserved_3[0x20];
4123 struct mlx5_ifc_page_fault_resume_out_bits {
4125 u8 reserved_0[0x18];
4129 u8 reserved_1[0x40];
4132 struct mlx5_ifc_page_fault_resume_in_bits {
4134 u8 reserved_0[0x10];
4136 u8 reserved_1[0x10];
4146 u8 reserved_3[0x20];
4149 struct mlx5_ifc_nop_out_bits {
4151 u8 reserved_0[0x18];
4155 u8 reserved_1[0x40];
4158 struct mlx5_ifc_nop_in_bits {
4160 u8 reserved_0[0x10];
4162 u8 reserved_1[0x10];
4165 u8 reserved_2[0x40];
4168 struct mlx5_ifc_modify_vport_state_out_bits {
4170 u8 reserved_0[0x18];
4174 u8 reserved_1[0x40];
4177 struct mlx5_ifc_modify_vport_state_in_bits {
4179 u8 reserved_0[0x10];
4181 u8 reserved_1[0x10];
4184 u8 other_vport[0x1];
4186 u8 vport_number[0x10];
4188 u8 reserved_3[0x18];
4189 u8 admin_state[0x4];
4193 struct mlx5_ifc_modify_tis_out_bits {
4195 u8 reserved_0[0x18];
4199 u8 reserved_1[0x40];
4202 struct mlx5_ifc_modify_tis_in_bits {
4204 u8 reserved_0[0x10];
4206 u8 reserved_1[0x10];
4212 u8 reserved_3[0x20];
4214 u8 modify_bitmask[0x40];
4216 u8 reserved_4[0x40];
4218 struct mlx5_ifc_tisc_bits ctx;
4221 struct mlx5_ifc_modify_tir_bitmask_bits {
4222 u8 reserved_0[0x20];
4224 u8 reserved_1[0x1b];
4230 struct mlx5_ifc_modify_tir_out_bits {
4232 u8 reserved_0[0x18];
4236 u8 reserved_1[0x40];
4239 struct mlx5_ifc_modify_tir_in_bits {
4241 u8 reserved_0[0x10];
4243 u8 reserved_1[0x10];
4249 u8 reserved_3[0x20];
4251 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4253 u8 reserved_4[0x40];
4255 struct mlx5_ifc_tirc_bits ctx;
4258 struct mlx5_ifc_modify_sq_out_bits {
4260 u8 reserved_0[0x18];
4264 u8 reserved_1[0x40];
4267 struct mlx5_ifc_modify_sq_in_bits {
4269 u8 reserved_0[0x10];
4271 u8 reserved_1[0x10];
4278 u8 reserved_3[0x20];
4280 u8 modify_bitmask[0x40];
4282 u8 reserved_4[0x40];
4284 struct mlx5_ifc_sqc_bits ctx;
4287 struct mlx5_ifc_modify_rqt_out_bits {
4289 u8 reserved_0[0x18];
4293 u8 reserved_1[0x40];
4296 struct mlx5_ifc_rqt_bitmask_bits {
4303 struct mlx5_ifc_modify_rqt_in_bits {
4305 u8 reserved_0[0x10];
4307 u8 reserved_1[0x10];
4313 u8 reserved_3[0x20];
4315 struct mlx5_ifc_rqt_bitmask_bits bitmask;
4317 u8 reserved_4[0x40];
4319 struct mlx5_ifc_rqtc_bits ctx;
4322 struct mlx5_ifc_modify_rq_out_bits {
4324 u8 reserved_0[0x18];
4328 u8 reserved_1[0x40];
4331 struct mlx5_ifc_modify_rq_in_bits {
4333 u8 reserved_0[0x10];
4335 u8 reserved_1[0x10];
4342 u8 reserved_3[0x20];
4344 u8 modify_bitmask[0x40];
4346 u8 reserved_4[0x40];
4348 struct mlx5_ifc_rqc_bits ctx;
4351 struct mlx5_ifc_modify_rmp_out_bits {
4353 u8 reserved_0[0x18];
4357 u8 reserved_1[0x40];
4360 struct mlx5_ifc_rmp_bitmask_bits {
4367 struct mlx5_ifc_modify_rmp_in_bits {
4369 u8 reserved_0[0x10];
4371 u8 reserved_1[0x10];
4378 u8 reserved_3[0x20];
4380 struct mlx5_ifc_rmp_bitmask_bits bitmask;
4382 u8 reserved_4[0x40];
4384 struct mlx5_ifc_rmpc_bits ctx;
4387 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4389 u8 reserved_0[0x18];
4393 u8 reserved_1[0x40];
4396 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4397 u8 reserved_0[0x19];
4399 u8 change_event[0x1];
4401 u8 permanent_address[0x1];
4402 u8 addresses_list[0x1];
4407 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4409 u8 reserved_0[0x10];
4411 u8 reserved_1[0x10];
4414 u8 other_vport[0x1];
4416 u8 vport_number[0x10];
4418 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4420 u8 reserved_3[0x780];
4422 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4425 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4427 u8 reserved_0[0x18];
4431 u8 reserved_1[0x40];
4434 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4436 u8 reserved_0[0x10];
4438 u8 reserved_1[0x10];
4441 u8 other_vport[0x1];
4444 u8 vport_number[0x10];
4446 u8 reserved_3[0x20];
4448 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4451 struct mlx5_ifc_modify_cq_out_bits {
4453 u8 reserved_0[0x18];
4457 u8 reserved_1[0x40];
4461 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4462 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4465 struct mlx5_ifc_modify_cq_in_bits {
4467 u8 reserved_0[0x10];
4469 u8 reserved_1[0x10];
4475 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4477 struct mlx5_ifc_cqc_bits cq_context;
4479 u8 reserved_3[0x600];
4484 struct mlx5_ifc_modify_cong_status_out_bits {
4486 u8 reserved_0[0x18];
4490 u8 reserved_1[0x40];
4493 struct mlx5_ifc_modify_cong_status_in_bits {
4495 u8 reserved_0[0x10];
4497 u8 reserved_1[0x10];
4500 u8 reserved_2[0x18];
4502 u8 cong_protocol[0x4];
4506 u8 reserved_3[0x1e];
4509 struct mlx5_ifc_modify_cong_params_out_bits {
4511 u8 reserved_0[0x18];
4515 u8 reserved_1[0x40];
4518 struct mlx5_ifc_modify_cong_params_in_bits {
4520 u8 reserved_0[0x10];
4522 u8 reserved_1[0x10];
4525 u8 reserved_2[0x1c];
4526 u8 cong_protocol[0x4];
4528 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4530 u8 reserved_3[0x80];
4532 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4535 struct mlx5_ifc_manage_pages_out_bits {
4537 u8 reserved_0[0x18];
4541 u8 output_num_entries[0x20];
4543 u8 reserved_1[0x20];
4549 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4550 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4551 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4554 struct mlx5_ifc_manage_pages_in_bits {
4556 u8 reserved_0[0x10];
4558 u8 reserved_1[0x10];
4561 u8 reserved_2[0x10];
4562 u8 function_id[0x10];
4564 u8 input_num_entries[0x20];
4569 struct mlx5_ifc_mad_ifc_out_bits {
4571 u8 reserved_0[0x18];
4575 u8 reserved_1[0x40];
4577 u8 response_mad_packet[256][0x8];
4580 struct mlx5_ifc_mad_ifc_in_bits {
4582 u8 reserved_0[0x10];
4584 u8 reserved_1[0x10];
4587 u8 remote_lid[0x10];
4591 u8 reserved_3[0x20];
4596 struct mlx5_ifc_init_hca_out_bits {
4598 u8 reserved_0[0x18];
4602 u8 reserved_1[0x40];
4605 struct mlx5_ifc_init_hca_in_bits {
4607 u8 reserved_0[0x10];
4609 u8 reserved_1[0x10];
4612 u8 reserved_2[0x40];
4615 struct mlx5_ifc_init2rtr_qp_out_bits {
4617 u8 reserved_0[0x18];
4621 u8 reserved_1[0x40];
4624 struct mlx5_ifc_init2rtr_qp_in_bits {
4626 u8 reserved_0[0x10];
4628 u8 reserved_1[0x10];
4634 u8 reserved_3[0x20];
4636 u8 opt_param_mask[0x20];
4638 u8 reserved_4[0x20];
4640 struct mlx5_ifc_qpc_bits qpc;
4642 u8 reserved_5[0x80];
4645 struct mlx5_ifc_init2init_qp_out_bits {
4647 u8 reserved_0[0x18];
4651 u8 reserved_1[0x40];
4654 struct mlx5_ifc_init2init_qp_in_bits {
4656 u8 reserved_0[0x10];
4658 u8 reserved_1[0x10];
4664 u8 reserved_3[0x20];
4666 u8 opt_param_mask[0x20];
4668 u8 reserved_4[0x20];
4670 struct mlx5_ifc_qpc_bits qpc;
4672 u8 reserved_5[0x80];
4675 struct mlx5_ifc_get_dropped_packet_log_out_bits {
4677 u8 reserved_0[0x18];
4681 u8 reserved_1[0x40];
4683 u8 packet_headers_log[128][0x8];
4685 u8 packet_syndrome[64][0x8];
4688 struct mlx5_ifc_get_dropped_packet_log_in_bits {
4690 u8 reserved_0[0x10];
4692 u8 reserved_1[0x10];
4695 u8 reserved_2[0x40];
4698 struct mlx5_ifc_gen_eqe_in_bits {
4700 u8 reserved_0[0x10];
4702 u8 reserved_1[0x10];
4705 u8 reserved_2[0x18];
4708 u8 reserved_3[0x20];
4713 struct mlx5_ifc_gen_eq_out_bits {
4715 u8 reserved_0[0x18];
4719 u8 reserved_1[0x40];
4722 struct mlx5_ifc_enable_hca_out_bits {
4724 u8 reserved_0[0x18];
4728 u8 reserved_1[0x20];
4731 struct mlx5_ifc_enable_hca_in_bits {
4733 u8 reserved_0[0x10];
4735 u8 reserved_1[0x10];
4738 u8 reserved_2[0x10];
4739 u8 function_id[0x10];
4741 u8 reserved_3[0x20];
4744 struct mlx5_ifc_drain_dct_out_bits {
4746 u8 reserved_0[0x18];
4750 u8 reserved_1[0x40];
4753 struct mlx5_ifc_drain_dct_in_bits {
4755 u8 reserved_0[0x10];
4757 u8 reserved_1[0x10];
4763 u8 reserved_3[0x20];
4766 struct mlx5_ifc_disable_hca_out_bits {
4768 u8 reserved_0[0x18];
4772 u8 reserved_1[0x20];
4775 struct mlx5_ifc_disable_hca_in_bits {
4777 u8 reserved_0[0x10];
4779 u8 reserved_1[0x10];
4782 u8 reserved_2[0x10];
4783 u8 function_id[0x10];
4785 u8 reserved_3[0x20];
4788 struct mlx5_ifc_detach_from_mcg_out_bits {
4790 u8 reserved_0[0x18];
4794 u8 reserved_1[0x40];
4797 struct mlx5_ifc_detach_from_mcg_in_bits {
4799 u8 reserved_0[0x10];
4801 u8 reserved_1[0x10];
4807 u8 reserved_3[0x20];
4809 u8 multicast_gid[16][0x8];
4812 struct mlx5_ifc_destroy_xrc_srq_out_bits {
4814 u8 reserved_0[0x18];
4818 u8 reserved_1[0x40];
4821 struct mlx5_ifc_destroy_xrc_srq_in_bits {
4823 u8 reserved_0[0x10];
4825 u8 reserved_1[0x10];
4831 u8 reserved_3[0x20];
4834 struct mlx5_ifc_destroy_tis_out_bits {
4836 u8 reserved_0[0x18];
4840 u8 reserved_1[0x40];
4843 struct mlx5_ifc_destroy_tis_in_bits {
4845 u8 reserved_0[0x10];
4847 u8 reserved_1[0x10];
4853 u8 reserved_3[0x20];
4856 struct mlx5_ifc_destroy_tir_out_bits {
4858 u8 reserved_0[0x18];
4862 u8 reserved_1[0x40];
4865 struct mlx5_ifc_destroy_tir_in_bits {
4867 u8 reserved_0[0x10];
4869 u8 reserved_1[0x10];
4875 u8 reserved_3[0x20];
4878 struct mlx5_ifc_destroy_srq_out_bits {
4880 u8 reserved_0[0x18];
4884 u8 reserved_1[0x40];
4887 struct mlx5_ifc_destroy_srq_in_bits {
4889 u8 reserved_0[0x10];
4891 u8 reserved_1[0x10];
4897 u8 reserved_3[0x20];
4900 struct mlx5_ifc_destroy_sq_out_bits {
4902 u8 reserved_0[0x18];
4906 u8 reserved_1[0x40];
4909 struct mlx5_ifc_destroy_sq_in_bits {
4911 u8 reserved_0[0x10];
4913 u8 reserved_1[0x10];
4919 u8 reserved_3[0x20];
4922 struct mlx5_ifc_destroy_rqt_out_bits {
4924 u8 reserved_0[0x18];
4928 u8 reserved_1[0x40];
4931 struct mlx5_ifc_destroy_rqt_in_bits {
4933 u8 reserved_0[0x10];
4935 u8 reserved_1[0x10];
4941 u8 reserved_3[0x20];
4944 struct mlx5_ifc_destroy_rq_out_bits {
4946 u8 reserved_0[0x18];
4950 u8 reserved_1[0x40];
4953 struct mlx5_ifc_destroy_rq_in_bits {
4955 u8 reserved_0[0x10];
4957 u8 reserved_1[0x10];
4963 u8 reserved_3[0x20];
4966 struct mlx5_ifc_destroy_rmp_out_bits {
4968 u8 reserved_0[0x18];
4972 u8 reserved_1[0x40];
4975 struct mlx5_ifc_destroy_rmp_in_bits {
4977 u8 reserved_0[0x10];
4979 u8 reserved_1[0x10];
4985 u8 reserved_3[0x20];
4988 struct mlx5_ifc_destroy_qp_out_bits {
4990 u8 reserved_0[0x18];
4994 u8 reserved_1[0x40];
4997 struct mlx5_ifc_destroy_qp_in_bits {
4999 u8 reserved_0[0x10];
5001 u8 reserved_1[0x10];
5007 u8 reserved_3[0x20];
5010 struct mlx5_ifc_destroy_psv_out_bits {
5012 u8 reserved_0[0x18];
5016 u8 reserved_1[0x40];
5019 struct mlx5_ifc_destroy_psv_in_bits {
5021 u8 reserved_0[0x10];
5023 u8 reserved_1[0x10];
5029 u8 reserved_3[0x20];
5032 struct mlx5_ifc_destroy_mkey_out_bits {
5034 u8 reserved_0[0x18];
5038 u8 reserved_1[0x40];
5041 struct mlx5_ifc_destroy_mkey_in_bits {
5043 u8 reserved_0[0x10];
5045 u8 reserved_1[0x10];
5049 u8 mkey_index[0x18];
5051 u8 reserved_3[0x20];
5054 struct mlx5_ifc_destroy_flow_table_out_bits {
5056 u8 reserved_0[0x18];
5060 u8 reserved_1[0x40];
5063 struct mlx5_ifc_destroy_flow_table_in_bits {
5065 u8 reserved_0[0x10];
5067 u8 reserved_1[0x10];
5070 u8 reserved_2[0x40];
5073 u8 reserved_3[0x18];
5078 u8 reserved_5[0x140];
5081 struct mlx5_ifc_destroy_flow_group_out_bits {
5083 u8 reserved_0[0x18];
5087 u8 reserved_1[0x40];
5090 struct mlx5_ifc_destroy_flow_group_in_bits {
5092 u8 reserved_0[0x10];
5094 u8 reserved_1[0x10];
5097 u8 reserved_2[0x40];
5100 u8 reserved_3[0x18];
5107 u8 reserved_5[0x120];
5110 struct mlx5_ifc_destroy_eq_out_bits {
5112 u8 reserved_0[0x18];
5116 u8 reserved_1[0x40];
5119 struct mlx5_ifc_destroy_eq_in_bits {
5121 u8 reserved_0[0x10];
5123 u8 reserved_1[0x10];
5126 u8 reserved_2[0x18];
5129 u8 reserved_3[0x20];
5132 struct mlx5_ifc_destroy_dct_out_bits {
5134 u8 reserved_0[0x18];
5138 u8 reserved_1[0x40];
5141 struct mlx5_ifc_destroy_dct_in_bits {
5143 u8 reserved_0[0x10];
5145 u8 reserved_1[0x10];
5151 u8 reserved_3[0x20];
5154 struct mlx5_ifc_destroy_cq_out_bits {
5156 u8 reserved_0[0x18];
5160 u8 reserved_1[0x40];
5163 struct mlx5_ifc_destroy_cq_in_bits {
5165 u8 reserved_0[0x10];
5167 u8 reserved_1[0x10];
5173 u8 reserved_3[0x20];
5176 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5178 u8 reserved_0[0x18];
5182 u8 reserved_1[0x40];
5185 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5187 u8 reserved_0[0x10];
5189 u8 reserved_1[0x10];
5192 u8 reserved_2[0x20];
5194 u8 reserved_3[0x10];
5195 u8 vxlan_udp_port[0x10];
5198 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5200 u8 reserved_0[0x18];
5204 u8 reserved_1[0x40];
5207 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5209 u8 reserved_0[0x10];
5211 u8 reserved_1[0x10];
5214 u8 reserved_2[0x60];
5217 u8 table_index[0x18];
5219 u8 reserved_4[0x140];
5222 struct mlx5_ifc_delete_fte_out_bits {
5224 u8 reserved_0[0x18];
5228 u8 reserved_1[0x40];
5231 struct mlx5_ifc_delete_fte_in_bits {
5233 u8 reserved_0[0x10];
5235 u8 reserved_1[0x10];
5238 u8 reserved_2[0x40];
5241 u8 reserved_3[0x18];
5246 u8 reserved_5[0x40];
5248 u8 flow_index[0x20];
5250 u8 reserved_6[0xe0];
5253 struct mlx5_ifc_dealloc_xrcd_out_bits {
5255 u8 reserved_0[0x18];
5259 u8 reserved_1[0x40];
5262 struct mlx5_ifc_dealloc_xrcd_in_bits {
5264 u8 reserved_0[0x10];
5266 u8 reserved_1[0x10];
5272 u8 reserved_3[0x20];
5275 struct mlx5_ifc_dealloc_uar_out_bits {
5277 u8 reserved_0[0x18];
5281 u8 reserved_1[0x40];
5284 struct mlx5_ifc_dealloc_uar_in_bits {
5286 u8 reserved_0[0x10];
5288 u8 reserved_1[0x10];
5294 u8 reserved_3[0x20];
5297 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5299 u8 reserved_0[0x18];
5303 u8 reserved_1[0x40];
5306 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5308 u8 reserved_0[0x10];
5310 u8 reserved_1[0x10];
5314 u8 transport_domain[0x18];
5316 u8 reserved_3[0x20];
5319 struct mlx5_ifc_dealloc_q_counter_out_bits {
5321 u8 reserved_0[0x18];
5325 u8 reserved_1[0x40];
5328 struct mlx5_ifc_dealloc_q_counter_in_bits {
5330 u8 reserved_0[0x10];
5332 u8 reserved_1[0x10];
5335 u8 reserved_2[0x18];
5336 u8 counter_set_id[0x8];
5338 u8 reserved_3[0x20];
5341 struct mlx5_ifc_dealloc_pd_out_bits {
5343 u8 reserved_0[0x18];
5347 u8 reserved_1[0x40];
5350 struct mlx5_ifc_dealloc_pd_in_bits {
5352 u8 reserved_0[0x10];
5354 u8 reserved_1[0x10];
5360 u8 reserved_3[0x20];
5363 struct mlx5_ifc_create_xrc_srq_out_bits {
5365 u8 reserved_0[0x18];
5372 u8 reserved_2[0x20];
5375 struct mlx5_ifc_create_xrc_srq_in_bits {
5377 u8 reserved_0[0x10];
5379 u8 reserved_1[0x10];
5382 u8 reserved_2[0x40];
5384 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5386 u8 reserved_3[0x600];
5391 struct mlx5_ifc_create_tis_out_bits {
5393 u8 reserved_0[0x18];
5400 u8 reserved_2[0x20];
5403 struct mlx5_ifc_create_tis_in_bits {
5405 u8 reserved_0[0x10];
5407 u8 reserved_1[0x10];
5410 u8 reserved_2[0xc0];
5412 struct mlx5_ifc_tisc_bits ctx;
5415 struct mlx5_ifc_create_tir_out_bits {
5417 u8 reserved_0[0x18];
5424 u8 reserved_2[0x20];
5427 struct mlx5_ifc_create_tir_in_bits {
5429 u8 reserved_0[0x10];
5431 u8 reserved_1[0x10];
5434 u8 reserved_2[0xc0];
5436 struct mlx5_ifc_tirc_bits ctx;
5439 struct mlx5_ifc_create_srq_out_bits {
5441 u8 reserved_0[0x18];
5448 u8 reserved_2[0x20];
5451 struct mlx5_ifc_create_srq_in_bits {
5453 u8 reserved_0[0x10];
5455 u8 reserved_1[0x10];
5458 u8 reserved_2[0x40];
5460 struct mlx5_ifc_srqc_bits srq_context_entry;
5462 u8 reserved_3[0x600];
5467 struct mlx5_ifc_create_sq_out_bits {
5469 u8 reserved_0[0x18];
5476 u8 reserved_2[0x20];
5479 struct mlx5_ifc_create_sq_in_bits {
5481 u8 reserved_0[0x10];
5483 u8 reserved_1[0x10];
5486 u8 reserved_2[0xc0];
5488 struct mlx5_ifc_sqc_bits ctx;
5491 struct mlx5_ifc_create_rqt_out_bits {
5493 u8 reserved_0[0x18];
5500 u8 reserved_2[0x20];
5503 struct mlx5_ifc_create_rqt_in_bits {
5505 u8 reserved_0[0x10];
5507 u8 reserved_1[0x10];
5510 u8 reserved_2[0xc0];
5512 struct mlx5_ifc_rqtc_bits rqt_context;
5515 struct mlx5_ifc_create_rq_out_bits {
5517 u8 reserved_0[0x18];
5524 u8 reserved_2[0x20];
5527 struct mlx5_ifc_create_rq_in_bits {
5529 u8 reserved_0[0x10];
5531 u8 reserved_1[0x10];
5534 u8 reserved_2[0xc0];
5536 struct mlx5_ifc_rqc_bits ctx;
5539 struct mlx5_ifc_create_rmp_out_bits {
5541 u8 reserved_0[0x18];
5548 u8 reserved_2[0x20];
5551 struct mlx5_ifc_create_rmp_in_bits {
5553 u8 reserved_0[0x10];
5555 u8 reserved_1[0x10];
5558 u8 reserved_2[0xc0];
5560 struct mlx5_ifc_rmpc_bits ctx;
5563 struct mlx5_ifc_create_qp_out_bits {
5565 u8 reserved_0[0x18];
5572 u8 reserved_2[0x20];
5575 struct mlx5_ifc_create_qp_in_bits {
5577 u8 reserved_0[0x10];
5579 u8 reserved_1[0x10];
5582 u8 reserved_2[0x40];
5584 u8 opt_param_mask[0x20];
5586 u8 reserved_3[0x20];
5588 struct mlx5_ifc_qpc_bits qpc;
5590 u8 reserved_4[0x80];
5595 struct mlx5_ifc_create_psv_out_bits {
5597 u8 reserved_0[0x18];
5601 u8 reserved_1[0x40];
5604 u8 psv0_index[0x18];
5607 u8 psv1_index[0x18];
5610 u8 psv2_index[0x18];
5613 u8 psv3_index[0x18];
5616 struct mlx5_ifc_create_psv_in_bits {
5618 u8 reserved_0[0x10];
5620 u8 reserved_1[0x10];
5627 u8 reserved_3[0x20];
5630 struct mlx5_ifc_create_mkey_out_bits {
5632 u8 reserved_0[0x18];
5637 u8 mkey_index[0x18];
5639 u8 reserved_2[0x20];
5642 struct mlx5_ifc_create_mkey_in_bits {
5644 u8 reserved_0[0x10];
5646 u8 reserved_1[0x10];
5649 u8 reserved_2[0x20];
5652 u8 reserved_3[0x1f];
5654 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5656 u8 reserved_4[0x80];
5658 u8 translations_octword_actual_size[0x20];
5660 u8 reserved_5[0x560];
5662 u8 klm_pas_mtt[0][0x20];
5665 struct mlx5_ifc_create_flow_table_out_bits {
5667 u8 reserved_0[0x18];
5674 u8 reserved_2[0x20];
5677 struct mlx5_ifc_create_flow_table_in_bits {
5679 u8 reserved_0[0x10];
5681 u8 reserved_1[0x10];
5684 u8 reserved_2[0x40];
5687 u8 reserved_3[0x18];
5689 u8 reserved_4[0x20];
5692 u8 table_miss_mode[0x4];
5698 u8 table_miss_id[0x18];
5700 u8 reserved_8[0x100];
5703 struct mlx5_ifc_create_flow_group_out_bits {
5705 u8 reserved_0[0x18];
5712 u8 reserved_2[0x20];
5716 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5717 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5718 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5721 struct mlx5_ifc_create_flow_group_in_bits {
5723 u8 reserved_0[0x10];
5725 u8 reserved_1[0x10];
5728 u8 reserved_2[0x40];
5731 u8 reserved_3[0x18];
5736 u8 reserved_5[0x20];
5738 u8 start_flow_index[0x20];
5740 u8 reserved_6[0x20];
5742 u8 end_flow_index[0x20];
5744 u8 reserved_7[0xa0];
5746 u8 reserved_8[0x18];
5747 u8 match_criteria_enable[0x8];
5749 struct mlx5_ifc_fte_match_param_bits match_criteria;
5751 u8 reserved_9[0xe00];
5754 struct mlx5_ifc_create_eq_out_bits {
5756 u8 reserved_0[0x18];
5760 u8 reserved_1[0x18];
5763 u8 reserved_2[0x20];
5766 struct mlx5_ifc_create_eq_in_bits {
5768 u8 reserved_0[0x10];
5770 u8 reserved_1[0x10];
5773 u8 reserved_2[0x40];
5775 struct mlx5_ifc_eqc_bits eq_context_entry;
5777 u8 reserved_3[0x40];
5779 u8 event_bitmask[0x40];
5781 u8 reserved_4[0x580];
5786 struct mlx5_ifc_create_dct_out_bits {
5788 u8 reserved_0[0x18];
5795 u8 reserved_2[0x20];
5798 struct mlx5_ifc_create_dct_in_bits {
5800 u8 reserved_0[0x10];
5802 u8 reserved_1[0x10];
5805 u8 reserved_2[0x40];
5807 struct mlx5_ifc_dctc_bits dct_context_entry;
5809 u8 reserved_3[0x180];
5812 struct mlx5_ifc_create_cq_out_bits {
5814 u8 reserved_0[0x18];
5821 u8 reserved_2[0x20];
5824 struct mlx5_ifc_create_cq_in_bits {
5826 u8 reserved_0[0x10];
5828 u8 reserved_1[0x10];
5831 u8 reserved_2[0x40];
5833 struct mlx5_ifc_cqc_bits cq_context;
5835 u8 reserved_3[0x600];
5840 struct mlx5_ifc_config_int_moderation_out_bits {
5842 u8 reserved_0[0x18];
5848 u8 int_vector[0x10];
5850 u8 reserved_2[0x20];
5854 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
5855 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
5858 struct mlx5_ifc_config_int_moderation_in_bits {
5860 u8 reserved_0[0x10];
5862 u8 reserved_1[0x10];
5867 u8 int_vector[0x10];
5869 u8 reserved_3[0x20];
5872 struct mlx5_ifc_attach_to_mcg_out_bits {
5874 u8 reserved_0[0x18];
5878 u8 reserved_1[0x40];
5881 struct mlx5_ifc_attach_to_mcg_in_bits {
5883 u8 reserved_0[0x10];
5885 u8 reserved_1[0x10];
5891 u8 reserved_3[0x20];
5893 u8 multicast_gid[16][0x8];
5896 struct mlx5_ifc_arm_xrc_srq_out_bits {
5898 u8 reserved_0[0x18];
5902 u8 reserved_1[0x40];
5906 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
5909 struct mlx5_ifc_arm_xrc_srq_in_bits {
5911 u8 reserved_0[0x10];
5913 u8 reserved_1[0x10];
5919 u8 reserved_3[0x10];
5923 struct mlx5_ifc_arm_rq_out_bits {
5925 u8 reserved_0[0x18];
5929 u8 reserved_1[0x40];
5933 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1,
5936 struct mlx5_ifc_arm_rq_in_bits {
5938 u8 reserved_0[0x10];
5940 u8 reserved_1[0x10];
5944 u8 srq_number[0x18];
5946 u8 reserved_3[0x10];
5950 struct mlx5_ifc_arm_dct_out_bits {
5952 u8 reserved_0[0x18];
5956 u8 reserved_1[0x40];
5959 struct mlx5_ifc_arm_dct_in_bits {
5961 u8 reserved_0[0x10];
5963 u8 reserved_1[0x10];
5967 u8 dct_number[0x18];
5969 u8 reserved_3[0x20];
5972 struct mlx5_ifc_alloc_xrcd_out_bits {
5974 u8 reserved_0[0x18];
5981 u8 reserved_2[0x20];
5984 struct mlx5_ifc_alloc_xrcd_in_bits {
5986 u8 reserved_0[0x10];
5988 u8 reserved_1[0x10];
5991 u8 reserved_2[0x40];
5994 struct mlx5_ifc_alloc_uar_out_bits {
5996 u8 reserved_0[0x18];
6003 u8 reserved_2[0x20];
6006 struct mlx5_ifc_alloc_uar_in_bits {
6008 u8 reserved_0[0x10];
6010 u8 reserved_1[0x10];
6013 u8 reserved_2[0x40];
6016 struct mlx5_ifc_alloc_transport_domain_out_bits {
6018 u8 reserved_0[0x18];
6023 u8 transport_domain[0x18];
6025 u8 reserved_2[0x20];
6028 struct mlx5_ifc_alloc_transport_domain_in_bits {
6030 u8 reserved_0[0x10];
6032 u8 reserved_1[0x10];
6035 u8 reserved_2[0x40];
6038 struct mlx5_ifc_alloc_q_counter_out_bits {
6040 u8 reserved_0[0x18];
6044 u8 reserved_1[0x18];
6045 u8 counter_set_id[0x8];
6047 u8 reserved_2[0x20];
6050 struct mlx5_ifc_alloc_q_counter_in_bits {
6052 u8 reserved_0[0x10];
6054 u8 reserved_1[0x10];
6057 u8 reserved_2[0x40];
6060 struct mlx5_ifc_alloc_pd_out_bits {
6062 u8 reserved_0[0x18];
6069 u8 reserved_2[0x20];
6072 struct mlx5_ifc_alloc_pd_in_bits {
6074 u8 reserved_0[0x10];
6076 u8 reserved_1[0x10];
6079 u8 reserved_2[0x40];
6082 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6084 u8 reserved_0[0x18];
6088 u8 reserved_1[0x40];
6091 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6093 u8 reserved_0[0x10];
6095 u8 reserved_1[0x10];
6098 u8 reserved_2[0x20];
6100 u8 reserved_3[0x10];
6101 u8 vxlan_udp_port[0x10];
6104 struct mlx5_ifc_access_register_out_bits {
6106 u8 reserved_0[0x18];
6110 u8 reserved_1[0x40];
6112 u8 register_data[0][0x20];
6116 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
6117 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
6120 struct mlx5_ifc_access_register_in_bits {
6122 u8 reserved_0[0x10];
6124 u8 reserved_1[0x10];
6127 u8 reserved_2[0x10];
6128 u8 register_id[0x10];
6132 u8 register_data[0][0x20];
6135 struct mlx5_ifc_sltp_reg_bits {
6144 u8 reserved_2[0x20];
6153 u8 ob_preemp_mode[0x4];
6157 u8 reserved_5[0x20];
6160 struct mlx5_ifc_slrg_reg_bits {
6169 u8 time_to_link_up[0x10];
6171 u8 grade_lane_speed[0x4];
6173 u8 grade_version[0x8];
6177 u8 height_grade_type[0x4];
6178 u8 height_grade[0x18];
6183 u8 reserved_4[0x10];
6184 u8 height_sigma[0x10];
6186 u8 reserved_5[0x20];
6189 u8 phase_grade_type[0x4];
6190 u8 phase_grade[0x18];
6193 u8 phase_eo_pos[0x8];
6195 u8 phase_eo_neg[0x8];
6197 u8 ffe_set_tested[0x10];
6198 u8 test_errors_per_lane[0x10];
6201 struct mlx5_ifc_pvlc_reg_bits {
6204 u8 reserved_1[0x10];
6206 u8 reserved_2[0x1c];
6209 u8 reserved_3[0x1c];
6212 u8 reserved_4[0x1c];
6213 u8 vl_operational[0x4];
6216 struct mlx5_ifc_pude_reg_bits {
6220 u8 admin_status[0x4];
6222 u8 oper_status[0x4];
6224 u8 reserved_2[0x60];
6227 struct mlx5_ifc_ptys_reg_bits {
6233 u8 reserved_2[0x40];
6235 u8 eth_proto_capability[0x20];
6237 u8 ib_link_width_capability[0x10];
6238 u8 ib_proto_capability[0x10];
6240 u8 reserved_3[0x20];
6242 u8 eth_proto_admin[0x20];
6244 u8 ib_link_width_admin[0x10];
6245 u8 ib_proto_admin[0x10];
6247 u8 reserved_4[0x20];
6249 u8 eth_proto_oper[0x20];
6251 u8 ib_link_width_oper[0x10];
6252 u8 ib_proto_oper[0x10];
6254 u8 reserved_5[0x20];
6256 u8 eth_proto_lp_advertise[0x20];
6258 u8 reserved_6[0x60];
6261 struct mlx5_ifc_ptas_reg_bits {
6262 u8 reserved_0[0x20];
6264 u8 algorithm_options[0x10];
6266 u8 repetitions_mode[0x4];
6267 u8 num_of_repetitions[0x8];
6269 u8 grade_version[0x8];
6270 u8 height_grade_type[0x4];
6271 u8 phase_grade_type[0x4];
6272 u8 height_grade_weight[0x8];
6273 u8 phase_grade_weight[0x8];
6275 u8 gisim_measure_bits[0x10];
6276 u8 adaptive_tap_measure_bits[0x10];
6278 u8 ber_bath_high_error_threshold[0x10];
6279 u8 ber_bath_mid_error_threshold[0x10];
6281 u8 ber_bath_low_error_threshold[0x10];
6282 u8 one_ratio_high_threshold[0x10];
6284 u8 one_ratio_high_mid_threshold[0x10];
6285 u8 one_ratio_low_mid_threshold[0x10];
6287 u8 one_ratio_low_threshold[0x10];
6288 u8 ndeo_error_threshold[0x10];
6290 u8 mixer_offset_step_size[0x10];
6292 u8 mix90_phase_for_voltage_bath[0x8];
6294 u8 mixer_offset_start[0x10];
6295 u8 mixer_offset_end[0x10];
6297 u8 reserved_3[0x15];
6298 u8 ber_test_time[0xb];
6301 struct mlx5_ifc_pspa_reg_bits {
6307 u8 reserved_1[0x20];
6310 struct mlx5_ifc_pqdr_reg_bits {
6318 u8 reserved_3[0x20];
6320 u8 reserved_4[0x10];
6321 u8 min_threshold[0x10];
6323 u8 reserved_5[0x10];
6324 u8 max_threshold[0x10];
6326 u8 reserved_6[0x10];
6327 u8 mark_probability_denominator[0x10];
6329 u8 reserved_7[0x60];
6332 struct mlx5_ifc_ppsc_reg_bits {
6335 u8 reserved_1[0x10];
6337 u8 reserved_2[0x60];
6339 u8 reserved_3[0x1c];
6342 u8 reserved_4[0x1c];
6343 u8 wrps_status[0x4];
6346 u8 up_threshold[0x8];
6348 u8 down_threshold[0x8];
6350 u8 reserved_7[0x20];
6352 u8 reserved_8[0x1c];
6355 u8 reserved_9[0x1c];
6356 u8 srps_status[0x4];
6358 u8 reserved_10[0x40];
6361 struct mlx5_ifc_pplr_reg_bits {
6364 u8 reserved_1[0x10];
6372 struct mlx5_ifc_pplm_reg_bits {
6375 u8 reserved_1[0x10];
6377 u8 reserved_2[0x20];
6379 u8 port_profile_mode[0x8];
6380 u8 static_port_profile[0x8];
6381 u8 active_port_profile[0x8];
6384 u8 retransmission_active[0x8];
6385 u8 fec_mode_active[0x18];
6387 u8 reserved_4[0x20];
6390 struct mlx5_ifc_ppcnt_reg_bits {
6398 u8 reserved_1[0x1c];
6401 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6404 struct mlx5_ifc_ppad_reg_bits {
6413 u8 reserved_2[0x40];
6416 struct mlx5_ifc_pmtu_reg_bits {
6419 u8 reserved_1[0x10];
6422 u8 reserved_2[0x10];
6425 u8 reserved_3[0x10];
6428 u8 reserved_4[0x10];
6431 struct mlx5_ifc_pmpr_reg_bits {
6434 u8 reserved_1[0x10];
6436 u8 reserved_2[0x18];
6437 u8 attenuation_5g[0x8];
6439 u8 reserved_3[0x18];
6440 u8 attenuation_7g[0x8];
6442 u8 reserved_4[0x18];
6443 u8 attenuation_12g[0x8];
6446 struct mlx5_ifc_pmpe_reg_bits {
6450 u8 module_status[0x4];
6452 u8 reserved_2[0x60];
6455 struct mlx5_ifc_pmpc_reg_bits {
6456 u8 module_state_updated[32][0x8];
6459 struct mlx5_ifc_pmlpn_reg_bits {
6461 u8 mlpn_status[0x4];
6463 u8 reserved_1[0x10];
6466 u8 reserved_2[0x1f];
6469 struct mlx5_ifc_pmlp_reg_bits {
6476 u8 lane0_module_mapping[0x20];
6478 u8 lane1_module_mapping[0x20];
6480 u8 lane2_module_mapping[0x20];
6482 u8 lane3_module_mapping[0x20];
6484 u8 reserved_2[0x160];
6487 struct mlx5_ifc_pmaos_reg_bits {
6491 u8 admin_status[0x4];
6493 u8 oper_status[0x4];
6497 u8 reserved_3[0x1c];
6500 u8 reserved_4[0x40];
6503 struct mlx5_ifc_plpc_reg_bits {
6510 u8 reserved_3[0x10];
6511 u8 lane_speed[0x10];
6513 u8 reserved_4[0x17];
6515 u8 fec_mode_policy[0x8];
6517 u8 retransmission_capability[0x8];
6518 u8 fec_mode_capability[0x18];
6520 u8 retransmission_support_admin[0x8];
6521 u8 fec_mode_support_admin[0x18];
6523 u8 retransmission_request_admin[0x8];
6524 u8 fec_mode_request_admin[0x18];
6526 u8 reserved_5[0x80];
6529 struct mlx5_ifc_plib_reg_bits {
6535 u8 reserved_2[0x60];
6538 struct mlx5_ifc_plbf_reg_bits {
6544 u8 reserved_2[0x20];
6547 struct mlx5_ifc_pipg_reg_bits {
6550 u8 reserved_1[0x10];
6553 u8 reserved_2[0x19];
6558 struct mlx5_ifc_pifr_reg_bits {
6561 u8 reserved_1[0x10];
6563 u8 reserved_2[0xe0];
6565 u8 port_filter[8][0x20];
6567 u8 port_filter_update_en[8][0x20];
6570 struct mlx5_ifc_pfcc_reg_bits {
6573 u8 reserved_1[0x10];
6577 u8 prio_mask_tx[0x8];
6579 u8 prio_mask_rx[0x8];
6585 u8 reserved_5[0x10];
6591 u8 reserved_7[0x10];
6593 u8 reserved_8[0x80];
6596 struct mlx5_ifc_pelc_reg_bits {
6600 u8 reserved_1[0x10];
6603 u8 op_capability[0x8];
6609 u8 capability[0x40];
6615 u8 reserved_2[0x80];
6618 struct mlx5_ifc_peir_reg_bits {
6621 u8 reserved_1[0x10];
6624 u8 error_count[0x4];
6625 u8 reserved_3[0x10];
6633 struct mlx5_ifc_pcap_reg_bits {
6636 u8 reserved_1[0x10];
6638 u8 port_capability_mask[4][0x20];
6641 struct mlx5_ifc_paos_reg_bits {
6645 u8 admin_status[0x4];
6647 u8 oper_status[0x4];
6651 u8 reserved_2[0x1c];
6654 u8 reserved_3[0x40];
6657 struct mlx5_ifc_pamp_reg_bits {
6659 u8 opamp_group[0x8];
6661 u8 opamp_group_type[0x4];
6663 u8 start_index[0x10];
6665 u8 num_of_indices[0xc];
6667 u8 index_data[18][0x10];
6670 struct mlx5_ifc_lane_2_module_mapping_bits {
6679 struct mlx5_ifc_bufferx_reg_bits {
6686 u8 xoff_threshold[0x10];
6687 u8 xon_threshold[0x10];
6690 struct mlx5_ifc_set_node_in_bits {
6691 u8 node_description[64][0x8];
6694 struct mlx5_ifc_register_power_settings_bits {
6695 u8 reserved_0[0x18];
6696 u8 power_settings_level[0x8];
6698 u8 reserved_1[0x60];
6701 struct mlx5_ifc_register_host_endianness_bits {
6703 u8 reserved_0[0x1f];
6705 u8 reserved_1[0x60];
6708 struct mlx5_ifc_umr_pointer_desc_argument_bits {
6709 u8 reserved_0[0x20];
6713 u8 addressh_63_32[0x20];
6715 u8 addressl_31_0[0x20];
6718 struct mlx5_ifc_ud_adrs_vector_bits {
6723 u8 destination_qp_dct[0x18];
6725 u8 static_rate[0x4];
6726 u8 sl_eth_prio[0x4];
6729 u8 rlid_udp_sport[0x10];
6731 u8 reserved_1[0x20];
6733 u8 rmac_47_16[0x20];
6742 u8 src_addr_index[0x8];
6743 u8 flow_label[0x14];
6745 u8 rgid_rip[16][0x8];
6748 struct mlx5_ifc_pages_req_event_bits {
6749 u8 reserved_0[0x10];
6750 u8 function_id[0x10];
6754 u8 reserved_1[0xa0];
6757 struct mlx5_ifc_eqe_bits {
6761 u8 event_sub_type[0x8];
6763 u8 reserved_2[0xe0];
6765 union mlx5_ifc_event_auto_bits event_data;
6767 u8 reserved_3[0x10];
6774 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
6777 struct mlx5_ifc_cmd_queue_entry_bits {
6779 u8 reserved_0[0x18];
6781 u8 input_length[0x20];
6783 u8 input_mailbox_pointer_63_32[0x20];
6785 u8 input_mailbox_pointer_31_9[0x17];
6788 u8 command_input_inline_data[16][0x8];
6790 u8 command_output_inline_data[16][0x8];
6792 u8 output_mailbox_pointer_63_32[0x20];
6794 u8 output_mailbox_pointer_31_9[0x17];
6797 u8 output_length[0x20];
6806 struct mlx5_ifc_cmd_out_bits {
6808 u8 reserved_0[0x18];
6812 u8 command_output[0x20];
6815 struct mlx5_ifc_cmd_in_bits {
6817 u8 reserved_0[0x10];
6819 u8 reserved_1[0x10];
6822 u8 command[0][0x20];
6825 struct mlx5_ifc_cmd_if_box_bits {
6826 u8 mailbox_data[512][0x8];
6828 u8 reserved_0[0x180];
6830 u8 next_pointer_63_32[0x20];
6832 u8 next_pointer_31_10[0x16];
6835 u8 block_number[0x20];
6839 u8 ctrl_signature[0x8];
6843 struct mlx5_ifc_mtt_bits {
6844 u8 ptag_63_32[0x20];
6853 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
6854 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
6855 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
6859 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
6860 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
6861 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
6865 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
6866 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
6867 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
6868 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
6869 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
6870 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
6871 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
6872 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
6873 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
6874 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
6875 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
6878 struct mlx5_ifc_initial_seg_bits {
6879 u8 fw_rev_minor[0x10];
6880 u8 fw_rev_major[0x10];
6882 u8 cmd_interface_rev[0x10];
6883 u8 fw_rev_subminor[0x10];
6885 u8 reserved_0[0x40];
6887 u8 cmdq_phy_addr_63_32[0x20];
6889 u8 cmdq_phy_addr_31_12[0x14];
6891 u8 nic_interface[0x2];
6892 u8 log_cmdq_size[0x4];
6893 u8 log_cmdq_stride[0x4];
6895 u8 command_doorbell_vector[0x20];
6897 u8 reserved_2[0xf00];
6899 u8 initializing[0x1];
6901 u8 nic_interface_supported[0x3];
6902 u8 reserved_4[0x18];
6904 struct mlx5_ifc_health_buffer_bits health_buffer;
6906 u8 no_dram_nic_offset[0x20];
6908 u8 reserved_5[0x6e40];
6910 u8 reserved_6[0x1f];
6913 u8 health_syndrome[0x8];
6914 u8 health_counter[0x18];
6916 u8 reserved_7[0x17fc0];
6919 union mlx5_ifc_ports_control_registers_document_bits {
6920 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
6921 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
6922 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
6923 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
6924 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
6925 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
6926 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
6927 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
6928 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
6929 struct mlx5_ifc_pamp_reg_bits pamp_reg;
6930 struct mlx5_ifc_paos_reg_bits paos_reg;
6931 struct mlx5_ifc_pcap_reg_bits pcap_reg;
6932 struct mlx5_ifc_peir_reg_bits peir_reg;
6933 struct mlx5_ifc_pelc_reg_bits pelc_reg;
6934 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
6935 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
6936 struct mlx5_ifc_pifr_reg_bits pifr_reg;
6937 struct mlx5_ifc_pipg_reg_bits pipg_reg;
6938 struct mlx5_ifc_plbf_reg_bits plbf_reg;
6939 struct mlx5_ifc_plib_reg_bits plib_reg;
6940 struct mlx5_ifc_plpc_reg_bits plpc_reg;
6941 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
6942 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
6943 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
6944 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
6945 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
6946 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
6947 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
6948 struct mlx5_ifc_ppad_reg_bits ppad_reg;
6949 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
6950 struct mlx5_ifc_pplm_reg_bits pplm_reg;
6951 struct mlx5_ifc_pplr_reg_bits pplr_reg;
6952 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
6953 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
6954 struct mlx5_ifc_pspa_reg_bits pspa_reg;
6955 struct mlx5_ifc_ptas_reg_bits ptas_reg;
6956 struct mlx5_ifc_ptys_reg_bits ptys_reg;
6957 struct mlx5_ifc_pude_reg_bits pude_reg;
6958 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
6959 struct mlx5_ifc_slrg_reg_bits slrg_reg;
6960 struct mlx5_ifc_sltp_reg_bits sltp_reg;
6961 u8 reserved_0[0x60e0];
6964 union mlx5_ifc_debug_enhancements_document_bits {
6965 struct mlx5_ifc_health_buffer_bits health_buffer;
6966 u8 reserved_0[0x200];
6969 union mlx5_ifc_uplink_pci_interface_document_bits {
6970 struct mlx5_ifc_initial_seg_bits initial_seg;
6971 u8 reserved_0[0x20060];
6974 struct mlx5_ifc_set_flow_table_root_out_bits {
6976 u8 reserved_0[0x18];
6980 u8 reserved_1[0x40];
6983 struct mlx5_ifc_set_flow_table_root_in_bits {
6985 u8 reserved_0[0x10];
6987 u8 reserved_1[0x10];
6990 u8 reserved_2[0x40];
6993 u8 reserved_3[0x18];
6998 u8 reserved_5[0x140];
7002 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7005 struct mlx5_ifc_modify_flow_table_out_bits {
7007 u8 reserved_0[0x18];
7011 u8 reserved_1[0x40];
7014 struct mlx5_ifc_modify_flow_table_in_bits {
7016 u8 reserved_0[0x10];
7018 u8 reserved_1[0x10];
7021 u8 reserved_2[0x20];
7023 u8 reserved_3[0x10];
7024 u8 modify_field_select[0x10];
7027 u8 reserved_4[0x18];
7033 u8 table_miss_mode[0x4];
7034 u8 reserved_7[0x18];
7037 u8 table_miss_id[0x18];
7039 u8 reserved_9[0x100];
7042 #endif /* MLX5_IFC_H */