include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  71 };
  72
  73 enum {
  74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  75         MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
  76         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  77 };
  78
  79 enum {
  80         MLX5_SHARED_RESOURCE_UID = 0xffff,
  81 };
  82
  83 enum {
  84         MLX5_OBJ_TYPE_SW_ICM = 0x0008,
  85 };
  86
  87 enum {
  88         MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
  89         MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
  90 };
  91
  92 enum {
  93         MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
  94         MLX5_OBJ_TYPE_MKEY = 0xff01,
  95         MLX5_OBJ_TYPE_QP = 0xff02,
  96         MLX5_OBJ_TYPE_PSV = 0xff03,
  97         MLX5_OBJ_TYPE_RMP = 0xff04,
  98         MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
  99         MLX5_OBJ_TYPE_RQ = 0xff06,
 100         MLX5_OBJ_TYPE_SQ = 0xff07,
 101         MLX5_OBJ_TYPE_TIR = 0xff08,
 102         MLX5_OBJ_TYPE_TIS = 0xff09,
 103         MLX5_OBJ_TYPE_DCT = 0xff0a,
 104         MLX5_OBJ_TYPE_XRQ = 0xff0b,
 105         MLX5_OBJ_TYPE_RQT = 0xff0e,
 106         MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
 107         MLX5_OBJ_TYPE_CQ = 0xff10,
 108 };
 109
 110 enum {
 111         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
 112         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
 113         MLX5_CMD_OP_INIT_HCA                      = 0x102,
 114         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
 115         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
 116         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
 117         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
 118         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 119         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 120         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 121         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 122         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 123         MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
 124         MLX5_CMD_OP_ALLOC_SF                      = 0x113,
 125         MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
 126         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 127         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 128         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 129         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 130         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 131         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 132         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 133         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 134         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 135         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 136         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 137         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 138         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 139         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 140         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 141         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 142         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 143         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 144         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 145         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 146         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 147         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 148         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 149         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 150         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 151         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 152         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 153         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 154         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 155         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 156         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 157         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 158         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 159         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 160         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 161         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 162         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 163         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 164         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 165         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 166         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 167         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 168         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 169         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 170         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 171         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 172         MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
 173         MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
 174         MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
 175         MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
 176         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 177         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 178         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 179         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 180         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 181         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 182         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 183         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 184         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 185         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 186         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 187         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 188         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 189         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 190         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 191         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 192         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 193         MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
 194         MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
 195         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 196         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 197         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 198         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 199         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 200         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 201         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 202         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 203         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 204         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 205         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 206         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 207         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 208         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 209         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 210         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 211         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 212         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 213         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 214         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 215         MLX5_CMD_OP_NOP                           = 0x80d,
 216         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 217         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 218         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 219         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 220         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 221         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 222         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 223         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 224         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 225         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 226         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 227         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 228         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 229         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 230         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 231         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 232         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 233         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 234         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 235         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 236         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 237         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 238         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 239         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 240         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 241         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 242         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 243         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 244         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 245         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 246         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 247         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 248         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 249         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 250         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 251         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 252         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 253         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 254         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 255         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 256         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 257         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 258         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 259         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 260         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 261         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 262         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 263         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 264         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 265         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 266         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 267         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 268         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 269         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 270         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 271         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 272         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 273         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 274         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 275         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 276         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 277         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 278         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 279         MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
 280         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 281         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 282         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 283         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 284         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 285         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 286         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 287         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 288         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 289         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 290         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 291         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 292         MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
 293         MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
 294         MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
 295         MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
 296         MLX5_CMD_OP_MAX
 297 };
 298
 299 /* Valid range for general commands that don't work over an object */
 300 enum {
 301         MLX5_CMD_OP_GENERAL_START = 0xb00,
 302         MLX5_CMD_OP_GENERAL_END = 0xd00,
 303 };
 304
 305 struct mlx5_ifc_flow_table_fields_supported_bits {
 306         u8         outer_dmac[0x1];
 307         u8         outer_smac[0x1];
 308         u8         outer_ether_type[0x1];
 309         u8         outer_ip_version[0x1];
 310         u8         outer_first_prio[0x1];
 311         u8         outer_first_cfi[0x1];
 312         u8         outer_first_vid[0x1];
 313         u8         outer_ipv4_ttl[0x1];
 314         u8         outer_second_prio[0x1];
 315         u8         outer_second_cfi[0x1];
 316         u8         outer_second_vid[0x1];
 317         u8         reserved_at_b[0x1];
 318         u8         outer_sip[0x1];
 319         u8         outer_dip[0x1];
 320         u8         outer_frag[0x1];
 321         u8         outer_ip_protocol[0x1];
 322         u8         outer_ip_ecn[0x1];
 323         u8         outer_ip_dscp[0x1];
 324         u8         outer_udp_sport[0x1];
 325         u8         outer_udp_dport[0x1];
 326         u8         outer_tcp_sport[0x1];
 327         u8         outer_tcp_dport[0x1];
 328         u8         outer_tcp_flags[0x1];
 329         u8         outer_gre_protocol[0x1];
 330         u8         outer_gre_key[0x1];
 331         u8         outer_vxlan_vni[0x1];
 332         u8         outer_geneve_vni[0x1];
 333         u8         outer_geneve_oam[0x1];
 334         u8         outer_geneve_protocol_type[0x1];
 335         u8         outer_geneve_opt_len[0x1];
 336         u8         reserved_at_1e[0x1];
 337         u8         source_eswitch_port[0x1];
 338
 339         u8         inner_dmac[0x1];
 340         u8         inner_smac[0x1];
 341         u8         inner_ether_type[0x1];
 342         u8         inner_ip_version[0x1];
 343         u8         inner_first_prio[0x1];
 344         u8         inner_first_cfi[0x1];
 345         u8         inner_first_vid[0x1];
 346         u8         reserved_at_27[0x1];
 347         u8         inner_second_prio[0x1];
 348         u8         inner_second_cfi[0x1];
 349         u8         inner_second_vid[0x1];
 350         u8         reserved_at_2b[0x1];
 351         u8         inner_sip[0x1];
 352         u8         inner_dip[0x1];
 353         u8         inner_frag[0x1];
 354         u8         inner_ip_protocol[0x1];
 355         u8         inner_ip_ecn[0x1];
 356         u8         inner_ip_dscp[0x1];
 357         u8         inner_udp_sport[0x1];
 358         u8         inner_udp_dport[0x1];
 359         u8         inner_tcp_sport[0x1];
 360         u8         inner_tcp_dport[0x1];
 361         u8         inner_tcp_flags[0x1];
 362         u8         reserved_at_37[0x9];
 363
 364         u8         geneve_tlv_option_0_data[0x1];
 365         u8         reserved_at_41[0x4];
 366         u8         outer_first_mpls_over_udp[0x4];
 367         u8         outer_first_mpls_over_gre[0x4];
 368         u8         inner_first_mpls[0x4];
 369         u8         outer_first_mpls[0x4];
 370         u8         reserved_at_55[0x2];
 371         u8         outer_esp_spi[0x1];
 372         u8         reserved_at_58[0x2];
 373         u8         bth_dst_qp[0x1];
 374
 375         u8         reserved_at_5b[0x25];
 376 };
 377
 378 struct mlx5_ifc_flow_table_prop_layout_bits {
 379         u8         ft_support[0x1];
 380         u8         reserved_at_1[0x1];
 381         u8         flow_counter[0x1];
 382         u8         flow_modify_en[0x1];
 383         u8         modify_root[0x1];
 384         u8         identified_miss_table_mode[0x1];
 385         u8         flow_table_modify[0x1];
 386         u8         reformat[0x1];
 387         u8         decap[0x1];
 388         u8         reserved_at_9[0x1];
 389         u8         pop_vlan[0x1];
 390         u8         push_vlan[0x1];
 391         u8         reserved_at_c[0x1];
 392         u8         pop_vlan_2[0x1];
 393         u8         push_vlan_2[0x1];
 394         u8         reformat_and_vlan_action[0x1];
 395         u8         reserved_at_10[0x1];
 396         u8         sw_owner[0x1];
 397         u8         reformat_l3_tunnel_to_l2[0x1];
 398         u8         reformat_l2_to_l3_tunnel[0x1];
 399         u8         reformat_and_modify_action[0x1];
 400         u8         reserved_at_15[0x2];
 401         u8         table_miss_action_domain[0x1];
 402         u8         termination_table[0x1];
 403         u8         reserved_at_19[0x7];
 404         u8         reserved_at_20[0x2];
 405         u8         log_max_ft_size[0x6];
 406         u8         log_max_modify_header_context[0x8];
 407         u8         max_modify_header_actions[0x8];
 408         u8         max_ft_level[0x8];
 409
 410         u8         reserved_at_40[0x20];
 411
 412         u8         reserved_at_60[0x18];
 413         u8         log_max_ft_num[0x8];
 414
 415         u8         reserved_at_80[0x18];
 416         u8         log_max_destination[0x8];
 417
 418         u8         log_max_flow_counter[0x8];
 419         u8         reserved_at_a8[0x10];
 420         u8         log_max_flow[0x8];
 421
 422         u8         reserved_at_c0[0x40];
 423
 424         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 425
 426         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 427 };
 428
 429 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 430         u8         send[0x1];
 431         u8         receive[0x1];
 432         u8         write[0x1];
 433         u8         read[0x1];
 434         u8         atomic[0x1];
 435         u8         srq_receive[0x1];
 436         u8         reserved_at_6[0x1a];
 437 };
 438
 439 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 440         u8         smac_47_16[0x20];
 441
 442         u8         smac_15_0[0x10];
 443         u8         ethertype[0x10];
 444
 445         u8         dmac_47_16[0x20];
 446
 447         u8         dmac_15_0[0x10];
 448         u8         first_prio[0x3];
 449         u8         first_cfi[0x1];
 450         u8         first_vid[0xc];
 451
 452         u8         ip_protocol[0x8];
 453         u8         ip_dscp[0x6];
 454         u8         ip_ecn[0x2];
 455         u8         cvlan_tag[0x1];
 456         u8         svlan_tag[0x1];
 457         u8         frag[0x1];
 458         u8         ip_version[0x4];
 459         u8         tcp_flags[0x9];
 460
 461         u8         tcp_sport[0x10];
 462         u8         tcp_dport[0x10];
 463
 464         u8         reserved_at_c0[0x18];
 465         u8         ttl_hoplimit[0x8];
 466
 467         u8         udp_sport[0x10];
 468         u8         udp_dport[0x10];
 469
 470         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 471
 472         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 473 };
 474
 475 struct mlx5_ifc_nvgre_key_bits {
 476         u8 hi[0x18];
 477         u8 lo[0x8];
 478 };
 479
 480 union mlx5_ifc_gre_key_bits {
 481         struct mlx5_ifc_nvgre_key_bits nvgre;
 482         u8 key[0x20];
 483 };
 484
 485 struct mlx5_ifc_fte_match_set_misc_bits {
 486         u8         reserved_at_0[0x8];
 487         u8         source_sqn[0x18];
 488
 489         u8         source_eswitch_owner_vhca_id[0x10];
 490         u8         source_port[0x10];
 491
 492         u8         outer_second_prio[0x3];
 493         u8         outer_second_cfi[0x1];
 494         u8         outer_second_vid[0xc];
 495         u8         inner_second_prio[0x3];
 496         u8         inner_second_cfi[0x1];
 497         u8         inner_second_vid[0xc];
 498
 499         u8         outer_second_cvlan_tag[0x1];
 500         u8         inner_second_cvlan_tag[0x1];
 501         u8         outer_second_svlan_tag[0x1];
 502         u8         inner_second_svlan_tag[0x1];
 503         u8         reserved_at_64[0xc];
 504         u8         gre_protocol[0x10];
 505
 506         union mlx5_ifc_gre_key_bits gre_key;
 507
 508         u8         vxlan_vni[0x18];
 509         u8         reserved_at_b8[0x8];
 510
 511         u8         geneve_vni[0x18];
 512         u8         reserved_at_d8[0x7];
 513         u8         geneve_oam[0x1];
 514
 515         u8         reserved_at_e0[0xc];
 516         u8         outer_ipv6_flow_label[0x14];
 517
 518         u8         reserved_at_100[0xc];
 519         u8         inner_ipv6_flow_label[0x14];
 520
 521         u8         reserved_at_120[0xa];
 522         u8         geneve_opt_len[0x6];
 523         u8         geneve_protocol_type[0x10];
 524
 525         u8         reserved_at_140[0x8];
 526         u8         bth_dst_qp[0x18];
 527         u8         reserved_at_160[0x20];
 528         u8         outer_esp_spi[0x20];
 529         u8         reserved_at_1a0[0x60];
 530 };
 531
 532 struct mlx5_ifc_fte_match_mpls_bits {
 533         u8         mpls_label[0x14];
 534         u8         mpls_exp[0x3];
 535         u8         mpls_s_bos[0x1];
 536         u8         mpls_ttl[0x8];
 537 };
 538
 539 struct mlx5_ifc_fte_match_set_misc2_bits {
 540         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 541
 542         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 543
 544         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 545
 546         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 547
 548         u8         metadata_reg_c_7[0x20];
 549
 550         u8         metadata_reg_c_6[0x20];
 551
 552         u8         metadata_reg_c_5[0x20];
 553
 554         u8         metadata_reg_c_4[0x20];
 555
 556         u8         metadata_reg_c_3[0x20];
 557
 558         u8         metadata_reg_c_2[0x20];
 559
 560         u8         metadata_reg_c_1[0x20];
 561
 562         u8         metadata_reg_c_0[0x20];
 563
 564         u8         metadata_reg_a[0x20];
 565
 566         u8         reserved_at_1a0[0x60];
 567 };
 568
 569 struct mlx5_ifc_fte_match_set_misc3_bits {
 570         u8         reserved_at_0[0x120];
 571         u8         geneve_tlv_option_0_data[0x20];
 572         u8         reserved_at_140[0xc0];
 573 };
 574
 575 struct mlx5_ifc_cmd_pas_bits {
 576         u8         pa_h[0x20];
 577
 578         u8         pa_l[0x14];
 579         u8         reserved_at_34[0xc];
 580 };
 581
 582 struct mlx5_ifc_uint64_bits {
 583         u8         hi[0x20];
 584
 585         u8         lo[0x20];
 586 };
 587
 588 enum {
 589         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 590         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 591         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 592         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 593         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 594         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 595         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 596         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 597         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 598         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 599 };
 600
 601 struct mlx5_ifc_ads_bits {
 602         u8         fl[0x1];
 603         u8         free_ar[0x1];
 604         u8         reserved_at_2[0xe];
 605         u8         pkey_index[0x10];
 606
 607         u8         reserved_at_20[0x8];
 608         u8         grh[0x1];
 609         u8         mlid[0x7];
 610         u8         rlid[0x10];
 611
 612         u8         ack_timeout[0x5];
 613         u8         reserved_at_45[0x3];
 614         u8         src_addr_index[0x8];
 615         u8         reserved_at_50[0x4];
 616         u8         stat_rate[0x4];
 617         u8         hop_limit[0x8];
 618
 619         u8         reserved_at_60[0x4];
 620         u8         tclass[0x8];
 621         u8         flow_label[0x14];
 622
 623         u8         rgid_rip[16][0x8];
 624
 625         u8         reserved_at_100[0x4];
 626         u8         f_dscp[0x1];
 627         u8         f_ecn[0x1];
 628         u8         reserved_at_106[0x1];
 629         u8         f_eth_prio[0x1];
 630         u8         ecn[0x2];
 631         u8         dscp[0x6];
 632         u8         udp_sport[0x10];
 633
 634         u8         dei_cfi[0x1];
 635         u8         eth_prio[0x3];
 636         u8         sl[0x4];
 637         u8         vhca_port_num[0x8];
 638         u8         rmac_47_32[0x10];
 639
 640         u8         rmac_31_0[0x20];
 641 };
 642
 643 struct mlx5_ifc_flow_table_nic_cap_bits {
 644         u8         nic_rx_multi_path_tirs[0x1];
 645         u8         nic_rx_multi_path_tirs_fts[0x1];
 646         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 647         u8         reserved_at_3[0x1d];
 648         u8         encap_general_header[0x1];
 649         u8         reserved_at_21[0xa];
 650         u8         log_max_packet_reformat_context[0x5];
 651         u8         reserved_at_30[0x6];
 652         u8         max_encap_header_size[0xa];
 653         u8         reserved_at_40[0x1c0];
 654
 655         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 656
 657         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 658
 659         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 660
 661         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 662
 663         u8         reserved_at_a00[0x200];
 664
 665         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 666
 667         u8         reserved_at_e00[0x7200];
 668 };
 669
 670 enum {
 671         MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
 672         MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
 673         MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
 674         MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
 675         MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
 676         MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
 677         MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
 678         MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
 679 };
 680
 681 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 682         u8      fdb_to_vport_reg_c_id[0x8];
 683         u8      reserved_at_8[0xf];
 684         u8      flow_source[0x1];
 685         u8      reserved_at_18[0x2];
 686         u8      multi_fdb_encap[0x1];
 687         u8      reserved_at_1b[0x1];
 688         u8      fdb_multi_path_to_table[0x1];
 689         u8      reserved_at_1d[0x3];
 690
 691         u8      reserved_at_20[0x1e0];
 692
 693         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 694
 695         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 696
 697         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 698
 699         u8      reserved_at_800[0x7800];
 700 };
 701
 702 enum {
 703         MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
 704         MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
 705 };
 706
 707 struct mlx5_ifc_e_switch_cap_bits {
 708         u8         vport_svlan_strip[0x1];
 709         u8         vport_cvlan_strip[0x1];
 710         u8         vport_svlan_insert[0x1];
 711         u8         vport_cvlan_insert_if_not_exist[0x1];
 712         u8         vport_cvlan_insert_overwrite[0x1];
 713         u8         reserved_at_5[0x3];
 714         u8         esw_uplink_ingress_acl[0x1];
 715         u8         reserved_at_9[0x10];
 716         u8         esw_functions_changed[0x1];
 717         u8         reserved_at_1a[0x1];
 718         u8         ecpf_vport_exists[0x1];
 719         u8         counter_eswitch_affinity[0x1];
 720         u8         merged_eswitch[0x1];
 721         u8         nic_vport_node_guid_modify[0x1];
 722         u8         nic_vport_port_guid_modify[0x1];
 723
 724         u8         vxlan_encap_decap[0x1];
 725         u8         nvgre_encap_decap[0x1];
 726         u8         reserved_at_22[0x1];
 727         u8         log_max_fdb_encap_uplink[0x5];
 728         u8         reserved_at_21[0x3];
 729         u8         log_max_packet_reformat_context[0x5];
 730         u8         reserved_2b[0x6];
 731         u8         max_encap_header_size[0xa];
 732
 733         u8         reserved_at_40[0xb];
 734         u8         log_max_esw_sf[0x5];
 735         u8         esw_sf_base_id[0x10];
 736
 737         u8         reserved_at_60[0x7a0];
 738
 739 };
 740
 741 struct mlx5_ifc_qos_cap_bits {
 742         u8         packet_pacing[0x1];
 743         u8         esw_scheduling[0x1];
 744         u8         esw_bw_share[0x1];
 745         u8         esw_rate_limit[0x1];
 746         u8         reserved_at_4[0x1];
 747         u8         packet_pacing_burst_bound[0x1];
 748         u8         packet_pacing_typical_size[0x1];
 749         u8         reserved_at_7[0x19];
 750
 751         u8         reserved_at_20[0x20];
 752
 753         u8         packet_pacing_max_rate[0x20];
 754
 755         u8         packet_pacing_min_rate[0x20];
 756
 757         u8         reserved_at_80[0x10];
 758         u8         packet_pacing_rate_table_size[0x10];
 759
 760         u8         esw_element_type[0x10];
 761         u8         esw_tsar_type[0x10];
 762
 763         u8         reserved_at_c0[0x10];
 764         u8         max_qos_para_vport[0x10];
 765
 766         u8         max_tsar_bw_share[0x20];
 767
 768         u8         reserved_at_100[0x700];
 769 };
 770
 771 struct mlx5_ifc_debug_cap_bits {
 772         u8         core_dump_general[0x1];
 773         u8         core_dump_qp[0x1];
 774         u8         reserved_at_2[0x1e];
 775
 776         u8         reserved_at_20[0x2];
 777         u8         stall_detect[0x1];
 778         u8         reserved_at_23[0x1d];
 779
 780         u8         reserved_at_40[0x7c0];
 781 };
 782
 783 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 784         u8         csum_cap[0x1];
 785         u8         vlan_cap[0x1];
 786         u8         lro_cap[0x1];
 787         u8         lro_psh_flag[0x1];
 788         u8         lro_time_stamp[0x1];
 789         u8         reserved_at_5[0x2];
 790         u8         wqe_vlan_insert[0x1];
 791         u8         self_lb_en_modifiable[0x1];
 792         u8         reserved_at_9[0x2];
 793         u8         max_lso_cap[0x5];
 794         u8         multi_pkt_send_wqe[0x2];
 795         u8         wqe_inline_mode[0x2];
 796         u8         rss_ind_tbl_cap[0x4];
 797         u8         reg_umr_sq[0x1];
 798         u8         scatter_fcs[0x1];
 799         u8         enhanced_multi_pkt_send_wqe[0x1];
 800         u8         tunnel_lso_const_out_ip_id[0x1];
 801         u8         reserved_at_1c[0x2];
 802         u8         tunnel_stateless_gre[0x1];
 803         u8         tunnel_stateless_vxlan[0x1];
 804
 805         u8         swp[0x1];
 806         u8         swp_csum[0x1];
 807         u8         swp_lso[0x1];
 808         u8         cqe_checksum_full[0x1];
 809         u8         reserved_at_24[0xc];
 810         u8         max_vxlan_udp_ports[0x8];
 811         u8         reserved_at_38[0x6];
 812         u8         max_geneve_opt_len[0x1];
 813         u8         tunnel_stateless_geneve_rx[0x1];
 814
 815         u8         reserved_at_40[0x10];
 816         u8         lro_min_mss_size[0x10];
 817
 818         u8         reserved_at_60[0x120];
 819
 820         u8         lro_timer_supported_periods[4][0x20];
 821
 822         u8         reserved_at_200[0x600];
 823 };
 824
 825 struct mlx5_ifc_roce_cap_bits {
 826         u8         roce_apm[0x1];
 827         u8         reserved_at_1[0x1f];
 828
 829         u8         reserved_at_20[0x60];
 830
 831         u8         reserved_at_80[0xc];
 832         u8         l3_type[0x4];
 833         u8         reserved_at_90[0x8];
 834         u8         roce_version[0x8];
 835
 836         u8         reserved_at_a0[0x10];
 837         u8         r_roce_dest_udp_port[0x10];
 838
 839         u8         r_roce_max_src_udp_port[0x10];
 840         u8         r_roce_min_src_udp_port[0x10];
 841
 842         u8         reserved_at_e0[0x10];
 843         u8         roce_address_table_size[0x10];
 844
 845         u8         reserved_at_100[0x700];
 846 };
 847
 848 struct mlx5_ifc_device_mem_cap_bits {
 849         u8         memic[0x1];
 850         u8         reserved_at_1[0x1f];
 851
 852         u8         reserved_at_20[0xb];
 853         u8         log_min_memic_alloc_size[0x5];
 854         u8         reserved_at_30[0x8];
 855         u8         log_max_memic_addr_alignment[0x8];
 856
 857         u8         memic_bar_start_addr[0x40];
 858
 859         u8         memic_bar_size[0x20];
 860
 861         u8         max_memic_size[0x20];
 862
 863         u8         steering_sw_icm_start_address[0x40];
 864
 865         u8         reserved_at_100[0x8];
 866         u8         log_header_modify_sw_icm_size[0x8];
 867         u8         reserved_at_110[0x2];
 868         u8         log_sw_icm_alloc_granularity[0x6];
 869         u8         log_steering_sw_icm_size[0x8];
 870
 871         u8         reserved_at_120[0x20];
 872
 873         u8         header_modify_sw_icm_start_address[0x40];
 874
 875         u8         reserved_at_180[0x680];
 876 };
 877
 878 struct mlx5_ifc_device_event_cap_bits {
 879         u8         user_affiliated_events[4][0x40];
 880
 881         u8         user_unaffiliated_events[4][0x40];
 882 };
 883
 884 enum {
 885         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 886         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 887         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 888         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 889         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 890         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 891         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 892         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 893         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 894 };
 895
 896 enum {
 897         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 898         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 899         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 900         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 901         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 902         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 903         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 904         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 905         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 906 };
 907
 908 struct mlx5_ifc_atomic_caps_bits {
 909         u8         reserved_at_0[0x40];
 910
 911         u8         atomic_req_8B_endianness_mode[0x2];
 912         u8         reserved_at_42[0x4];
 913         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 914
 915         u8         reserved_at_47[0x19];
 916
 917         u8         reserved_at_60[0x20];
 918
 919         u8         reserved_at_80[0x10];
 920         u8         atomic_operations[0x10];
 921
 922         u8         reserved_at_a0[0x10];
 923         u8         atomic_size_qp[0x10];
 924
 925         u8         reserved_at_c0[0x10];
 926         u8         atomic_size_dc[0x10];
 927
 928         u8         reserved_at_e0[0x720];
 929 };
 930
 931 struct mlx5_ifc_odp_cap_bits {
 932         u8         reserved_at_0[0x40];
 933
 934         u8         sig[0x1];
 935         u8         reserved_at_41[0x1f];
 936
 937         u8         reserved_at_60[0x20];
 938
 939         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 940
 941         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 942
 943         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 944
 945         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
 946
 947         u8         reserved_at_100[0x700];
 948 };
 949
 950 struct mlx5_ifc_calc_op {
 951         u8        reserved_at_0[0x10];
 952         u8        reserved_at_10[0x9];
 953         u8        op_swap_endianness[0x1];
 954         u8        op_min[0x1];
 955         u8        op_xor[0x1];
 956         u8        op_or[0x1];
 957         u8        op_and[0x1];
 958         u8        op_max[0x1];
 959         u8        op_add[0x1];
 960 };
 961
 962 struct mlx5_ifc_vector_calc_cap_bits {
 963         u8         calc_matrix[0x1];
 964         u8         reserved_at_1[0x1f];
 965         u8         reserved_at_20[0x8];
 966         u8         max_vec_count[0x8];
 967         u8         reserved_at_30[0xd];
 968         u8         max_chunk_size[0x3];
 969         struct mlx5_ifc_calc_op calc0;
 970         struct mlx5_ifc_calc_op calc1;
 971         struct mlx5_ifc_calc_op calc2;
 972         struct mlx5_ifc_calc_op calc3;
 973
 974         u8         reserved_at_c0[0x720];
 975 };
 976
 977 struct mlx5_ifc_tls_cap_bits {
 978         u8         tls_1_2_aes_gcm_128[0x1];
 979         u8         tls_1_3_aes_gcm_128[0x1];
 980         u8         tls_1_2_aes_gcm_256[0x1];
 981         u8         tls_1_3_aes_gcm_256[0x1];
 982         u8         reserved_at_4[0x1c];
 983
 984         u8         reserved_at_20[0x7e0];
 985 };
 986
 987 enum {
 988         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 989         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 990         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 991         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
 992 };
 993
 994 enum {
 995         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 996         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 997 };
 998
 999 enum {
1000         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1001         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1002         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1003         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1004         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1005 };
1006
1007 enum {
1008         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1009         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1010         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1011         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1012         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1013         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1014 };
1015
1016 enum {
1017         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1018         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1019 };
1020
1021 enum {
1022         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1023         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1024         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1025 };
1026
1027 enum {
1028         MLX5_CAP_PORT_TYPE_IB  = 0x0,
1029         MLX5_CAP_PORT_TYPE_ETH = 0x1,
1030 };
1031
1032 enum {
1033         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
1034         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
1035         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
1036 };
1037
1038 enum {
1039         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1040         MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1041 };
1042
1043 struct mlx5_ifc_cmd_hca_cap_bits {
1044         u8         reserved_at_0[0x30];
1045         u8         vhca_id[0x10];
1046
1047         u8         reserved_at_40[0x40];
1048
1049         u8         log_max_srq_sz[0x8];
1050         u8         log_max_qp_sz[0x8];
1051         u8         event_cap[0x1];
1052         u8         reserved_at_91[0x7];
1053         u8         prio_tag_required[0x1];
1054         u8         reserved_at_99[0x2];
1055         u8         log_max_qp[0x5];
1056
1057         u8         reserved_at_a0[0xb];
1058         u8         log_max_srq[0x5];
1059         u8         reserved_at_b0[0x10];
1060
1061         u8         reserved_at_c0[0x8];
1062         u8         log_max_cq_sz[0x8];
1063         u8         reserved_at_d0[0xb];
1064         u8         log_max_cq[0x5];
1065
1066         u8         log_max_eq_sz[0x8];
1067         u8         reserved_at_e8[0x2];
1068         u8         log_max_mkey[0x6];
1069         u8         reserved_at_f0[0x8];
1070         u8         dump_fill_mkey[0x1];
1071         u8         reserved_at_f9[0x2];
1072         u8         fast_teardown[0x1];
1073         u8         log_max_eq[0x4];
1074
1075         u8         max_indirection[0x8];
1076         u8         fixed_buffer_size[0x1];
1077         u8         log_max_mrw_sz[0x7];
1078         u8         force_teardown[0x1];
1079         u8         reserved_at_111[0x1];
1080         u8         log_max_bsf_list_size[0x6];
1081         u8         umr_extended_translation_offset[0x1];
1082         u8         null_mkey[0x1];
1083         u8         log_max_klm_list_size[0x6];
1084
1085         u8         reserved_at_120[0xa];
1086         u8         log_max_ra_req_dc[0x6];
1087         u8         reserved_at_130[0xa];
1088         u8         log_max_ra_res_dc[0x6];
1089
1090         u8         reserved_at_140[0xa];
1091         u8         log_max_ra_req_qp[0x6];
1092         u8         reserved_at_150[0xa];
1093         u8         log_max_ra_res_qp[0x6];
1094
1095         u8         end_pad[0x1];
1096         u8         cc_query_allowed[0x1];
1097         u8         cc_modify_allowed[0x1];
1098         u8         start_pad[0x1];
1099         u8         cache_line_128byte[0x1];
1100         u8         reserved_at_165[0x4];
1101         u8         rts2rts_qp_counters_set_id[0x1];
1102         u8         reserved_at_16a[0x5];
1103         u8         qcam_reg[0x1];
1104         u8         gid_table_size[0x10];
1105
1106         u8         out_of_seq_cnt[0x1];
1107         u8         vport_counters[0x1];
1108         u8         retransmission_q_counters[0x1];
1109         u8         debug[0x1];
1110         u8         modify_rq_counter_set_id[0x1];
1111         u8         rq_delay_drop[0x1];
1112         u8         max_qp_cnt[0xa];
1113         u8         pkey_table_size[0x10];
1114
1115         u8         vport_group_manager[0x1];
1116         u8         vhca_group_manager[0x1];
1117         u8         ib_virt[0x1];
1118         u8         eth_virt[0x1];
1119         u8         vnic_env_queue_counters[0x1];
1120         u8         ets[0x1];
1121         u8         nic_flow_table[0x1];
1122         u8         eswitch_manager[0x1];
1123         u8         device_memory[0x1];
1124         u8         mcam_reg[0x1];
1125         u8         pcam_reg[0x1];
1126         u8         local_ca_ack_delay[0x5];
1127         u8         port_module_event[0x1];
1128         u8         enhanced_error_q_counters[0x1];
1129         u8         ports_check[0x1];
1130         u8         reserved_at_1b3[0x1];
1131         u8         disable_link_up[0x1];
1132         u8         beacon_led[0x1];
1133         u8         port_type[0x2];
1134         u8         num_ports[0x8];
1135
1136         u8         reserved_at_1c0[0x1];
1137         u8         pps[0x1];
1138         u8         pps_modify[0x1];
1139         u8         log_max_msg[0x5];
1140         u8         reserved_at_1c8[0x4];
1141         u8         max_tc[0x4];
1142         u8         temp_warn_event[0x1];
1143         u8         dcbx[0x1];
1144         u8         general_notification_event[0x1];
1145         u8         reserved_at_1d3[0x2];
1146         u8         fpga[0x1];
1147         u8         rol_s[0x1];
1148         u8         rol_g[0x1];
1149         u8         reserved_at_1d8[0x1];
1150         u8         wol_s[0x1];
1151         u8         wol_g[0x1];
1152         u8         wol_a[0x1];
1153         u8         wol_b[0x1];
1154         u8         wol_m[0x1];
1155         u8         wol_u[0x1];
1156         u8         wol_p[0x1];
1157
1158         u8         stat_rate_support[0x10];
1159         u8         reserved_at_1f0[0xc];
1160         u8         cqe_version[0x4];
1161
1162         u8         compact_address_vector[0x1];
1163         u8         striding_rq[0x1];
1164         u8         reserved_at_202[0x1];
1165         u8         ipoib_enhanced_offloads[0x1];
1166         u8         ipoib_basic_offloads[0x1];
1167         u8         reserved_at_205[0x1];
1168         u8         repeated_block_disabled[0x1];
1169         u8         umr_modify_entity_size_disabled[0x1];
1170         u8         umr_modify_atomic_disabled[0x1];
1171         u8         umr_indirect_mkey_disabled[0x1];
1172         u8         umr_fence[0x2];
1173         u8         dc_req_scat_data_cqe[0x1];
1174         u8         reserved_at_20d[0x2];
1175         u8         drain_sigerr[0x1];
1176         u8         cmdif_checksum[0x2];
1177         u8         sigerr_cqe[0x1];
1178         u8         reserved_at_213[0x1];
1179         u8         wq_signature[0x1];
1180         u8         sctr_data_cqe[0x1];
1181         u8         reserved_at_216[0x1];
1182         u8         sho[0x1];
1183         u8         tph[0x1];
1184         u8         rf[0x1];
1185         u8         dct[0x1];
1186         u8         qos[0x1];
1187         u8         eth_net_offloads[0x1];
1188         u8         roce[0x1];
1189         u8         atomic[0x1];
1190         u8         reserved_at_21f[0x1];
1191
1192         u8         cq_oi[0x1];
1193         u8         cq_resize[0x1];
1194         u8         cq_moderation[0x1];
1195         u8         reserved_at_223[0x3];
1196         u8         cq_eq_remap[0x1];
1197         u8         pg[0x1];
1198         u8         block_lb_mc[0x1];
1199         u8         reserved_at_229[0x1];
1200         u8         scqe_break_moderation[0x1];
1201         u8         cq_period_start_from_cqe[0x1];
1202         u8         cd[0x1];
1203         u8         reserved_at_22d[0x1];
1204         u8         apm[0x1];
1205         u8         vector_calc[0x1];
1206         u8         umr_ptr_rlky[0x1];
1207         u8         imaicl[0x1];
1208         u8         qp_packet_based[0x1];
1209         u8         reserved_at_233[0x3];
1210         u8         qkv[0x1];
1211         u8         pkv[0x1];
1212         u8         set_deth_sqpn[0x1];
1213         u8         reserved_at_239[0x3];
1214         u8         xrc[0x1];
1215         u8         ud[0x1];
1216         u8         uc[0x1];
1217         u8         rc[0x1];
1218
1219         u8         uar_4k[0x1];
1220         u8         reserved_at_241[0x9];
1221         u8         uar_sz[0x6];
1222         u8         reserved_at_250[0x8];
1223         u8         log_pg_sz[0x8];
1224
1225         u8         bf[0x1];
1226         u8         driver_version[0x1];
1227         u8         pad_tx_eth_packet[0x1];
1228         u8         reserved_at_263[0x8];
1229         u8         log_bf_reg_size[0x5];
1230
1231         u8         reserved_at_270[0xb];
1232         u8         lag_master[0x1];
1233         u8         num_lag_ports[0x4];
1234
1235         u8         reserved_at_280[0x10];
1236         u8         max_wqe_sz_sq[0x10];
1237
1238         u8         reserved_at_2a0[0x10];
1239         u8         max_wqe_sz_rq[0x10];
1240
1241         u8         max_flow_counter_31_16[0x10];
1242         u8         max_wqe_sz_sq_dc[0x10];
1243
1244         u8         reserved_at_2e0[0x7];
1245         u8         max_qp_mcg[0x19];
1246
1247         u8         reserved_at_300[0x18];
1248         u8         log_max_mcg[0x8];
1249
1250         u8         reserved_at_320[0x3];
1251         u8         log_max_transport_domain[0x5];
1252         u8         reserved_at_328[0x3];
1253         u8         log_max_pd[0x5];
1254         u8         reserved_at_330[0xb];
1255         u8         log_max_xrcd[0x5];
1256
1257         u8         nic_receive_steering_discard[0x1];
1258         u8         receive_discard_vport_down[0x1];
1259         u8         transmit_discard_vport_down[0x1];
1260         u8         reserved_at_343[0x5];
1261         u8         log_max_flow_counter_bulk[0x8];
1262         u8         max_flow_counter_15_0[0x10];
1263
1264
1265         u8         reserved_at_360[0x3];
1266         u8         log_max_rq[0x5];
1267         u8         reserved_at_368[0x3];
1268         u8         log_max_sq[0x5];
1269         u8         reserved_at_370[0x3];
1270         u8         log_max_tir[0x5];
1271         u8         reserved_at_378[0x3];
1272         u8         log_max_tis[0x5];
1273
1274         u8         basic_cyclic_rcv_wqe[0x1];
1275         u8         reserved_at_381[0x2];
1276         u8         log_max_rmp[0x5];
1277         u8         reserved_at_388[0x3];
1278         u8         log_max_rqt[0x5];
1279         u8         reserved_at_390[0x3];
1280         u8         log_max_rqt_size[0x5];
1281         u8         reserved_at_398[0x3];
1282         u8         log_max_tis_per_sq[0x5];
1283
1284         u8         ext_stride_num_range[0x1];
1285         u8         reserved_at_3a1[0x2];
1286         u8         log_max_stride_sz_rq[0x5];
1287         u8         reserved_at_3a8[0x3];
1288         u8         log_min_stride_sz_rq[0x5];
1289         u8         reserved_at_3b0[0x3];
1290         u8         log_max_stride_sz_sq[0x5];
1291         u8         reserved_at_3b8[0x3];
1292         u8         log_min_stride_sz_sq[0x5];
1293
1294         u8         hairpin[0x1];
1295         u8         reserved_at_3c1[0x2];
1296         u8         log_max_hairpin_queues[0x5];
1297         u8         reserved_at_3c8[0x3];
1298         u8         log_max_hairpin_wq_data_sz[0x5];
1299         u8         reserved_at_3d0[0x3];
1300         u8         log_max_hairpin_num_packets[0x5];
1301         u8         reserved_at_3d8[0x3];
1302         u8         log_max_wq_sz[0x5];
1303
1304         u8         nic_vport_change_event[0x1];
1305         u8         disable_local_lb_uc[0x1];
1306         u8         disable_local_lb_mc[0x1];
1307         u8         log_min_hairpin_wq_data_sz[0x5];
1308         u8         reserved_at_3e8[0x3];
1309         u8         log_max_vlan_list[0x5];
1310         u8         reserved_at_3f0[0x3];
1311         u8         log_max_current_mc_list[0x5];
1312         u8         reserved_at_3f8[0x3];
1313         u8         log_max_current_uc_list[0x5];
1314
1315         u8         general_obj_types[0x40];
1316
1317         u8         reserved_at_440[0x20];
1318
1319         u8         tls[0x1];
1320         u8         reserved_at_461[0x2];
1321         u8         log_max_uctx[0x5];
1322         u8         reserved_at_468[0x3];
1323         u8         log_max_umem[0x5];
1324         u8         max_num_eqs[0x10];
1325
1326         u8         reserved_at_480[0x3];
1327         u8         log_max_l2_table[0x5];
1328         u8         reserved_at_488[0x8];
1329         u8         log_uar_page_sz[0x10];
1330
1331         u8         reserved_at_4a0[0x20];
1332         u8         device_frequency_mhz[0x20];
1333         u8         device_frequency_khz[0x20];
1334
1335         u8         reserved_at_500[0x20];
1336         u8         num_of_uars_per_page[0x20];
1337
1338         u8         flex_parser_protocols[0x20];
1339
1340         u8         max_geneve_tlv_options[0x8];
1341         u8         reserved_at_568[0x3];
1342         u8         max_geneve_tlv_option_data_len[0x5];
1343         u8         reserved_at_570[0x10];
1344
1345         u8         reserved_at_580[0x33];
1346         u8         log_max_dek[0x5];
1347         u8         reserved_at_5b8[0x4];
1348         u8         mini_cqe_resp_stride_index[0x1];
1349         u8         cqe_128_always[0x1];
1350         u8         cqe_compression_128[0x1];
1351         u8         cqe_compression[0x1];
1352
1353         u8         cqe_compression_timeout[0x10];
1354         u8         cqe_compression_max_num[0x10];
1355
1356         u8         reserved_at_5e0[0x10];
1357         u8         tag_matching[0x1];
1358         u8         rndv_offload_rc[0x1];
1359         u8         rndv_offload_dc[0x1];
1360         u8         log_tag_matching_list_sz[0x5];
1361         u8         reserved_at_5f8[0x3];
1362         u8         log_max_xrq[0x5];
1363
1364         u8         affiliate_nic_vport_criteria[0x8];
1365         u8         native_port_num[0x8];
1366         u8         num_vhca_ports[0x8];
1367         u8         reserved_at_618[0x6];
1368         u8         sw_owner_id[0x1];
1369         u8         reserved_at_61f[0x1];
1370
1371         u8         max_num_of_monitor_counters[0x10];
1372         u8         num_ppcnt_monitor_counters[0x10];
1373
1374         u8         reserved_at_640[0x10];
1375         u8         num_q_monitor_counters[0x10];
1376
1377         u8         reserved_at_660[0x20];
1378
1379         u8         sf[0x1];
1380         u8         sf_set_partition[0x1];
1381         u8         reserved_at_682[0x1];
1382         u8         log_max_sf[0x5];
1383         u8         reserved_at_688[0x8];
1384         u8         log_min_sf_size[0x8];
1385         u8         max_num_sf_partitions[0x8];
1386
1387         u8         uctx_cap[0x20];
1388
1389         u8         reserved_at_6c0[0x4];
1390         u8         flex_parser_id_geneve_tlv_option_0[0x4];
1391         u8         reserved_at_6c8[0x28];
1392         u8         sf_base_id[0x10];
1393
1394         u8         reserved_at_700[0x100];
1395 };
1396
1397 enum mlx5_flow_destination_type {
1398         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1399         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1400         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1401
1402         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1403         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1404         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1405 };
1406
1407 enum mlx5_flow_table_miss_action {
1408         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1409         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1410         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1411 };
1412
1413 struct mlx5_ifc_dest_format_struct_bits {
1414         u8         destination_type[0x8];
1415         u8         destination_id[0x18];
1416
1417         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1418         u8         packet_reformat[0x1];
1419         u8         reserved_at_22[0xe];
1420         u8         destination_eswitch_owner_vhca_id[0x10];
1421 };
1422
1423 struct mlx5_ifc_flow_counter_list_bits {
1424         u8         flow_counter_id[0x20];
1425
1426         u8         reserved_at_20[0x20];
1427 };
1428
1429 struct mlx5_ifc_extended_dest_format_bits {
1430         struct mlx5_ifc_dest_format_struct_bits destination_entry;
1431
1432         u8         packet_reformat_id[0x20];
1433
1434         u8         reserved_at_60[0x20];
1435 };
1436
1437 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1438         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1439         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1440         u8         reserved_at_0[0x40];
1441 };
1442
1443 struct mlx5_ifc_fte_match_param_bits {
1444         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1445
1446         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1447
1448         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1449
1450         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1451
1452         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1453
1454         u8         reserved_at_a00[0x600];
1455 };
1456
1457 enum {
1458         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1459         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1460         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1461         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1462         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1463 };
1464
1465 struct mlx5_ifc_rx_hash_field_select_bits {
1466         u8         l3_prot_type[0x1];
1467         u8         l4_prot_type[0x1];
1468         u8         selected_fields[0x1e];
1469 };
1470
1471 enum {
1472         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1473         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1474 };
1475
1476 enum {
1477         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1478         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1479 };
1480
1481 struct mlx5_ifc_wq_bits {
1482         u8         wq_type[0x4];
1483         u8         wq_signature[0x1];
1484         u8         end_padding_mode[0x2];
1485         u8         cd_slave[0x1];
1486         u8         reserved_at_8[0x18];
1487
1488         u8         hds_skip_first_sge[0x1];
1489         u8         log2_hds_buf_size[0x3];
1490         u8         reserved_at_24[0x7];
1491         u8         page_offset[0x5];
1492         u8         lwm[0x10];
1493
1494         u8         reserved_at_40[0x8];
1495         u8         pd[0x18];
1496
1497         u8         reserved_at_60[0x8];
1498         u8         uar_page[0x18];
1499
1500         u8         dbr_addr[0x40];
1501
1502         u8         hw_counter[0x20];
1503
1504         u8         sw_counter[0x20];
1505
1506         u8         reserved_at_100[0xc];
1507         u8         log_wq_stride[0x4];
1508         u8         reserved_at_110[0x3];
1509         u8         log_wq_pg_sz[0x5];
1510         u8         reserved_at_118[0x3];
1511         u8         log_wq_sz[0x5];
1512
1513         u8         dbr_umem_valid[0x1];
1514         u8         wq_umem_valid[0x1];
1515         u8         reserved_at_122[0x1];
1516         u8         log_hairpin_num_packets[0x5];
1517         u8         reserved_at_128[0x3];
1518         u8         log_hairpin_data_sz[0x5];
1519
1520         u8         reserved_at_130[0x4];
1521         u8         log_wqe_num_of_strides[0x4];
1522         u8         two_byte_shift_en[0x1];
1523         u8         reserved_at_139[0x4];
1524         u8         log_wqe_stride_size[0x3];
1525
1526         u8         reserved_at_140[0x4c0];
1527
1528         struct mlx5_ifc_cmd_pas_bits pas[0];
1529 };
1530
1531 struct mlx5_ifc_rq_num_bits {
1532         u8         reserved_at_0[0x8];
1533         u8         rq_num[0x18];
1534 };
1535
1536 struct mlx5_ifc_mac_address_layout_bits {
1537         u8         reserved_at_0[0x10];
1538         u8         mac_addr_47_32[0x10];
1539
1540         u8         mac_addr_31_0[0x20];
1541 };
1542
1543 struct mlx5_ifc_vlan_layout_bits {
1544         u8         reserved_at_0[0x14];
1545         u8         vlan[0x0c];
1546
1547         u8         reserved_at_20[0x20];
1548 };
1549
1550 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1551         u8         reserved_at_0[0xa0];
1552
1553         u8         min_time_between_cnps[0x20];
1554
1555         u8         reserved_at_c0[0x12];
1556         u8         cnp_dscp[0x6];
1557         u8         reserved_at_d8[0x4];
1558         u8         cnp_prio_mode[0x1];
1559         u8         cnp_802p_prio[0x3];
1560
1561         u8         reserved_at_e0[0x720];
1562 };
1563
1564 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1565         u8         reserved_at_0[0x60];
1566
1567         u8         reserved_at_60[0x4];
1568         u8         clamp_tgt_rate[0x1];
1569         u8         reserved_at_65[0x3];
1570         u8         clamp_tgt_rate_after_time_inc[0x1];
1571         u8         reserved_at_69[0x17];
1572
1573         u8         reserved_at_80[0x20];
1574
1575         u8         rpg_time_reset[0x20];
1576
1577         u8         rpg_byte_reset[0x20];
1578
1579         u8         rpg_threshold[0x20];
1580
1581         u8         rpg_max_rate[0x20];
1582
1583         u8         rpg_ai_rate[0x20];
1584
1585         u8         rpg_hai_rate[0x20];
1586
1587         u8         rpg_gd[0x20];
1588
1589         u8         rpg_min_dec_fac[0x20];
1590
1591         u8         rpg_min_rate[0x20];
1592
1593         u8         reserved_at_1c0[0xe0];
1594
1595         u8         rate_to_set_on_first_cnp[0x20];
1596
1597         u8         dce_tcp_g[0x20];
1598
1599         u8         dce_tcp_rtt[0x20];
1600
1601         u8         rate_reduce_monitor_period[0x20];
1602
1603         u8         reserved_at_320[0x20];
1604
1605         u8         initial_alpha_value[0x20];
1606
1607         u8         reserved_at_360[0x4a0];
1608 };
1609
1610 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1611         u8         reserved_at_0[0x80];
1612
1613         u8         rppp_max_rps[0x20];
1614
1615         u8         rpg_time_reset[0x20];
1616
1617         u8         rpg_byte_reset[0x20];
1618
1619         u8         rpg_threshold[0x20];
1620
1621         u8         rpg_max_rate[0x20];
1622
1623         u8         rpg_ai_rate[0x20];
1624
1625         u8         rpg_hai_rate[0x20];
1626
1627         u8         rpg_gd[0x20];
1628
1629         u8         rpg_min_dec_fac[0x20];
1630
1631         u8         rpg_min_rate[0x20];
1632
1633         u8         reserved_at_1c0[0x640];
1634 };
1635
1636 enum {
1637         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1638         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1639         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1640 };
1641
1642 struct mlx5_ifc_resize_field_select_bits {
1643         u8         resize_field_select[0x20];
1644 };
1645
1646 enum {
1647         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1648         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1649         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1650         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1651 };
1652
1653 struct mlx5_ifc_modify_field_select_bits {
1654         u8         modify_field_select[0x20];
1655 };
1656
1657 struct mlx5_ifc_field_select_r_roce_np_bits {
1658         u8         field_select_r_roce_np[0x20];
1659 };
1660
1661 struct mlx5_ifc_field_select_r_roce_rp_bits {
1662         u8         field_select_r_roce_rp[0x20];
1663 };
1664
1665 enum {
1666         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1667         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1668         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1669         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1670         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1671         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1672         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1673         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1674         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1675         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1676 };
1677
1678 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1679         u8         field_select_8021qaurp[0x20];
1680 };
1681
1682 struct mlx5_ifc_phys_layer_cntrs_bits {
1683         u8         time_since_last_clear_high[0x20];
1684
1685         u8         time_since_last_clear_low[0x20];
1686
1687         u8         symbol_errors_high[0x20];
1688
1689         u8         symbol_errors_low[0x20];
1690
1691         u8         sync_headers_errors_high[0x20];
1692
1693         u8         sync_headers_errors_low[0x20];
1694
1695         u8         edpl_bip_errors_lane0_high[0x20];
1696
1697         u8         edpl_bip_errors_lane0_low[0x20];
1698
1699         u8         edpl_bip_errors_lane1_high[0x20];
1700
1701         u8         edpl_bip_errors_lane1_low[0x20];
1702
1703         u8         edpl_bip_errors_lane2_high[0x20];
1704
1705         u8         edpl_bip_errors_lane2_low[0x20];
1706
1707         u8         edpl_bip_errors_lane3_high[0x20];
1708
1709         u8         edpl_bip_errors_lane3_low[0x20];
1710
1711         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1712
1713         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1714
1715         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1716
1717         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1718
1719         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1720
1721         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1722
1723         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1724
1725         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1726
1727         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1728
1729         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1730
1731         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1732
1733         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1734
1735         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1736
1737         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1738
1739         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1740
1741         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1742
1743         u8         rs_fec_corrected_blocks_high[0x20];
1744
1745         u8         rs_fec_corrected_blocks_low[0x20];
1746
1747         u8         rs_fec_uncorrectable_blocks_high[0x20];
1748
1749         u8         rs_fec_uncorrectable_blocks_low[0x20];
1750
1751         u8         rs_fec_no_errors_blocks_high[0x20];
1752
1753         u8         rs_fec_no_errors_blocks_low[0x20];
1754
1755         u8         rs_fec_single_error_blocks_high[0x20];
1756
1757         u8         rs_fec_single_error_blocks_low[0x20];
1758
1759         u8         rs_fec_corrected_symbols_total_high[0x20];
1760
1761         u8         rs_fec_corrected_symbols_total_low[0x20];
1762
1763         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1764
1765         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1766
1767         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1768
1769         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1770
1771         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1772
1773         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1774
1775         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1776
1777         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1778
1779         u8         link_down_events[0x20];
1780
1781         u8         successful_recovery_events[0x20];
1782
1783         u8         reserved_at_640[0x180];
1784 };
1785
1786 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1787         u8         time_since_last_clear_high[0x20];
1788
1789         u8         time_since_last_clear_low[0x20];
1790
1791         u8         phy_received_bits_high[0x20];
1792
1793         u8         phy_received_bits_low[0x20];
1794
1795         u8         phy_symbol_errors_high[0x20];
1796
1797         u8         phy_symbol_errors_low[0x20];
1798
1799         u8         phy_corrected_bits_high[0x20];
1800
1801         u8         phy_corrected_bits_low[0x20];
1802
1803         u8         phy_corrected_bits_lane0_high[0x20];
1804
1805         u8         phy_corrected_bits_lane0_low[0x20];
1806
1807         u8         phy_corrected_bits_lane1_high[0x20];
1808
1809         u8         phy_corrected_bits_lane1_low[0x20];
1810
1811         u8         phy_corrected_bits_lane2_high[0x20];
1812
1813         u8         phy_corrected_bits_lane2_low[0x20];
1814
1815         u8         phy_corrected_bits_lane3_high[0x20];
1816
1817         u8         phy_corrected_bits_lane3_low[0x20];
1818
1819         u8         reserved_at_200[0x5c0];
1820 };
1821
1822 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1823         u8         symbol_error_counter[0x10];
1824
1825         u8         link_error_recovery_counter[0x8];
1826
1827         u8         link_downed_counter[0x8];
1828
1829         u8         port_rcv_errors[0x10];
1830
1831         u8         port_rcv_remote_physical_errors[0x10];
1832
1833         u8         port_rcv_switch_relay_errors[0x10];
1834
1835         u8         port_xmit_discards[0x10];
1836
1837         u8         port_xmit_constraint_errors[0x8];
1838
1839         u8         port_rcv_constraint_errors[0x8];
1840
1841         u8         reserved_at_70[0x8];
1842
1843         u8         link_overrun_errors[0x8];
1844
1845         u8         reserved_at_80[0x10];
1846
1847         u8         vl_15_dropped[0x10];
1848
1849         u8         reserved_at_a0[0x80];
1850
1851         u8         port_xmit_wait[0x20];
1852 };
1853
1854 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1855         u8         transmit_queue_high[0x20];
1856
1857         u8         transmit_queue_low[0x20];
1858
1859         u8         reserved_at_40[0x780];
1860 };
1861
1862 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1863         u8         rx_octets_high[0x20];
1864
1865         u8         rx_octets_low[0x20];
1866
1867         u8         reserved_at_40[0xc0];
1868
1869         u8         rx_frames_high[0x20];
1870
1871         u8         rx_frames_low[0x20];
1872
1873         u8         tx_octets_high[0x20];
1874
1875         u8         tx_octets_low[0x20];
1876
1877         u8         reserved_at_180[0xc0];
1878
1879         u8         tx_frames_high[0x20];
1880
1881         u8         tx_frames_low[0x20];
1882
1883         u8         rx_pause_high[0x20];
1884
1885         u8         rx_pause_low[0x20];
1886
1887         u8         rx_pause_duration_high[0x20];
1888
1889         u8         rx_pause_duration_low[0x20];
1890
1891         u8         tx_pause_high[0x20];
1892
1893         u8         tx_pause_low[0x20];
1894
1895         u8         tx_pause_duration_high[0x20];
1896
1897         u8         tx_pause_duration_low[0x20];
1898
1899         u8         rx_pause_transition_high[0x20];
1900
1901         u8         rx_pause_transition_low[0x20];
1902
1903         u8         reserved_at_3c0[0x40];
1904
1905         u8         device_stall_minor_watermark_cnt_high[0x20];
1906
1907         u8         device_stall_minor_watermark_cnt_low[0x20];
1908
1909         u8         device_stall_critical_watermark_cnt_high[0x20];
1910
1911         u8         device_stall_critical_watermark_cnt_low[0x20];
1912
1913         u8         reserved_at_480[0x340];
1914 };
1915
1916 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1917         u8         port_transmit_wait_high[0x20];
1918
1919         u8         port_transmit_wait_low[0x20];
1920
1921         u8         reserved_at_40[0x100];
1922
1923         u8         rx_buffer_almost_full_high[0x20];
1924
1925         u8         rx_buffer_almost_full_low[0x20];
1926
1927         u8         rx_buffer_full_high[0x20];
1928
1929         u8         rx_buffer_full_low[0x20];
1930
1931         u8         rx_icrc_encapsulated_high[0x20];
1932
1933         u8         rx_icrc_encapsulated_low[0x20];
1934
1935         u8         reserved_at_200[0x5c0];
1936 };
1937
1938 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1939         u8         dot3stats_alignment_errors_high[0x20];
1940
1941         u8         dot3stats_alignment_errors_low[0x20];
1942
1943         u8         dot3stats_fcs_errors_high[0x20];
1944
1945         u8         dot3stats_fcs_errors_low[0x20];
1946
1947         u8         dot3stats_single_collision_frames_high[0x20];
1948
1949         u8         dot3stats_single_collision_frames_low[0x20];
1950
1951         u8         dot3stats_multiple_collision_frames_high[0x20];
1952
1953         u8         dot3stats_multiple_collision_frames_low[0x20];
1954
1955         u8         dot3stats_sqe_test_errors_high[0x20];
1956
1957         u8         dot3stats_sqe_test_errors_low[0x20];
1958
1959         u8         dot3stats_deferred_transmissions_high[0x20];
1960
1961         u8         dot3stats_deferred_transmissions_low[0x20];
1962
1963         u8         dot3stats_late_collisions_high[0x20];
1964
1965         u8         dot3stats_late_collisions_low[0x20];
1966
1967         u8         dot3stats_excessive_collisions_high[0x20];
1968
1969         u8         dot3stats_excessive_collisions_low[0x20];
1970
1971         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1972
1973         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1974
1975         u8         dot3stats_carrier_sense_errors_high[0x20];
1976
1977         u8         dot3stats_carrier_sense_errors_low[0x20];
1978
1979         u8         dot3stats_frame_too_longs_high[0x20];
1980
1981         u8         dot3stats_frame_too_longs_low[0x20];
1982
1983         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1984
1985         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1986
1987         u8         dot3stats_symbol_errors_high[0x20];
1988
1989         u8         dot3stats_symbol_errors_low[0x20];
1990
1991         u8         dot3control_in_unknown_opcodes_high[0x20];
1992
1993         u8         dot3control_in_unknown_opcodes_low[0x20];
1994
1995         u8         dot3in_pause_frames_high[0x20];
1996
1997         u8         dot3in_pause_frames_low[0x20];
1998
1999         u8         dot3out_pause_frames_high[0x20];
2000
2001         u8         dot3out_pause_frames_low[0x20];
2002
2003         u8         reserved_at_400[0x3c0];
2004 };
2005
2006 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2007         u8         ether_stats_drop_events_high[0x20];
2008
2009         u8         ether_stats_drop_events_low[0x20];
2010
2011         u8         ether_stats_octets_high[0x20];
2012
2013         u8         ether_stats_octets_low[0x20];
2014
2015         u8         ether_stats_pkts_high[0x20];
2016
2017         u8         ether_stats_pkts_low[0x20];
2018
2019         u8         ether_stats_broadcast_pkts_high[0x20];
2020
2021         u8         ether_stats_broadcast_pkts_low[0x20];
2022
2023         u8         ether_stats_multicast_pkts_high[0x20];
2024
2025         u8         ether_stats_multicast_pkts_low[0x20];
2026
2027         u8         ether_stats_crc_align_errors_high[0x20];
2028
2029         u8         ether_stats_crc_align_errors_low[0x20];
2030
2031         u8         ether_stats_undersize_pkts_high[0x20];
2032
2033         u8         ether_stats_undersize_pkts_low[0x20];
2034
2035         u8         ether_stats_oversize_pkts_high[0x20];
2036
2037         u8         ether_stats_oversize_pkts_low[0x20];
2038
2039         u8         ether_stats_fragments_high[0x20];
2040
2041         u8         ether_stats_fragments_low[0x20];
2042
2043         u8         ether_stats_jabbers_high[0x20];
2044
2045         u8         ether_stats_jabbers_low[0x20];
2046
2047         u8         ether_stats_collisions_high[0x20];
2048
2049         u8         ether_stats_collisions_low[0x20];
2050
2051         u8         ether_stats_pkts64octets_high[0x20];
2052
2053         u8         ether_stats_pkts64octets_low[0x20];
2054
2055         u8         ether_stats_pkts65to127octets_high[0x20];
2056
2057         u8         ether_stats_pkts65to127octets_low[0x20];
2058
2059         u8         ether_stats_pkts128to255octets_high[0x20];
2060
2061         u8         ether_stats_pkts128to255octets_low[0x20];
2062
2063         u8         ether_stats_pkts256to511octets_high[0x20];
2064
2065         u8         ether_stats_pkts256to511octets_low[0x20];
2066
2067         u8         ether_stats_pkts512to1023octets_high[0x20];
2068
2069         u8         ether_stats_pkts512to1023octets_low[0x20];
2070
2071         u8         ether_stats_pkts1024to1518octets_high[0x20];
2072
2073         u8         ether_stats_pkts1024to1518octets_low[0x20];
2074
2075         u8         ether_stats_pkts1519to2047octets_high[0x20];
2076
2077         u8         ether_stats_pkts1519to2047octets_low[0x20];
2078
2079         u8         ether_stats_pkts2048to4095octets_high[0x20];
2080
2081         u8         ether_stats_pkts2048to4095octets_low[0x20];
2082
2083         u8         ether_stats_pkts4096to8191octets_high[0x20];
2084
2085         u8         ether_stats_pkts4096to8191octets_low[0x20];
2086
2087         u8         ether_stats_pkts8192to10239octets_high[0x20];
2088
2089         u8         ether_stats_pkts8192to10239octets_low[0x20];
2090
2091         u8         reserved_at_540[0x280];
2092 };
2093
2094 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2095         u8         if_in_octets_high[0x20];
2096
2097         u8         if_in_octets_low[0x20];
2098
2099         u8         if_in_ucast_pkts_high[0x20];
2100
2101         u8         if_in_ucast_pkts_low[0x20];
2102
2103         u8         if_in_discards_high[0x20];
2104
2105         u8         if_in_discards_low[0x20];
2106
2107         u8         if_in_errors_high[0x20];
2108
2109         u8         if_in_errors_low[0x20];
2110
2111         u8         if_in_unknown_protos_high[0x20];
2112
2113         u8         if_in_unknown_protos_low[0x20];
2114
2115         u8         if_out_octets_high[0x20];
2116
2117         u8         if_out_octets_low[0x20];
2118
2119         u8         if_out_ucast_pkts_high[0x20];
2120
2121         u8         if_out_ucast_pkts_low[0x20];
2122
2123         u8         if_out_discards_high[0x20];
2124
2125         u8         if_out_discards_low[0x20];
2126
2127         u8         if_out_errors_high[0x20];
2128
2129         u8         if_out_errors_low[0x20];
2130
2131         u8         if_in_multicast_pkts_high[0x20];
2132
2133         u8         if_in_multicast_pkts_low[0x20];
2134
2135         u8         if_in_broadcast_pkts_high[0x20];
2136
2137         u8         if_in_broadcast_pkts_low[0x20];
2138
2139         u8         if_out_multicast_pkts_high[0x20];
2140
2141         u8         if_out_multicast_pkts_low[0x20];
2142
2143         u8         if_out_broadcast_pkts_high[0x20];
2144
2145         u8         if_out_broadcast_pkts_low[0x20];
2146
2147         u8         reserved_at_340[0x480];
2148 };
2149
2150 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2151         u8         a_frames_transmitted_ok_high[0x20];
2152
2153         u8         a_frames_transmitted_ok_low[0x20];
2154
2155         u8         a_frames_received_ok_high[0x20];
2156
2157         u8         a_frames_received_ok_low[0x20];
2158
2159         u8         a_frame_check_sequence_errors_high[0x20];
2160
2161         u8         a_frame_check_sequence_errors_low[0x20];
2162
2163         u8         a_alignment_errors_high[0x20];
2164
2165         u8         a_alignment_errors_low[0x20];
2166
2167         u8         a_octets_transmitted_ok_high[0x20];
2168
2169         u8         a_octets_transmitted_ok_low[0x20];
2170
2171         u8         a_octets_received_ok_high[0x20];
2172
2173         u8         a_octets_received_ok_low[0x20];
2174
2175         u8         a_multicast_frames_xmitted_ok_high[0x20];
2176
2177         u8         a_multicast_frames_xmitted_ok_low[0x20];
2178
2179         u8         a_broadcast_frames_xmitted_ok_high[0x20];
2180
2181         u8         a_broadcast_frames_xmitted_ok_low[0x20];
2182
2183         u8         a_multicast_frames_received_ok_high[0x20];
2184
2185         u8         a_multicast_frames_received_ok_low[0x20];
2186
2187         u8         a_broadcast_frames_received_ok_high[0x20];
2188
2189         u8         a_broadcast_frames_received_ok_low[0x20];
2190
2191         u8         a_in_range_length_errors_high[0x20];
2192
2193         u8         a_in_range_length_errors_low[0x20];
2194
2195         u8         a_out_of_range_length_field_high[0x20];
2196
2197         u8         a_out_of_range_length_field_low[0x20];
2198
2199         u8         a_frame_too_long_errors_high[0x20];
2200
2201         u8         a_frame_too_long_errors_low[0x20];
2202
2203         u8         a_symbol_error_during_carrier_high[0x20];
2204
2205         u8         a_symbol_error_during_carrier_low[0x20];
2206
2207         u8         a_mac_control_frames_transmitted_high[0x20];
2208
2209         u8         a_mac_control_frames_transmitted_low[0x20];
2210
2211         u8         a_mac_control_frames_received_high[0x20];
2212
2213         u8         a_mac_control_frames_received_low[0x20];
2214
2215         u8         a_unsupported_opcodes_received_high[0x20];
2216
2217         u8         a_unsupported_opcodes_received_low[0x20];
2218
2219         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2220
2221         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2222
2223         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2224
2225         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2226
2227         u8         reserved_at_4c0[0x300];
2228 };
2229
2230 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2231         u8         life_time_counter_high[0x20];
2232
2233         u8         life_time_counter_low[0x20];
2234
2235         u8         rx_errors[0x20];
2236
2237         u8         tx_errors[0x20];
2238
2239         u8         l0_to_recovery_eieos[0x20];
2240
2241         u8         l0_to_recovery_ts[0x20];
2242
2243         u8         l0_to_recovery_framing[0x20];
2244
2245         u8         l0_to_recovery_retrain[0x20];
2246
2247         u8         crc_error_dllp[0x20];
2248
2249         u8         crc_error_tlp[0x20];
2250
2251         u8         tx_overflow_buffer_pkt_high[0x20];
2252
2253         u8         tx_overflow_buffer_pkt_low[0x20];
2254
2255         u8         outbound_stalled_reads[0x20];
2256
2257         u8         outbound_stalled_writes[0x20];
2258
2259         u8         outbound_stalled_reads_events[0x20];
2260
2261         u8         outbound_stalled_writes_events[0x20];
2262
2263         u8         reserved_at_200[0x5c0];
2264 };
2265
2266 struct mlx5_ifc_cmd_inter_comp_event_bits {
2267         u8         command_completion_vector[0x20];
2268
2269         u8         reserved_at_20[0xc0];
2270 };
2271
2272 struct mlx5_ifc_stall_vl_event_bits {
2273         u8         reserved_at_0[0x18];
2274         u8         port_num[0x1];
2275         u8         reserved_at_19[0x3];
2276         u8         vl[0x4];
2277
2278         u8         reserved_at_20[0xa0];
2279 };
2280
2281 struct mlx5_ifc_db_bf_congestion_event_bits {
2282         u8         event_subtype[0x8];
2283         u8         reserved_at_8[0x8];
2284         u8         congestion_level[0x8];
2285         u8         reserved_at_18[0x8];
2286
2287         u8         reserved_at_20[0xa0];
2288 };
2289
2290 struct mlx5_ifc_gpio_event_bits {
2291         u8         reserved_at_0[0x60];
2292
2293         u8         gpio_event_hi[0x20];
2294
2295         u8         gpio_event_lo[0x20];
2296
2297         u8         reserved_at_a0[0x40];
2298 };
2299
2300 struct mlx5_ifc_port_state_change_event_bits {
2301         u8         reserved_at_0[0x40];
2302
2303         u8         port_num[0x4];
2304         u8         reserved_at_44[0x1c];
2305
2306         u8         reserved_at_60[0x80];
2307 };
2308
2309 struct mlx5_ifc_dropped_packet_logged_bits {
2310         u8         reserved_at_0[0xe0];
2311 };
2312
2313 enum {
2314         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2315         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2316 };
2317
2318 struct mlx5_ifc_cq_error_bits {
2319         u8         reserved_at_0[0x8];
2320         u8         cqn[0x18];
2321
2322         u8         reserved_at_20[0x20];
2323
2324         u8         reserved_at_40[0x18];
2325         u8         syndrome[0x8];
2326
2327         u8         reserved_at_60[0x80];
2328 };
2329
2330 struct mlx5_ifc_rdma_page_fault_event_bits {
2331         u8         bytes_committed[0x20];
2332
2333         u8         r_key[0x20];
2334
2335         u8         reserved_at_40[0x10];
2336         u8         packet_len[0x10];
2337
2338         u8         rdma_op_len[0x20];
2339
2340         u8         rdma_va[0x40];
2341
2342         u8         reserved_at_c0[0x5];
2343         u8         rdma[0x1];
2344         u8         write[0x1];
2345         u8         requestor[0x1];
2346         u8         qp_number[0x18];
2347 };
2348
2349 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2350         u8         bytes_committed[0x20];
2351
2352         u8         reserved_at_20[0x10];
2353         u8         wqe_index[0x10];
2354
2355         u8         reserved_at_40[0x10];
2356         u8         len[0x10];
2357
2358         u8         reserved_at_60[0x60];
2359
2360         u8         reserved_at_c0[0x5];
2361         u8         rdma[0x1];
2362         u8         write_read[0x1];
2363         u8         requestor[0x1];
2364         u8         qpn[0x18];
2365 };
2366
2367 struct mlx5_ifc_qp_events_bits {
2368         u8         reserved_at_0[0xa0];
2369
2370         u8         type[0x8];
2371         u8         reserved_at_a8[0x18];
2372
2373         u8         reserved_at_c0[0x8];
2374         u8         qpn_rqn_sqn[0x18];
2375 };
2376
2377 struct mlx5_ifc_dct_events_bits {
2378         u8         reserved_at_0[0xc0];
2379
2380         u8         reserved_at_c0[0x8];
2381         u8         dct_number[0x18];
2382 };
2383
2384 struct mlx5_ifc_comp_event_bits {
2385         u8         reserved_at_0[0xc0];
2386
2387         u8         reserved_at_c0[0x8];
2388         u8         cq_number[0x18];
2389 };
2390
2391 enum {
2392         MLX5_QPC_STATE_RST        = 0x0,
2393         MLX5_QPC_STATE_INIT       = 0x1,
2394         MLX5_QPC_STATE_RTR        = 0x2,
2395         MLX5_QPC_STATE_RTS        = 0x3,
2396         MLX5_QPC_STATE_SQER       = 0x4,
2397         MLX5_QPC_STATE_ERR        = 0x6,
2398         MLX5_QPC_STATE_SQD        = 0x7,
2399         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2400 };
2401
2402 enum {
2403         MLX5_QPC_ST_RC            = 0x0,
2404         MLX5_QPC_ST_UC            = 0x1,
2405         MLX5_QPC_ST_UD            = 0x2,
2406         MLX5_QPC_ST_XRC           = 0x3,
2407         MLX5_QPC_ST_DCI           = 0x5,
2408         MLX5_QPC_ST_QP0           = 0x7,
2409         MLX5_QPC_ST_QP1           = 0x8,
2410         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2411         MLX5_QPC_ST_REG_UMR       = 0xc,
2412 };
2413
2414 enum {
2415         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2416         MLX5_QPC_PM_STATE_REARM     = 0x1,
2417         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2418         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2419 };
2420
2421 enum {
2422         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2423 };
2424
2425 enum {
2426         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2427         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2428 };
2429
2430 enum {
2431         MLX5_QPC_MTU_256_BYTES        = 0x1,
2432         MLX5_QPC_MTU_512_BYTES        = 0x2,
2433         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2434         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2435         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2436         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2437 };
2438
2439 enum {
2440         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2441         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2442         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2443         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2444         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2445         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2446         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2447         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2448 };
2449
2450 enum {
2451         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2452         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2453         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2454 };
2455
2456 enum {
2457         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2458         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2459         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2460 };
2461
2462 struct mlx5_ifc_qpc_bits {
2463         u8         state[0x4];
2464         u8         lag_tx_port_affinity[0x4];
2465         u8         st[0x8];
2466         u8         reserved_at_10[0x3];
2467         u8         pm_state[0x2];
2468         u8         reserved_at_15[0x1];
2469         u8         req_e2e_credit_mode[0x2];
2470         u8         offload_type[0x4];
2471         u8         end_padding_mode[0x2];
2472         u8         reserved_at_1e[0x2];
2473
2474         u8         wq_signature[0x1];
2475         u8         block_lb_mc[0x1];
2476         u8         atomic_like_write_en[0x1];
2477         u8         latency_sensitive[0x1];
2478         u8         reserved_at_24[0x1];
2479         u8         drain_sigerr[0x1];
2480         u8         reserved_at_26[0x2];
2481         u8         pd[0x18];
2482
2483         u8         mtu[0x3];
2484         u8         log_msg_max[0x5];
2485         u8         reserved_at_48[0x1];
2486         u8         log_rq_size[0x4];
2487         u8         log_rq_stride[0x3];
2488         u8         no_sq[0x1];
2489         u8         log_sq_size[0x4];
2490         u8         reserved_at_55[0x6];
2491         u8         rlky[0x1];
2492         u8         ulp_stateless_offload_mode[0x4];
2493
2494         u8         counter_set_id[0x8];
2495         u8         uar_page[0x18];
2496
2497         u8         reserved_at_80[0x8];
2498         u8         user_index[0x18];
2499
2500         u8         reserved_at_a0[0x3];
2501         u8         log_page_size[0x5];
2502         u8         remote_qpn[0x18];
2503
2504         struct mlx5_ifc_ads_bits primary_address_path;
2505
2506         struct mlx5_ifc_ads_bits secondary_address_path;
2507
2508         u8         log_ack_req_freq[0x4];
2509         u8         reserved_at_384[0x4];
2510         u8         log_sra_max[0x3];
2511         u8         reserved_at_38b[0x2];
2512         u8         retry_count[0x3];
2513         u8         rnr_retry[0x3];
2514         u8         reserved_at_393[0x1];
2515         u8         fre[0x1];
2516         u8         cur_rnr_retry[0x3];
2517         u8         cur_retry_count[0x3];
2518         u8         reserved_at_39b[0x5];
2519
2520         u8         reserved_at_3a0[0x20];
2521
2522         u8         reserved_at_3c0[0x8];
2523         u8         next_send_psn[0x18];
2524
2525         u8         reserved_at_3e0[0x8];
2526         u8         cqn_snd[0x18];
2527
2528         u8         reserved_at_400[0x8];
2529         u8         deth_sqpn[0x18];
2530
2531         u8         reserved_at_420[0x20];
2532
2533         u8         reserved_at_440[0x8];
2534         u8         last_acked_psn[0x18];
2535
2536         u8         reserved_at_460[0x8];
2537         u8         ssn[0x18];
2538
2539         u8         reserved_at_480[0x8];
2540         u8         log_rra_max[0x3];
2541         u8         reserved_at_48b[0x1];
2542         u8         atomic_mode[0x4];
2543         u8         rre[0x1];
2544         u8         rwe[0x1];
2545         u8         rae[0x1];
2546         u8         reserved_at_493[0x1];
2547         u8         page_offset[0x6];
2548         u8         reserved_at_49a[0x3];
2549         u8         cd_slave_receive[0x1];
2550         u8         cd_slave_send[0x1];
2551         u8         cd_master[0x1];
2552
2553         u8         reserved_at_4a0[0x3];
2554         u8         min_rnr_nak[0x5];
2555         u8         next_rcv_psn[0x18];
2556
2557         u8         reserved_at_4c0[0x8];
2558         u8         xrcd[0x18];
2559
2560         u8         reserved_at_4e0[0x8];
2561         u8         cqn_rcv[0x18];
2562
2563         u8         dbr_addr[0x40];
2564
2565         u8         q_key[0x20];
2566
2567         u8         reserved_at_560[0x5];
2568         u8         rq_type[0x3];
2569         u8         srqn_rmpn_xrqn[0x18];
2570
2571         u8         reserved_at_580[0x8];
2572         u8         rmsn[0x18];
2573
2574         u8         hw_sq_wqebb_counter[0x10];
2575         u8         sw_sq_wqebb_counter[0x10];
2576
2577         u8         hw_rq_counter[0x20];
2578
2579         u8         sw_rq_counter[0x20];
2580
2581         u8         reserved_at_600[0x20];
2582
2583         u8         reserved_at_620[0xf];
2584         u8         cgs[0x1];
2585         u8         cs_req[0x8];
2586         u8         cs_res[0x8];
2587
2588         u8         dc_access_key[0x40];
2589
2590         u8         reserved_at_680[0x3];
2591         u8         dbr_umem_valid[0x1];
2592
2593         u8         reserved_at_684[0xbc];
2594 };
2595
2596 struct mlx5_ifc_roce_addr_layout_bits {
2597         u8         source_l3_address[16][0x8];
2598
2599         u8         reserved_at_80[0x3];
2600         u8         vlan_valid[0x1];
2601         u8         vlan_id[0xc];
2602         u8         source_mac_47_32[0x10];
2603
2604         u8         source_mac_31_0[0x20];
2605
2606         u8         reserved_at_c0[0x14];
2607         u8         roce_l3_type[0x4];
2608         u8         roce_version[0x8];
2609
2610         u8         reserved_at_e0[0x20];
2611 };
2612
2613 union mlx5_ifc_hca_cap_union_bits {
2614         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2615         struct mlx5_ifc_odp_cap_bits odp_cap;
2616         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2617         struct mlx5_ifc_roce_cap_bits roce_cap;
2618         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2619         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2620         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2621         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2622         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2623         struct mlx5_ifc_qos_cap_bits qos_cap;
2624         struct mlx5_ifc_debug_cap_bits debug_cap;
2625         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2626         struct mlx5_ifc_tls_cap_bits tls_cap;
2627         u8         reserved_at_0[0x8000];
2628 };
2629
2630 enum {
2631         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2632         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2633         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2634         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2635         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2636         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2637         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2638         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2639         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2640         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
2641         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2642 };
2643
2644 enum {
2645         MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
2646         MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
2647         MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
2648 };
2649
2650 struct mlx5_ifc_vlan_bits {
2651         u8         ethtype[0x10];
2652         u8         prio[0x3];
2653         u8         cfi[0x1];
2654         u8         vid[0xc];
2655 };
2656
2657 struct mlx5_ifc_flow_context_bits {
2658         struct mlx5_ifc_vlan_bits push_vlan;
2659
2660         u8         group_id[0x20];
2661
2662         u8         reserved_at_40[0x8];
2663         u8         flow_tag[0x18];
2664
2665         u8         reserved_at_60[0x10];
2666         u8         action[0x10];
2667
2668         u8         extended_destination[0x1];
2669         u8         reserved_at_81[0x1];
2670         u8         flow_source[0x2];
2671         u8         reserved_at_84[0x4];
2672         u8         destination_list_size[0x18];
2673
2674         u8         reserved_at_a0[0x8];
2675         u8         flow_counter_list_size[0x18];
2676
2677         u8         packet_reformat_id[0x20];
2678
2679         u8         modify_header_id[0x20];
2680
2681         struct mlx5_ifc_vlan_bits push_vlan_2;
2682
2683         u8         reserved_at_120[0xe0];
2684
2685         struct mlx5_ifc_fte_match_param_bits match_value;
2686
2687         u8         reserved_at_1200[0x600];
2688
2689         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2690 };
2691
2692 enum {
2693         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2694         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2695 };
2696
2697 struct mlx5_ifc_xrc_srqc_bits {
2698         u8         state[0x4];
2699         u8         log_xrc_srq_size[0x4];
2700         u8         reserved_at_8[0x18];
2701
2702         u8         wq_signature[0x1];
2703         u8         cont_srq[0x1];
2704         u8         reserved_at_22[0x1];
2705         u8         rlky[0x1];
2706         u8         basic_cyclic_rcv_wqe[0x1];
2707         u8         log_rq_stride[0x3];
2708         u8         xrcd[0x18];
2709
2710         u8         page_offset[0x6];
2711         u8         reserved_at_46[0x1];
2712         u8         dbr_umem_valid[0x1];
2713         u8         cqn[0x18];
2714
2715         u8         reserved_at_60[0x20];
2716
2717         u8         user_index_equal_xrc_srqn[0x1];
2718         u8         reserved_at_81[0x1];
2719         u8         log_page_size[0x6];
2720         u8         user_index[0x18];
2721
2722         u8         reserved_at_a0[0x20];
2723
2724         u8         reserved_at_c0[0x8];
2725         u8         pd[0x18];
2726
2727         u8         lwm[0x10];
2728         u8         wqe_cnt[0x10];
2729
2730         u8         reserved_at_100[0x40];
2731
2732         u8         db_record_addr_h[0x20];
2733
2734         u8         db_record_addr_l[0x1e];
2735         u8         reserved_at_17e[0x2];
2736
2737         u8         reserved_at_180[0x80];
2738 };
2739
2740 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2741         u8         counter_error_queues[0x20];
2742
2743         u8         total_error_queues[0x20];
2744
2745         u8         send_queue_priority_update_flow[0x20];
2746
2747         u8         reserved_at_60[0x20];
2748
2749         u8         nic_receive_steering_discard[0x40];
2750
2751         u8         receive_discard_vport_down[0x40];
2752
2753         u8         transmit_discard_vport_down[0x40];
2754
2755         u8         reserved_at_140[0xec0];
2756 };
2757
2758 struct mlx5_ifc_traffic_counter_bits {
2759         u8         packets[0x40];
2760
2761         u8         octets[0x40];
2762 };
2763
2764 struct mlx5_ifc_tisc_bits {
2765         u8         strict_lag_tx_port_affinity[0x1];
2766         u8         tls_en[0x1];
2767         u8         reserved_at_1[0x2];
2768         u8         lag_tx_port_affinity[0x04];
2769
2770         u8         reserved_at_8[0x4];
2771         u8         prio[0x4];
2772         u8         reserved_at_10[0x10];
2773
2774         u8         reserved_at_20[0x100];
2775
2776         u8         reserved_at_120[0x8];
2777         u8         transport_domain[0x18];
2778
2779         u8         reserved_at_140[0x8];
2780         u8         underlay_qpn[0x18];
2781
2782         u8         reserved_at_160[0x8];
2783         u8         pd[0x18];
2784
2785         u8         reserved_at_180[0x380];
2786 };
2787
2788 enum {
2789         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2790         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2791 };
2792
2793 enum {
2794         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2795         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2796 };
2797
2798 enum {
2799         MLX5_RX_HASH_FN_NONE           = 0x0,
2800         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2801         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2802 };
2803
2804 enum {
2805         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
2806         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
2807 };
2808
2809 struct mlx5_ifc_tirc_bits {
2810         u8         reserved_at_0[0x20];
2811
2812         u8         disp_type[0x4];
2813         u8         reserved_at_24[0x1c];
2814
2815         u8         reserved_at_40[0x40];
2816
2817         u8         reserved_at_80[0x4];
2818         u8         lro_timeout_period_usecs[0x10];
2819         u8         lro_enable_mask[0x4];
2820         u8         lro_max_ip_payload_size[0x8];
2821
2822         u8         reserved_at_a0[0x40];
2823
2824         u8         reserved_at_e0[0x8];
2825         u8         inline_rqn[0x18];
2826
2827         u8         rx_hash_symmetric[0x1];
2828         u8         reserved_at_101[0x1];
2829         u8         tunneled_offload_en[0x1];
2830         u8         reserved_at_103[0x5];
2831         u8         indirect_table[0x18];
2832
2833         u8         rx_hash_fn[0x4];
2834         u8         reserved_at_124[0x2];
2835         u8         self_lb_block[0x2];
2836         u8         transport_domain[0x18];
2837
2838         u8         rx_hash_toeplitz_key[10][0x20];
2839
2840         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2841
2842         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2843
2844         u8         reserved_at_2c0[0x4c0];
2845 };
2846
2847 enum {
2848         MLX5_SRQC_STATE_GOOD   = 0x0,
2849         MLX5_SRQC_STATE_ERROR  = 0x1,
2850 };
2851
2852 struct mlx5_ifc_srqc_bits {
2853         u8         state[0x4];
2854         u8         log_srq_size[0x4];
2855         u8         reserved_at_8[0x18];
2856
2857         u8         wq_signature[0x1];
2858         u8         cont_srq[0x1];
2859         u8         reserved_at_22[0x1];
2860         u8         rlky[0x1];
2861         u8         reserved_at_24[0x1];
2862         u8         log_rq_stride[0x3];
2863         u8         xrcd[0x18];
2864
2865         u8         page_offset[0x6];
2866         u8         reserved_at_46[0x2];
2867         u8         cqn[0x18];
2868
2869         u8         reserved_at_60[0x20];
2870
2871         u8         reserved_at_80[0x2];
2872         u8         log_page_size[0x6];
2873         u8         reserved_at_88[0x18];
2874
2875         u8         reserved_at_a0[0x20];
2876
2877         u8         reserved_at_c0[0x8];
2878         u8         pd[0x18];
2879
2880         u8         lwm[0x10];
2881         u8         wqe_cnt[0x10];
2882
2883         u8         reserved_at_100[0x40];
2884
2885         u8         dbr_addr[0x40];
2886
2887         u8         reserved_at_180[0x80];
2888 };
2889
2890 enum {
2891         MLX5_SQC_STATE_RST  = 0x0,
2892         MLX5_SQC_STATE_RDY  = 0x1,
2893         MLX5_SQC_STATE_ERR  = 0x3,
2894 };
2895
2896 struct mlx5_ifc_sqc_bits {
2897         u8         rlky[0x1];
2898         u8         cd_master[0x1];
2899         u8         fre[0x1];
2900         u8         flush_in_error_en[0x1];
2901         u8         allow_multi_pkt_send_wqe[0x1];
2902         u8         min_wqe_inline_mode[0x3];
2903         u8         state[0x4];
2904         u8         reg_umr[0x1];
2905         u8         allow_swp[0x1];
2906         u8         hairpin[0x1];
2907         u8         reserved_at_f[0x11];
2908
2909         u8         reserved_at_20[0x8];
2910         u8         user_index[0x18];
2911
2912         u8         reserved_at_40[0x8];
2913         u8         cqn[0x18];
2914
2915         u8         reserved_at_60[0x8];
2916         u8         hairpin_peer_rq[0x18];
2917
2918         u8         reserved_at_80[0x10];
2919         u8         hairpin_peer_vhca[0x10];
2920
2921         u8         reserved_at_a0[0x50];
2922
2923         u8         packet_pacing_rate_limit_index[0x10];
2924         u8         tis_lst_sz[0x10];
2925         u8         reserved_at_110[0x10];
2926
2927         u8         reserved_at_120[0x40];
2928
2929         u8         reserved_at_160[0x8];
2930         u8         tis_num_0[0x18];
2931
2932         struct mlx5_ifc_wq_bits wq;
2933 };
2934
2935 enum {
2936         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2937         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2938         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2939         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2940 };
2941
2942 struct mlx5_ifc_scheduling_context_bits {
2943         u8         element_type[0x8];
2944         u8         reserved_at_8[0x18];
2945
2946         u8         element_attributes[0x20];
2947
2948         u8         parent_element_id[0x20];
2949
2950         u8         reserved_at_60[0x40];
2951
2952         u8         bw_share[0x20];
2953
2954         u8         max_average_bw[0x20];
2955
2956         u8         reserved_at_e0[0x120];
2957 };
2958
2959 struct mlx5_ifc_rqtc_bits {
2960         u8         reserved_at_0[0xa0];
2961
2962         u8         reserved_at_a0[0x10];
2963         u8         rqt_max_size[0x10];
2964
2965         u8         reserved_at_c0[0x10];
2966         u8         rqt_actual_size[0x10];
2967
2968         u8         reserved_at_e0[0x6a0];
2969
2970         struct mlx5_ifc_rq_num_bits rq_num[0];
2971 };
2972
2973 enum {
2974         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2975         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2976 };
2977
2978 enum {
2979         MLX5_RQC_STATE_RST  = 0x0,
2980         MLX5_RQC_STATE_RDY  = 0x1,
2981         MLX5_RQC_STATE_ERR  = 0x3,
2982 };
2983
2984 struct mlx5_ifc_rqc_bits {
2985         u8         rlky[0x1];
2986         u8         delay_drop_en[0x1];
2987         u8         scatter_fcs[0x1];
2988         u8         vsd[0x1];
2989         u8         mem_rq_type[0x4];
2990         u8         state[0x4];
2991         u8         reserved_at_c[0x1];
2992         u8         flush_in_error_en[0x1];
2993         u8         hairpin[0x1];
2994         u8         reserved_at_f[0x11];
2995
2996         u8         reserved_at_20[0x8];
2997         u8         user_index[0x18];
2998
2999         u8         reserved_at_40[0x8];
3000         u8         cqn[0x18];
3001
3002         u8         counter_set_id[0x8];
3003         u8         reserved_at_68[0x18];
3004
3005         u8         reserved_at_80[0x8];
3006         u8         rmpn[0x18];
3007
3008         u8         reserved_at_a0[0x8];
3009         u8         hairpin_peer_sq[0x18];
3010
3011         u8         reserved_at_c0[0x10];
3012         u8         hairpin_peer_vhca[0x10];
3013
3014         u8         reserved_at_e0[0xa0];
3015
3016         struct mlx5_ifc_wq_bits wq;
3017 };
3018
3019 enum {
3020         MLX5_RMPC_STATE_RDY  = 0x1,
3021         MLX5_RMPC_STATE_ERR  = 0x3,
3022 };
3023
3024 struct mlx5_ifc_rmpc_bits {
3025         u8         reserved_at_0[0x8];
3026         u8         state[0x4];
3027         u8         reserved_at_c[0x14];
3028
3029         u8         basic_cyclic_rcv_wqe[0x1];
3030         u8         reserved_at_21[0x1f];
3031
3032         u8         reserved_at_40[0x140];
3033
3034         struct mlx5_ifc_wq_bits wq;
3035 };
3036
3037 struct mlx5_ifc_nic_vport_context_bits {
3038         u8         reserved_at_0[0x5];
3039         u8         min_wqe_inline_mode[0x3];
3040         u8         reserved_at_8[0x15];
3041         u8         disable_mc_local_lb[0x1];
3042         u8         disable_uc_local_lb[0x1];
3043         u8         roce_en[0x1];
3044
3045         u8         arm_change_event[0x1];
3046         u8         reserved_at_21[0x1a];
3047         u8         event_on_mtu[0x1];
3048         u8         event_on_promisc_change[0x1];
3049         u8         event_on_vlan_change[0x1];
3050         u8         event_on_mc_address_change[0x1];
3051         u8         event_on_uc_address_change[0x1];
3052
3053         u8         reserved_at_40[0xc];
3054
3055         u8         affiliation_criteria[0x4];
3056         u8         affiliated_vhca_id[0x10];
3057
3058         u8         reserved_at_60[0xd0];
3059
3060         u8         mtu[0x10];
3061
3062         u8         system_image_guid[0x40];
3063         u8         port_guid[0x40];
3064         u8         node_guid[0x40];
3065
3066         u8         reserved_at_200[0x140];
3067         u8         qkey_violation_counter[0x10];
3068         u8         reserved_at_350[0x430];
3069
3070         u8         promisc_uc[0x1];
3071         u8         promisc_mc[0x1];
3072         u8         promisc_all[0x1];
3073         u8         reserved_at_783[0x2];
3074         u8         allowed_list_type[0x3];
3075         u8         reserved_at_788[0xc];
3076         u8         allowed_list_size[0xc];
3077
3078         struct mlx5_ifc_mac_address_layout_bits permanent_address;
3079
3080         u8         reserved_at_7e0[0x20];
3081
3082         u8         current_uc_mac_address[0][0x40];
3083 };
3084
3085 enum {
3086         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
3087         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
3088         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
3089         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
3090         MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3091         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3092 };
3093
3094 struct mlx5_ifc_mkc_bits {
3095         u8         reserved_at_0[0x1];
3096         u8         free[0x1];
3097         u8         reserved_at_2[0x1];
3098         u8         access_mode_4_2[0x3];
3099         u8         reserved_at_6[0x7];
3100         u8         relaxed_ordering_write[0x1];
3101         u8         reserved_at_e[0x1];
3102         u8         small_fence_on_rdma_read_response[0x1];
3103         u8         umr_en[0x1];
3104         u8         a[0x1];
3105         u8         rw[0x1];
3106         u8         rr[0x1];
3107         u8         lw[0x1];
3108         u8         lr[0x1];
3109         u8         access_mode_1_0[0x2];
3110         u8         reserved_at_18[0x8];
3111
3112         u8         qpn[0x18];
3113         u8         mkey_7_0[0x8];
3114
3115         u8         reserved_at_40[0x20];
3116
3117         u8         length64[0x1];
3118         u8         bsf_en[0x1];
3119         u8         sync_umr[0x1];
3120         u8         reserved_at_63[0x2];
3121         u8         expected_sigerr_count[0x1];
3122         u8         reserved_at_66[0x1];
3123         u8         en_rinval[0x1];
3124         u8         pd[0x18];
3125
3126         u8         start_addr[0x40];
3127
3128         u8         len[0x40];
3129
3130         u8         bsf_octword_size[0x20];
3131
3132         u8         reserved_at_120[0x80];
3133
3134         u8         translations_octword_size[0x20];
3135
3136         u8         reserved_at_1c0[0x1b];
3137         u8         log_page_size[0x5];
3138
3139         u8         reserved_at_1e0[0x20];
3140 };
3141
3142 struct mlx5_ifc_pkey_bits {
3143         u8         reserved_at_0[0x10];
3144         u8         pkey[0x10];
3145 };
3146
3147 struct mlx5_ifc_array128_auto_bits {
3148         u8         array128_auto[16][0x8];
3149 };
3150
3151 struct mlx5_ifc_hca_vport_context_bits {
3152         u8         field_select[0x20];
3153
3154         u8         reserved_at_20[0xe0];
3155
3156         u8         sm_virt_aware[0x1];
3157         u8         has_smi[0x1];
3158         u8         has_raw[0x1];
3159         u8         grh_required[0x1];
3160         u8         reserved_at_104[0xc];
3161         u8         port_physical_state[0x4];
3162         u8         vport_state_policy[0x4];
3163         u8         port_state[0x4];
3164         u8         vport_state[0x4];
3165
3166         u8         reserved_at_120[0x20];
3167
3168         u8         system_image_guid[0x40];
3169
3170         u8         port_guid[0x40];
3171
3172         u8         node_guid[0x40];
3173
3174         u8         cap_mask1[0x20];
3175
3176         u8         cap_mask1_field_select[0x20];
3177
3178         u8         cap_mask2[0x20];
3179
3180         u8         cap_mask2_field_select[0x20];
3181
3182         u8         reserved_at_280[0x80];
3183
3184         u8         lid[0x10];
3185         u8         reserved_at_310[0x4];
3186         u8         init_type_reply[0x4];
3187         u8         lmc[0x3];
3188         u8         subnet_timeout[0x5];
3189
3190         u8         sm_lid[0x10];
3191         u8         sm_sl[0x4];
3192         u8         reserved_at_334[0xc];
3193
3194         u8         qkey_violation_counter[0x10];
3195         u8         pkey_violation_counter[0x10];
3196
3197         u8         reserved_at_360[0xca0];
3198 };
3199
3200 struct mlx5_ifc_esw_vport_context_bits {
3201         u8         fdb_to_vport_reg_c[0x1];
3202         u8         reserved_at_1[0x2];
3203         u8         vport_svlan_strip[0x1];
3204         u8         vport_cvlan_strip[0x1];
3205         u8         vport_svlan_insert[0x1];
3206         u8         vport_cvlan_insert[0x2];
3207         u8         fdb_to_vport_reg_c_id[0x8];
3208         u8         reserved_at_10[0x10];
3209
3210         u8         reserved_at_20[0x20];
3211
3212         u8         svlan_cfi[0x1];
3213         u8         svlan_pcp[0x3];
3214         u8         svlan_id[0xc];
3215         u8         cvlan_cfi[0x1];
3216         u8         cvlan_pcp[0x3];
3217         u8         cvlan_id[0xc];
3218
3219         u8         reserved_at_60[0x7a0];
3220 };
3221
3222 enum {
3223         MLX5_EQC_STATUS_OK                = 0x0,
3224         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
3225 };
3226
3227 enum {
3228         MLX5_EQC_ST_ARMED  = 0x9,
3229         MLX5_EQC_ST_FIRED  = 0xa,
3230 };
3231
3232 struct mlx5_ifc_eqc_bits {
3233         u8         status[0x4];
3234         u8         reserved_at_4[0x9];
3235         u8         ec[0x1];
3236         u8         oi[0x1];
3237         u8         reserved_at_f[0x5];
3238         u8         st[0x4];
3239         u8         reserved_at_18[0x8];
3240
3241         u8         reserved_at_20[0x20];
3242
3243         u8         reserved_at_40[0x14];
3244         u8         page_offset[0x6];
3245         u8         reserved_at_5a[0x6];
3246
3247         u8         reserved_at_60[0x3];
3248         u8         log_eq_size[0x5];
3249         u8         uar_page[0x18];
3250
3251         u8         reserved_at_80[0x20];
3252
3253         u8         reserved_at_a0[0x18];
3254         u8         intr[0x8];
3255
3256         u8         reserved_at_c0[0x3];
3257         u8         log_page_size[0x5];
3258         u8         reserved_at_c8[0x18];
3259
3260         u8         reserved_at_e0[0x60];
3261
3262         u8         reserved_at_140[0x8];
3263         u8         consumer_counter[0x18];
3264
3265         u8         reserved_at_160[0x8];
3266         u8         producer_counter[0x18];
3267
3268         u8         reserved_at_180[0x80];
3269 };
3270
3271 enum {
3272         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3273         MLX5_DCTC_STATE_DRAINING  = 0x1,
3274         MLX5_DCTC_STATE_DRAINED   = 0x2,
3275 };
3276
3277 enum {
3278         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3279         MLX5_DCTC_CS_RES_NA         = 0x1,
3280         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3281 };
3282
3283 enum {
3284         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3285         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3286         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3287         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3288         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3289 };
3290
3291 struct mlx5_ifc_dctc_bits {
3292         u8         reserved_at_0[0x4];
3293         u8         state[0x4];
3294         u8         reserved_at_8[0x18];
3295
3296         u8         reserved_at_20[0x8];
3297         u8         user_index[0x18];
3298
3299         u8         reserved_at_40[0x8];
3300         u8         cqn[0x18];
3301
3302         u8         counter_set_id[0x8];
3303         u8         atomic_mode[0x4];
3304         u8         rre[0x1];
3305         u8         rwe[0x1];
3306         u8         rae[0x1];
3307         u8         atomic_like_write_en[0x1];
3308         u8         latency_sensitive[0x1];
3309         u8         rlky[0x1];
3310         u8         free_ar[0x1];
3311         u8         reserved_at_73[0xd];
3312
3313         u8         reserved_at_80[0x8];
3314         u8         cs_res[0x8];
3315         u8         reserved_at_90[0x3];
3316         u8         min_rnr_nak[0x5];
3317         u8         reserved_at_98[0x8];
3318
3319         u8         reserved_at_a0[0x8];
3320         u8         srqn_xrqn[0x18];
3321
3322         u8         reserved_at_c0[0x8];
3323         u8         pd[0x18];
3324
3325         u8         tclass[0x8];
3326         u8         reserved_at_e8[0x4];
3327         u8         flow_label[0x14];
3328
3329         u8         dc_access_key[0x40];
3330
3331         u8         reserved_at_140[0x5];
3332         u8         mtu[0x3];
3333         u8         port[0x8];
3334         u8         pkey_index[0x10];
3335
3336         u8         reserved_at_160[0x8];
3337         u8         my_addr_index[0x8];
3338         u8         reserved_at_170[0x8];
3339         u8         hop_limit[0x8];
3340
3341         u8         dc_access_key_violation_count[0x20];
3342
3343         u8         reserved_at_1a0[0x14];
3344         u8         dei_cfi[0x1];
3345         u8         eth_prio[0x3];
3346         u8         ecn[0x2];
3347         u8         dscp[0x6];
3348
3349         u8         reserved_at_1c0[0x40];
3350 };
3351
3352 enum {
3353         MLX5_CQC_STATUS_OK             = 0x0,
3354         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3355         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3356 };
3357
3358 enum {
3359         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3360         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3361 };
3362
3363 enum {
3364         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3365         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3366         MLX5_CQC_ST_FIRED                                 = 0xa,
3367 };
3368
3369 enum {
3370         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3371         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3372         MLX5_CQ_PERIOD_NUM_MODES
3373 };
3374
3375 struct mlx5_ifc_cqc_bits {
3376         u8         status[0x4];
3377         u8         reserved_at_4[0x2];
3378         u8         dbr_umem_valid[0x1];
3379         u8         reserved_at_7[0x1];
3380         u8         cqe_sz[0x3];
3381         u8         cc[0x1];
3382         u8         reserved_at_c[0x1];
3383         u8         scqe_break_moderation_en[0x1];
3384         u8         oi[0x1];
3385         u8         cq_period_mode[0x2];
3386         u8         cqe_comp_en[0x1];
3387         u8         mini_cqe_res_format[0x2];
3388         u8         st[0x4];
3389         u8         reserved_at_18[0x8];
3390
3391         u8         reserved_at_20[0x20];
3392
3393         u8         reserved_at_40[0x14];
3394         u8         page_offset[0x6];
3395         u8         reserved_at_5a[0x6];
3396
3397         u8         reserved_at_60[0x3];
3398         u8         log_cq_size[0x5];
3399         u8         uar_page[0x18];
3400
3401         u8         reserved_at_80[0x4];
3402         u8         cq_period[0xc];
3403         u8         cq_max_count[0x10];
3404
3405         u8         reserved_at_a0[0x18];
3406         u8         c_eqn[0x8];
3407
3408         u8         reserved_at_c0[0x3];
3409         u8         log_page_size[0x5];
3410         u8         reserved_at_c8[0x18];
3411
3412         u8         reserved_at_e0[0x20];
3413
3414         u8         reserved_at_100[0x8];
3415         u8         last_notified_index[0x18];
3416
3417         u8         reserved_at_120[0x8];
3418         u8         last_solicit_index[0x18];
3419
3420         u8         reserved_at_140[0x8];
3421         u8         consumer_counter[0x18];
3422
3423         u8         reserved_at_160[0x8];
3424         u8         producer_counter[0x18];
3425
3426         u8         reserved_at_180[0x40];
3427
3428         u8         dbr_addr[0x40];
3429 };
3430
3431 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3432         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3433         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3434         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3435         u8         reserved_at_0[0x800];
3436 };
3437
3438 struct mlx5_ifc_query_adapter_param_block_bits {
3439         u8         reserved_at_0[0xc0];
3440
3441         u8         reserved_at_c0[0x8];
3442         u8         ieee_vendor_id[0x18];
3443
3444         u8         reserved_at_e0[0x10];
3445         u8         vsd_vendor_id[0x10];
3446
3447         u8         vsd[208][0x8];
3448
3449         u8         vsd_contd_psid[16][0x8];
3450 };
3451
3452 enum {
3453         MLX5_XRQC_STATE_GOOD   = 0x0,
3454         MLX5_XRQC_STATE_ERROR  = 0x1,
3455 };
3456
3457 enum {
3458         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3459         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3460 };
3461
3462 enum {
3463         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3464 };
3465
3466 struct mlx5_ifc_tag_matching_topology_context_bits {
3467         u8         log_matching_list_sz[0x4];
3468         u8         reserved_at_4[0xc];
3469         u8         append_next_index[0x10];
3470
3471         u8         sw_phase_cnt[0x10];
3472         u8         hw_phase_cnt[0x10];
3473
3474         u8         reserved_at_40[0x40];
3475 };
3476
3477 struct mlx5_ifc_xrqc_bits {
3478         u8         state[0x4];
3479         u8         rlkey[0x1];
3480         u8         reserved_at_5[0xf];
3481         u8         topology[0x4];
3482         u8         reserved_at_18[0x4];
3483         u8         offload[0x4];
3484
3485         u8         reserved_at_20[0x8];
3486         u8         user_index[0x18];
3487
3488         u8         reserved_at_40[0x8];
3489         u8         cqn[0x18];
3490
3491         u8         reserved_at_60[0xa0];
3492
3493         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3494
3495         u8         reserved_at_180[0x280];
3496
3497         struct mlx5_ifc_wq_bits wq;
3498 };
3499
3500 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3501         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3502         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3503         u8         reserved_at_0[0x20];
3504 };
3505
3506 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3507         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3508         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3509         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3510         u8         reserved_at_0[0x20];
3511 };
3512
3513 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3514         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3515         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3516         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3517         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3518         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3519         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3520         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3521         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3522         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3523         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3524         u8         reserved_at_0[0x7c0];
3525 };
3526
3527 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3528         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3529         u8         reserved_at_0[0x7c0];
3530 };
3531
3532 union mlx5_ifc_event_auto_bits {
3533         struct mlx5_ifc_comp_event_bits comp_event;
3534         struct mlx5_ifc_dct_events_bits dct_events;
3535         struct mlx5_ifc_qp_events_bits qp_events;
3536         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3537         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3538         struct mlx5_ifc_cq_error_bits cq_error;
3539         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3540         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3541         struct mlx5_ifc_gpio_event_bits gpio_event;
3542         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3543         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3544         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3545         u8         reserved_at_0[0xe0];
3546 };
3547
3548 struct mlx5_ifc_health_buffer_bits {
3549         u8         reserved_at_0[0x100];
3550
3551         u8         assert_existptr[0x20];
3552
3553         u8         assert_callra[0x20];
3554
3555         u8         reserved_at_140[0x40];
3556
3557         u8         fw_version[0x20];
3558
3559         u8         hw_id[0x20];
3560
3561         u8         reserved_at_1c0[0x20];
3562
3563         u8         irisc_index[0x8];
3564         u8         synd[0x8];
3565         u8         ext_synd[0x10];
3566 };
3567
3568 struct mlx5_ifc_register_loopback_control_bits {
3569         u8         no_lb[0x1];
3570         u8         reserved_at_1[0x7];
3571         u8         port[0x8];
3572         u8         reserved_at_10[0x10];
3573
3574         u8         reserved_at_20[0x60];
3575 };
3576
3577 struct mlx5_ifc_vport_tc_element_bits {
3578         u8         traffic_class[0x4];
3579         u8         reserved_at_4[0xc];
3580         u8         vport_number[0x10];
3581 };
3582
3583 struct mlx5_ifc_vport_element_bits {
3584         u8         reserved_at_0[0x10];
3585         u8         vport_number[0x10];
3586 };
3587
3588 enum {
3589         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3590         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3591         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3592 };
3593
3594 struct mlx5_ifc_tsar_element_bits {
3595         u8         reserved_at_0[0x8];
3596         u8         tsar_type[0x8];
3597         u8         reserved_at_10[0x10];
3598 };
3599
3600 enum {
3601         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3602         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3603 };
3604
3605 struct mlx5_ifc_teardown_hca_out_bits {
3606         u8         status[0x8];
3607         u8         reserved_at_8[0x18];
3608
3609         u8         syndrome[0x20];
3610
3611         u8         reserved_at_40[0x3f];
3612
3613         u8         state[0x1];
3614 };
3615
3616 enum {
3617         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3618         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3619         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3620 };
3621
3622 struct mlx5_ifc_teardown_hca_in_bits {
3623         u8         opcode[0x10];
3624         u8         reserved_at_10[0x10];
3625
3626         u8         reserved_at_20[0x10];
3627         u8         op_mod[0x10];
3628
3629         u8         reserved_at_40[0x10];
3630         u8         profile[0x10];
3631
3632         u8         reserved_at_60[0x20];
3633 };
3634
3635 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3636         u8         status[0x8];
3637         u8         reserved_at_8[0x18];
3638
3639         u8         syndrome[0x20];
3640
3641         u8         reserved_at_40[0x40];
3642 };
3643
3644 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3645         u8         opcode[0x10];
3646         u8         uid[0x10];
3647
3648         u8         reserved_at_20[0x10];
3649         u8         op_mod[0x10];
3650
3651         u8         reserved_at_40[0x8];
3652         u8         qpn[0x18];
3653
3654         u8         reserved_at_60[0x20];
3655
3656         u8         opt_param_mask[0x20];
3657
3658         u8         reserved_at_a0[0x20];
3659
3660         struct mlx5_ifc_qpc_bits qpc;
3661
3662         u8         reserved_at_800[0x80];
3663 };
3664
3665 struct mlx5_ifc_sqd2rts_qp_out_bits {
3666         u8         status[0x8];
3667         u8         reserved_at_8[0x18];
3668
3669         u8         syndrome[0x20];
3670
3671         u8         reserved_at_40[0x40];
3672 };
3673
3674 struct mlx5_ifc_sqd2rts_qp_in_bits {
3675         u8         opcode[0x10];
3676         u8         uid[0x10];
3677
3678         u8         reserved_at_20[0x10];
3679         u8         op_mod[0x10];
3680
3681         u8         reserved_at_40[0x8];
3682         u8         qpn[0x18];
3683
3684         u8         reserved_at_60[0x20];
3685
3686         u8         opt_param_mask[0x20];
3687
3688         u8         reserved_at_a0[0x20];
3689
3690         struct mlx5_ifc_qpc_bits qpc;
3691
3692         u8         reserved_at_800[0x80];
3693 };
3694
3695 struct mlx5_ifc_set_roce_address_out_bits {
3696         u8         status[0x8];
3697         u8         reserved_at_8[0x18];
3698
3699         u8         syndrome[0x20];
3700
3701         u8         reserved_at_40[0x40];
3702 };
3703
3704 struct mlx5_ifc_set_roce_address_in_bits {
3705         u8         opcode[0x10];
3706         u8         reserved_at_10[0x10];
3707
3708         u8         reserved_at_20[0x10];
3709         u8         op_mod[0x10];
3710
3711         u8         roce_address_index[0x10];
3712         u8         reserved_at_50[0xc];
3713         u8         vhca_port_num[0x4];
3714
3715         u8         reserved_at_60[0x20];
3716
3717         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3718 };
3719
3720 struct mlx5_ifc_set_mad_demux_out_bits {
3721         u8         status[0x8];
3722         u8         reserved_at_8[0x18];
3723
3724         u8         syndrome[0x20];
3725
3726         u8         reserved_at_40[0x40];
3727 };
3728
3729 enum {
3730         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3731         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3732 };
3733
3734 struct mlx5_ifc_set_mad_demux_in_bits {
3735         u8         opcode[0x10];
3736         u8         reserved_at_10[0x10];
3737
3738         u8         reserved_at_20[0x10];
3739         u8         op_mod[0x10];
3740
3741         u8         reserved_at_40[0x20];
3742
3743         u8         reserved_at_60[0x6];
3744         u8         demux_mode[0x2];
3745         u8         reserved_at_68[0x18];
3746 };
3747
3748 struct mlx5_ifc_set_l2_table_entry_out_bits {
3749         u8         status[0x8];
3750         u8         reserved_at_8[0x18];
3751
3752         u8         syndrome[0x20];
3753
3754         u8         reserved_at_40[0x40];
3755 };
3756
3757 struct mlx5_ifc_set_l2_table_entry_in_bits {
3758         u8         opcode[0x10];
3759         u8         reserved_at_10[0x10];
3760
3761         u8         reserved_at_20[0x10];
3762         u8         op_mod[0x10];
3763
3764         u8         reserved_at_40[0x60];
3765
3766         u8         reserved_at_a0[0x8];
3767         u8         table_index[0x18];
3768
3769         u8         reserved_at_c0[0x20];
3770
3771         u8         reserved_at_e0[0x13];
3772         u8         vlan_valid[0x1];
3773         u8         vlan[0xc];
3774
3775         struct mlx5_ifc_mac_address_layout_bits mac_address;
3776
3777         u8         reserved_at_140[0xc0];
3778 };
3779
3780 struct mlx5_ifc_set_issi_out_bits {
3781         u8         status[0x8];
3782         u8         reserved_at_8[0x18];
3783
3784         u8         syndrome[0x20];
3785
3786         u8         reserved_at_40[0x40];
3787 };
3788
3789 struct mlx5_ifc_set_issi_in_bits {
3790         u8         opcode[0x10];
3791         u8         reserved_at_10[0x10];
3792
3793         u8         reserved_at_20[0x10];
3794         u8         op_mod[0x10];
3795
3796         u8         reserved_at_40[0x10];
3797         u8         current_issi[0x10];
3798
3799         u8         reserved_at_60[0x20];
3800 };
3801
3802 struct mlx5_ifc_set_hca_cap_out_bits {
3803         u8         status[0x8];
3804         u8         reserved_at_8[0x18];
3805
3806         u8         syndrome[0x20];
3807
3808         u8         reserved_at_40[0x40];
3809 };
3810
3811 struct mlx5_ifc_set_hca_cap_in_bits {
3812         u8         opcode[0x10];
3813         u8         reserved_at_10[0x10];
3814
3815         u8         reserved_at_20[0x10];
3816         u8         op_mod[0x10];
3817
3818         u8         reserved_at_40[0x40];
3819
3820         union mlx5_ifc_hca_cap_union_bits capability;
3821 };
3822
3823 enum {
3824         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3825         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3826         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3827         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3828 };
3829
3830 struct mlx5_ifc_set_fte_out_bits {
3831         u8         status[0x8];
3832         u8         reserved_at_8[0x18];
3833
3834         u8         syndrome[0x20];
3835
3836         u8         reserved_at_40[0x40];
3837 };
3838
3839 struct mlx5_ifc_set_fte_in_bits {
3840         u8         opcode[0x10];
3841         u8         reserved_at_10[0x10];
3842
3843         u8         reserved_at_20[0x10];
3844         u8         op_mod[0x10];
3845
3846         u8         other_vport[0x1];
3847         u8         reserved_at_41[0xf];
3848         u8         vport_number[0x10];
3849
3850         u8         reserved_at_60[0x20];
3851
3852         u8         table_type[0x8];
3853         u8         reserved_at_88[0x18];
3854
3855         u8         reserved_at_a0[0x8];
3856         u8         table_id[0x18];
3857
3858         u8         reserved_at_c0[0x18];
3859         u8         modify_enable_mask[0x8];
3860
3861         u8         reserved_at_e0[0x20];
3862
3863         u8         flow_index[0x20];
3864
3865         u8         reserved_at_120[0xe0];
3866
3867         struct mlx5_ifc_flow_context_bits flow_context;
3868 };
3869
3870 struct mlx5_ifc_rts2rts_qp_out_bits {
3871         u8         status[0x8];
3872         u8         reserved_at_8[0x18];
3873
3874         u8         syndrome[0x20];
3875
3876         u8         reserved_at_40[0x40];
3877 };
3878
3879 struct mlx5_ifc_rts2rts_qp_in_bits {
3880         u8         opcode[0x10];
3881         u8         uid[0x10];
3882
3883         u8         reserved_at_20[0x10];
3884         u8         op_mod[0x10];
3885
3886         u8         reserved_at_40[0x8];
3887         u8         qpn[0x18];
3888
3889         u8         reserved_at_60[0x20];
3890
3891         u8         opt_param_mask[0x20];
3892
3893         u8         reserved_at_a0[0x20];
3894
3895         struct mlx5_ifc_qpc_bits qpc;
3896
3897         u8         reserved_at_800[0x80];
3898 };
3899
3900 struct mlx5_ifc_rtr2rts_qp_out_bits {
3901         u8         status[0x8];
3902         u8         reserved_at_8[0x18];
3903
3904         u8         syndrome[0x20];
3905
3906         u8         reserved_at_40[0x40];
3907 };
3908
3909 struct mlx5_ifc_rtr2rts_qp_in_bits {
3910         u8         opcode[0x10];
3911         u8         uid[0x10];
3912
3913         u8         reserved_at_20[0x10];
3914         u8         op_mod[0x10];
3915
3916         u8         reserved_at_40[0x8];
3917         u8         qpn[0x18];
3918
3919         u8         reserved_at_60[0x20];
3920
3921         u8         opt_param_mask[0x20];
3922
3923         u8         reserved_at_a0[0x20];
3924
3925         struct mlx5_ifc_qpc_bits qpc;
3926
3927         u8         reserved_at_800[0x80];
3928 };
3929
3930 struct mlx5_ifc_rst2init_qp_out_bits {
3931         u8         status[0x8];
3932         u8         reserved_at_8[0x18];
3933
3934         u8         syndrome[0x20];
3935
3936         u8         reserved_at_40[0x40];
3937 };
3938
3939 struct mlx5_ifc_rst2init_qp_in_bits {
3940         u8         opcode[0x10];
3941         u8         uid[0x10];
3942
3943         u8         reserved_at_20[0x10];
3944         u8         op_mod[0x10];
3945
3946         u8         reserved_at_40[0x8];
3947         u8         qpn[0x18];
3948
3949         u8         reserved_at_60[0x20];
3950
3951         u8         opt_param_mask[0x20];
3952
3953         u8         reserved_at_a0[0x20];
3954
3955         struct mlx5_ifc_qpc_bits qpc;
3956
3957         u8         reserved_at_800[0x80];
3958 };
3959
3960 struct mlx5_ifc_query_xrq_out_bits {
3961         u8         status[0x8];
3962         u8         reserved_at_8[0x18];
3963
3964         u8         syndrome[0x20];
3965
3966         u8         reserved_at_40[0x40];
3967
3968         struct mlx5_ifc_xrqc_bits xrq_context;
3969 };
3970
3971 struct mlx5_ifc_query_xrq_in_bits {
3972         u8         opcode[0x10];
3973         u8         reserved_at_10[0x10];
3974
3975         u8         reserved_at_20[0x10];
3976         u8         op_mod[0x10];
3977
3978         u8         reserved_at_40[0x8];
3979         u8         xrqn[0x18];
3980
3981         u8         reserved_at_60[0x20];
3982 };
3983
3984 struct mlx5_ifc_query_xrc_srq_out_bits {
3985         u8         status[0x8];
3986         u8         reserved_at_8[0x18];
3987
3988         u8         syndrome[0x20];
3989
3990         u8         reserved_at_40[0x40];
3991
3992         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3993
3994         u8         reserved_at_280[0x600];
3995
3996         u8         pas[0][0x40];
3997 };
3998
3999 struct mlx5_ifc_query_xrc_srq_in_bits {
4000         u8         opcode[0x10];
4001         u8         reserved_at_10[0x10];
4002
4003         u8         reserved_at_20[0x10];
4004         u8         op_mod[0x10];
4005
4006         u8         reserved_at_40[0x8];
4007         u8         xrc_srqn[0x18];
4008
4009         u8         reserved_at_60[0x20];
4010 };
4011
4012 enum {
4013         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4014         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4015 };
4016
4017 struct mlx5_ifc_query_vport_state_out_bits {
4018         u8         status[0x8];
4019         u8         reserved_at_8[0x18];
4020
4021         u8         syndrome[0x20];
4022
4023         u8         reserved_at_40[0x20];
4024
4025         u8         reserved_at_60[0x18];
4026         u8         admin_state[0x4];
4027         u8         state[0x4];
4028 };
4029
4030 enum {
4031         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
4032         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
4033 };
4034
4035 struct mlx5_ifc_arm_monitor_counter_in_bits {
4036         u8         opcode[0x10];
4037         u8         uid[0x10];
4038
4039         u8         reserved_at_20[0x10];
4040         u8         op_mod[0x10];
4041
4042         u8         reserved_at_40[0x20];
4043
4044         u8         reserved_at_60[0x20];
4045 };
4046
4047 struct mlx5_ifc_arm_monitor_counter_out_bits {
4048         u8         status[0x8];
4049         u8         reserved_at_8[0x18];
4050
4051         u8         syndrome[0x20];
4052
4053         u8         reserved_at_40[0x40];
4054 };
4055
4056 enum {
4057         MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
4058         MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4059 };
4060
4061 enum mlx5_monitor_counter_ppcnt {
4062         MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
4063         MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
4064         MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
4065         MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4066         MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
4067         MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
4068 };
4069
4070 enum {
4071         MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
4072 };
4073
4074 struct mlx5_ifc_monitor_counter_output_bits {
4075         u8         reserved_at_0[0x4];
4076         u8         type[0x4];
4077         u8         reserved_at_8[0x8];
4078         u8         counter[0x10];
4079
4080         u8         counter_group_id[0x20];
4081 };
4082
4083 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4084 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
4085 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4086                                           MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4087
4088 struct mlx5_ifc_set_monitor_counter_in_bits {
4089         u8         opcode[0x10];
4090         u8         uid[0x10];
4091
4092         u8         reserved_at_20[0x10];
4093         u8         op_mod[0x10];
4094
4095         u8         reserved_at_40[0x10];
4096         u8         num_of_counters[0x10];
4097
4098         u8         reserved_at_60[0x20];
4099
4100         struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4101 };
4102
4103 struct mlx5_ifc_set_monitor_counter_out_bits {
4104         u8         status[0x8];
4105         u8         reserved_at_8[0x18];
4106
4107         u8         syndrome[0x20];
4108
4109         u8         reserved_at_40[0x40];
4110 };
4111
4112 struct mlx5_ifc_query_vport_state_in_bits {
4113         u8         opcode[0x10];
4114         u8         reserved_at_10[0x10];
4115
4116         u8         reserved_at_20[0x10];
4117         u8         op_mod[0x10];
4118
4119         u8         other_vport[0x1];
4120         u8         reserved_at_41[0xf];
4121         u8         vport_number[0x10];
4122
4123         u8         reserved_at_60[0x20];
4124 };
4125
4126 struct mlx5_ifc_query_vnic_env_out_bits {
4127         u8         status[0x8];
4128         u8         reserved_at_8[0x18];
4129
4130         u8         syndrome[0x20];
4131
4132         u8         reserved_at_40[0x40];
4133
4134         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4135 };
4136
4137 enum {
4138         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4139 };
4140
4141 struct mlx5_ifc_query_vnic_env_in_bits {
4142         u8         opcode[0x10];
4143         u8         reserved_at_10[0x10];
4144
4145         u8         reserved_at_20[0x10];
4146         u8         op_mod[0x10];
4147
4148         u8         other_vport[0x1];
4149         u8         reserved_at_41[0xf];
4150         u8         vport_number[0x10];
4151
4152         u8         reserved_at_60[0x20];
4153 };
4154
4155 struct mlx5_ifc_query_vport_counter_out_bits {
4156         u8         status[0x8];
4157         u8         reserved_at_8[0x18];
4158
4159         u8         syndrome[0x20];
4160
4161         u8         reserved_at_40[0x40];
4162
4163         struct mlx5_ifc_traffic_counter_bits received_errors;
4164
4165         struct mlx5_ifc_traffic_counter_bits transmit_errors;
4166
4167         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4168
4169         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4170
4171         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4172
4173         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4174
4175         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4176
4177         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4178
4179         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4180
4181         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4182
4183         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4184
4185         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4186
4187         u8         reserved_at_680[0xa00];
4188 };
4189
4190 enum {
4191         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4192 };
4193
4194 struct mlx5_ifc_query_vport_counter_in_bits {
4195         u8         opcode[0x10];
4196         u8         reserved_at_10[0x10];
4197
4198         u8         reserved_at_20[0x10];
4199         u8         op_mod[0x10];
4200
4201         u8         other_vport[0x1];
4202         u8         reserved_at_41[0xb];
4203         u8         port_num[0x4];
4204         u8         vport_number[0x10];
4205
4206         u8         reserved_at_60[0x60];
4207
4208         u8         clear[0x1];
4209         u8         reserved_at_c1[0x1f];
4210
4211         u8         reserved_at_e0[0x20];
4212 };
4213
4214 struct mlx5_ifc_query_tis_out_bits {
4215         u8         status[0x8];
4216         u8         reserved_at_8[0x18];
4217
4218         u8         syndrome[0x20];
4219
4220         u8         reserved_at_40[0x40];
4221
4222         struct mlx5_ifc_tisc_bits tis_context;
4223 };
4224
4225 struct mlx5_ifc_query_tis_in_bits {
4226         u8         opcode[0x10];
4227         u8         reserved_at_10[0x10];
4228
4229         u8         reserved_at_20[0x10];
4230         u8         op_mod[0x10];
4231
4232         u8         reserved_at_40[0x8];
4233         u8         tisn[0x18];
4234
4235         u8         reserved_at_60[0x20];
4236 };
4237
4238 struct mlx5_ifc_query_tir_out_bits {
4239         u8         status[0x8];
4240         u8         reserved_at_8[0x18];
4241
4242         u8         syndrome[0x20];
4243
4244         u8         reserved_at_40[0xc0];
4245
4246         struct mlx5_ifc_tirc_bits tir_context;
4247 };
4248
4249 struct mlx5_ifc_query_tir_in_bits {
4250         u8         opcode[0x10];
4251         u8         reserved_at_10[0x10];
4252
4253         u8         reserved_at_20[0x10];
4254         u8         op_mod[0x10];
4255
4256         u8         reserved_at_40[0x8];
4257         u8         tirn[0x18];
4258
4259         u8         reserved_at_60[0x20];
4260 };
4261
4262 struct mlx5_ifc_query_srq_out_bits {
4263         u8         status[0x8];
4264         u8         reserved_at_8[0x18];
4265
4266         u8         syndrome[0x20];
4267
4268         u8         reserved_at_40[0x40];
4269
4270         struct mlx5_ifc_srqc_bits srq_context_entry;
4271
4272         u8         reserved_at_280[0x600];
4273
4274         u8         pas[0][0x40];
4275 };
4276
4277 struct mlx5_ifc_query_srq_in_bits {
4278         u8         opcode[0x10];
4279         u8         reserved_at_10[0x10];
4280
4281         u8         reserved_at_20[0x10];
4282         u8         op_mod[0x10];
4283
4284         u8         reserved_at_40[0x8];
4285         u8         srqn[0x18];
4286
4287         u8         reserved_at_60[0x20];
4288 };
4289
4290 struct mlx5_ifc_query_sq_out_bits {
4291         u8         status[0x8];
4292         u8         reserved_at_8[0x18];
4293
4294         u8         syndrome[0x20];
4295
4296         u8         reserved_at_40[0xc0];
4297
4298         struct mlx5_ifc_sqc_bits sq_context;
4299 };
4300
4301 struct mlx5_ifc_query_sq_in_bits {
4302         u8         opcode[0x10];
4303         u8         reserved_at_10[0x10];
4304
4305         u8         reserved_at_20[0x10];
4306         u8         op_mod[0x10];
4307
4308         u8         reserved_at_40[0x8];
4309         u8         sqn[0x18];
4310
4311         u8         reserved_at_60[0x20];
4312 };
4313
4314 struct mlx5_ifc_query_special_contexts_out_bits {
4315         u8         status[0x8];
4316         u8         reserved_at_8[0x18];
4317
4318         u8         syndrome[0x20];
4319
4320         u8         dump_fill_mkey[0x20];
4321
4322         u8         resd_lkey[0x20];
4323
4324         u8         null_mkey[0x20];
4325
4326         u8         reserved_at_a0[0x60];
4327 };
4328
4329 struct mlx5_ifc_query_special_contexts_in_bits {
4330         u8         opcode[0x10];
4331         u8         reserved_at_10[0x10];
4332
4333         u8         reserved_at_20[0x10];
4334         u8         op_mod[0x10];
4335
4336         u8         reserved_at_40[0x40];
4337 };
4338
4339 struct mlx5_ifc_query_scheduling_element_out_bits {
4340         u8         opcode[0x10];
4341         u8         reserved_at_10[0x10];
4342
4343         u8         reserved_at_20[0x10];
4344         u8         op_mod[0x10];
4345
4346         u8         reserved_at_40[0xc0];
4347
4348         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4349
4350         u8         reserved_at_300[0x100];
4351 };
4352
4353 enum {
4354         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4355 };
4356
4357 struct mlx5_ifc_query_scheduling_element_in_bits {
4358         u8         opcode[0x10];
4359         u8         reserved_at_10[0x10];
4360
4361         u8         reserved_at_20[0x10];
4362         u8         op_mod[0x10];
4363
4364         u8         scheduling_hierarchy[0x8];
4365         u8         reserved_at_48[0x18];
4366
4367         u8         scheduling_element_id[0x20];
4368
4369         u8         reserved_at_80[0x180];
4370 };
4371
4372 struct mlx5_ifc_query_rqt_out_bits {
4373         u8         status[0x8];
4374         u8         reserved_at_8[0x18];
4375
4376         u8         syndrome[0x20];
4377
4378         u8         reserved_at_40[0xc0];
4379
4380         struct mlx5_ifc_rqtc_bits rqt_context;
4381 };
4382
4383 struct mlx5_ifc_query_rqt_in_bits {
4384         u8         opcode[0x10];
4385         u8         reserved_at_10[0x10];
4386
4387         u8         reserved_at_20[0x10];
4388         u8         op_mod[0x10];
4389
4390         u8         reserved_at_40[0x8];
4391         u8         rqtn[0x18];
4392
4393         u8         reserved_at_60[0x20];
4394 };
4395
4396 struct mlx5_ifc_query_rq_out_bits {
4397         u8         status[0x8];
4398         u8         reserved_at_8[0x18];
4399
4400         u8         syndrome[0x20];
4401
4402         u8         reserved_at_40[0xc0];
4403
4404         struct mlx5_ifc_rqc_bits rq_context;
4405 };
4406
4407 struct mlx5_ifc_query_rq_in_bits {
4408         u8         opcode[0x10];
4409         u8         reserved_at_10[0x10];
4410
4411         u8         reserved_at_20[0x10];
4412         u8         op_mod[0x10];
4413
4414         u8         reserved_at_40[0x8];
4415         u8         rqn[0x18];
4416
4417         u8         reserved_at_60[0x20];
4418 };
4419
4420 struct mlx5_ifc_query_roce_address_out_bits {
4421         u8         status[0x8];
4422         u8         reserved_at_8[0x18];
4423
4424         u8         syndrome[0x20];
4425
4426         u8         reserved_at_40[0x40];
4427
4428         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4429 };
4430
4431 struct mlx5_ifc_query_roce_address_in_bits {
4432         u8         opcode[0x10];
4433         u8         reserved_at_10[0x10];
4434
4435         u8         reserved_at_20[0x10];
4436         u8         op_mod[0x10];
4437
4438         u8         roce_address_index[0x10];
4439         u8         reserved_at_50[0xc];
4440         u8         vhca_port_num[0x4];
4441
4442         u8         reserved_at_60[0x20];
4443 };
4444
4445 struct mlx5_ifc_query_rmp_out_bits {
4446         u8         status[0x8];
4447         u8         reserved_at_8[0x18];
4448
4449         u8         syndrome[0x20];
4450
4451         u8         reserved_at_40[0xc0];
4452
4453         struct mlx5_ifc_rmpc_bits rmp_context;
4454 };
4455
4456 struct mlx5_ifc_query_rmp_in_bits {
4457         u8         opcode[0x10];
4458         u8         reserved_at_10[0x10];
4459
4460         u8         reserved_at_20[0x10];
4461         u8         op_mod[0x10];
4462
4463         u8         reserved_at_40[0x8];
4464         u8         rmpn[0x18];
4465
4466         u8         reserved_at_60[0x20];
4467 };
4468
4469 struct mlx5_ifc_query_qp_out_bits {
4470         u8         status[0x8];
4471         u8         reserved_at_8[0x18];
4472
4473         u8         syndrome[0x20];
4474
4475         u8         reserved_at_40[0x40];
4476
4477         u8         opt_param_mask[0x20];
4478
4479         u8         reserved_at_a0[0x20];
4480
4481         struct mlx5_ifc_qpc_bits qpc;
4482
4483         u8         reserved_at_800[0x80];
4484
4485         u8         pas[0][0x40];
4486 };
4487
4488 struct mlx5_ifc_query_qp_in_bits {
4489         u8         opcode[0x10];
4490         u8         reserved_at_10[0x10];
4491
4492         u8         reserved_at_20[0x10];
4493         u8         op_mod[0x10];
4494
4495         u8         reserved_at_40[0x8];
4496         u8         qpn[0x18];
4497
4498         u8         reserved_at_60[0x20];
4499 };
4500
4501 struct mlx5_ifc_query_q_counter_out_bits {
4502         u8         status[0x8];
4503         u8         reserved_at_8[0x18];
4504
4505         u8         syndrome[0x20];
4506
4507         u8         reserved_at_40[0x40];
4508
4509         u8         rx_write_requests[0x20];
4510
4511         u8         reserved_at_a0[0x20];
4512
4513         u8         rx_read_requests[0x20];
4514
4515         u8         reserved_at_e0[0x20];
4516
4517         u8         rx_atomic_requests[0x20];
4518
4519         u8         reserved_at_120[0x20];
4520
4521         u8         rx_dct_connect[0x20];
4522
4523         u8         reserved_at_160[0x20];
4524
4525         u8         out_of_buffer[0x20];
4526
4527         u8         reserved_at_1a0[0x20];
4528
4529         u8         out_of_sequence[0x20];
4530
4531         u8         reserved_at_1e0[0x20];
4532
4533         u8         duplicate_request[0x20];
4534
4535         u8         reserved_at_220[0x20];
4536
4537         u8         rnr_nak_retry_err[0x20];
4538
4539         u8         reserved_at_260[0x20];
4540
4541         u8         packet_seq_err[0x20];
4542
4543         u8         reserved_at_2a0[0x20];
4544
4545         u8         implied_nak_seq_err[0x20];
4546
4547         u8         reserved_at_2e0[0x20];
4548
4549         u8         local_ack_timeout_err[0x20];
4550
4551         u8         reserved_at_320[0xa0];
4552
4553         u8         resp_local_length_error[0x20];
4554
4555         u8         req_local_length_error[0x20];
4556
4557         u8         resp_local_qp_error[0x20];
4558
4559         u8         local_operation_error[0x20];
4560
4561         u8         resp_local_protection[0x20];
4562
4563         u8         req_local_protection[0x20];
4564
4565         u8         resp_cqe_error[0x20];
4566
4567         u8         req_cqe_error[0x20];
4568
4569         u8         req_mw_binding[0x20];
4570
4571         u8         req_bad_response[0x20];
4572
4573         u8         req_remote_invalid_request[0x20];
4574
4575         u8         resp_remote_invalid_request[0x20];
4576
4577         u8         req_remote_access_errors[0x20];
4578
4579         u8         resp_remote_access_errors[0x20];
4580
4581         u8         req_remote_operation_errors[0x20];
4582
4583         u8         req_transport_retries_exceeded[0x20];
4584
4585         u8         cq_overflow[0x20];
4586
4587         u8         resp_cqe_flush_error[0x20];
4588
4589         u8         req_cqe_flush_error[0x20];
4590
4591         u8         reserved_at_620[0x1e0];
4592 };
4593
4594 struct mlx5_ifc_query_q_counter_in_bits {
4595         u8         opcode[0x10];
4596         u8         reserved_at_10[0x10];
4597
4598         u8         reserved_at_20[0x10];
4599         u8         op_mod[0x10];
4600
4601         u8         reserved_at_40[0x80];
4602
4603         u8         clear[0x1];
4604         u8         reserved_at_c1[0x1f];
4605
4606         u8         reserved_at_e0[0x18];
4607         u8         counter_set_id[0x8];
4608 };
4609
4610 struct mlx5_ifc_query_pages_out_bits {
4611         u8         status[0x8];
4612         u8         reserved_at_8[0x18];
4613
4614         u8         syndrome[0x20];
4615
4616         u8         embedded_cpu_function[0x1];
4617         u8         reserved_at_41[0xf];
4618         u8         function_id[0x10];
4619
4620         u8         num_pages[0x20];
4621 };
4622
4623 enum {
4624         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4625         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4626         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4627 };
4628
4629 struct mlx5_ifc_query_pages_in_bits {
4630         u8         opcode[0x10];
4631         u8         reserved_at_10[0x10];
4632
4633         u8         reserved_at_20[0x10];
4634         u8         op_mod[0x10];
4635
4636         u8         embedded_cpu_function[0x1];
4637         u8         reserved_at_41[0xf];
4638         u8         function_id[0x10];
4639
4640         u8         reserved_at_60[0x20];
4641 };
4642
4643 struct mlx5_ifc_query_nic_vport_context_out_bits {
4644         u8         status[0x8];
4645         u8         reserved_at_8[0x18];
4646
4647         u8         syndrome[0x20];
4648
4649         u8         reserved_at_40[0x40];
4650
4651         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4652 };
4653
4654 struct mlx5_ifc_query_nic_vport_context_in_bits {
4655         u8         opcode[0x10];
4656         u8         reserved_at_10[0x10];
4657
4658         u8         reserved_at_20[0x10];
4659         u8         op_mod[0x10];
4660
4661         u8         other_vport[0x1];
4662         u8         reserved_at_41[0xf];
4663         u8         vport_number[0x10];
4664
4665         u8         reserved_at_60[0x5];
4666         u8         allowed_list_type[0x3];
4667         u8         reserved_at_68[0x18];
4668 };
4669
4670 struct mlx5_ifc_query_mkey_out_bits {
4671         u8         status[0x8];
4672         u8         reserved_at_8[0x18];
4673
4674         u8         syndrome[0x20];
4675
4676         u8         reserved_at_40[0x40];
4677
4678         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4679
4680         u8         reserved_at_280[0x600];
4681
4682         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4683
4684         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4685 };
4686
4687 struct mlx5_ifc_query_mkey_in_bits {
4688         u8         opcode[0x10];
4689         u8         reserved_at_10[0x10];
4690
4691         u8         reserved_at_20[0x10];
4692         u8         op_mod[0x10];
4693
4694         u8         reserved_at_40[0x8];
4695         u8         mkey_index[0x18];
4696
4697         u8         pg_access[0x1];
4698         u8         reserved_at_61[0x1f];
4699 };
4700
4701 struct mlx5_ifc_query_mad_demux_out_bits {
4702         u8         status[0x8];
4703         u8         reserved_at_8[0x18];
4704
4705         u8         syndrome[0x20];
4706
4707         u8         reserved_at_40[0x40];
4708
4709         u8         mad_dumux_parameters_block[0x20];
4710 };
4711
4712 struct mlx5_ifc_query_mad_demux_in_bits {
4713         u8         opcode[0x10];
4714         u8         reserved_at_10[0x10];
4715
4716         u8         reserved_at_20[0x10];
4717         u8         op_mod[0x10];
4718
4719         u8         reserved_at_40[0x40];
4720 };
4721
4722 struct mlx5_ifc_query_l2_table_entry_out_bits {
4723         u8         status[0x8];
4724         u8         reserved_at_8[0x18];
4725
4726         u8         syndrome[0x20];
4727
4728         u8         reserved_at_40[0xa0];
4729
4730         u8         reserved_at_e0[0x13];
4731         u8         vlan_valid[0x1];
4732         u8         vlan[0xc];
4733
4734         struct mlx5_ifc_mac_address_layout_bits mac_address;
4735
4736         u8         reserved_at_140[0xc0];
4737 };
4738
4739 struct mlx5_ifc_query_l2_table_entry_in_bits {
4740         u8         opcode[0x10];
4741         u8         reserved_at_10[0x10];
4742
4743         u8         reserved_at_20[0x10];
4744         u8         op_mod[0x10];
4745
4746         u8         reserved_at_40[0x60];
4747
4748         u8         reserved_at_a0[0x8];
4749         u8         table_index[0x18];
4750
4751         u8         reserved_at_c0[0x140];
4752 };
4753
4754 struct mlx5_ifc_query_issi_out_bits {
4755         u8         status[0x8];
4756         u8         reserved_at_8[0x18];
4757
4758         u8         syndrome[0x20];
4759
4760         u8         reserved_at_40[0x10];
4761         u8         current_issi[0x10];
4762
4763         u8         reserved_at_60[0xa0];
4764
4765         u8         reserved_at_100[76][0x8];
4766         u8         supported_issi_dw0[0x20];
4767 };
4768
4769 struct mlx5_ifc_query_issi_in_bits {
4770         u8         opcode[0x10];
4771         u8         reserved_at_10[0x10];
4772
4773         u8         reserved_at_20[0x10];
4774         u8         op_mod[0x10];
4775
4776         u8         reserved_at_40[0x40];
4777 };
4778
4779 struct mlx5_ifc_set_driver_version_out_bits {
4780         u8         status[0x8];
4781         u8         reserved_0[0x18];
4782
4783         u8         syndrome[0x20];
4784         u8         reserved_1[0x40];
4785 };
4786
4787 struct mlx5_ifc_set_driver_version_in_bits {
4788         u8         opcode[0x10];
4789         u8         reserved_0[0x10];
4790
4791         u8         reserved_1[0x10];
4792         u8         op_mod[0x10];
4793
4794         u8         reserved_2[0x40];
4795         u8         driver_version[64][0x8];
4796 };
4797
4798 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4799         u8         status[0x8];
4800         u8         reserved_at_8[0x18];
4801
4802         u8         syndrome[0x20];
4803
4804         u8         reserved_at_40[0x40];
4805
4806         struct mlx5_ifc_pkey_bits pkey[0];
4807 };
4808
4809 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4810         u8         opcode[0x10];
4811         u8         reserved_at_10[0x10];
4812
4813         u8         reserved_at_20[0x10];
4814         u8         op_mod[0x10];
4815
4816         u8         other_vport[0x1];
4817         u8         reserved_at_41[0xb];
4818         u8         port_num[0x4];
4819         u8         vport_number[0x10];
4820
4821         u8         reserved_at_60[0x10];
4822         u8         pkey_index[0x10];
4823 };
4824
4825 enum {
4826         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4827         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4828         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4829 };
4830
4831 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4832         u8         status[0x8];
4833         u8         reserved_at_8[0x18];
4834
4835         u8         syndrome[0x20];
4836
4837         u8         reserved_at_40[0x20];
4838
4839         u8         gids_num[0x10];
4840         u8         reserved_at_70[0x10];
4841
4842         struct mlx5_ifc_array128_auto_bits gid[0];
4843 };
4844
4845 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4846         u8         opcode[0x10];
4847         u8         reserved_at_10[0x10];
4848
4849         u8         reserved_at_20[0x10];
4850         u8         op_mod[0x10];
4851
4852         u8         other_vport[0x1];
4853         u8         reserved_at_41[0xb];
4854         u8         port_num[0x4];
4855         u8         vport_number[0x10];
4856
4857         u8         reserved_at_60[0x10];
4858         u8         gid_index[0x10];
4859 };
4860
4861 struct mlx5_ifc_query_hca_vport_context_out_bits {
4862         u8         status[0x8];
4863         u8         reserved_at_8[0x18];
4864
4865         u8         syndrome[0x20];
4866
4867         u8         reserved_at_40[0x40];
4868
4869         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4870 };
4871
4872 struct mlx5_ifc_query_hca_vport_context_in_bits {
4873         u8         opcode[0x10];
4874         u8         reserved_at_10[0x10];
4875
4876         u8         reserved_at_20[0x10];
4877         u8         op_mod[0x10];
4878
4879         u8         other_vport[0x1];
4880         u8         reserved_at_41[0xb];
4881         u8         port_num[0x4];
4882         u8         vport_number[0x10];
4883
4884         u8         reserved_at_60[0x20];
4885 };
4886
4887 struct mlx5_ifc_query_hca_cap_out_bits {
4888         u8         status[0x8];
4889         u8         reserved_at_8[0x18];
4890
4891         u8         syndrome[0x20];
4892
4893         u8         reserved_at_40[0x40];
4894
4895         union mlx5_ifc_hca_cap_union_bits capability;
4896 };
4897
4898 struct mlx5_ifc_query_hca_cap_in_bits {
4899         u8         opcode[0x10];
4900         u8         reserved_at_10[0x10];
4901
4902         u8         reserved_at_20[0x10];
4903         u8         op_mod[0x10];
4904
4905         u8         reserved_at_40[0x40];
4906 };
4907
4908 struct mlx5_ifc_query_flow_table_out_bits {
4909         u8         status[0x8];
4910         u8         reserved_at_8[0x18];
4911
4912         u8         syndrome[0x20];
4913
4914         u8         reserved_at_40[0x80];
4915
4916         u8         reserved_at_c0[0x8];
4917         u8         level[0x8];
4918         u8         reserved_at_d0[0x8];
4919         u8         log_size[0x8];
4920
4921         u8         reserved_at_e0[0x120];
4922 };
4923
4924 struct mlx5_ifc_query_flow_table_in_bits {
4925         u8         opcode[0x10];
4926         u8         reserved_at_10[0x10];
4927
4928         u8         reserved_at_20[0x10];
4929         u8         op_mod[0x10];
4930
4931         u8         reserved_at_40[0x40];
4932
4933         u8         table_type[0x8];
4934         u8         reserved_at_88[0x18];
4935
4936         u8         reserved_at_a0[0x8];
4937         u8         table_id[0x18];
4938
4939         u8         reserved_at_c0[0x140];
4940 };
4941
4942 struct mlx5_ifc_query_fte_out_bits {
4943         u8         status[0x8];
4944         u8         reserved_at_8[0x18];
4945
4946         u8         syndrome[0x20];
4947
4948         u8         reserved_at_40[0x1c0];
4949
4950         struct mlx5_ifc_flow_context_bits flow_context;
4951 };
4952
4953 struct mlx5_ifc_query_fte_in_bits {
4954         u8         opcode[0x10];
4955         u8         reserved_at_10[0x10];
4956
4957         u8         reserved_at_20[0x10];
4958         u8         op_mod[0x10];
4959
4960         u8         reserved_at_40[0x40];
4961
4962         u8         table_type[0x8];
4963         u8         reserved_at_88[0x18];
4964
4965         u8         reserved_at_a0[0x8];
4966         u8         table_id[0x18];
4967
4968         u8         reserved_at_c0[0x40];
4969
4970         u8         flow_index[0x20];
4971
4972         u8         reserved_at_120[0xe0];
4973 };
4974
4975 enum {
4976         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4977         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4978         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4979         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
4980         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
4981 };
4982
4983 struct mlx5_ifc_query_flow_group_out_bits {
4984         u8         status[0x8];
4985         u8         reserved_at_8[0x18];
4986
4987         u8         syndrome[0x20];
4988
4989         u8         reserved_at_40[0xa0];
4990
4991         u8         start_flow_index[0x20];
4992
4993         u8         reserved_at_100[0x20];
4994
4995         u8         end_flow_index[0x20];
4996
4997         u8         reserved_at_140[0xa0];
4998
4999         u8         reserved_at_1e0[0x18];
5000         u8         match_criteria_enable[0x8];
5001
5002         struct mlx5_ifc_fte_match_param_bits match_criteria;
5003
5004         u8         reserved_at_1200[0xe00];
5005 };
5006
5007 struct mlx5_ifc_query_flow_group_in_bits {
5008         u8         opcode[0x10];
5009         u8         reserved_at_10[0x10];
5010
5011         u8         reserved_at_20[0x10];
5012         u8         op_mod[0x10];
5013
5014         u8         reserved_at_40[0x40];
5015
5016         u8         table_type[0x8];
5017         u8         reserved_at_88[0x18];
5018
5019         u8         reserved_at_a0[0x8];
5020         u8         table_id[0x18];
5021
5022         u8         group_id[0x20];
5023
5024         u8         reserved_at_e0[0x120];
5025 };
5026
5027 struct mlx5_ifc_query_flow_counter_out_bits {
5028         u8         status[0x8];
5029         u8         reserved_at_8[0x18];
5030
5031         u8         syndrome[0x20];
5032
5033         u8         reserved_at_40[0x40];
5034
5035         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
5036 };
5037
5038 struct mlx5_ifc_query_flow_counter_in_bits {
5039         u8         opcode[0x10];
5040         u8         reserved_at_10[0x10];
5041
5042         u8         reserved_at_20[0x10];
5043         u8         op_mod[0x10];
5044
5045         u8         reserved_at_40[0x80];
5046
5047         u8         clear[0x1];
5048         u8         reserved_at_c1[0xf];
5049         u8         num_of_counters[0x10];
5050
5051         u8         flow_counter_id[0x20];
5052 };
5053
5054 struct mlx5_ifc_query_esw_vport_context_out_bits {
5055         u8         status[0x8];
5056         u8         reserved_at_8[0x18];
5057
5058         u8         syndrome[0x20];
5059
5060         u8         reserved_at_40[0x40];
5061
5062         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5063 };
5064
5065 struct mlx5_ifc_query_esw_vport_context_in_bits {
5066         u8         opcode[0x10];
5067         u8         reserved_at_10[0x10];
5068
5069         u8         reserved_at_20[0x10];
5070         u8         op_mod[0x10];
5071
5072         u8         other_vport[0x1];
5073         u8         reserved_at_41[0xf];
5074         u8         vport_number[0x10];
5075
5076         u8         reserved_at_60[0x20];
5077 };
5078
5079 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5080         u8         status[0x8];
5081         u8         reserved_at_8[0x18];
5082
5083         u8         syndrome[0x20];
5084
5085         u8         reserved_at_40[0x40];
5086 };
5087
5088 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5089         u8         reserved_at_0[0x1b];
5090         u8         fdb_to_vport_reg_c_id[0x1];
5091         u8         vport_cvlan_insert[0x1];
5092         u8         vport_svlan_insert[0x1];
5093         u8         vport_cvlan_strip[0x1];
5094         u8         vport_svlan_strip[0x1];
5095 };
5096
5097 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5098         u8         opcode[0x10];
5099         u8         reserved_at_10[0x10];
5100
5101         u8         reserved_at_20[0x10];
5102         u8         op_mod[0x10];
5103
5104         u8         other_vport[0x1];
5105         u8         reserved_at_41[0xf];
5106         u8         vport_number[0x10];
5107
5108         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5109
5110         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5111 };
5112
5113 struct mlx5_ifc_query_eq_out_bits {
5114         u8         status[0x8];
5115         u8         reserved_at_8[0x18];
5116
5117         u8         syndrome[0x20];
5118
5119         u8         reserved_at_40[0x40];
5120
5121         struct mlx5_ifc_eqc_bits eq_context_entry;
5122
5123         u8         reserved_at_280[0x40];
5124
5125         u8         event_bitmask[0x40];
5126
5127         u8         reserved_at_300[0x580];
5128
5129         u8         pas[0][0x40];
5130 };
5131
5132 struct mlx5_ifc_query_eq_in_bits {
5133         u8         opcode[0x10];
5134         u8         reserved_at_10[0x10];
5135
5136         u8         reserved_at_20[0x10];
5137         u8         op_mod[0x10];
5138
5139         u8         reserved_at_40[0x18];
5140         u8         eq_number[0x8];
5141
5142         u8         reserved_at_60[0x20];
5143 };
5144
5145 struct mlx5_ifc_packet_reformat_context_in_bits {
5146         u8         reserved_at_0[0x5];
5147         u8         reformat_type[0x3];
5148         u8         reserved_at_8[0xe];
5149         u8         reformat_data_size[0xa];
5150
5151         u8         reserved_at_20[0x10];
5152         u8         reformat_data[2][0x8];
5153
5154         u8         more_reformat_data[0][0x8];
5155 };
5156
5157 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5158         u8         status[0x8];
5159         u8         reserved_at_8[0x18];
5160
5161         u8         syndrome[0x20];
5162
5163         u8         reserved_at_40[0xa0];
5164
5165         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
5166 };
5167
5168 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5169         u8         opcode[0x10];
5170         u8         reserved_at_10[0x10];
5171
5172         u8         reserved_at_20[0x10];
5173         u8         op_mod[0x10];
5174
5175         u8         packet_reformat_id[0x20];
5176
5177         u8         reserved_at_60[0xa0];
5178 };
5179
5180 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5181         u8         status[0x8];
5182         u8         reserved_at_8[0x18];
5183
5184         u8         syndrome[0x20];
5185
5186         u8         packet_reformat_id[0x20];
5187
5188         u8         reserved_at_60[0x20];
5189 };
5190
5191 enum {
5192         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5193         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5194         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5195         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5196         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5197 };
5198
5199 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5200         u8         opcode[0x10];
5201         u8         reserved_at_10[0x10];
5202
5203         u8         reserved_at_20[0x10];
5204         u8         op_mod[0x10];
5205
5206         u8         reserved_at_40[0xa0];
5207
5208         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5209 };
5210
5211 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5212         u8         status[0x8];
5213         u8         reserved_at_8[0x18];
5214
5215         u8         syndrome[0x20];
5216
5217         u8         reserved_at_40[0x40];
5218 };
5219
5220 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5221         u8         opcode[0x10];
5222         u8         reserved_at_10[0x10];
5223
5224         u8         reserved_20[0x10];
5225         u8         op_mod[0x10];
5226
5227         u8         packet_reformat_id[0x20];
5228
5229         u8         reserved_60[0x20];
5230 };
5231
5232 struct mlx5_ifc_set_action_in_bits {
5233         u8         action_type[0x4];
5234         u8         field[0xc];
5235         u8         reserved_at_10[0x3];
5236         u8         offset[0x5];
5237         u8         reserved_at_18[0x3];
5238         u8         length[0x5];
5239
5240         u8         data[0x20];
5241 };
5242
5243 struct mlx5_ifc_add_action_in_bits {
5244         u8         action_type[0x4];
5245         u8         field[0xc];
5246         u8         reserved_at_10[0x10];
5247
5248         u8         data[0x20];
5249 };
5250
5251 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
5252         struct mlx5_ifc_set_action_in_bits set_action_in;
5253         struct mlx5_ifc_add_action_in_bits add_action_in;
5254         u8         reserved_at_0[0x40];
5255 };
5256
5257 enum {
5258         MLX5_ACTION_TYPE_SET   = 0x1,
5259         MLX5_ACTION_TYPE_ADD   = 0x2,
5260 };
5261
5262 enum {
5263         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
5264         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
5265         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
5266         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
5267         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
5268         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
5269         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
5270         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
5271         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
5272         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
5273         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
5274         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
5275         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
5276         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
5277         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
5278         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
5279         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
5280         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
5281         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
5282         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
5283         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
5284         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
5285         MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
5286         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5287         MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
5288 };
5289
5290 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5291         u8         status[0x8];
5292         u8         reserved_at_8[0x18];
5293
5294         u8         syndrome[0x20];
5295
5296         u8         modify_header_id[0x20];
5297
5298         u8         reserved_at_60[0x20];
5299 };
5300
5301 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5302         u8         opcode[0x10];
5303         u8         reserved_at_10[0x10];
5304
5305         u8         reserved_at_20[0x10];
5306         u8         op_mod[0x10];
5307
5308         u8         reserved_at_40[0x20];
5309
5310         u8         table_type[0x8];
5311         u8         reserved_at_68[0x10];
5312         u8         num_of_actions[0x8];
5313
5314         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
5315 };
5316
5317 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5318         u8         status[0x8];
5319         u8         reserved_at_8[0x18];
5320
5321         u8         syndrome[0x20];
5322
5323         u8         reserved_at_40[0x40];
5324 };
5325
5326 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5327         u8         opcode[0x10];
5328         u8         reserved_at_10[0x10];
5329
5330         u8         reserved_at_20[0x10];
5331         u8         op_mod[0x10];
5332
5333         u8         modify_header_id[0x20];
5334
5335         u8         reserved_at_60[0x20];
5336 };
5337
5338 struct mlx5_ifc_query_dct_out_bits {
5339         u8         status[0x8];
5340         u8         reserved_at_8[0x18];
5341
5342         u8         syndrome[0x20];
5343
5344         u8         reserved_at_40[0x40];
5345
5346         struct mlx5_ifc_dctc_bits dct_context_entry;
5347
5348         u8         reserved_at_280[0x180];
5349 };
5350
5351 struct mlx5_ifc_query_dct_in_bits {
5352         u8         opcode[0x10];
5353         u8         reserved_at_10[0x10];
5354
5355         u8         reserved_at_20[0x10];
5356         u8         op_mod[0x10];
5357
5358         u8         reserved_at_40[0x8];
5359         u8         dctn[0x18];
5360
5361         u8         reserved_at_60[0x20];
5362 };
5363
5364 struct mlx5_ifc_query_cq_out_bits {
5365         u8         status[0x8];
5366         u8         reserved_at_8[0x18];
5367
5368         u8         syndrome[0x20];
5369
5370         u8         reserved_at_40[0x40];
5371
5372         struct mlx5_ifc_cqc_bits cq_context;
5373
5374         u8         reserved_at_280[0x600];
5375
5376         u8         pas[0][0x40];
5377 };
5378
5379 struct mlx5_ifc_query_cq_in_bits {
5380         u8         opcode[0x10];
5381         u8         reserved_at_10[0x10];
5382
5383         u8         reserved_at_20[0x10];
5384         u8         op_mod[0x10];
5385
5386         u8         reserved_at_40[0x8];
5387         u8         cqn[0x18];
5388
5389         u8         reserved_at_60[0x20];
5390 };
5391
5392 struct mlx5_ifc_query_cong_status_out_bits {
5393         u8         status[0x8];
5394         u8         reserved_at_8[0x18];
5395
5396         u8         syndrome[0x20];
5397
5398         u8         reserved_at_40[0x20];
5399
5400         u8         enable[0x1];
5401         u8         tag_enable[0x1];
5402         u8         reserved_at_62[0x1e];
5403 };
5404
5405 struct mlx5_ifc_query_cong_status_in_bits {
5406         u8         opcode[0x10];
5407         u8         reserved_at_10[0x10];
5408
5409         u8         reserved_at_20[0x10];
5410         u8         op_mod[0x10];
5411
5412         u8         reserved_at_40[0x18];
5413         u8         priority[0x4];
5414         u8         cong_protocol[0x4];
5415
5416         u8         reserved_at_60[0x20];
5417 };
5418
5419 struct mlx5_ifc_query_cong_statistics_out_bits {
5420         u8         status[0x8];
5421         u8         reserved_at_8[0x18];
5422
5423         u8         syndrome[0x20];
5424
5425         u8         reserved_at_40[0x40];
5426
5427         u8         rp_cur_flows[0x20];
5428
5429         u8         sum_flows[0x20];
5430
5431         u8         rp_cnp_ignored_high[0x20];
5432
5433         u8         rp_cnp_ignored_low[0x20];
5434
5435         u8         rp_cnp_handled_high[0x20];
5436
5437         u8         rp_cnp_handled_low[0x20];
5438
5439         u8         reserved_at_140[0x100];
5440
5441         u8         time_stamp_high[0x20];
5442
5443         u8         time_stamp_low[0x20];
5444
5445         u8         accumulators_period[0x20];
5446
5447         u8         np_ecn_marked_roce_packets_high[0x20];
5448
5449         u8         np_ecn_marked_roce_packets_low[0x20];
5450
5451         u8         np_cnp_sent_high[0x20];
5452
5453         u8         np_cnp_sent_low[0x20];
5454
5455         u8         reserved_at_320[0x560];
5456 };
5457
5458 struct mlx5_ifc_query_cong_statistics_in_bits {
5459         u8         opcode[0x10];
5460         u8         reserved_at_10[0x10];
5461
5462         u8         reserved_at_20[0x10];
5463         u8         op_mod[0x10];
5464
5465         u8         clear[0x1];
5466         u8         reserved_at_41[0x1f];
5467
5468         u8         reserved_at_60[0x20];
5469 };
5470
5471 struct mlx5_ifc_query_cong_params_out_bits {
5472         u8         status[0x8];
5473         u8         reserved_at_8[0x18];
5474
5475         u8         syndrome[0x20];
5476
5477         u8         reserved_at_40[0x40];
5478
5479         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5480 };
5481
5482 struct mlx5_ifc_query_cong_params_in_bits {
5483         u8         opcode[0x10];
5484         u8         reserved_at_10[0x10];
5485
5486         u8         reserved_at_20[0x10];
5487         u8         op_mod[0x10];
5488
5489         u8         reserved_at_40[0x1c];
5490         u8         cong_protocol[0x4];
5491
5492         u8         reserved_at_60[0x20];
5493 };
5494
5495 struct mlx5_ifc_query_adapter_out_bits {
5496         u8         status[0x8];
5497         u8         reserved_at_8[0x18];
5498
5499         u8         syndrome[0x20];
5500
5501         u8         reserved_at_40[0x40];
5502
5503         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5504 };
5505
5506 struct mlx5_ifc_query_adapter_in_bits {
5507         u8         opcode[0x10];
5508         u8         reserved_at_10[0x10];
5509
5510         u8         reserved_at_20[0x10];
5511         u8         op_mod[0x10];
5512
5513         u8         reserved_at_40[0x40];
5514 };
5515
5516 struct mlx5_ifc_qp_2rst_out_bits {
5517         u8         status[0x8];
5518         u8         reserved_at_8[0x18];
5519
5520         u8         syndrome[0x20];
5521
5522         u8         reserved_at_40[0x40];
5523 };
5524
5525 struct mlx5_ifc_qp_2rst_in_bits {
5526         u8         opcode[0x10];
5527         u8         uid[0x10];
5528
5529         u8         reserved_at_20[0x10];
5530         u8         op_mod[0x10];
5531
5532         u8         reserved_at_40[0x8];
5533         u8         qpn[0x18];
5534
5535         u8         reserved_at_60[0x20];
5536 };
5537
5538 struct mlx5_ifc_qp_2err_out_bits {
5539         u8         status[0x8];
5540         u8         reserved_at_8[0x18];
5541
5542         u8         syndrome[0x20];
5543
5544         u8         reserved_at_40[0x40];
5545 };
5546
5547 struct mlx5_ifc_qp_2err_in_bits {
5548         u8         opcode[0x10];
5549         u8         uid[0x10];
5550
5551         u8         reserved_at_20[0x10];
5552         u8         op_mod[0x10];
5553
5554         u8         reserved_at_40[0x8];
5555         u8         qpn[0x18];
5556
5557         u8         reserved_at_60[0x20];
5558 };
5559
5560 struct mlx5_ifc_page_fault_resume_out_bits {
5561         u8         status[0x8];
5562         u8         reserved_at_8[0x18];
5563
5564         u8         syndrome[0x20];
5565
5566         u8         reserved_at_40[0x40];
5567 };
5568
5569 struct mlx5_ifc_page_fault_resume_in_bits {
5570         u8         opcode[0x10];
5571         u8         reserved_at_10[0x10];
5572
5573         u8         reserved_at_20[0x10];
5574         u8         op_mod[0x10];
5575
5576         u8         error[0x1];
5577         u8         reserved_at_41[0x4];
5578         u8         page_fault_type[0x3];
5579         u8         wq_number[0x18];
5580
5581         u8         reserved_at_60[0x8];
5582         u8         token[0x18];
5583 };
5584
5585 struct mlx5_ifc_nop_out_bits {
5586         u8         status[0x8];
5587         u8         reserved_at_8[0x18];
5588
5589         u8         syndrome[0x20];
5590
5591         u8         reserved_at_40[0x40];
5592 };
5593
5594 struct mlx5_ifc_nop_in_bits {
5595         u8         opcode[0x10];
5596         u8         reserved_at_10[0x10];
5597
5598         u8         reserved_at_20[0x10];
5599         u8         op_mod[0x10];
5600
5601         u8         reserved_at_40[0x40];
5602 };
5603
5604 struct mlx5_ifc_modify_vport_state_out_bits {
5605         u8         status[0x8];
5606         u8         reserved_at_8[0x18];
5607
5608         u8         syndrome[0x20];
5609
5610         u8         reserved_at_40[0x40];
5611 };
5612
5613 struct mlx5_ifc_modify_vport_state_in_bits {
5614         u8         opcode[0x10];
5615         u8         reserved_at_10[0x10];
5616
5617         u8         reserved_at_20[0x10];
5618         u8         op_mod[0x10];
5619
5620         u8         other_vport[0x1];
5621         u8         reserved_at_41[0xf];
5622         u8         vport_number[0x10];
5623
5624         u8         reserved_at_60[0x18];
5625         u8         admin_state[0x4];
5626         u8         reserved_at_7c[0x4];
5627 };
5628
5629 struct mlx5_ifc_modify_tis_out_bits {
5630         u8         status[0x8];
5631         u8         reserved_at_8[0x18];
5632
5633         u8         syndrome[0x20];
5634
5635         u8         reserved_at_40[0x40];
5636 };
5637
5638 struct mlx5_ifc_modify_tis_bitmask_bits {
5639         u8         reserved_at_0[0x20];
5640
5641         u8         reserved_at_20[0x1d];
5642         u8         lag_tx_port_affinity[0x1];
5643         u8         strict_lag_tx_port_affinity[0x1];
5644         u8         prio[0x1];
5645 };
5646
5647 struct mlx5_ifc_modify_tis_in_bits {
5648         u8         opcode[0x10];
5649         u8         uid[0x10];
5650
5651         u8         reserved_at_20[0x10];
5652         u8         op_mod[0x10];
5653
5654         u8         reserved_at_40[0x8];
5655         u8         tisn[0x18];
5656
5657         u8         reserved_at_60[0x20];
5658
5659         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5660
5661         u8         reserved_at_c0[0x40];
5662
5663         struct mlx5_ifc_tisc_bits ctx;
5664 };
5665
5666 struct mlx5_ifc_modify_tir_bitmask_bits {
5667         u8         reserved_at_0[0x20];
5668
5669         u8         reserved_at_20[0x1b];
5670         u8         self_lb_en[0x1];
5671         u8         reserved_at_3c[0x1];
5672         u8         hash[0x1];
5673         u8         reserved_at_3e[0x1];
5674         u8         lro[0x1];
5675 };
5676
5677 struct mlx5_ifc_modify_tir_out_bits {
5678         u8         status[0x8];
5679         u8         reserved_at_8[0x18];
5680
5681         u8         syndrome[0x20];
5682
5683         u8         reserved_at_40[0x40];
5684 };
5685
5686 struct mlx5_ifc_modify_tir_in_bits {
5687         u8         opcode[0x10];
5688         u8         uid[0x10];
5689
5690         u8         reserved_at_20[0x10];
5691         u8         op_mod[0x10];
5692
5693         u8         reserved_at_40[0x8];
5694         u8         tirn[0x18];
5695
5696         u8         reserved_at_60[0x20];
5697
5698         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5699
5700         u8         reserved_at_c0[0x40];
5701
5702         struct mlx5_ifc_tirc_bits ctx;
5703 };
5704
5705 struct mlx5_ifc_modify_sq_out_bits {
5706         u8         status[0x8];
5707         u8         reserved_at_8[0x18];
5708
5709         u8         syndrome[0x20];
5710
5711         u8         reserved_at_40[0x40];
5712 };
5713
5714 struct mlx5_ifc_modify_sq_in_bits {
5715         u8         opcode[0x10];
5716         u8         uid[0x10];
5717
5718         u8         reserved_at_20[0x10];
5719         u8         op_mod[0x10];
5720
5721         u8         sq_state[0x4];
5722         u8         reserved_at_44[0x4];
5723         u8         sqn[0x18];
5724
5725         u8         reserved_at_60[0x20];
5726
5727         u8         modify_bitmask[0x40];
5728
5729         u8         reserved_at_c0[0x40];
5730
5731         struct mlx5_ifc_sqc_bits ctx;
5732 };
5733
5734 struct mlx5_ifc_modify_scheduling_element_out_bits {
5735         u8         status[0x8];
5736         u8         reserved_at_8[0x18];
5737
5738         u8         syndrome[0x20];
5739
5740         u8         reserved_at_40[0x1c0];
5741 };
5742
5743 enum {
5744         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5745         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5746 };
5747
5748 struct mlx5_ifc_modify_scheduling_element_in_bits {
5749         u8         opcode[0x10];
5750         u8         reserved_at_10[0x10];
5751
5752         u8         reserved_at_20[0x10];
5753         u8         op_mod[0x10];
5754
5755         u8         scheduling_hierarchy[0x8];
5756         u8         reserved_at_48[0x18];
5757
5758         u8         scheduling_element_id[0x20];
5759
5760         u8         reserved_at_80[0x20];
5761
5762         u8         modify_bitmask[0x20];
5763
5764         u8         reserved_at_c0[0x40];
5765
5766         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5767
5768         u8         reserved_at_300[0x100];
5769 };
5770
5771 struct mlx5_ifc_modify_rqt_out_bits {
5772         u8         status[0x8];
5773         u8         reserved_at_8[0x18];
5774
5775         u8         syndrome[0x20];
5776
5777         u8         reserved_at_40[0x40];
5778 };
5779
5780 struct mlx5_ifc_rqt_bitmask_bits {
5781         u8         reserved_at_0[0x20];
5782
5783         u8         reserved_at_20[0x1f];
5784         u8         rqn_list[0x1];
5785 };
5786
5787 struct mlx5_ifc_modify_rqt_in_bits {
5788         u8         opcode[0x10];
5789         u8         uid[0x10];
5790
5791         u8         reserved_at_20[0x10];
5792         u8         op_mod[0x10];
5793
5794         u8         reserved_at_40[0x8];
5795         u8         rqtn[0x18];
5796
5797         u8         reserved_at_60[0x20];
5798
5799         struct mlx5_ifc_rqt_bitmask_bits bitmask;
5800
5801         u8         reserved_at_c0[0x40];
5802
5803         struct mlx5_ifc_rqtc_bits ctx;
5804 };
5805
5806 struct mlx5_ifc_modify_rq_out_bits {
5807         u8         status[0x8];
5808         u8         reserved_at_8[0x18];
5809
5810         u8         syndrome[0x20];
5811
5812         u8         reserved_at_40[0x40];
5813 };
5814
5815 enum {
5816         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5817         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5818         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5819 };
5820
5821 struct mlx5_ifc_modify_rq_in_bits {
5822         u8         opcode[0x10];
5823         u8         uid[0x10];
5824
5825         u8         reserved_at_20[0x10];
5826         u8         op_mod[0x10];
5827
5828         u8         rq_state[0x4];
5829         u8         reserved_at_44[0x4];
5830         u8         rqn[0x18];
5831
5832         u8         reserved_at_60[0x20];
5833
5834         u8         modify_bitmask[0x40];
5835
5836         u8         reserved_at_c0[0x40];
5837
5838         struct mlx5_ifc_rqc_bits ctx;
5839 };
5840
5841 struct mlx5_ifc_modify_rmp_out_bits {
5842         u8         status[0x8];
5843         u8         reserved_at_8[0x18];
5844
5845         u8         syndrome[0x20];
5846
5847         u8         reserved_at_40[0x40];
5848 };
5849
5850 struct mlx5_ifc_rmp_bitmask_bits {
5851         u8         reserved_at_0[0x20];
5852
5853         u8         reserved_at_20[0x1f];
5854         u8         lwm[0x1];
5855 };
5856
5857 struct mlx5_ifc_modify_rmp_in_bits {
5858         u8         opcode[0x10];
5859         u8         uid[0x10];
5860
5861         u8         reserved_at_20[0x10];
5862         u8         op_mod[0x10];
5863
5864         u8         rmp_state[0x4];
5865         u8         reserved_at_44[0x4];
5866         u8         rmpn[0x18];
5867
5868         u8         reserved_at_60[0x20];
5869
5870         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5871
5872         u8         reserved_at_c0[0x40];
5873
5874         struct mlx5_ifc_rmpc_bits ctx;
5875 };
5876
5877 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5878         u8         status[0x8];
5879         u8         reserved_at_8[0x18];
5880
5881         u8         syndrome[0x20];
5882
5883         u8         reserved_at_40[0x40];
5884 };
5885
5886 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5887         u8         reserved_at_0[0x12];
5888         u8         affiliation[0x1];
5889         u8         reserved_at_13[0x1];
5890         u8         disable_uc_local_lb[0x1];
5891         u8         disable_mc_local_lb[0x1];
5892         u8         node_guid[0x1];
5893         u8         port_guid[0x1];
5894         u8         min_inline[0x1];
5895         u8         mtu[0x1];
5896         u8         change_event[0x1];
5897         u8         promisc[0x1];
5898         u8         permanent_address[0x1];
5899         u8         addresses_list[0x1];
5900         u8         roce_en[0x1];
5901         u8         reserved_at_1f[0x1];
5902 };
5903
5904 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5905         u8         opcode[0x10];
5906         u8         reserved_at_10[0x10];
5907
5908         u8         reserved_at_20[0x10];
5909         u8         op_mod[0x10];
5910
5911         u8         other_vport[0x1];
5912         u8         reserved_at_41[0xf];
5913         u8         vport_number[0x10];
5914
5915         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5916
5917         u8         reserved_at_80[0x780];
5918
5919         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5920 };
5921
5922 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5923         u8         status[0x8];
5924         u8         reserved_at_8[0x18];
5925
5926         u8         syndrome[0x20];
5927
5928         u8         reserved_at_40[0x40];
5929 };
5930
5931 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5932         u8         opcode[0x10];
5933         u8         reserved_at_10[0x10];
5934
5935         u8         reserved_at_20[0x10];
5936         u8         op_mod[0x10];
5937
5938         u8         other_vport[0x1];
5939         u8         reserved_at_41[0xb];
5940         u8         port_num[0x4];
5941         u8         vport_number[0x10];
5942
5943         u8         reserved_at_60[0x20];
5944
5945         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5946 };
5947
5948 struct mlx5_ifc_modify_cq_out_bits {
5949         u8         status[0x8];
5950         u8         reserved_at_8[0x18];
5951
5952         u8         syndrome[0x20];
5953
5954         u8         reserved_at_40[0x40];
5955 };
5956
5957 enum {
5958         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5959         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5960 };
5961
5962 struct mlx5_ifc_modify_cq_in_bits {
5963         u8         opcode[0x10];
5964         u8         uid[0x10];
5965
5966         u8         reserved_at_20[0x10];
5967         u8         op_mod[0x10];
5968
5969         u8         reserved_at_40[0x8];
5970         u8         cqn[0x18];
5971
5972         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5973
5974         struct mlx5_ifc_cqc_bits cq_context;
5975
5976         u8         reserved_at_280[0x40];
5977
5978         u8         cq_umem_valid[0x1];
5979         u8         reserved_at_2c1[0x5bf];
5980
5981         u8         pas[0][0x40];
5982 };
5983
5984 struct mlx5_ifc_modify_cong_status_out_bits {
5985         u8         status[0x8];
5986         u8         reserved_at_8[0x18];
5987
5988         u8         syndrome[0x20];
5989
5990         u8         reserved_at_40[0x40];
5991 };
5992
5993 struct mlx5_ifc_modify_cong_status_in_bits {
5994         u8         opcode[0x10];
5995         u8         reserved_at_10[0x10];
5996
5997         u8         reserved_at_20[0x10];
5998         u8         op_mod[0x10];
5999
6000         u8         reserved_at_40[0x18];
6001         u8         priority[0x4];
6002         u8         cong_protocol[0x4];
6003
6004         u8         enable[0x1];
6005         u8         tag_enable[0x1];
6006         u8         reserved_at_62[0x1e];
6007 };
6008
6009 struct mlx5_ifc_modify_cong_params_out_bits {
6010         u8         status[0x8];
6011         u8         reserved_at_8[0x18];
6012
6013         u8         syndrome[0x20];
6014
6015         u8         reserved_at_40[0x40];
6016 };
6017
6018 struct mlx5_ifc_modify_cong_params_in_bits {
6019         u8         opcode[0x10];
6020         u8         reserved_at_10[0x10];
6021
6022         u8         reserved_at_20[0x10];
6023         u8         op_mod[0x10];
6024
6025         u8         reserved_at_40[0x1c];
6026         u8         cong_protocol[0x4];
6027
6028         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6029
6030         u8         reserved_at_80[0x80];
6031
6032         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6033 };
6034
6035 struct mlx5_ifc_manage_pages_out_bits {
6036         u8         status[0x8];
6037         u8         reserved_at_8[0x18];
6038
6039         u8         syndrome[0x20];
6040
6041         u8         output_num_entries[0x20];
6042
6043         u8         reserved_at_60[0x20];
6044
6045         u8         pas[0][0x40];
6046 };
6047
6048 enum {
6049         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
6050         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
6051         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
6052 };
6053
6054 struct mlx5_ifc_manage_pages_in_bits {
6055         u8         opcode[0x10];
6056         u8         reserved_at_10[0x10];
6057
6058         u8         reserved_at_20[0x10];
6059         u8         op_mod[0x10];
6060
6061         u8         embedded_cpu_function[0x1];
6062         u8         reserved_at_41[0xf];
6063         u8         function_id[0x10];
6064
6065         u8         input_num_entries[0x20];
6066
6067         u8         pas[0][0x40];
6068 };
6069
6070 struct mlx5_ifc_mad_ifc_out_bits {
6071         u8         status[0x8];
6072         u8         reserved_at_8[0x18];
6073
6074         u8         syndrome[0x20];
6075
6076         u8         reserved_at_40[0x40];
6077
6078         u8         response_mad_packet[256][0x8];
6079 };
6080
6081 struct mlx5_ifc_mad_ifc_in_bits {
6082         u8         opcode[0x10];
6083         u8         reserved_at_10[0x10];
6084
6085         u8         reserved_at_20[0x10];
6086         u8         op_mod[0x10];
6087
6088         u8         remote_lid[0x10];
6089         u8         reserved_at_50[0x8];
6090         u8         port[0x8];
6091
6092         u8         reserved_at_60[0x20];
6093
6094         u8         mad[256][0x8];
6095 };
6096
6097 struct mlx5_ifc_init_hca_out_bits {
6098         u8         status[0x8];
6099         u8         reserved_at_8[0x18];
6100
6101         u8         syndrome[0x20];
6102
6103         u8         reserved_at_40[0x40];
6104 };
6105
6106 struct mlx5_ifc_init_hca_in_bits {
6107         u8         opcode[0x10];
6108         u8         reserved_at_10[0x10];
6109
6110         u8         reserved_at_20[0x10];
6111         u8         op_mod[0x10];
6112
6113         u8         reserved_at_40[0x40];
6114         u8         sw_owner_id[4][0x20];
6115 };
6116
6117 struct mlx5_ifc_init2rtr_qp_out_bits {
6118         u8         status[0x8];
6119         u8         reserved_at_8[0x18];
6120
6121         u8         syndrome[0x20];
6122
6123         u8         reserved_at_40[0x40];
6124 };
6125
6126 struct mlx5_ifc_init2rtr_qp_in_bits {
6127         u8         opcode[0x10];
6128         u8         uid[0x10];
6129
6130         u8         reserved_at_20[0x10];
6131         u8         op_mod[0x10];
6132
6133         u8         reserved_at_40[0x8];
6134         u8         qpn[0x18];
6135
6136         u8         reserved_at_60[0x20];
6137
6138         u8         opt_param_mask[0x20];
6139
6140         u8         reserved_at_a0[0x20];
6141
6142         struct mlx5_ifc_qpc_bits qpc;
6143
6144         u8         reserved_at_800[0x80];
6145 };
6146
6147 struct mlx5_ifc_init2init_qp_out_bits {
6148         u8         status[0x8];
6149         u8         reserved_at_8[0x18];
6150
6151         u8         syndrome[0x20];
6152
6153         u8         reserved_at_40[0x40];
6154 };
6155
6156 struct mlx5_ifc_init2init_qp_in_bits {
6157         u8         opcode[0x10];
6158         u8         uid[0x10];
6159
6160         u8         reserved_at_20[0x10];
6161         u8         op_mod[0x10];
6162
6163         u8         reserved_at_40[0x8];
6164         u8         qpn[0x18];
6165
6166         u8         reserved_at_60[0x20];
6167
6168         u8         opt_param_mask[0x20];
6169
6170         u8         reserved_at_a0[0x20];
6171
6172         struct mlx5_ifc_qpc_bits qpc;
6173
6174         u8         reserved_at_800[0x80];
6175 };
6176
6177 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6178         u8         status[0x8];
6179         u8         reserved_at_8[0x18];
6180
6181         u8         syndrome[0x20];
6182
6183         u8         reserved_at_40[0x40];
6184
6185         u8         packet_headers_log[128][0x8];
6186
6187         u8         packet_syndrome[64][0x8];
6188 };
6189
6190 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6191         u8         opcode[0x10];
6192         u8         reserved_at_10[0x10];
6193
6194         u8         reserved_at_20[0x10];
6195         u8         op_mod[0x10];
6196
6197         u8         reserved_at_40[0x40];
6198 };
6199
6200 struct mlx5_ifc_gen_eqe_in_bits {
6201         u8         opcode[0x10];
6202         u8         reserved_at_10[0x10];
6203
6204         u8         reserved_at_20[0x10];
6205         u8         op_mod[0x10];
6206
6207         u8         reserved_at_40[0x18];
6208         u8         eq_number[0x8];
6209
6210         u8         reserved_at_60[0x20];
6211
6212         u8         eqe[64][0x8];
6213 };
6214
6215 struct mlx5_ifc_gen_eq_out_bits {
6216         u8         status[0x8];
6217         u8         reserved_at_8[0x18];
6218
6219         u8         syndrome[0x20];
6220
6221         u8         reserved_at_40[0x40];
6222 };
6223
6224 struct mlx5_ifc_enable_hca_out_bits {
6225         u8         status[0x8];
6226         u8         reserved_at_8[0x18];
6227
6228         u8         syndrome[0x20];
6229
6230         u8         reserved_at_40[0x20];
6231 };
6232
6233 struct mlx5_ifc_enable_hca_in_bits {
6234         u8         opcode[0x10];
6235         u8         reserved_at_10[0x10];
6236
6237         u8         reserved_at_20[0x10];
6238         u8         op_mod[0x10];
6239
6240         u8         embedded_cpu_function[0x1];
6241         u8         reserved_at_41[0xf];
6242         u8         function_id[0x10];
6243
6244         u8         reserved_at_60[0x20];
6245 };
6246
6247 struct mlx5_ifc_drain_dct_out_bits {
6248         u8         status[0x8];
6249         u8         reserved_at_8[0x18];
6250
6251         u8         syndrome[0x20];
6252
6253         u8         reserved_at_40[0x40];
6254 };
6255
6256 struct mlx5_ifc_drain_dct_in_bits {
6257         u8         opcode[0x10];
6258         u8         uid[0x10];
6259
6260         u8         reserved_at_20[0x10];
6261         u8         op_mod[0x10];
6262
6263         u8         reserved_at_40[0x8];
6264         u8         dctn[0x18];
6265
6266         u8         reserved_at_60[0x20];
6267 };
6268
6269 struct mlx5_ifc_disable_hca_out_bits {
6270         u8         status[0x8];
6271         u8         reserved_at_8[0x18];
6272
6273         u8         syndrome[0x20];
6274
6275         u8         reserved_at_40[0x20];
6276 };
6277
6278 struct mlx5_ifc_disable_hca_in_bits {
6279         u8         opcode[0x10];
6280         u8         reserved_at_10[0x10];
6281
6282         u8         reserved_at_20[0x10];
6283         u8         op_mod[0x10];
6284
6285         u8         embedded_cpu_function[0x1];
6286         u8         reserved_at_41[0xf];
6287         u8         function_id[0x10];
6288
6289         u8         reserved_at_60[0x20];
6290 };
6291
6292 struct mlx5_ifc_detach_from_mcg_out_bits {
6293         u8         status[0x8];
6294         u8         reserved_at_8[0x18];
6295
6296         u8         syndrome[0x20];
6297
6298         u8         reserved_at_40[0x40];
6299 };
6300
6301 struct mlx5_ifc_detach_from_mcg_in_bits {
6302         u8         opcode[0x10];
6303         u8         uid[0x10];
6304
6305         u8         reserved_at_20[0x10];
6306         u8         op_mod[0x10];
6307
6308         u8         reserved_at_40[0x8];
6309         u8         qpn[0x18];
6310
6311         u8         reserved_at_60[0x20];
6312
6313         u8         multicast_gid[16][0x8];
6314 };
6315
6316 struct mlx5_ifc_destroy_xrq_out_bits {
6317         u8         status[0x8];
6318         u8         reserved_at_8[0x18];
6319
6320         u8         syndrome[0x20];
6321
6322         u8         reserved_at_40[0x40];
6323 };
6324
6325 struct mlx5_ifc_destroy_xrq_in_bits {
6326         u8         opcode[0x10];
6327         u8         uid[0x10];
6328
6329         u8         reserved_at_20[0x10];
6330         u8         op_mod[0x10];
6331
6332         u8         reserved_at_40[0x8];
6333         u8         xrqn[0x18];
6334
6335         u8         reserved_at_60[0x20];
6336 };
6337
6338 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6339         u8         status[0x8];
6340         u8         reserved_at_8[0x18];
6341
6342         u8         syndrome[0x20];
6343
6344         u8         reserved_at_40[0x40];
6345 };
6346
6347 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6348         u8         opcode[0x10];
6349         u8         uid[0x10];
6350
6351         u8         reserved_at_20[0x10];
6352         u8         op_mod[0x10];
6353
6354         u8         reserved_at_40[0x8];
6355         u8         xrc_srqn[0x18];
6356
6357         u8         reserved_at_60[0x20];
6358 };
6359
6360 struct mlx5_ifc_destroy_tis_out_bits {
6361         u8         status[0x8];
6362         u8         reserved_at_8[0x18];
6363
6364         u8         syndrome[0x20];
6365
6366         u8         reserved_at_40[0x40];
6367 };
6368
6369 struct mlx5_ifc_destroy_tis_in_bits {
6370         u8         opcode[0x10];
6371         u8         uid[0x10];
6372
6373         u8         reserved_at_20[0x10];
6374         u8         op_mod[0x10];
6375
6376         u8         reserved_at_40[0x8];
6377         u8         tisn[0x18];
6378
6379         u8         reserved_at_60[0x20];
6380 };
6381
6382 struct mlx5_ifc_destroy_tir_out_bits {
6383         u8         status[0x8];
6384         u8         reserved_at_8[0x18];
6385
6386         u8         syndrome[0x20];
6387
6388         u8         reserved_at_40[0x40];
6389 };
6390
6391 struct mlx5_ifc_destroy_tir_in_bits {
6392         u8         opcode[0x10];
6393         u8         uid[0x10];
6394
6395         u8         reserved_at_20[0x10];
6396         u8         op_mod[0x10];
6397
6398         u8         reserved_at_40[0x8];
6399         u8         tirn[0x18];
6400
6401         u8         reserved_at_60[0x20];
6402 };
6403
6404 struct mlx5_ifc_destroy_srq_out_bits {
6405         u8         status[0x8];
6406         u8         reserved_at_8[0x18];
6407
6408         u8         syndrome[0x20];
6409
6410         u8         reserved_at_40[0x40];
6411 };
6412
6413 struct mlx5_ifc_destroy_srq_in_bits {
6414         u8         opcode[0x10];
6415         u8         uid[0x10];
6416
6417         u8         reserved_at_20[0x10];
6418         u8         op_mod[0x10];
6419
6420         u8         reserved_at_40[0x8];
6421         u8         srqn[0x18];
6422
6423         u8         reserved_at_60[0x20];
6424 };
6425
6426 struct mlx5_ifc_destroy_sq_out_bits {
6427         u8         status[0x8];
6428         u8         reserved_at_8[0x18];
6429
6430         u8         syndrome[0x20];
6431
6432         u8         reserved_at_40[0x40];
6433 };
6434
6435 struct mlx5_ifc_destroy_sq_in_bits {
6436         u8         opcode[0x10];
6437         u8         uid[0x10];
6438
6439         u8         reserved_at_20[0x10];
6440         u8         op_mod[0x10];
6441
6442         u8         reserved_at_40[0x8];
6443         u8         sqn[0x18];
6444
6445         u8         reserved_at_60[0x20];
6446 };
6447
6448 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6449         u8         status[0x8];
6450         u8         reserved_at_8[0x18];
6451
6452         u8         syndrome[0x20];
6453
6454         u8         reserved_at_40[0x1c0];
6455 };
6456
6457 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6458         u8         opcode[0x10];
6459         u8         reserved_at_10[0x10];
6460
6461         u8         reserved_at_20[0x10];
6462         u8         op_mod[0x10];
6463
6464         u8         scheduling_hierarchy[0x8];
6465         u8         reserved_at_48[0x18];
6466
6467         u8         scheduling_element_id[0x20];
6468
6469         u8         reserved_at_80[0x180];
6470 };
6471
6472 struct mlx5_ifc_destroy_rqt_out_bits {
6473         u8         status[0x8];
6474         u8         reserved_at_8[0x18];
6475
6476         u8         syndrome[0x20];
6477
6478         u8         reserved_at_40[0x40];
6479 };
6480
6481 struct mlx5_ifc_destroy_rqt_in_bits {
6482         u8         opcode[0x10];
6483         u8         uid[0x10];
6484
6485         u8         reserved_at_20[0x10];
6486         u8         op_mod[0x10];
6487
6488         u8         reserved_at_40[0x8];
6489         u8         rqtn[0x18];
6490
6491         u8         reserved_at_60[0x20];
6492 };
6493
6494 struct mlx5_ifc_destroy_rq_out_bits {
6495         u8         status[0x8];
6496         u8         reserved_at_8[0x18];
6497
6498         u8         syndrome[0x20];
6499
6500         u8         reserved_at_40[0x40];
6501 };
6502
6503 struct mlx5_ifc_destroy_rq_in_bits {
6504         u8         opcode[0x10];
6505         u8         uid[0x10];
6506
6507         u8         reserved_at_20[0x10];
6508         u8         op_mod[0x10];
6509
6510         u8         reserved_at_40[0x8];
6511         u8         rqn[0x18];
6512
6513         u8         reserved_at_60[0x20];
6514 };
6515
6516 struct mlx5_ifc_set_delay_drop_params_in_bits {
6517         u8         opcode[0x10];
6518         u8         reserved_at_10[0x10];
6519
6520         u8         reserved_at_20[0x10];
6521         u8         op_mod[0x10];
6522
6523         u8         reserved_at_40[0x20];
6524
6525         u8         reserved_at_60[0x10];
6526         u8         delay_drop_timeout[0x10];
6527 };
6528
6529 struct mlx5_ifc_set_delay_drop_params_out_bits {
6530         u8         status[0x8];
6531         u8         reserved_at_8[0x18];
6532
6533         u8         syndrome[0x20];
6534
6535         u8         reserved_at_40[0x40];
6536 };
6537
6538 struct mlx5_ifc_destroy_rmp_out_bits {
6539         u8         status[0x8];
6540         u8         reserved_at_8[0x18];
6541
6542         u8         syndrome[0x20];
6543
6544         u8         reserved_at_40[0x40];
6545 };
6546
6547 struct mlx5_ifc_destroy_rmp_in_bits {
6548         u8         opcode[0x10];
6549         u8         uid[0x10];
6550
6551         u8         reserved_at_20[0x10];
6552         u8         op_mod[0x10];
6553
6554         u8         reserved_at_40[0x8];
6555         u8         rmpn[0x18];
6556
6557         u8         reserved_at_60[0x20];
6558 };
6559
6560 struct mlx5_ifc_destroy_qp_out_bits {
6561         u8         status[0x8];
6562         u8         reserved_at_8[0x18];
6563
6564         u8         syndrome[0x20];
6565
6566         u8         reserved_at_40[0x40];
6567 };
6568
6569 struct mlx5_ifc_destroy_qp_in_bits {
6570         u8         opcode[0x10];
6571         u8         uid[0x10];
6572
6573         u8         reserved_at_20[0x10];
6574         u8         op_mod[0x10];
6575
6576         u8         reserved_at_40[0x8];
6577         u8         qpn[0x18];
6578
6579         u8         reserved_at_60[0x20];
6580 };
6581
6582 struct mlx5_ifc_destroy_psv_out_bits {
6583         u8         status[0x8];
6584         u8         reserved_at_8[0x18];
6585
6586         u8         syndrome[0x20];
6587
6588         u8         reserved_at_40[0x40];
6589 };
6590
6591 struct mlx5_ifc_destroy_psv_in_bits {
6592         u8         opcode[0x10];
6593         u8         reserved_at_10[0x10];
6594
6595         u8         reserved_at_20[0x10];
6596         u8         op_mod[0x10];
6597
6598         u8         reserved_at_40[0x8];
6599         u8         psvn[0x18];
6600
6601         u8         reserved_at_60[0x20];
6602 };
6603
6604 struct mlx5_ifc_destroy_mkey_out_bits {
6605         u8         status[0x8];
6606         u8         reserved_at_8[0x18];
6607
6608         u8         syndrome[0x20];
6609
6610         u8         reserved_at_40[0x40];
6611 };
6612
6613 struct mlx5_ifc_destroy_mkey_in_bits {
6614         u8         opcode[0x10];
6615         u8         reserved_at_10[0x10];
6616
6617         u8         reserved_at_20[0x10];
6618         u8         op_mod[0x10];
6619
6620         u8         reserved_at_40[0x8];
6621         u8         mkey_index[0x18];
6622
6623         u8         reserved_at_60[0x20];
6624 };
6625
6626 struct mlx5_ifc_destroy_flow_table_out_bits {
6627         u8         status[0x8];
6628         u8         reserved_at_8[0x18];
6629
6630         u8         syndrome[0x20];
6631
6632         u8         reserved_at_40[0x40];
6633 };
6634
6635 struct mlx5_ifc_destroy_flow_table_in_bits {
6636         u8         opcode[0x10];
6637         u8         reserved_at_10[0x10];
6638
6639         u8         reserved_at_20[0x10];
6640         u8         op_mod[0x10];
6641
6642         u8         other_vport[0x1];
6643         u8         reserved_at_41[0xf];
6644         u8         vport_number[0x10];
6645
6646         u8         reserved_at_60[0x20];
6647
6648         u8         table_type[0x8];
6649         u8         reserved_at_88[0x18];
6650
6651         u8         reserved_at_a0[0x8];
6652         u8         table_id[0x18];
6653
6654         u8         reserved_at_c0[0x140];
6655 };
6656
6657 struct mlx5_ifc_destroy_flow_group_out_bits {
6658         u8         status[0x8];
6659         u8         reserved_at_8[0x18];
6660
6661         u8         syndrome[0x20];
6662
6663         u8         reserved_at_40[0x40];
6664 };
6665
6666 struct mlx5_ifc_destroy_flow_group_in_bits {
6667         u8         opcode[0x10];
6668         u8         reserved_at_10[0x10];
6669
6670         u8         reserved_at_20[0x10];
6671         u8         op_mod[0x10];
6672
6673         u8         other_vport[0x1];
6674         u8         reserved_at_41[0xf];
6675         u8         vport_number[0x10];
6676
6677         u8         reserved_at_60[0x20];
6678
6679         u8         table_type[0x8];
6680         u8         reserved_at_88[0x18];
6681
6682         u8         reserved_at_a0[0x8];
6683         u8         table_id[0x18];
6684
6685         u8         group_id[0x20];
6686
6687         u8         reserved_at_e0[0x120];
6688 };
6689
6690 struct mlx5_ifc_destroy_eq_out_bits {
6691         u8         status[0x8];
6692         u8         reserved_at_8[0x18];
6693
6694         u8         syndrome[0x20];
6695
6696         u8         reserved_at_40[0x40];
6697 };
6698
6699 struct mlx5_ifc_destroy_eq_in_bits {
6700         u8         opcode[0x10];
6701         u8         reserved_at_10[0x10];
6702
6703         u8         reserved_at_20[0x10];
6704         u8         op_mod[0x10];
6705
6706         u8         reserved_at_40[0x18];
6707         u8         eq_number[0x8];
6708
6709         u8         reserved_at_60[0x20];
6710 };
6711
6712 struct mlx5_ifc_destroy_dct_out_bits {
6713         u8         status[0x8];
6714         u8         reserved_at_8[0x18];
6715
6716         u8         syndrome[0x20];
6717
6718         u8         reserved_at_40[0x40];
6719 };
6720
6721 struct mlx5_ifc_destroy_dct_in_bits {
6722         u8         opcode[0x10];
6723         u8         uid[0x10];
6724
6725         u8         reserved_at_20[0x10];
6726         u8         op_mod[0x10];
6727
6728         u8         reserved_at_40[0x8];
6729         u8         dctn[0x18];
6730
6731         u8         reserved_at_60[0x20];
6732 };
6733
6734 struct mlx5_ifc_destroy_cq_out_bits {
6735         u8         status[0x8];
6736         u8         reserved_at_8[0x18];
6737
6738         u8         syndrome[0x20];
6739
6740         u8         reserved_at_40[0x40];
6741 };
6742
6743 struct mlx5_ifc_destroy_cq_in_bits {
6744         u8         opcode[0x10];
6745         u8         uid[0x10];
6746
6747         u8         reserved_at_20[0x10];
6748         u8         op_mod[0x10];
6749
6750         u8         reserved_at_40[0x8];
6751         u8         cqn[0x18];
6752
6753         u8         reserved_at_60[0x20];
6754 };
6755
6756 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6757         u8         status[0x8];
6758         u8         reserved_at_8[0x18];
6759
6760         u8         syndrome[0x20];
6761
6762         u8         reserved_at_40[0x40];
6763 };
6764
6765 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6766         u8         opcode[0x10];
6767         u8         reserved_at_10[0x10];
6768
6769         u8         reserved_at_20[0x10];
6770         u8         op_mod[0x10];
6771
6772         u8         reserved_at_40[0x20];
6773
6774         u8         reserved_at_60[0x10];
6775         u8         vxlan_udp_port[0x10];
6776 };
6777
6778 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6779         u8         status[0x8];
6780         u8         reserved_at_8[0x18];
6781
6782         u8         syndrome[0x20];
6783
6784         u8         reserved_at_40[0x40];
6785 };
6786
6787 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6788         u8         opcode[0x10];
6789         u8         reserved_at_10[0x10];
6790
6791         u8         reserved_at_20[0x10];
6792         u8         op_mod[0x10];
6793
6794         u8         reserved_at_40[0x60];
6795
6796         u8         reserved_at_a0[0x8];
6797         u8         table_index[0x18];
6798
6799         u8         reserved_at_c0[0x140];
6800 };
6801
6802 struct mlx5_ifc_delete_fte_out_bits {
6803         u8         status[0x8];
6804         u8         reserved_at_8[0x18];
6805
6806         u8         syndrome[0x20];
6807
6808         u8         reserved_at_40[0x40];
6809 };
6810
6811 struct mlx5_ifc_delete_fte_in_bits {
6812         u8         opcode[0x10];
6813         u8         reserved_at_10[0x10];
6814
6815         u8         reserved_at_20[0x10];
6816         u8         op_mod[0x10];
6817
6818         u8         other_vport[0x1];
6819         u8         reserved_at_41[0xf];
6820         u8         vport_number[0x10];
6821
6822         u8         reserved_at_60[0x20];
6823
6824         u8         table_type[0x8];
6825         u8         reserved_at_88[0x18];
6826
6827         u8         reserved_at_a0[0x8];
6828         u8         table_id[0x18];
6829
6830         u8         reserved_at_c0[0x40];
6831
6832         u8         flow_index[0x20];
6833
6834         u8         reserved_at_120[0xe0];
6835 };
6836
6837 struct mlx5_ifc_dealloc_xrcd_out_bits {
6838         u8         status[0x8];
6839         u8         reserved_at_8[0x18];
6840
6841         u8         syndrome[0x20];
6842
6843         u8         reserved_at_40[0x40];
6844 };
6845
6846 struct mlx5_ifc_dealloc_xrcd_in_bits {
6847         u8         opcode[0x10];
6848         u8         uid[0x10];
6849
6850         u8         reserved_at_20[0x10];
6851         u8         op_mod[0x10];
6852
6853         u8         reserved_at_40[0x8];
6854         u8         xrcd[0x18];
6855
6856         u8         reserved_at_60[0x20];
6857 };
6858
6859 struct mlx5_ifc_dealloc_uar_out_bits {
6860         u8         status[0x8];
6861         u8         reserved_at_8[0x18];
6862
6863         u8         syndrome[0x20];
6864
6865         u8         reserved_at_40[0x40];
6866 };
6867
6868 struct mlx5_ifc_dealloc_uar_in_bits {
6869         u8         opcode[0x10];
6870         u8         reserved_at_10[0x10];
6871
6872         u8         reserved_at_20[0x10];
6873         u8         op_mod[0x10];
6874
6875         u8         reserved_at_40[0x8];
6876         u8         uar[0x18];
6877
6878         u8         reserved_at_60[0x20];
6879 };
6880
6881 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6882         u8         status[0x8];
6883         u8         reserved_at_8[0x18];
6884
6885         u8         syndrome[0x20];
6886
6887         u8         reserved_at_40[0x40];
6888 };
6889
6890 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6891         u8         opcode[0x10];
6892         u8         uid[0x10];
6893
6894         u8         reserved_at_20[0x10];
6895         u8         op_mod[0x10];
6896
6897         u8         reserved_at_40[0x8];
6898         u8         transport_domain[0x18];
6899
6900         u8         reserved_at_60[0x20];
6901 };
6902
6903 struct mlx5_ifc_dealloc_q_counter_out_bits {
6904         u8         status[0x8];
6905         u8         reserved_at_8[0x18];
6906
6907         u8         syndrome[0x20];
6908
6909         u8         reserved_at_40[0x40];
6910 };
6911
6912 struct mlx5_ifc_dealloc_q_counter_in_bits {
6913         u8         opcode[0x10];
6914         u8         reserved_at_10[0x10];
6915
6916         u8         reserved_at_20[0x10];
6917         u8         op_mod[0x10];
6918
6919         u8         reserved_at_40[0x18];
6920         u8         counter_set_id[0x8];
6921
6922         u8         reserved_at_60[0x20];
6923 };
6924
6925 struct mlx5_ifc_dealloc_pd_out_bits {
6926         u8         status[0x8];
6927         u8         reserved_at_8[0x18];
6928
6929         u8         syndrome[0x20];
6930
6931         u8         reserved_at_40[0x40];
6932 };
6933
6934 struct mlx5_ifc_dealloc_pd_in_bits {
6935         u8         opcode[0x10];
6936         u8         uid[0x10];
6937
6938         u8         reserved_at_20[0x10];
6939         u8         op_mod[0x10];
6940
6941         u8         reserved_at_40[0x8];
6942         u8         pd[0x18];
6943
6944         u8         reserved_at_60[0x20];
6945 };
6946
6947 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6948         u8         status[0x8];
6949         u8         reserved_at_8[0x18];
6950
6951         u8         syndrome[0x20];
6952
6953         u8         reserved_at_40[0x40];
6954 };
6955
6956 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6957         u8         opcode[0x10];
6958         u8         reserved_at_10[0x10];
6959
6960         u8         reserved_at_20[0x10];
6961         u8         op_mod[0x10];
6962
6963         u8         flow_counter_id[0x20];
6964
6965         u8         reserved_at_60[0x20];
6966 };
6967
6968 struct mlx5_ifc_create_xrq_out_bits {
6969         u8         status[0x8];
6970         u8         reserved_at_8[0x18];
6971
6972         u8         syndrome[0x20];
6973
6974         u8         reserved_at_40[0x8];
6975         u8         xrqn[0x18];
6976
6977         u8         reserved_at_60[0x20];
6978 };
6979
6980 struct mlx5_ifc_create_xrq_in_bits {
6981         u8         opcode[0x10];
6982         u8         uid[0x10];
6983
6984         u8         reserved_at_20[0x10];
6985         u8         op_mod[0x10];
6986
6987         u8         reserved_at_40[0x40];
6988
6989         struct mlx5_ifc_xrqc_bits xrq_context;
6990 };
6991
6992 struct mlx5_ifc_create_xrc_srq_out_bits {
6993         u8         status[0x8];
6994         u8         reserved_at_8[0x18];
6995
6996         u8         syndrome[0x20];
6997
6998         u8         reserved_at_40[0x8];
6999         u8         xrc_srqn[0x18];
7000
7001         u8         reserved_at_60[0x20];
7002 };
7003
7004 struct mlx5_ifc_create_xrc_srq_in_bits {
7005         u8         opcode[0x10];
7006         u8         uid[0x10];
7007
7008         u8         reserved_at_20[0x10];
7009         u8         op_mod[0x10];
7010
7011         u8         reserved_at_40[0x40];
7012
7013         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7014
7015         u8         reserved_at_280[0x60];
7016
7017         u8         xrc_srq_umem_valid[0x1];
7018         u8         reserved_at_2e1[0x1f];
7019
7020         u8         reserved_at_300[0x580];
7021
7022         u8         pas[0][0x40];
7023 };
7024
7025 struct mlx5_ifc_create_tis_out_bits {
7026         u8         status[0x8];
7027         u8         reserved_at_8[0x18];
7028
7029         u8         syndrome[0x20];
7030
7031         u8         reserved_at_40[0x8];
7032         u8         tisn[0x18];
7033
7034         u8         reserved_at_60[0x20];
7035 };
7036
7037 struct mlx5_ifc_create_tis_in_bits {
7038         u8         opcode[0x10];
7039         u8         uid[0x10];
7040
7041         u8         reserved_at_20[0x10];
7042         u8         op_mod[0x10];
7043
7044         u8         reserved_at_40[0xc0];
7045
7046         struct mlx5_ifc_tisc_bits ctx;
7047 };
7048
7049 struct mlx5_ifc_create_tir_out_bits {
7050         u8         status[0x8];
7051         u8         icm_address_63_40[0x18];
7052
7053         u8         syndrome[0x20];
7054
7055         u8         icm_address_39_32[0x8];
7056         u8         tirn[0x18];
7057
7058         u8         icm_address_31_0[0x20];
7059 };
7060
7061 struct mlx5_ifc_create_tir_in_bits {
7062         u8         opcode[0x10];
7063         u8         uid[0x10];
7064
7065         u8         reserved_at_20[0x10];
7066         u8         op_mod[0x10];
7067
7068         u8         reserved_at_40[0xc0];
7069
7070         struct mlx5_ifc_tirc_bits ctx;
7071 };
7072
7073 struct mlx5_ifc_create_srq_out_bits {
7074         u8         status[0x8];
7075         u8         reserved_at_8[0x18];
7076
7077         u8         syndrome[0x20];
7078
7079         u8         reserved_at_40[0x8];
7080         u8         srqn[0x18];
7081
7082         u8         reserved_at_60[0x20];
7083 };
7084
7085 struct mlx5_ifc_create_srq_in_bits {
7086         u8         opcode[0x10];
7087         u8         uid[0x10];
7088
7089         u8         reserved_at_20[0x10];
7090         u8         op_mod[0x10];
7091
7092         u8         reserved_at_40[0x40];
7093
7094         struct mlx5_ifc_srqc_bits srq_context_entry;
7095
7096         u8         reserved_at_280[0x600];
7097
7098         u8         pas[0][0x40];
7099 };
7100
7101 struct mlx5_ifc_create_sq_out_bits {
7102         u8         status[0x8];
7103         u8         reserved_at_8[0x18];
7104
7105         u8         syndrome[0x20];
7106
7107         u8         reserved_at_40[0x8];
7108         u8         sqn[0x18];
7109
7110         u8         reserved_at_60[0x20];
7111 };
7112
7113 struct mlx5_ifc_create_sq_in_bits {
7114         u8         opcode[0x10];
7115         u8         uid[0x10];
7116
7117         u8         reserved_at_20[0x10];
7118         u8         op_mod[0x10];
7119
7120         u8         reserved_at_40[0xc0];
7121
7122         struct mlx5_ifc_sqc_bits ctx;
7123 };
7124
7125 struct mlx5_ifc_create_scheduling_element_out_bits {
7126         u8         status[0x8];
7127         u8         reserved_at_8[0x18];
7128
7129         u8         syndrome[0x20];
7130
7131         u8         reserved_at_40[0x40];
7132
7133         u8         scheduling_element_id[0x20];
7134
7135         u8         reserved_at_a0[0x160];
7136 };
7137
7138 struct mlx5_ifc_create_scheduling_element_in_bits {
7139         u8         opcode[0x10];
7140         u8         reserved_at_10[0x10];
7141
7142         u8         reserved_at_20[0x10];
7143         u8         op_mod[0x10];
7144
7145         u8         scheduling_hierarchy[0x8];
7146         u8         reserved_at_48[0x18];
7147
7148         u8         reserved_at_60[0xa0];
7149
7150         struct mlx5_ifc_scheduling_context_bits scheduling_context;
7151
7152         u8         reserved_at_300[0x100];
7153 };
7154
7155 struct mlx5_ifc_create_rqt_out_bits {
7156         u8         status[0x8];
7157         u8         reserved_at_8[0x18];
7158
7159         u8         syndrome[0x20];
7160
7161         u8         reserved_at_40[0x8];
7162         u8         rqtn[0x18];
7163
7164         u8         reserved_at_60[0x20];
7165 };
7166
7167 struct mlx5_ifc_create_rqt_in_bits {
7168         u8         opcode[0x10];
7169         u8         uid[0x10];
7170
7171         u8         reserved_at_20[0x10];
7172         u8         op_mod[0x10];
7173
7174         u8         reserved_at_40[0xc0];
7175
7176         struct mlx5_ifc_rqtc_bits rqt_context;
7177 };
7178
7179 struct mlx5_ifc_create_rq_out_bits {
7180         u8         status[0x8];
7181         u8         reserved_at_8[0x18];
7182
7183         u8         syndrome[0x20];
7184
7185         u8         reserved_at_40[0x8];
7186         u8         rqn[0x18];
7187
7188         u8         reserved_at_60[0x20];
7189 };
7190
7191 struct mlx5_ifc_create_rq_in_bits {
7192         u8         opcode[0x10];
7193         u8         uid[0x10];
7194
7195         u8         reserved_at_20[0x10];
7196         u8         op_mod[0x10];
7197
7198         u8         reserved_at_40[0xc0];
7199
7200         struct mlx5_ifc_rqc_bits ctx;
7201 };
7202
7203 struct mlx5_ifc_create_rmp_out_bits {
7204         u8         status[0x8];
7205         u8         reserved_at_8[0x18];
7206
7207         u8         syndrome[0x20];
7208
7209         u8         reserved_at_40[0x8];
7210         u8         rmpn[0x18];
7211
7212         u8         reserved_at_60[0x20];
7213 };
7214
7215 struct mlx5_ifc_create_rmp_in_bits {
7216         u8         opcode[0x10];
7217         u8         uid[0x10];
7218
7219         u8         reserved_at_20[0x10];
7220         u8         op_mod[0x10];
7221
7222         u8         reserved_at_40[0xc0];
7223
7224         struct mlx5_ifc_rmpc_bits ctx;
7225 };
7226
7227 struct mlx5_ifc_create_qp_out_bits {
7228         u8         status[0x8];
7229         u8         reserved_at_8[0x18];
7230
7231         u8         syndrome[0x20];
7232
7233         u8         reserved_at_40[0x8];
7234         u8         qpn[0x18];
7235
7236         u8         reserved_at_60[0x20];
7237 };
7238
7239 struct mlx5_ifc_create_qp_in_bits {
7240         u8         opcode[0x10];
7241         u8         uid[0x10];
7242
7243         u8         reserved_at_20[0x10];
7244         u8         op_mod[0x10];
7245
7246         u8         reserved_at_40[0x40];
7247
7248         u8         opt_param_mask[0x20];
7249
7250         u8         reserved_at_a0[0x20];
7251
7252         struct mlx5_ifc_qpc_bits qpc;
7253
7254         u8         reserved_at_800[0x60];
7255
7256         u8         wq_umem_valid[0x1];
7257         u8         reserved_at_861[0x1f];
7258
7259         u8         pas[0][0x40];
7260 };
7261
7262 struct mlx5_ifc_create_psv_out_bits {
7263         u8         status[0x8];
7264         u8         reserved_at_8[0x18];
7265
7266         u8         syndrome[0x20];
7267
7268         u8         reserved_at_40[0x40];
7269
7270         u8         reserved_at_80[0x8];
7271         u8         psv0_index[0x18];
7272
7273         u8         reserved_at_a0[0x8];
7274         u8         psv1_index[0x18];
7275
7276         u8         reserved_at_c0[0x8];
7277         u8         psv2_index[0x18];
7278
7279         u8         reserved_at_e0[0x8];
7280         u8         psv3_index[0x18];
7281 };
7282
7283 struct mlx5_ifc_create_psv_in_bits {
7284         u8         opcode[0x10];
7285         u8         reserved_at_10[0x10];
7286
7287         u8         reserved_at_20[0x10];
7288         u8         op_mod[0x10];
7289
7290         u8         num_psv[0x4];
7291         u8         reserved_at_44[0x4];
7292         u8         pd[0x18];
7293
7294         u8         reserved_at_60[0x20];
7295 };
7296
7297 struct mlx5_ifc_create_mkey_out_bits {
7298         u8         status[0x8];
7299         u8         reserved_at_8[0x18];
7300
7301         u8         syndrome[0x20];
7302
7303         u8         reserved_at_40[0x8];
7304         u8         mkey_index[0x18];
7305
7306         u8         reserved_at_60[0x20];
7307 };
7308
7309 struct mlx5_ifc_create_mkey_in_bits {
7310         u8         opcode[0x10];
7311         u8         reserved_at_10[0x10];
7312
7313         u8         reserved_at_20[0x10];
7314         u8         op_mod[0x10];
7315
7316         u8         reserved_at_40[0x20];
7317
7318         u8         pg_access[0x1];
7319         u8         mkey_umem_valid[0x1];
7320         u8         reserved_at_62[0x1e];
7321
7322         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7323
7324         u8         reserved_at_280[0x80];
7325
7326         u8         translations_octword_actual_size[0x20];
7327
7328         u8         reserved_at_320[0x560];
7329
7330         u8         klm_pas_mtt[0][0x20];
7331 };
7332
7333 struct mlx5_ifc_create_flow_table_out_bits {
7334         u8         status[0x8];
7335         u8         reserved_at_8[0x18];
7336
7337         u8         syndrome[0x20];
7338
7339         u8         reserved_at_40[0x8];
7340         u8         table_id[0x18];
7341
7342         u8         reserved_at_60[0x20];
7343 };
7344
7345 struct mlx5_ifc_flow_table_context_bits {
7346         u8         reformat_en[0x1];
7347         u8         decap_en[0x1];
7348         u8         reserved_at_2[0x1];
7349         u8         termination_table[0x1];
7350         u8         table_miss_action[0x4];
7351         u8         level[0x8];
7352         u8         reserved_at_10[0x8];
7353         u8         log_size[0x8];
7354
7355         u8         reserved_at_20[0x8];
7356         u8         table_miss_id[0x18];
7357
7358         u8         reserved_at_40[0x8];
7359         u8         lag_master_next_table_id[0x18];
7360
7361         u8         reserved_at_60[0xe0];
7362 };
7363
7364 struct mlx5_ifc_create_flow_table_in_bits {
7365         u8         opcode[0x10];
7366         u8         reserved_at_10[0x10];
7367
7368         u8         reserved_at_20[0x10];
7369         u8         op_mod[0x10];
7370
7371         u8         other_vport[0x1];
7372         u8         reserved_at_41[0xf];
7373         u8         vport_number[0x10];
7374
7375         u8         reserved_at_60[0x20];
7376
7377         u8         table_type[0x8];
7378         u8         reserved_at_88[0x18];
7379
7380         u8         reserved_at_a0[0x20];
7381
7382         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7383 };
7384
7385 struct mlx5_ifc_create_flow_group_out_bits {
7386         u8         status[0x8];
7387         u8         reserved_at_8[0x18];
7388
7389         u8         syndrome[0x20];
7390
7391         u8         reserved_at_40[0x8];
7392         u8         group_id[0x18];
7393
7394         u8         reserved_at_60[0x20];
7395 };
7396
7397 enum {
7398         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
7399         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
7400         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
7401         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7402 };
7403
7404 struct mlx5_ifc_create_flow_group_in_bits {
7405         u8         opcode[0x10];
7406         u8         reserved_at_10[0x10];
7407
7408         u8         reserved_at_20[0x10];
7409         u8         op_mod[0x10];
7410
7411         u8         other_vport[0x1];
7412         u8         reserved_at_41[0xf];
7413         u8         vport_number[0x10];
7414
7415         u8         reserved_at_60[0x20];
7416
7417         u8         table_type[0x8];
7418         u8         reserved_at_88[0x18];
7419
7420         u8         reserved_at_a0[0x8];
7421         u8         table_id[0x18];
7422
7423         u8         source_eswitch_owner_vhca_id_valid[0x1];
7424
7425         u8         reserved_at_c1[0x1f];
7426
7427         u8         start_flow_index[0x20];
7428
7429         u8         reserved_at_100[0x20];
7430
7431         u8         end_flow_index[0x20];
7432
7433         u8         reserved_at_140[0xa0];
7434
7435         u8         reserved_at_1e0[0x18];
7436         u8         match_criteria_enable[0x8];
7437
7438         struct mlx5_ifc_fte_match_param_bits match_criteria;
7439
7440         u8         reserved_at_1200[0xe00];
7441 };
7442
7443 struct mlx5_ifc_create_eq_out_bits {
7444         u8         status[0x8];
7445         u8         reserved_at_8[0x18];
7446
7447         u8         syndrome[0x20];
7448
7449         u8         reserved_at_40[0x18];
7450         u8         eq_number[0x8];
7451
7452         u8         reserved_at_60[0x20];
7453 };
7454
7455 struct mlx5_ifc_create_eq_in_bits {
7456         u8         opcode[0x10];
7457         u8         uid[0x10];
7458
7459         u8         reserved_at_20[0x10];
7460         u8         op_mod[0x10];
7461
7462         u8         reserved_at_40[0x40];
7463
7464         struct mlx5_ifc_eqc_bits eq_context_entry;
7465
7466         u8         reserved_at_280[0x40];
7467
7468         u8         event_bitmask[4][0x40];
7469
7470         u8         reserved_at_3c0[0x4c0];
7471
7472         u8         pas[0][0x40];
7473 };
7474
7475 struct mlx5_ifc_create_dct_out_bits {
7476         u8         status[0x8];
7477         u8         reserved_at_8[0x18];
7478
7479         u8         syndrome[0x20];
7480
7481         u8         reserved_at_40[0x8];
7482         u8         dctn[0x18];
7483
7484         u8         reserved_at_60[0x20];
7485 };
7486
7487 struct mlx5_ifc_create_dct_in_bits {
7488         u8         opcode[0x10];
7489         u8         uid[0x10];
7490
7491         u8         reserved_at_20[0x10];
7492         u8         op_mod[0x10];
7493
7494         u8         reserved_at_40[0x40];
7495
7496         struct mlx5_ifc_dctc_bits dct_context_entry;
7497
7498         u8         reserved_at_280[0x180];
7499 };
7500
7501 struct mlx5_ifc_create_cq_out_bits {
7502         u8         status[0x8];
7503         u8         reserved_at_8[0x18];
7504
7505         u8         syndrome[0x20];
7506
7507         u8         reserved_at_40[0x8];
7508         u8         cqn[0x18];
7509
7510         u8         reserved_at_60[0x20];
7511 };
7512
7513 struct mlx5_ifc_create_cq_in_bits {
7514         u8         opcode[0x10];
7515         u8         uid[0x10];
7516
7517         u8         reserved_at_20[0x10];
7518         u8         op_mod[0x10];
7519
7520         u8         reserved_at_40[0x40];
7521
7522         struct mlx5_ifc_cqc_bits cq_context;
7523
7524         u8         reserved_at_280[0x60];
7525
7526         u8         cq_umem_valid[0x1];
7527         u8         reserved_at_2e1[0x59f];
7528
7529         u8         pas[0][0x40];
7530 };
7531
7532 struct mlx5_ifc_config_int_moderation_out_bits {
7533         u8         status[0x8];
7534         u8         reserved_at_8[0x18];
7535
7536         u8         syndrome[0x20];
7537
7538         u8         reserved_at_40[0x4];
7539         u8         min_delay[0xc];
7540         u8         int_vector[0x10];
7541
7542         u8         reserved_at_60[0x20];
7543 };
7544
7545 enum {
7546         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7547         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7548 };
7549
7550 struct mlx5_ifc_config_int_moderation_in_bits {
7551         u8         opcode[0x10];
7552         u8         reserved_at_10[0x10];
7553
7554         u8         reserved_at_20[0x10];
7555         u8         op_mod[0x10];
7556
7557         u8         reserved_at_40[0x4];
7558         u8         min_delay[0xc];
7559         u8         int_vector[0x10];
7560
7561         u8         reserved_at_60[0x20];
7562 };
7563
7564 struct mlx5_ifc_attach_to_mcg_out_bits {
7565         u8         status[0x8];
7566         u8         reserved_at_8[0x18];
7567
7568         u8         syndrome[0x20];
7569
7570         u8         reserved_at_40[0x40];
7571 };
7572
7573 struct mlx5_ifc_attach_to_mcg_in_bits {
7574         u8         opcode[0x10];
7575         u8         uid[0x10];
7576
7577         u8         reserved_at_20[0x10];
7578         u8         op_mod[0x10];
7579
7580         u8         reserved_at_40[0x8];
7581         u8         qpn[0x18];
7582
7583         u8         reserved_at_60[0x20];
7584
7585         u8         multicast_gid[16][0x8];
7586 };
7587
7588 struct mlx5_ifc_arm_xrq_out_bits {
7589         u8         status[0x8];
7590         u8         reserved_at_8[0x18];
7591
7592         u8         syndrome[0x20];
7593
7594         u8         reserved_at_40[0x40];
7595 };
7596
7597 struct mlx5_ifc_arm_xrq_in_bits {
7598         u8         opcode[0x10];
7599         u8         reserved_at_10[0x10];
7600
7601         u8         reserved_at_20[0x10];
7602         u8         op_mod[0x10];
7603
7604         u8         reserved_at_40[0x8];
7605         u8         xrqn[0x18];
7606
7607         u8         reserved_at_60[0x10];
7608         u8         lwm[0x10];
7609 };
7610
7611 struct mlx5_ifc_arm_xrc_srq_out_bits {
7612         u8         status[0x8];
7613         u8         reserved_at_8[0x18];
7614
7615         u8         syndrome[0x20];
7616
7617         u8         reserved_at_40[0x40];
7618 };
7619
7620 enum {
7621         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7622 };
7623
7624 struct mlx5_ifc_arm_xrc_srq_in_bits {
7625         u8         opcode[0x10];
7626         u8         uid[0x10];
7627
7628         u8         reserved_at_20[0x10];
7629         u8         op_mod[0x10];
7630
7631         u8         reserved_at_40[0x8];
7632         u8         xrc_srqn[0x18];
7633
7634         u8         reserved_at_60[0x10];
7635         u8         lwm[0x10];
7636 };
7637
7638 struct mlx5_ifc_arm_rq_out_bits {
7639         u8         status[0x8];
7640         u8         reserved_at_8[0x18];
7641
7642         u8         syndrome[0x20];
7643
7644         u8         reserved_at_40[0x40];
7645 };
7646
7647 enum {
7648         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7649         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7650 };
7651
7652 struct mlx5_ifc_arm_rq_in_bits {
7653         u8         opcode[0x10];
7654         u8         uid[0x10];
7655
7656         u8         reserved_at_20[0x10];
7657         u8         op_mod[0x10];
7658
7659         u8         reserved_at_40[0x8];
7660         u8         srq_number[0x18];
7661
7662         u8         reserved_at_60[0x10];
7663         u8         lwm[0x10];
7664 };
7665
7666 struct mlx5_ifc_arm_dct_out_bits {
7667         u8         status[0x8];
7668         u8         reserved_at_8[0x18];
7669
7670         u8         syndrome[0x20];
7671
7672         u8         reserved_at_40[0x40];
7673 };
7674
7675 struct mlx5_ifc_arm_dct_in_bits {
7676         u8         opcode[0x10];
7677         u8         reserved_at_10[0x10];
7678
7679         u8         reserved_at_20[0x10];
7680         u8         op_mod[0x10];
7681
7682         u8         reserved_at_40[0x8];
7683         u8         dct_number[0x18];
7684
7685         u8         reserved_at_60[0x20];
7686 };
7687
7688 struct mlx5_ifc_alloc_xrcd_out_bits {
7689         u8         status[0x8];
7690         u8         reserved_at_8[0x18];
7691
7692         u8         syndrome[0x20];
7693
7694         u8         reserved_at_40[0x8];
7695         u8         xrcd[0x18];
7696
7697         u8         reserved_at_60[0x20];
7698 };
7699
7700 struct mlx5_ifc_alloc_xrcd_in_bits {
7701         u8         opcode[0x10];
7702         u8         uid[0x10];
7703
7704         u8         reserved_at_20[0x10];
7705         u8         op_mod[0x10];
7706
7707         u8         reserved_at_40[0x40];
7708 };
7709
7710 struct mlx5_ifc_alloc_uar_out_bits {
7711         u8         status[0x8];
7712         u8         reserved_at_8[0x18];
7713
7714         u8         syndrome[0x20];
7715
7716         u8         reserved_at_40[0x8];
7717         u8         uar[0x18];
7718
7719         u8         reserved_at_60[0x20];
7720 };
7721
7722 struct mlx5_ifc_alloc_uar_in_bits {
7723         u8         opcode[0x10];
7724         u8         reserved_at_10[0x10];
7725
7726         u8         reserved_at_20[0x10];
7727         u8         op_mod[0x10];
7728
7729         u8         reserved_at_40[0x40];
7730 };
7731
7732 struct mlx5_ifc_alloc_transport_domain_out_bits {
7733         u8         status[0x8];
7734         u8         reserved_at_8[0x18];
7735
7736         u8         syndrome[0x20];
7737
7738         u8         reserved_at_40[0x8];
7739         u8         transport_domain[0x18];
7740
7741         u8         reserved_at_60[0x20];
7742 };
7743
7744 struct mlx5_ifc_alloc_transport_domain_in_bits {
7745         u8         opcode[0x10];
7746         u8         uid[0x10];
7747
7748         u8         reserved_at_20[0x10];
7749         u8         op_mod[0x10];
7750
7751         u8         reserved_at_40[0x40];
7752 };
7753
7754 struct mlx5_ifc_alloc_q_counter_out_bits {
7755         u8         status[0x8];
7756         u8         reserved_at_8[0x18];
7757
7758         u8         syndrome[0x20];
7759
7760         u8         reserved_at_40[0x18];
7761         u8         counter_set_id[0x8];
7762
7763         u8         reserved_at_60[0x20];
7764 };
7765
7766 struct mlx5_ifc_alloc_q_counter_in_bits {
7767         u8         opcode[0x10];
7768         u8         uid[0x10];
7769
7770         u8         reserved_at_20[0x10];
7771         u8         op_mod[0x10];
7772
7773         u8         reserved_at_40[0x40];
7774 };
7775
7776 struct mlx5_ifc_alloc_pd_out_bits {
7777         u8         status[0x8];
7778         u8         reserved_at_8[0x18];
7779
7780         u8         syndrome[0x20];
7781
7782         u8         reserved_at_40[0x8];
7783         u8         pd[0x18];
7784
7785         u8         reserved_at_60[0x20];
7786 };
7787
7788 struct mlx5_ifc_alloc_pd_in_bits {
7789         u8         opcode[0x10];
7790         u8         uid[0x10];
7791
7792         u8         reserved_at_20[0x10];
7793         u8         op_mod[0x10];
7794
7795         u8         reserved_at_40[0x40];
7796 };
7797
7798 struct mlx5_ifc_alloc_flow_counter_out_bits {
7799         u8         status[0x8];
7800         u8         reserved_at_8[0x18];
7801
7802         u8         syndrome[0x20];
7803
7804         u8         flow_counter_id[0x20];
7805
7806         u8         reserved_at_60[0x20];
7807 };
7808
7809 struct mlx5_ifc_alloc_flow_counter_in_bits {
7810         u8         opcode[0x10];
7811         u8         reserved_at_10[0x10];
7812
7813         u8         reserved_at_20[0x10];
7814         u8         op_mod[0x10];
7815
7816         u8         reserved_at_40[0x40];
7817 };
7818
7819 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7820         u8         status[0x8];
7821         u8         reserved_at_8[0x18];
7822
7823         u8         syndrome[0x20];
7824
7825         u8         reserved_at_40[0x40];
7826 };
7827
7828 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7829         u8         opcode[0x10];
7830         u8         reserved_at_10[0x10];
7831
7832         u8         reserved_at_20[0x10];
7833         u8         op_mod[0x10];
7834
7835         u8         reserved_at_40[0x20];
7836
7837         u8         reserved_at_60[0x10];
7838         u8         vxlan_udp_port[0x10];
7839 };
7840
7841 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7842         u8         status[0x8];
7843         u8         reserved_at_8[0x18];
7844
7845         u8         syndrome[0x20];
7846
7847         u8         reserved_at_40[0x40];
7848 };
7849
7850 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7851         u8         opcode[0x10];
7852         u8         reserved_at_10[0x10];
7853
7854         u8         reserved_at_20[0x10];
7855         u8         op_mod[0x10];
7856
7857         u8         reserved_at_40[0x10];
7858         u8         rate_limit_index[0x10];
7859
7860         u8         reserved_at_60[0x20];
7861
7862         u8         rate_limit[0x20];
7863
7864         u8         burst_upper_bound[0x20];
7865
7866         u8         reserved_at_c0[0x10];
7867         u8         typical_packet_size[0x10];
7868
7869         u8         reserved_at_e0[0x120];
7870 };
7871
7872 struct mlx5_ifc_access_register_out_bits {
7873         u8         status[0x8];
7874         u8         reserved_at_8[0x18];
7875
7876         u8         syndrome[0x20];
7877
7878         u8         reserved_at_40[0x40];
7879
7880         u8         register_data[0][0x20];
7881 };
7882
7883 enum {
7884         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7885         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7886 };
7887
7888 struct mlx5_ifc_access_register_in_bits {
7889         u8         opcode[0x10];
7890         u8         reserved_at_10[0x10];
7891
7892         u8         reserved_at_20[0x10];
7893         u8         op_mod[0x10];
7894
7895         u8         reserved_at_40[0x10];
7896         u8         register_id[0x10];
7897
7898         u8         argument[0x20];
7899
7900         u8         register_data[0][0x20];
7901 };
7902
7903 struct mlx5_ifc_sltp_reg_bits {
7904         u8         status[0x4];
7905         u8         version[0x4];
7906         u8         local_port[0x8];
7907         u8         pnat[0x2];
7908         u8         reserved_at_12[0x2];
7909         u8         lane[0x4];
7910         u8         reserved_at_18[0x8];
7911
7912         u8         reserved_at_20[0x20];
7913
7914         u8         reserved_at_40[0x7];
7915         u8         polarity[0x1];
7916         u8         ob_tap0[0x8];
7917         u8         ob_tap1[0x8];
7918         u8         ob_tap2[0x8];
7919
7920         u8         reserved_at_60[0xc];
7921         u8         ob_preemp_mode[0x4];
7922         u8         ob_reg[0x8];
7923         u8         ob_bias[0x8];
7924
7925         u8         reserved_at_80[0x20];
7926 };
7927
7928 struct mlx5_ifc_slrg_reg_bits {
7929         u8         status[0x4];
7930         u8         version[0x4];
7931         u8         local_port[0x8];
7932         u8         pnat[0x2];
7933         u8         reserved_at_12[0x2];
7934         u8         lane[0x4];
7935         u8         reserved_at_18[0x8];
7936
7937         u8         time_to_link_up[0x10];
7938         u8         reserved_at_30[0xc];
7939         u8         grade_lane_speed[0x4];
7940
7941         u8         grade_version[0x8];
7942         u8         grade[0x18];
7943
7944         u8         reserved_at_60[0x4];
7945         u8         height_grade_type[0x4];
7946         u8         height_grade[0x18];
7947
7948         u8         height_dz[0x10];
7949         u8         height_dv[0x10];
7950
7951         u8         reserved_at_a0[0x10];
7952         u8         height_sigma[0x10];
7953
7954         u8         reserved_at_c0[0x20];
7955
7956         u8         reserved_at_e0[0x4];
7957         u8         phase_grade_type[0x4];
7958         u8         phase_grade[0x18];
7959
7960         u8         reserved_at_100[0x8];
7961         u8         phase_eo_pos[0x8];
7962         u8         reserved_at_110[0x8];
7963         u8         phase_eo_neg[0x8];
7964
7965         u8         ffe_set_tested[0x10];
7966         u8         test_errors_per_lane[0x10];
7967 };
7968
7969 struct mlx5_ifc_pvlc_reg_bits {
7970         u8         reserved_at_0[0x8];
7971         u8         local_port[0x8];
7972         u8         reserved_at_10[0x10];
7973
7974         u8         reserved_at_20[0x1c];
7975         u8         vl_hw_cap[0x4];
7976
7977         u8         reserved_at_40[0x1c];
7978         u8         vl_admin[0x4];
7979
7980         u8         reserved_at_60[0x1c];
7981         u8         vl_operational[0x4];
7982 };
7983
7984 struct mlx5_ifc_pude_reg_bits {
7985         u8         swid[0x8];
7986         u8         local_port[0x8];
7987         u8         reserved_at_10[0x4];
7988         u8         admin_status[0x4];
7989         u8         reserved_at_18[0x4];
7990         u8         oper_status[0x4];
7991
7992         u8         reserved_at_20[0x60];
7993 };
7994
7995 struct mlx5_ifc_ptys_reg_bits {
7996         u8         reserved_at_0[0x1];
7997         u8         an_disable_admin[0x1];
7998         u8         an_disable_cap[0x1];
7999         u8         reserved_at_3[0x5];
8000         u8         local_port[0x8];
8001         u8         reserved_at_10[0xd];
8002         u8         proto_mask[0x3];
8003
8004         u8         an_status[0x4];
8005         u8         reserved_at_24[0x1c];
8006
8007         u8         ext_eth_proto_capability[0x20];
8008
8009         u8         eth_proto_capability[0x20];
8010
8011         u8         ib_link_width_capability[0x10];
8012         u8         ib_proto_capability[0x10];
8013
8014         u8         ext_eth_proto_admin[0x20];
8015
8016         u8         eth_proto_admin[0x20];
8017
8018         u8         ib_link_width_admin[0x10];
8019         u8         ib_proto_admin[0x10];
8020
8021         u8         ext_eth_proto_oper[0x20];
8022
8023         u8         eth_proto_oper[0x20];
8024
8025         u8         ib_link_width_oper[0x10];
8026         u8         ib_proto_oper[0x10];
8027
8028         u8         reserved_at_160[0x1c];
8029         u8         connector_type[0x4];
8030
8031         u8         eth_proto_lp_advertise[0x20];
8032
8033         u8         reserved_at_1a0[0x60];
8034 };
8035
8036 struct mlx5_ifc_mlcr_reg_bits {
8037         u8         reserved_at_0[0x8];
8038         u8         local_port[0x8];
8039         u8         reserved_at_10[0x20];
8040
8041         u8         beacon_duration[0x10];
8042         u8         reserved_at_40[0x10];
8043
8044         u8         beacon_remain[0x10];
8045 };
8046
8047 struct mlx5_ifc_ptas_reg_bits {
8048         u8         reserved_at_0[0x20];
8049
8050         u8         algorithm_options[0x10];
8051         u8         reserved_at_30[0x4];
8052         u8         repetitions_mode[0x4];
8053         u8         num_of_repetitions[0x8];
8054
8055         u8         grade_version[0x8];
8056         u8         height_grade_type[0x4];
8057         u8         phase_grade_type[0x4];
8058         u8         height_grade_weight[0x8];
8059         u8         phase_grade_weight[0x8];
8060
8061         u8         gisim_measure_bits[0x10];
8062         u8         adaptive_tap_measure_bits[0x10];
8063
8064         u8         ber_bath_high_error_threshold[0x10];
8065         u8         ber_bath_mid_error_threshold[0x10];
8066
8067         u8         ber_bath_low_error_threshold[0x10];
8068         u8         one_ratio_high_threshold[0x10];
8069
8070         u8         one_ratio_high_mid_threshold[0x10];
8071         u8         one_ratio_low_mid_threshold[0x10];
8072
8073         u8         one_ratio_low_threshold[0x10];
8074         u8         ndeo_error_threshold[0x10];
8075
8076         u8         mixer_offset_step_size[0x10];
8077         u8         reserved_at_110[0x8];
8078         u8         mix90_phase_for_voltage_bath[0x8];
8079
8080         u8         mixer_offset_start[0x10];
8081         u8         mixer_offset_end[0x10];
8082
8083         u8         reserved_at_140[0x15];
8084         u8         ber_test_time[0xb];
8085 };
8086
8087 struct mlx5_ifc_pspa_reg_bits {
8088         u8         swid[0x8];
8089         u8         local_port[0x8];
8090         u8         sub_port[0x8];
8091         u8         reserved_at_18[0x8];
8092
8093         u8         reserved_at_20[0x20];
8094 };
8095
8096 struct mlx5_ifc_pqdr_reg_bits {
8097         u8         reserved_at_0[0x8];
8098         u8         local_port[0x8];
8099         u8         reserved_at_10[0x5];
8100         u8         prio[0x3];
8101         u8         reserved_at_18[0x6];
8102         u8         mode[0x2];
8103
8104         u8         reserved_at_20[0x20];
8105
8106         u8         reserved_at_40[0x10];
8107         u8         min_threshold[0x10];
8108
8109         u8         reserved_at_60[0x10];
8110         u8         max_threshold[0x10];
8111
8112         u8         reserved_at_80[0x10];
8113         u8         mark_probability_denominator[0x10];
8114
8115         u8         reserved_at_a0[0x60];
8116 };
8117
8118 struct mlx5_ifc_ppsc_reg_bits {
8119         u8         reserved_at_0[0x8];
8120         u8         local_port[0x8];
8121         u8         reserved_at_10[0x10];
8122
8123         u8         reserved_at_20[0x60];
8124
8125         u8         reserved_at_80[0x1c];
8126         u8         wrps_admin[0x4];
8127
8128         u8         reserved_at_a0[0x1c];
8129         u8         wrps_status[0x4];
8130
8131         u8         reserved_at_c0[0x8];
8132         u8         up_threshold[0x8];
8133         u8         reserved_at_d0[0x8];
8134         u8         down_threshold[0x8];
8135
8136         u8         reserved_at_e0[0x20];
8137
8138         u8         reserved_at_100[0x1c];
8139         u8         srps_admin[0x4];
8140
8141         u8         reserved_at_120[0x1c];
8142         u8         srps_status[0x4];
8143
8144         u8         reserved_at_140[0x40];
8145 };
8146
8147 struct mlx5_ifc_pplr_reg_bits {
8148         u8         reserved_at_0[0x8];
8149         u8         local_port[0x8];
8150         u8         reserved_at_10[0x10];
8151
8152         u8         reserved_at_20[0x8];
8153         u8         lb_cap[0x8];
8154         u8         reserved_at_30[0x8];
8155         u8         lb_en[0x8];
8156 };
8157
8158 struct mlx5_ifc_pplm_reg_bits {
8159         u8         reserved_at_0[0x8];
8160         u8         local_port[0x8];
8161         u8         reserved_at_10[0x10];
8162
8163         u8         reserved_at_20[0x20];
8164
8165         u8         port_profile_mode[0x8];
8166         u8         static_port_profile[0x8];
8167         u8         active_port_profile[0x8];
8168         u8         reserved_at_58[0x8];
8169
8170         u8         retransmission_active[0x8];
8171         u8         fec_mode_active[0x18];
8172
8173         u8         rs_fec_correction_bypass_cap[0x4];
8174         u8         reserved_at_84[0x8];
8175         u8         fec_override_cap_56g[0x4];
8176         u8         fec_override_cap_100g[0x4];
8177         u8         fec_override_cap_50g[0x4];
8178         u8         fec_override_cap_25g[0x4];
8179         u8         fec_override_cap_10g_40g[0x4];
8180
8181         u8         rs_fec_correction_bypass_admin[0x4];
8182         u8         reserved_at_a4[0x8];
8183         u8         fec_override_admin_56g[0x4];
8184         u8         fec_override_admin_100g[0x4];
8185         u8         fec_override_admin_50g[0x4];
8186         u8         fec_override_admin_25g[0x4];
8187         u8         fec_override_admin_10g_40g[0x4];
8188 };
8189
8190 struct mlx5_ifc_ppcnt_reg_bits {
8191         u8         swid[0x8];
8192         u8         local_port[0x8];
8193         u8         pnat[0x2];
8194         u8         reserved_at_12[0x8];
8195         u8         grp[0x6];
8196
8197         u8         clr[0x1];
8198         u8         reserved_at_21[0x1c];
8199         u8         prio_tc[0x3];
8200
8201         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8202 };
8203
8204 struct mlx5_ifc_mpein_reg_bits {
8205         u8         reserved_at_0[0x2];
8206         u8         depth[0x6];
8207         u8         pcie_index[0x8];
8208         u8         node[0x8];
8209         u8         reserved_at_18[0x8];
8210
8211         u8         capability_mask[0x20];
8212
8213         u8         reserved_at_40[0x8];
8214         u8         link_width_enabled[0x8];
8215         u8         link_speed_enabled[0x10];
8216
8217         u8         lane0_physical_position[0x8];
8218         u8         link_width_active[0x8];
8219         u8         link_speed_active[0x10];
8220
8221         u8         num_of_pfs[0x10];
8222         u8         num_of_vfs[0x10];
8223
8224         u8         bdf0[0x10];
8225         u8         reserved_at_b0[0x10];
8226
8227         u8         max_read_request_size[0x4];
8228         u8         max_payload_size[0x4];
8229         u8         reserved_at_c8[0x5];
8230         u8         pwr_status[0x3];
8231         u8         port_type[0x4];
8232         u8         reserved_at_d4[0xb];
8233         u8         lane_reversal[0x1];
8234
8235         u8         reserved_at_e0[0x14];
8236         u8         pci_power[0xc];
8237
8238         u8         reserved_at_100[0x20];
8239
8240         u8         device_status[0x10];
8241         u8         port_state[0x8];
8242         u8         reserved_at_138[0x8];
8243
8244         u8         reserved_at_140[0x10];
8245         u8         receiver_detect_result[0x10];
8246
8247         u8         reserved_at_160[0x20];
8248 };
8249
8250 struct mlx5_ifc_mpcnt_reg_bits {
8251         u8         reserved_at_0[0x8];
8252         u8         pcie_index[0x8];
8253         u8         reserved_at_10[0xa];
8254         u8         grp[0x6];
8255
8256         u8         clr[0x1];
8257         u8         reserved_at_21[0x1f];
8258
8259         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8260 };
8261
8262 struct mlx5_ifc_ppad_reg_bits {
8263         u8         reserved_at_0[0x3];
8264         u8         single_mac[0x1];
8265         u8         reserved_at_4[0x4];
8266         u8         local_port[0x8];
8267         u8         mac_47_32[0x10];
8268
8269         u8         mac_31_0[0x20];
8270
8271         u8         reserved_at_40[0x40];
8272 };
8273
8274 struct mlx5_ifc_pmtu_reg_bits {
8275         u8         reserved_at_0[0x8];
8276         u8         local_port[0x8];
8277         u8         reserved_at_10[0x10];
8278
8279         u8         max_mtu[0x10];
8280         u8         reserved_at_30[0x10];
8281
8282         u8         admin_mtu[0x10];
8283         u8         reserved_at_50[0x10];
8284
8285         u8         oper_mtu[0x10];
8286         u8         reserved_at_70[0x10];
8287 };
8288
8289 struct mlx5_ifc_pmpr_reg_bits {
8290         u8         reserved_at_0[0x8];
8291         u8         module[0x8];
8292         u8         reserved_at_10[0x10];
8293
8294         u8         reserved_at_20[0x18];
8295         u8         attenuation_5g[0x8];
8296
8297         u8         reserved_at_40[0x18];
8298         u8         attenuation_7g[0x8];
8299
8300         u8         reserved_at_60[0x18];
8301         u8         attenuation_12g[0x8];
8302 };
8303
8304 struct mlx5_ifc_pmpe_reg_bits {
8305         u8         reserved_at_0[0x8];
8306         u8         module[0x8];
8307         u8         reserved_at_10[0xc];
8308         u8         module_status[0x4];
8309
8310         u8         reserved_at_20[0x60];
8311 };
8312
8313 struct mlx5_ifc_pmpc_reg_bits {
8314         u8         module_state_updated[32][0x8];
8315 };
8316
8317 struct mlx5_ifc_pmlpn_reg_bits {
8318         u8         reserved_at_0[0x4];
8319         u8         mlpn_status[0x4];
8320         u8         local_port[0x8];
8321         u8         reserved_at_10[0x10];
8322
8323         u8         e[0x1];
8324         u8         reserved_at_21[0x1f];
8325 };
8326
8327 struct mlx5_ifc_pmlp_reg_bits {
8328         u8         rxtx[0x1];
8329         u8         reserved_at_1[0x7];
8330         u8         local_port[0x8];
8331         u8         reserved_at_10[0x8];
8332         u8         width[0x8];
8333
8334         u8         lane0_module_mapping[0x20];
8335
8336         u8         lane1_module_mapping[0x20];
8337
8338         u8         lane2_module_mapping[0x20];
8339
8340         u8         lane3_module_mapping[0x20];
8341
8342         u8         reserved_at_a0[0x160];
8343 };
8344
8345 struct mlx5_ifc_pmaos_reg_bits {
8346         u8         reserved_at_0[0x8];
8347         u8         module[0x8];
8348         u8         reserved_at_10[0x4];
8349         u8         admin_status[0x4];
8350         u8         reserved_at_18[0x4];
8351         u8         oper_status[0x4];
8352
8353         u8         ase[0x1];
8354         u8         ee[0x1];
8355         u8         reserved_at_22[0x1c];
8356         u8         e[0x2];
8357
8358         u8         reserved_at_40[0x40];
8359 };
8360
8361 struct mlx5_ifc_plpc_reg_bits {
8362         u8         reserved_at_0[0x4];
8363         u8         profile_id[0xc];
8364         u8         reserved_at_10[0x4];
8365         u8         proto_mask[0x4];
8366         u8         reserved_at_18[0x8];
8367
8368         u8         reserved_at_20[0x10];
8369         u8         lane_speed[0x10];
8370
8371         u8         reserved_at_40[0x17];
8372         u8         lpbf[0x1];
8373         u8         fec_mode_policy[0x8];
8374
8375         u8         retransmission_capability[0x8];
8376         u8         fec_mode_capability[0x18];
8377
8378         u8         retransmission_support_admin[0x8];
8379         u8         fec_mode_support_admin[0x18];
8380
8381         u8         retransmission_request_admin[0x8];
8382         u8         fec_mode_request_admin[0x18];
8383
8384         u8         reserved_at_c0[0x80];
8385 };
8386
8387 struct mlx5_ifc_plib_reg_bits {
8388         u8         reserved_at_0[0x8];
8389         u8         local_port[0x8];
8390         u8         reserved_at_10[0x8];
8391         u8         ib_port[0x8];
8392
8393         u8         reserved_at_20[0x60];
8394 };
8395
8396 struct mlx5_ifc_plbf_reg_bits {
8397         u8         reserved_at_0[0x8];
8398         u8         local_port[0x8];
8399         u8         reserved_at_10[0xd];
8400         u8         lbf_mode[0x3];
8401
8402         u8         reserved_at_20[0x20];
8403 };
8404
8405 struct mlx5_ifc_pipg_reg_bits {
8406         u8         reserved_at_0[0x8];
8407         u8         local_port[0x8];
8408         u8         reserved_at_10[0x10];
8409
8410         u8         dic[0x1];
8411         u8         reserved_at_21[0x19];
8412         u8         ipg[0x4];
8413         u8         reserved_at_3e[0x2];
8414 };
8415
8416 struct mlx5_ifc_pifr_reg_bits {
8417         u8         reserved_at_0[0x8];
8418         u8         local_port[0x8];
8419         u8         reserved_at_10[0x10];
8420
8421         u8         reserved_at_20[0xe0];
8422
8423         u8         port_filter[8][0x20];
8424
8425         u8         port_filter_update_en[8][0x20];
8426 };
8427
8428 struct mlx5_ifc_pfcc_reg_bits {
8429         u8         reserved_at_0[0x8];
8430         u8         local_port[0x8];
8431         u8         reserved_at_10[0xb];
8432         u8         ppan_mask_n[0x1];
8433         u8         minor_stall_mask[0x1];
8434         u8         critical_stall_mask[0x1];
8435         u8         reserved_at_1e[0x2];
8436
8437         u8         ppan[0x4];
8438         u8         reserved_at_24[0x4];
8439         u8         prio_mask_tx[0x8];
8440         u8         reserved_at_30[0x8];
8441         u8         prio_mask_rx[0x8];
8442
8443         u8         pptx[0x1];
8444         u8         aptx[0x1];
8445         u8         pptx_mask_n[0x1];
8446         u8         reserved_at_43[0x5];
8447         u8         pfctx[0x8];
8448         u8         reserved_at_50[0x10];
8449
8450         u8         pprx[0x1];
8451         u8         aprx[0x1];
8452         u8         pprx_mask_n[0x1];
8453         u8         reserved_at_63[0x5];
8454         u8         pfcrx[0x8];
8455         u8         reserved_at_70[0x10];
8456
8457         u8         device_stall_minor_watermark[0x10];
8458         u8         device_stall_critical_watermark[0x10];
8459
8460         u8         reserved_at_a0[0x60];
8461 };
8462
8463 struct mlx5_ifc_pelc_reg_bits {
8464         u8         op[0x4];
8465         u8         reserved_at_4[0x4];
8466         u8         local_port[0x8];
8467         u8         reserved_at_10[0x10];
8468
8469         u8         op_admin[0x8];
8470         u8         op_capability[0x8];
8471         u8         op_request[0x8];
8472         u8         op_active[0x8];
8473
8474         u8         admin[0x40];
8475
8476         u8         capability[0x40];
8477
8478         u8         request[0x40];
8479
8480         u8         active[0x40];
8481
8482         u8         reserved_at_140[0x80];
8483 };
8484
8485 struct mlx5_ifc_peir_reg_bits {
8486         u8         reserved_at_0[0x8];
8487         u8         local_port[0x8];
8488         u8         reserved_at_10[0x10];
8489
8490         u8         reserved_at_20[0xc];
8491         u8         error_count[0x4];
8492         u8         reserved_at_30[0x10];
8493
8494         u8         reserved_at_40[0xc];
8495         u8         lane[0x4];
8496         u8         reserved_at_50[0x8];
8497         u8         error_type[0x8];
8498 };
8499
8500 struct mlx5_ifc_mpegc_reg_bits {
8501         u8         reserved_at_0[0x30];
8502         u8         field_select[0x10];
8503
8504         u8         tx_overflow_sense[0x1];
8505         u8         mark_cqe[0x1];
8506         u8         mark_cnp[0x1];
8507         u8         reserved_at_43[0x1b];
8508         u8         tx_lossy_overflow_oper[0x2];
8509
8510         u8         reserved_at_60[0x100];
8511 };
8512
8513 struct mlx5_ifc_pcam_enhanced_features_bits {
8514         u8         reserved_at_0[0x6d];
8515         u8         rx_icrc_encapsulated_counter[0x1];
8516         u8         reserved_at_6e[0x4];
8517         u8         ptys_extended_ethernet[0x1];
8518         u8         reserved_at_73[0x3];
8519         u8         pfcc_mask[0x1];
8520         u8         reserved_at_77[0x3];
8521         u8         per_lane_error_counters[0x1];
8522         u8         rx_buffer_fullness_counters[0x1];
8523         u8         ptys_connector_type[0x1];
8524         u8         reserved_at_7d[0x1];
8525         u8         ppcnt_discard_group[0x1];
8526         u8         ppcnt_statistical_group[0x1];
8527 };
8528
8529 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8530         u8         port_access_reg_cap_mask_127_to_96[0x20];
8531         u8         port_access_reg_cap_mask_95_to_64[0x20];
8532
8533         u8         port_access_reg_cap_mask_63_to_36[0x1c];
8534         u8         pplm[0x1];
8535         u8         port_access_reg_cap_mask_34_to_32[0x3];
8536
8537         u8         port_access_reg_cap_mask_31_to_13[0x13];
8538         u8         pbmc[0x1];
8539         u8         pptb[0x1];
8540         u8         port_access_reg_cap_mask_10_to_09[0x2];
8541         u8         ppcnt[0x1];
8542         u8         port_access_reg_cap_mask_07_to_00[0x8];
8543 };
8544
8545 struct mlx5_ifc_pcam_reg_bits {
8546         u8         reserved_at_0[0x8];
8547         u8         feature_group[0x8];
8548         u8         reserved_at_10[0x8];
8549         u8         access_reg_group[0x8];
8550
8551         u8         reserved_at_20[0x20];
8552
8553         union {
8554                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8555                 u8         reserved_at_0[0x80];
8556         } port_access_reg_cap_mask;
8557
8558         u8         reserved_at_c0[0x80];
8559
8560         union {
8561                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8562                 u8         reserved_at_0[0x80];
8563         } feature_cap_mask;
8564
8565         u8         reserved_at_1c0[0xc0];
8566 };
8567
8568 struct mlx5_ifc_mcam_enhanced_features_bits {
8569         u8         reserved_at_0[0x6e];
8570         u8         pci_status_and_power[0x1];
8571         u8         reserved_at_6f[0x5];
8572         u8         mark_tx_action_cnp[0x1];
8573         u8         mark_tx_action_cqe[0x1];
8574         u8         dynamic_tx_overflow[0x1];
8575         u8         reserved_at_77[0x4];
8576         u8         pcie_outbound_stalled[0x1];
8577         u8         tx_overflow_buffer_pkt[0x1];
8578         u8         mtpps_enh_out_per_adj[0x1];
8579         u8         mtpps_fs[0x1];
8580         u8         pcie_performance_group[0x1];
8581 };
8582
8583 struct mlx5_ifc_mcam_access_reg_bits {
8584         u8         reserved_at_0[0x1c];
8585         u8         mcda[0x1];
8586         u8         mcc[0x1];
8587         u8         mcqi[0x1];
8588         u8         mcqs[0x1];
8589
8590         u8         regs_95_to_87[0x9];
8591         u8         mpegc[0x1];
8592         u8         regs_85_to_68[0x12];
8593         u8         tracer_registers[0x4];
8594
8595         u8         regs_63_to_32[0x20];
8596         u8         regs_31_to_0[0x20];
8597 };
8598
8599 struct mlx5_ifc_mcam_reg_bits {
8600         u8         reserved_at_0[0x8];
8601         u8         feature_group[0x8];
8602         u8         reserved_at_10[0x8];
8603         u8         access_reg_group[0x8];
8604
8605         u8         reserved_at_20[0x20];
8606
8607         union {
8608                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8609                 u8         reserved_at_0[0x80];
8610         } mng_access_reg_cap_mask;
8611
8612         u8         reserved_at_c0[0x80];
8613
8614         union {
8615                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8616                 u8         reserved_at_0[0x80];
8617         } mng_feature_cap_mask;
8618
8619         u8         reserved_at_1c0[0x80];
8620 };
8621
8622 struct mlx5_ifc_qcam_access_reg_cap_mask {
8623         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8624         u8         qpdpm[0x1];
8625         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8626         u8         qdpm[0x1];
8627         u8         qpts[0x1];
8628         u8         qcap[0x1];
8629         u8         qcam_access_reg_cap_mask_0[0x1];
8630 };
8631
8632 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8633         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8634         u8         qpts_trust_both[0x1];
8635 };
8636
8637 struct mlx5_ifc_qcam_reg_bits {
8638         u8         reserved_at_0[0x8];
8639         u8         feature_group[0x8];
8640         u8         reserved_at_10[0x8];
8641         u8         access_reg_group[0x8];
8642         u8         reserved_at_20[0x20];
8643
8644         union {
8645                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8646                 u8  reserved_at_0[0x80];
8647         } qos_access_reg_cap_mask;
8648
8649         u8         reserved_at_c0[0x80];
8650
8651         union {
8652                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8653                 u8  reserved_at_0[0x80];
8654         } qos_feature_cap_mask;
8655
8656         u8         reserved_at_1c0[0x80];
8657 };
8658
8659 struct mlx5_ifc_core_dump_reg_bits {
8660         u8         reserved_at_0[0x18];
8661         u8         core_dump_type[0x8];
8662
8663         u8         reserved_at_20[0x30];
8664         u8         vhca_id[0x10];
8665
8666         u8         reserved_at_60[0x8];
8667         u8         qpn[0x18];
8668         u8         reserved_at_80[0x180];
8669 };
8670
8671 struct mlx5_ifc_pcap_reg_bits {
8672         u8         reserved_at_0[0x8];
8673         u8         local_port[0x8];
8674         u8         reserved_at_10[0x10];
8675
8676         u8         port_capability_mask[4][0x20];
8677 };
8678
8679 struct mlx5_ifc_paos_reg_bits {
8680         u8         swid[0x8];
8681         u8         local_port[0x8];
8682         u8         reserved_at_10[0x4];
8683         u8         admin_status[0x4];
8684         u8         reserved_at_18[0x4];
8685         u8         oper_status[0x4];
8686
8687         u8         ase[0x1];
8688         u8         ee[0x1];
8689         u8         reserved_at_22[0x1c];
8690         u8         e[0x2];
8691
8692         u8         reserved_at_40[0x40];
8693 };
8694
8695 struct mlx5_ifc_pamp_reg_bits {
8696         u8         reserved_at_0[0x8];
8697         u8         opamp_group[0x8];
8698         u8         reserved_at_10[0xc];
8699         u8         opamp_group_type[0x4];
8700
8701         u8         start_index[0x10];
8702         u8         reserved_at_30[0x4];
8703         u8         num_of_indices[0xc];
8704
8705         u8         index_data[18][0x10];
8706 };
8707
8708 struct mlx5_ifc_pcmr_reg_bits {
8709         u8         reserved_at_0[0x8];
8710         u8         local_port[0x8];
8711         u8         reserved_at_10[0x10];
8712         u8         entropy_force_cap[0x1];
8713         u8         entropy_calc_cap[0x1];
8714         u8         entropy_gre_calc_cap[0x1];
8715         u8         reserved_at_23[0x1b];
8716         u8         fcs_cap[0x1];
8717         u8         reserved_at_3f[0x1];
8718         u8         entropy_force[0x1];
8719         u8         entropy_calc[0x1];
8720         u8         entropy_gre_calc[0x1];
8721         u8         reserved_at_43[0x1b];
8722         u8         fcs_chk[0x1];
8723         u8         reserved_at_5f[0x1];
8724 };
8725
8726 struct mlx5_ifc_lane_2_module_mapping_bits {
8727         u8         reserved_at_0[0x6];
8728         u8         rx_lane[0x2];
8729         u8         reserved_at_8[0x6];
8730         u8         tx_lane[0x2];
8731         u8         reserved_at_10[0x8];
8732         u8         module[0x8];
8733 };
8734
8735 struct mlx5_ifc_bufferx_reg_bits {
8736         u8         reserved_at_0[0x6];
8737         u8         lossy[0x1];
8738         u8         epsb[0x1];
8739         u8         reserved_at_8[0xc];
8740         u8         size[0xc];
8741
8742         u8         xoff_threshold[0x10];
8743         u8         xon_threshold[0x10];
8744 };
8745
8746 struct mlx5_ifc_set_node_in_bits {
8747         u8         node_description[64][0x8];
8748 };
8749
8750 struct mlx5_ifc_register_power_settings_bits {
8751         u8         reserved_at_0[0x18];
8752         u8         power_settings_level[0x8];
8753
8754         u8         reserved_at_20[0x60];
8755 };
8756
8757 struct mlx5_ifc_register_host_endianness_bits {
8758         u8         he[0x1];
8759         u8         reserved_at_1[0x1f];
8760
8761         u8         reserved_at_20[0x60];
8762 };
8763
8764 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8765         u8         reserved_at_0[0x20];
8766
8767         u8         mkey[0x20];
8768
8769         u8         addressh_63_32[0x20];
8770
8771         u8         addressl_31_0[0x20];
8772 };
8773
8774 struct mlx5_ifc_ud_adrs_vector_bits {
8775         u8         dc_key[0x40];
8776
8777         u8         ext[0x1];
8778         u8         reserved_at_41[0x7];
8779         u8         destination_qp_dct[0x18];
8780
8781         u8         static_rate[0x4];
8782         u8         sl_eth_prio[0x4];
8783         u8         fl[0x1];
8784         u8         mlid[0x7];
8785         u8         rlid_udp_sport[0x10];
8786
8787         u8         reserved_at_80[0x20];
8788
8789         u8         rmac_47_16[0x20];
8790
8791         u8         rmac_15_0[0x10];
8792         u8         tclass[0x8];
8793         u8         hop_limit[0x8];
8794
8795         u8         reserved_at_e0[0x1];
8796         u8         grh[0x1];
8797         u8         reserved_at_e2[0x2];
8798         u8         src_addr_index[0x8];
8799         u8         flow_label[0x14];
8800
8801         u8         rgid_rip[16][0x8];
8802 };
8803
8804 struct mlx5_ifc_pages_req_event_bits {
8805         u8         reserved_at_0[0x10];
8806         u8         function_id[0x10];
8807
8808         u8         num_pages[0x20];
8809
8810         u8         reserved_at_40[0xa0];
8811 };
8812
8813 struct mlx5_ifc_eqe_bits {
8814         u8         reserved_at_0[0x8];
8815         u8         event_type[0x8];
8816         u8         reserved_at_10[0x8];
8817         u8         event_sub_type[0x8];
8818
8819         u8         reserved_at_20[0xe0];
8820
8821         union mlx5_ifc_event_auto_bits event_data;
8822
8823         u8         reserved_at_1e0[0x10];
8824         u8         signature[0x8];
8825         u8         reserved_at_1f8[0x7];
8826         u8         owner[0x1];
8827 };
8828
8829 enum {
8830         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
8831 };
8832
8833 struct mlx5_ifc_cmd_queue_entry_bits {
8834         u8         type[0x8];
8835         u8         reserved_at_8[0x18];
8836
8837         u8         input_length[0x20];
8838
8839         u8         input_mailbox_pointer_63_32[0x20];
8840
8841         u8         input_mailbox_pointer_31_9[0x17];
8842         u8         reserved_at_77[0x9];
8843
8844         u8         command_input_inline_data[16][0x8];
8845
8846         u8         command_output_inline_data[16][0x8];
8847
8848         u8         output_mailbox_pointer_63_32[0x20];
8849
8850         u8         output_mailbox_pointer_31_9[0x17];
8851         u8         reserved_at_1b7[0x9];
8852
8853         u8         output_length[0x20];
8854
8855         u8         token[0x8];
8856         u8         signature[0x8];
8857         u8         reserved_at_1f0[0x8];
8858         u8         status[0x7];
8859         u8         ownership[0x1];
8860 };
8861
8862 struct mlx5_ifc_cmd_out_bits {
8863         u8         status[0x8];
8864         u8         reserved_at_8[0x18];
8865
8866         u8         syndrome[0x20];
8867
8868         u8         command_output[0x20];
8869 };
8870
8871 struct mlx5_ifc_cmd_in_bits {
8872         u8         opcode[0x10];
8873         u8         reserved_at_10[0x10];
8874
8875         u8         reserved_at_20[0x10];
8876         u8         op_mod[0x10];
8877
8878         u8         command[0][0x20];
8879 };
8880
8881 struct mlx5_ifc_cmd_if_box_bits {
8882         u8         mailbox_data[512][0x8];
8883
8884         u8         reserved_at_1000[0x180];
8885
8886         u8         next_pointer_63_32[0x20];
8887
8888         u8         next_pointer_31_10[0x16];
8889         u8         reserved_at_11b6[0xa];
8890
8891         u8         block_number[0x20];
8892
8893         u8         reserved_at_11e0[0x8];
8894         u8         token[0x8];
8895         u8         ctrl_signature[0x8];
8896         u8         signature[0x8];
8897 };
8898
8899 struct mlx5_ifc_mtt_bits {
8900         u8         ptag_63_32[0x20];
8901
8902         u8         ptag_31_8[0x18];
8903         u8         reserved_at_38[0x6];
8904         u8         wr_en[0x1];
8905         u8         rd_en[0x1];
8906 };
8907
8908 struct mlx5_ifc_query_wol_rol_out_bits {
8909         u8         status[0x8];
8910         u8         reserved_at_8[0x18];
8911
8912         u8         syndrome[0x20];
8913
8914         u8         reserved_at_40[0x10];
8915         u8         rol_mode[0x8];
8916         u8         wol_mode[0x8];
8917
8918         u8         reserved_at_60[0x20];
8919 };
8920
8921 struct mlx5_ifc_query_wol_rol_in_bits {
8922         u8         opcode[0x10];
8923         u8         reserved_at_10[0x10];
8924
8925         u8         reserved_at_20[0x10];
8926         u8         op_mod[0x10];
8927
8928         u8         reserved_at_40[0x40];
8929 };
8930
8931 struct mlx5_ifc_set_wol_rol_out_bits {
8932         u8         status[0x8];
8933         u8         reserved_at_8[0x18];
8934
8935         u8         syndrome[0x20];
8936
8937         u8         reserved_at_40[0x40];
8938 };
8939
8940 struct mlx5_ifc_set_wol_rol_in_bits {
8941         u8         opcode[0x10];
8942         u8         reserved_at_10[0x10];
8943
8944         u8         reserved_at_20[0x10];
8945         u8         op_mod[0x10];
8946
8947         u8         rol_mode_valid[0x1];
8948         u8         wol_mode_valid[0x1];
8949         u8         reserved_at_42[0xe];
8950         u8         rol_mode[0x8];
8951         u8         wol_mode[0x8];
8952
8953         u8         reserved_at_60[0x20];
8954 };
8955
8956 enum {
8957         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8958         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8959         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8960 };
8961
8962 enum {
8963         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8964         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8965         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8966 };
8967
8968 enum {
8969         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
8970         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
8971         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
8972         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
8973         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
8974         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
8975         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
8976         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
8977         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
8978         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
8979         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
8980 };
8981
8982 struct mlx5_ifc_initial_seg_bits {
8983         u8         fw_rev_minor[0x10];
8984         u8         fw_rev_major[0x10];
8985
8986         u8         cmd_interface_rev[0x10];
8987         u8         fw_rev_subminor[0x10];
8988
8989         u8         reserved_at_40[0x40];
8990
8991         u8         cmdq_phy_addr_63_32[0x20];
8992
8993         u8         cmdq_phy_addr_31_12[0x14];
8994         u8         reserved_at_b4[0x2];
8995         u8         nic_interface[0x2];
8996         u8         log_cmdq_size[0x4];
8997         u8         log_cmdq_stride[0x4];
8998
8999         u8         command_doorbell_vector[0x20];
9000
9001         u8         reserved_at_e0[0xf00];
9002
9003         u8         initializing[0x1];
9004         u8         reserved_at_fe1[0x4];
9005         u8         nic_interface_supported[0x3];
9006         u8         embedded_cpu[0x1];
9007         u8         reserved_at_fe9[0x17];
9008
9009         struct mlx5_ifc_health_buffer_bits health_buffer;
9010
9011         u8         no_dram_nic_offset[0x20];
9012
9013         u8         reserved_at_1220[0x6e40];
9014
9015         u8         reserved_at_8060[0x1f];
9016         u8         clear_int[0x1];
9017
9018         u8         health_syndrome[0x8];
9019         u8         health_counter[0x18];
9020
9021         u8         reserved_at_80a0[0x17fc0];
9022 };
9023
9024 struct mlx5_ifc_mtpps_reg_bits {
9025         u8         reserved_at_0[0xc];
9026         u8         cap_number_of_pps_pins[0x4];
9027         u8         reserved_at_10[0x4];
9028         u8         cap_max_num_of_pps_in_pins[0x4];
9029         u8         reserved_at_18[0x4];
9030         u8         cap_max_num_of_pps_out_pins[0x4];
9031
9032         u8         reserved_at_20[0x24];
9033         u8         cap_pin_3_mode[0x4];
9034         u8         reserved_at_48[0x4];
9035         u8         cap_pin_2_mode[0x4];
9036         u8         reserved_at_50[0x4];
9037         u8         cap_pin_1_mode[0x4];
9038         u8         reserved_at_58[0x4];
9039         u8         cap_pin_0_mode[0x4];
9040
9041         u8         reserved_at_60[0x4];
9042         u8         cap_pin_7_mode[0x4];
9043         u8         reserved_at_68[0x4];
9044         u8         cap_pin_6_mode[0x4];
9045         u8         reserved_at_70[0x4];
9046         u8         cap_pin_5_mode[0x4];
9047         u8         reserved_at_78[0x4];
9048         u8         cap_pin_4_mode[0x4];
9049
9050         u8         field_select[0x20];
9051         u8         reserved_at_a0[0x60];
9052
9053         u8         enable[0x1];
9054         u8         reserved_at_101[0xb];
9055         u8         pattern[0x4];
9056         u8         reserved_at_110[0x4];
9057         u8         pin_mode[0x4];
9058         u8         pin[0x8];
9059
9060         u8         reserved_at_120[0x20];
9061
9062         u8         time_stamp[0x40];
9063
9064         u8         out_pulse_duration[0x10];
9065         u8         out_periodic_adjustment[0x10];
9066         u8         enhanced_out_periodic_adjustment[0x20];
9067
9068         u8         reserved_at_1c0[0x20];
9069 };
9070
9071 struct mlx5_ifc_mtppse_reg_bits {
9072         u8         reserved_at_0[0x18];
9073         u8         pin[0x8];
9074         u8         event_arm[0x1];
9075         u8         reserved_at_21[0x1b];
9076         u8         event_generation_mode[0x4];
9077         u8         reserved_at_40[0x40];
9078 };
9079
9080 struct mlx5_ifc_mcqs_reg_bits {
9081         u8         last_index_flag[0x1];
9082         u8         reserved_at_1[0x7];
9083         u8         fw_device[0x8];
9084         u8         component_index[0x10];
9085
9086         u8         reserved_at_20[0x10];
9087         u8         identifier[0x10];
9088
9089         u8         reserved_at_40[0x17];
9090         u8         component_status[0x5];
9091         u8         component_update_state[0x4];
9092
9093         u8         last_update_state_changer_type[0x4];
9094         u8         last_update_state_changer_host_id[0x4];
9095         u8         reserved_at_68[0x18];
9096 };
9097
9098 struct mlx5_ifc_mcqi_cap_bits {
9099         u8         supported_info_bitmask[0x20];
9100
9101         u8         component_size[0x20];
9102
9103         u8         max_component_size[0x20];
9104
9105         u8         log_mcda_word_size[0x4];
9106         u8         reserved_at_64[0xc];
9107         u8         mcda_max_write_size[0x10];
9108
9109         u8         rd_en[0x1];
9110         u8         reserved_at_81[0x1];
9111         u8         match_chip_id[0x1];
9112         u8         match_psid[0x1];
9113         u8         check_user_timestamp[0x1];
9114         u8         match_base_guid_mac[0x1];
9115         u8         reserved_at_86[0x1a];
9116 };
9117
9118 struct mlx5_ifc_mcqi_version_bits {
9119         u8         reserved_at_0[0x2];
9120         u8         build_time_valid[0x1];
9121         u8         user_defined_time_valid[0x1];
9122         u8         reserved_at_4[0x14];
9123         u8         version_string_length[0x8];
9124
9125         u8         version[0x20];
9126
9127         u8         build_time[0x40];
9128
9129         u8         user_defined_time[0x40];
9130
9131         u8         build_tool_version[0x20];
9132
9133         u8         reserved_at_e0[0x20];
9134
9135         u8         version_string[92][0x8];
9136 };
9137
9138 struct mlx5_ifc_mcqi_activation_method_bits {
9139         u8         pending_server_ac_power_cycle[0x1];
9140         u8         pending_server_dc_power_cycle[0x1];
9141         u8         pending_server_reboot[0x1];
9142         u8         pending_fw_reset[0x1];
9143         u8         auto_activate[0x1];
9144         u8         all_hosts_sync[0x1];
9145         u8         device_hw_reset[0x1];
9146         u8         reserved_at_7[0x19];
9147 };
9148
9149 union mlx5_ifc_mcqi_reg_data_bits {
9150         struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
9151         struct mlx5_ifc_mcqi_version_bits           mcqi_version;
9152         struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9153 };
9154
9155 struct mlx5_ifc_mcqi_reg_bits {
9156         u8         read_pending_component[0x1];
9157         u8         reserved_at_1[0xf];
9158         u8         component_index[0x10];
9159
9160         u8         reserved_at_20[0x20];
9161
9162         u8         reserved_at_40[0x1b];
9163         u8         info_type[0x5];
9164
9165         u8         info_size[0x20];
9166
9167         u8         offset[0x20];
9168
9169         u8         reserved_at_a0[0x10];
9170         u8         data_size[0x10];
9171
9172         union mlx5_ifc_mcqi_reg_data_bits data[0];
9173 };
9174
9175 struct mlx5_ifc_mcc_reg_bits {
9176         u8         reserved_at_0[0x4];
9177         u8         time_elapsed_since_last_cmd[0xc];
9178         u8         reserved_at_10[0x8];
9179         u8         instruction[0x8];
9180
9181         u8         reserved_at_20[0x10];
9182         u8         component_index[0x10];
9183
9184         u8         reserved_at_40[0x8];
9185         u8         update_handle[0x18];
9186
9187         u8         handle_owner_type[0x4];
9188         u8         handle_owner_host_id[0x4];
9189         u8         reserved_at_68[0x1];
9190         u8         control_progress[0x7];
9191         u8         error_code[0x8];
9192         u8         reserved_at_78[0x4];
9193         u8         control_state[0x4];
9194
9195         u8         component_size[0x20];
9196
9197         u8         reserved_at_a0[0x60];
9198 };
9199
9200 struct mlx5_ifc_mcda_reg_bits {
9201         u8         reserved_at_0[0x8];
9202         u8         update_handle[0x18];
9203
9204         u8         offset[0x20];
9205
9206         u8         reserved_at_40[0x10];
9207         u8         size[0x10];
9208
9209         u8         reserved_at_60[0x20];
9210
9211         u8         data[0][0x20];
9212 };
9213
9214 union mlx5_ifc_ports_control_registers_document_bits {
9215         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9216         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9217         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9218         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9219         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9220         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9221         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9222         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
9223         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9224         struct mlx5_ifc_pamp_reg_bits pamp_reg;
9225         struct mlx5_ifc_paos_reg_bits paos_reg;
9226         struct mlx5_ifc_pcap_reg_bits pcap_reg;
9227         struct mlx5_ifc_peir_reg_bits peir_reg;
9228         struct mlx5_ifc_pelc_reg_bits pelc_reg;
9229         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9230         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
9231         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9232         struct mlx5_ifc_pifr_reg_bits pifr_reg;
9233         struct mlx5_ifc_pipg_reg_bits pipg_reg;
9234         struct mlx5_ifc_plbf_reg_bits plbf_reg;
9235         struct mlx5_ifc_plib_reg_bits plib_reg;
9236         struct mlx5_ifc_plpc_reg_bits plpc_reg;
9237         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9238         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9239         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9240         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9241         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9242         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9243         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9244         struct mlx5_ifc_ppad_reg_bits ppad_reg;
9245         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9246         struct mlx5_ifc_mpein_reg_bits mpein_reg;
9247         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
9248         struct mlx5_ifc_pplm_reg_bits pplm_reg;
9249         struct mlx5_ifc_pplr_reg_bits pplr_reg;
9250         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9251         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9252         struct mlx5_ifc_pspa_reg_bits pspa_reg;
9253         struct mlx5_ifc_ptas_reg_bits ptas_reg;
9254         struct mlx5_ifc_ptys_reg_bits ptys_reg;
9255         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
9256         struct mlx5_ifc_pude_reg_bits pude_reg;
9257         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9258         struct mlx5_ifc_slrg_reg_bits slrg_reg;
9259         struct mlx5_ifc_sltp_reg_bits sltp_reg;
9260         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9261         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
9262         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
9263         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9264         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
9265         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9266         struct mlx5_ifc_mcc_reg_bits mcc_reg;
9267         struct mlx5_ifc_mcda_reg_bits mcda_reg;
9268         u8         reserved_at_0[0x60e0];
9269 };
9270
9271 union mlx5_ifc_debug_enhancements_document_bits {
9272         struct mlx5_ifc_health_buffer_bits health_buffer;
9273         u8         reserved_at_0[0x200];
9274 };
9275
9276 union mlx5_ifc_uplink_pci_interface_document_bits {
9277         struct mlx5_ifc_initial_seg_bits initial_seg;
9278         u8         reserved_at_0[0x20060];
9279 };
9280
9281 struct mlx5_ifc_set_flow_table_root_out_bits {
9282         u8         status[0x8];
9283         u8         reserved_at_8[0x18];
9284
9285         u8         syndrome[0x20];
9286
9287         u8         reserved_at_40[0x40];
9288 };
9289
9290 struct mlx5_ifc_set_flow_table_root_in_bits {
9291         u8         opcode[0x10];
9292         u8         reserved_at_10[0x10];
9293
9294         u8         reserved_at_20[0x10];
9295         u8         op_mod[0x10];
9296
9297         u8         other_vport[0x1];
9298         u8         reserved_at_41[0xf];
9299         u8         vport_number[0x10];
9300
9301         u8         reserved_at_60[0x20];
9302
9303         u8         table_type[0x8];
9304         u8         reserved_at_88[0x18];
9305
9306         u8         reserved_at_a0[0x8];
9307         u8         table_id[0x18];
9308
9309         u8         reserved_at_c0[0x8];
9310         u8         underlay_qpn[0x18];
9311         u8         reserved_at_e0[0x120];
9312 };
9313
9314 enum {
9315         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
9316         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
9317 };
9318
9319 struct mlx5_ifc_modify_flow_table_out_bits {
9320         u8         status[0x8];
9321         u8         reserved_at_8[0x18];
9322
9323         u8         syndrome[0x20];
9324
9325         u8         reserved_at_40[0x40];
9326 };
9327
9328 struct mlx5_ifc_modify_flow_table_in_bits {
9329         u8         opcode[0x10];
9330         u8         reserved_at_10[0x10];
9331
9332         u8         reserved_at_20[0x10];
9333         u8         op_mod[0x10];
9334
9335         u8         other_vport[0x1];
9336         u8         reserved_at_41[0xf];
9337         u8         vport_number[0x10];
9338
9339         u8         reserved_at_60[0x10];
9340         u8         modify_field_select[0x10];
9341
9342         u8         table_type[0x8];
9343         u8         reserved_at_88[0x18];
9344
9345         u8         reserved_at_a0[0x8];
9346         u8         table_id[0x18];
9347
9348         struct mlx5_ifc_flow_table_context_bits flow_table_context;
9349 };
9350
9351 struct mlx5_ifc_ets_tcn_config_reg_bits {
9352         u8         g[0x1];
9353         u8         b[0x1];
9354         u8         r[0x1];
9355         u8         reserved_at_3[0x9];
9356         u8         group[0x4];
9357         u8         reserved_at_10[0x9];
9358         u8         bw_allocation[0x7];
9359
9360         u8         reserved_at_20[0xc];
9361         u8         max_bw_units[0x4];
9362         u8         reserved_at_30[0x8];
9363         u8         max_bw_value[0x8];
9364 };
9365
9366 struct mlx5_ifc_ets_global_config_reg_bits {
9367         u8         reserved_at_0[0x2];
9368         u8         r[0x1];
9369         u8         reserved_at_3[0x1d];
9370
9371         u8         reserved_at_20[0xc];
9372         u8         max_bw_units[0x4];
9373         u8         reserved_at_30[0x8];
9374         u8         max_bw_value[0x8];
9375 };
9376
9377 struct mlx5_ifc_qetc_reg_bits {
9378         u8                                         reserved_at_0[0x8];
9379         u8                                         port_number[0x8];
9380         u8                                         reserved_at_10[0x30];
9381
9382         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
9383         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9384 };
9385
9386 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9387         u8         e[0x1];
9388         u8         reserved_at_01[0x0b];
9389         u8         prio[0x04];
9390 };
9391
9392 struct mlx5_ifc_qpdpm_reg_bits {
9393         u8                                     reserved_at_0[0x8];
9394         u8                                     local_port[0x8];
9395         u8                                     reserved_at_10[0x10];
9396         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
9397 };
9398
9399 struct mlx5_ifc_qpts_reg_bits {
9400         u8         reserved_at_0[0x8];
9401         u8         local_port[0x8];
9402         u8         reserved_at_10[0x2d];
9403         u8         trust_state[0x3];
9404 };
9405
9406 struct mlx5_ifc_pptb_reg_bits {
9407         u8         reserved_at_0[0x2];
9408         u8         mm[0x2];
9409         u8         reserved_at_4[0x4];
9410         u8         local_port[0x8];
9411         u8         reserved_at_10[0x6];
9412         u8         cm[0x1];
9413         u8         um[0x1];
9414         u8         pm[0x8];
9415
9416         u8         prio_x_buff[0x20];
9417
9418         u8         pm_msb[0x8];
9419         u8         reserved_at_48[0x10];
9420         u8         ctrl_buff[0x4];
9421         u8         untagged_buff[0x4];
9422 };
9423
9424 struct mlx5_ifc_pbmc_reg_bits {
9425         u8         reserved_at_0[0x8];
9426         u8         local_port[0x8];
9427         u8         reserved_at_10[0x10];
9428
9429         u8         xoff_timer_value[0x10];
9430         u8         xoff_refresh[0x10];
9431
9432         u8         reserved_at_40[0x9];
9433         u8         fullness_threshold[0x7];
9434         u8         port_buffer_size[0x10];
9435
9436         struct mlx5_ifc_bufferx_reg_bits buffer[10];
9437
9438         u8         reserved_at_2e0[0x40];
9439 };
9440
9441 struct mlx5_ifc_qtct_reg_bits {
9442         u8         reserved_at_0[0x8];
9443         u8         port_number[0x8];
9444         u8         reserved_at_10[0xd];
9445         u8         prio[0x3];
9446
9447         u8         reserved_at_20[0x1d];
9448         u8         tclass[0x3];
9449 };
9450
9451 struct mlx5_ifc_mcia_reg_bits {
9452         u8         l[0x1];
9453         u8         reserved_at_1[0x7];
9454         u8         module[0x8];
9455         u8         reserved_at_10[0x8];
9456         u8         status[0x8];
9457
9458         u8         i2c_device_address[0x8];
9459         u8         page_number[0x8];
9460         u8         device_address[0x10];
9461
9462         u8         reserved_at_40[0x10];
9463         u8         size[0x10];
9464
9465         u8         reserved_at_60[0x20];
9466
9467         u8         dword_0[0x20];
9468         u8         dword_1[0x20];
9469         u8         dword_2[0x20];
9470         u8         dword_3[0x20];
9471         u8         dword_4[0x20];
9472         u8         dword_5[0x20];
9473         u8         dword_6[0x20];
9474         u8         dword_7[0x20];
9475         u8         dword_8[0x20];
9476         u8         dword_9[0x20];
9477         u8         dword_10[0x20];
9478         u8         dword_11[0x20];
9479 };
9480
9481 struct mlx5_ifc_dcbx_param_bits {
9482         u8         dcbx_cee_cap[0x1];
9483         u8         dcbx_ieee_cap[0x1];
9484         u8         dcbx_standby_cap[0x1];
9485         u8         reserved_at_3[0x5];
9486         u8         port_number[0x8];
9487         u8         reserved_at_10[0xa];
9488         u8         max_application_table_size[6];
9489         u8         reserved_at_20[0x15];
9490         u8         version_oper[0x3];
9491         u8         reserved_at_38[5];
9492         u8         version_admin[0x3];
9493         u8         willing_admin[0x1];
9494         u8         reserved_at_41[0x3];
9495         u8         pfc_cap_oper[0x4];
9496         u8         reserved_at_48[0x4];
9497         u8         pfc_cap_admin[0x4];
9498         u8         reserved_at_50[0x4];
9499         u8         num_of_tc_oper[0x4];
9500         u8         reserved_at_58[0x4];
9501         u8         num_of_tc_admin[0x4];
9502         u8         remote_willing[0x1];
9503         u8         reserved_at_61[3];
9504         u8         remote_pfc_cap[4];
9505         u8         reserved_at_68[0x14];
9506         u8         remote_num_of_tc[0x4];
9507         u8         reserved_at_80[0x18];
9508         u8         error[0x8];
9509         u8         reserved_at_a0[0x160];
9510 };
9511
9512 struct mlx5_ifc_lagc_bits {
9513         u8         reserved_at_0[0x1d];
9514         u8         lag_state[0x3];
9515
9516         u8         reserved_at_20[0x14];
9517         u8         tx_remap_affinity_2[0x4];
9518         u8         reserved_at_38[0x4];
9519         u8         tx_remap_affinity_1[0x4];
9520 };
9521
9522 struct mlx5_ifc_create_lag_out_bits {
9523         u8         status[0x8];
9524         u8         reserved_at_8[0x18];
9525
9526         u8         syndrome[0x20];
9527
9528         u8         reserved_at_40[0x40];
9529 };
9530
9531 struct mlx5_ifc_create_lag_in_bits {
9532         u8         opcode[0x10];
9533         u8         reserved_at_10[0x10];
9534
9535         u8         reserved_at_20[0x10];
9536         u8         op_mod[0x10];
9537
9538         struct mlx5_ifc_lagc_bits ctx;
9539 };
9540
9541 struct mlx5_ifc_modify_lag_out_bits {
9542         u8         status[0x8];
9543         u8         reserved_at_8[0x18];
9544
9545         u8         syndrome[0x20];
9546
9547         u8         reserved_at_40[0x40];
9548 };
9549
9550 struct mlx5_ifc_modify_lag_in_bits {
9551         u8         opcode[0x10];
9552         u8         reserved_at_10[0x10];
9553
9554         u8         reserved_at_20[0x10];
9555         u8         op_mod[0x10];
9556
9557         u8         reserved_at_40[0x20];
9558         u8         field_select[0x20];
9559
9560         struct mlx5_ifc_lagc_bits ctx;
9561 };
9562
9563 struct mlx5_ifc_query_lag_out_bits {
9564         u8         status[0x8];
9565         u8         reserved_at_8[0x18];
9566
9567         u8         syndrome[0x20];
9568
9569         u8         reserved_at_40[0x40];
9570
9571         struct mlx5_ifc_lagc_bits ctx;
9572 };
9573
9574 struct mlx5_ifc_query_lag_in_bits {
9575         u8         opcode[0x10];
9576         u8         reserved_at_10[0x10];
9577
9578         u8         reserved_at_20[0x10];
9579         u8         op_mod[0x10];
9580
9581         u8         reserved_at_40[0x40];
9582 };
9583
9584 struct mlx5_ifc_destroy_lag_out_bits {
9585         u8         status[0x8];
9586         u8         reserved_at_8[0x18];
9587
9588         u8         syndrome[0x20];
9589
9590         u8         reserved_at_40[0x40];
9591 };
9592
9593 struct mlx5_ifc_destroy_lag_in_bits {
9594         u8         opcode[0x10];
9595         u8         reserved_at_10[0x10];
9596
9597         u8         reserved_at_20[0x10];
9598         u8         op_mod[0x10];
9599
9600         u8         reserved_at_40[0x40];
9601 };
9602
9603 struct mlx5_ifc_create_vport_lag_out_bits {
9604         u8         status[0x8];
9605         u8         reserved_at_8[0x18];
9606
9607         u8         syndrome[0x20];
9608
9609         u8         reserved_at_40[0x40];
9610 };
9611
9612 struct mlx5_ifc_create_vport_lag_in_bits {
9613         u8         opcode[0x10];
9614         u8         reserved_at_10[0x10];
9615
9616         u8         reserved_at_20[0x10];
9617         u8         op_mod[0x10];
9618
9619         u8         reserved_at_40[0x40];
9620 };
9621
9622 struct mlx5_ifc_destroy_vport_lag_out_bits {
9623         u8         status[0x8];
9624         u8         reserved_at_8[0x18];
9625
9626         u8         syndrome[0x20];
9627
9628         u8         reserved_at_40[0x40];
9629 };
9630
9631 struct mlx5_ifc_destroy_vport_lag_in_bits {
9632         u8         opcode[0x10];
9633         u8         reserved_at_10[0x10];
9634
9635         u8         reserved_at_20[0x10];
9636         u8         op_mod[0x10];
9637
9638         u8         reserved_at_40[0x40];
9639 };
9640
9641 struct mlx5_ifc_alloc_memic_in_bits {
9642         u8         opcode[0x10];
9643         u8         reserved_at_10[0x10];
9644
9645         u8         reserved_at_20[0x10];
9646         u8         op_mod[0x10];
9647
9648         u8         reserved_at_30[0x20];
9649
9650         u8         reserved_at_40[0x18];
9651         u8         log_memic_addr_alignment[0x8];
9652
9653         u8         range_start_addr[0x40];
9654
9655         u8         range_size[0x20];
9656
9657         u8         memic_size[0x20];
9658 };
9659
9660 struct mlx5_ifc_alloc_memic_out_bits {
9661         u8         status[0x8];
9662         u8         reserved_at_8[0x18];
9663
9664         u8         syndrome[0x20];
9665
9666         u8         memic_start_addr[0x40];
9667 };
9668
9669 struct mlx5_ifc_dealloc_memic_in_bits {
9670         u8         opcode[0x10];
9671         u8         reserved_at_10[0x10];
9672
9673         u8         reserved_at_20[0x10];
9674         u8         op_mod[0x10];
9675
9676         u8         reserved_at_40[0x40];
9677
9678         u8         memic_start_addr[0x40];
9679
9680         u8         memic_size[0x20];
9681
9682         u8         reserved_at_e0[0x20];
9683 };
9684
9685 struct mlx5_ifc_dealloc_memic_out_bits {
9686         u8         status[0x8];
9687         u8         reserved_at_8[0x18];
9688
9689         u8         syndrome[0x20];
9690
9691         u8         reserved_at_40[0x40];
9692 };
9693
9694 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9695         u8         opcode[0x10];
9696         u8         uid[0x10];
9697
9698         u8         reserved_at_20[0x10];
9699         u8         obj_type[0x10];
9700
9701         u8         obj_id[0x20];
9702
9703         u8         reserved_at_60[0x20];
9704 };
9705
9706 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9707         u8         status[0x8];
9708         u8         reserved_at_8[0x18];
9709
9710         u8         syndrome[0x20];
9711
9712         u8         obj_id[0x20];
9713
9714         u8         reserved_at_60[0x20];
9715 };
9716
9717 struct mlx5_ifc_umem_bits {
9718         u8         reserved_at_0[0x80];
9719
9720         u8         reserved_at_80[0x1b];
9721         u8         log_page_size[0x5];
9722
9723         u8         page_offset[0x20];
9724
9725         u8         num_of_mtt[0x40];
9726
9727         struct mlx5_ifc_mtt_bits  mtt[0];
9728 };
9729
9730 struct mlx5_ifc_uctx_bits {
9731         u8         cap[0x20];
9732
9733         u8         reserved_at_20[0x160];
9734 };
9735
9736 struct mlx5_ifc_sw_icm_bits {
9737         u8         modify_field_select[0x40];
9738
9739         u8         reserved_at_40[0x18];
9740         u8         log_sw_icm_size[0x8];
9741
9742         u8         reserved_at_60[0x20];
9743
9744         u8         sw_icm_start_addr[0x40];
9745
9746         u8         reserved_at_c0[0x140];
9747 };
9748
9749 struct mlx5_ifc_geneve_tlv_option_bits {
9750         u8         modify_field_select[0x40];
9751
9752         u8         reserved_at_40[0x18];
9753         u8         geneve_option_fte_index[0x8];
9754
9755         u8         option_class[0x10];
9756         u8         option_type[0x8];
9757         u8         reserved_at_78[0x3];
9758         u8         option_data_length[0x5];
9759
9760         u8         reserved_at_80[0x180];
9761 };
9762
9763 struct mlx5_ifc_create_umem_in_bits {
9764         u8         opcode[0x10];
9765         u8         uid[0x10];
9766
9767         u8         reserved_at_20[0x10];
9768         u8         op_mod[0x10];
9769
9770         u8         reserved_at_40[0x40];
9771
9772         struct mlx5_ifc_umem_bits  umem;
9773 };
9774
9775 struct mlx5_ifc_create_uctx_in_bits {
9776         u8         opcode[0x10];
9777         u8         reserved_at_10[0x10];
9778
9779         u8         reserved_at_20[0x10];
9780         u8         op_mod[0x10];
9781
9782         u8         reserved_at_40[0x40];
9783
9784         struct mlx5_ifc_uctx_bits  uctx;
9785 };
9786
9787 struct mlx5_ifc_destroy_uctx_in_bits {
9788         u8         opcode[0x10];
9789         u8         reserved_at_10[0x10];
9790
9791         u8         reserved_at_20[0x10];
9792         u8         op_mod[0x10];
9793
9794         u8         reserved_at_40[0x10];
9795         u8         uid[0x10];
9796
9797         u8         reserved_at_60[0x20];
9798 };
9799
9800 struct mlx5_ifc_create_sw_icm_in_bits {
9801         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
9802         struct mlx5_ifc_sw_icm_bits                   sw_icm;
9803 };
9804
9805 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
9806         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
9807         struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
9808 };
9809
9810 struct mlx5_ifc_mtrc_string_db_param_bits {
9811         u8         string_db_base_address[0x20];
9812
9813         u8         reserved_at_20[0x8];
9814         u8         string_db_size[0x18];
9815 };
9816
9817 struct mlx5_ifc_mtrc_cap_bits {
9818         u8         trace_owner[0x1];
9819         u8         trace_to_memory[0x1];
9820         u8         reserved_at_2[0x4];
9821         u8         trc_ver[0x2];
9822         u8         reserved_at_8[0x14];
9823         u8         num_string_db[0x4];
9824
9825         u8         first_string_trace[0x8];
9826         u8         num_string_trace[0x8];
9827         u8         reserved_at_30[0x28];
9828
9829         u8         log_max_trace_buffer_size[0x8];
9830
9831         u8         reserved_at_60[0x20];
9832
9833         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
9834
9835         u8         reserved_at_280[0x180];
9836 };
9837
9838 struct mlx5_ifc_mtrc_conf_bits {
9839         u8         reserved_at_0[0x1c];
9840         u8         trace_mode[0x4];
9841         u8         reserved_at_20[0x18];
9842         u8         log_trace_buffer_size[0x8];
9843         u8         trace_mkey[0x20];
9844         u8         reserved_at_60[0x3a0];
9845 };
9846
9847 struct mlx5_ifc_mtrc_stdb_bits {
9848         u8         string_db_index[0x4];
9849         u8         reserved_at_4[0x4];
9850         u8         read_size[0x18];
9851         u8         start_offset[0x20];
9852         u8         string_db_data[0];
9853 };
9854
9855 struct mlx5_ifc_mtrc_ctrl_bits {
9856         u8         trace_status[0x2];
9857         u8         reserved_at_2[0x2];
9858         u8         arm_event[0x1];
9859         u8         reserved_at_5[0xb];
9860         u8         modify_field_select[0x10];
9861         u8         reserved_at_20[0x2b];
9862         u8         current_timestamp52_32[0x15];
9863         u8         current_timestamp31_0[0x20];
9864         u8         reserved_at_80[0x180];
9865 };
9866
9867 struct mlx5_ifc_host_params_context_bits {
9868         u8         host_number[0x8];
9869         u8         reserved_at_8[0x7];
9870         u8         host_pf_disabled[0x1];
9871         u8         host_num_of_vfs[0x10];
9872
9873         u8         host_total_vfs[0x10];
9874         u8         host_pci_bus[0x10];
9875
9876         u8         reserved_at_40[0x10];
9877         u8         host_pci_device[0x10];
9878
9879         u8         reserved_at_60[0x10];
9880         u8         host_pci_function[0x10];
9881
9882         u8         reserved_at_80[0x180];
9883 };
9884
9885 struct mlx5_ifc_query_esw_functions_in_bits {
9886         u8         opcode[0x10];
9887         u8         reserved_at_10[0x10];
9888
9889         u8         reserved_at_20[0x10];
9890         u8         op_mod[0x10];
9891
9892         u8         reserved_at_40[0x40];
9893 };
9894
9895 struct mlx5_ifc_query_esw_functions_out_bits {
9896         u8         status[0x8];
9897         u8         reserved_at_8[0x18];
9898
9899         u8         syndrome[0x20];
9900
9901         u8         reserved_at_40[0x40];
9902
9903         struct mlx5_ifc_host_params_context_bits host_params_context;
9904
9905         u8         reserved_at_280[0x180];
9906         u8         host_sf_enable[0][0x40];
9907 };
9908
9909 struct mlx5_ifc_sf_partition_bits {
9910         u8         reserved_at_0[0x10];
9911         u8         log_num_sf[0x8];
9912         u8         log_sf_bar_size[0x8];
9913 };
9914
9915 struct mlx5_ifc_query_sf_partitions_out_bits {
9916         u8         status[0x8];
9917         u8         reserved_at_8[0x18];
9918
9919         u8         syndrome[0x20];
9920
9921         u8         reserved_at_40[0x18];
9922         u8         num_sf_partitions[0x8];
9923
9924         u8         reserved_at_60[0x20];
9925
9926         struct mlx5_ifc_sf_partition_bits sf_partition[0];
9927 };
9928
9929 struct mlx5_ifc_query_sf_partitions_in_bits {
9930         u8         opcode[0x10];
9931         u8         reserved_at_10[0x10];
9932
9933         u8         reserved_at_20[0x10];
9934         u8         op_mod[0x10];
9935
9936         u8         reserved_at_40[0x40];
9937 };
9938
9939 struct mlx5_ifc_dealloc_sf_out_bits {
9940         u8         status[0x8];
9941         u8         reserved_at_8[0x18];
9942
9943         u8         syndrome[0x20];
9944
9945         u8         reserved_at_40[0x40];
9946 };
9947
9948 struct mlx5_ifc_dealloc_sf_in_bits {
9949         u8         opcode[0x10];
9950         u8         reserved_at_10[0x10];
9951
9952         u8         reserved_at_20[0x10];
9953         u8         op_mod[0x10];
9954
9955         u8         reserved_at_40[0x10];
9956         u8         function_id[0x10];
9957
9958         u8         reserved_at_60[0x20];
9959 };
9960
9961 struct mlx5_ifc_alloc_sf_out_bits {
9962         u8         status[0x8];
9963         u8         reserved_at_8[0x18];
9964
9965         u8         syndrome[0x20];
9966
9967         u8         reserved_at_40[0x40];
9968 };
9969
9970 struct mlx5_ifc_alloc_sf_in_bits {
9971         u8         opcode[0x10];
9972         u8         reserved_at_10[0x10];
9973
9974         u8         reserved_at_20[0x10];
9975         u8         op_mod[0x10];
9976
9977         u8         reserved_at_40[0x10];
9978         u8         function_id[0x10];
9979
9980         u8         reserved_at_60[0x20];
9981 };
9982
9983 struct mlx5_ifc_affiliated_event_header_bits {
9984         u8         reserved_at_0[0x10];
9985         u8         obj_type[0x10];
9986
9987         u8         obj_id[0x20];
9988 };
9989
9990 enum {
9991         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
9992 };
9993
9994 enum {
9995         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
9996 };
9997
9998 struct mlx5_ifc_encryption_key_obj_bits {
9999         u8         modify_field_select[0x40];
10000
10001         u8         reserved_at_40[0x14];
10002         u8         key_size[0x4];
10003         u8         reserved_at_58[0x4];
10004         u8         key_type[0x4];
10005
10006         u8         reserved_at_60[0x8];
10007         u8         pd[0x18];
10008
10009         u8         reserved_at_80[0x180];
10010         u8         key[8][0x20];
10011
10012         u8         reserved_at_300[0x500];
10013 };
10014
10015 struct mlx5_ifc_create_encryption_key_in_bits {
10016         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10017         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10018 };
10019
10020 enum {
10021         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10022         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10023 };
10024
10025 enum {
10026         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
10027 };
10028
10029 struct mlx5_ifc_tls_static_params_bits {
10030         u8         const_2[0x2];
10031         u8         tls_version[0x4];
10032         u8         const_1[0x2];
10033         u8         reserved_at_8[0x14];
10034         u8         encryption_standard[0x4];
10035
10036         u8         reserved_at_20[0x20];
10037
10038         u8         initial_record_number[0x40];
10039
10040         u8         resync_tcp_sn[0x20];
10041
10042         u8         gcm_iv[0x20];
10043
10044         u8         implicit_iv[0x40];
10045
10046         u8         reserved_at_100[0x8];
10047         u8         dek_index[0x18];
10048
10049         u8         reserved_at_120[0xe0];
10050 };
10051
10052 struct mlx5_ifc_tls_progress_params_bits {
10053         u8         valid[0x1];
10054         u8         reserved_at_1[0x7];
10055         u8         pd[0x18];
10056
10057         u8         next_record_tcp_sn[0x20];
10058
10059         u8         hw_resync_tcp_sn[0x20];
10060
10061         u8         record_tracker_state[0x2];
10062         u8         auth_state[0x2];
10063         u8         reserved_at_64[0x4];
10064         u8         hw_offset_record_number[0x18];
10065 };
10066
10067 #endif /* MLX5_IFC_H */