2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "mlx5_ifc_fpga.h"
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
66 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
68 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
78 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
79 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
80 MLX5_CMD_OP_INIT_HCA = 0x102,
81 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
82 MLX5_CMD_OP_ENABLE_HCA = 0x104,
83 MLX5_CMD_OP_DISABLE_HCA = 0x105,
84 MLX5_CMD_OP_QUERY_PAGES = 0x107,
85 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
86 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
87 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
88 MLX5_CMD_OP_SET_ISSI = 0x10b,
89 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
90 MLX5_CMD_OP_CREATE_MKEY = 0x200,
91 MLX5_CMD_OP_QUERY_MKEY = 0x201,
92 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
94 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
95 MLX5_CMD_OP_CREATE_EQ = 0x301,
96 MLX5_CMD_OP_DESTROY_EQ = 0x302,
97 MLX5_CMD_OP_QUERY_EQ = 0x303,
98 MLX5_CMD_OP_GEN_EQE = 0x304,
99 MLX5_CMD_OP_CREATE_CQ = 0x400,
100 MLX5_CMD_OP_DESTROY_CQ = 0x401,
101 MLX5_CMD_OP_QUERY_CQ = 0x402,
102 MLX5_CMD_OP_MODIFY_CQ = 0x403,
103 MLX5_CMD_OP_CREATE_QP = 0x500,
104 MLX5_CMD_OP_DESTROY_QP = 0x501,
105 MLX5_CMD_OP_RST2INIT_QP = 0x502,
106 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
107 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
108 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
109 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
110 MLX5_CMD_OP_2ERR_QP = 0x507,
111 MLX5_CMD_OP_2RST_QP = 0x50a,
112 MLX5_CMD_OP_QUERY_QP = 0x50b,
113 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
114 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
115 MLX5_CMD_OP_CREATE_PSV = 0x600,
116 MLX5_CMD_OP_DESTROY_PSV = 0x601,
117 MLX5_CMD_OP_CREATE_SRQ = 0x700,
118 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
119 MLX5_CMD_OP_QUERY_SRQ = 0x702,
120 MLX5_CMD_OP_ARM_RQ = 0x703,
121 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
122 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
123 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
124 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
125 MLX5_CMD_OP_CREATE_DCT = 0x710,
126 MLX5_CMD_OP_DESTROY_DCT = 0x711,
127 MLX5_CMD_OP_DRAIN_DCT = 0x712,
128 MLX5_CMD_OP_QUERY_DCT = 0x713,
129 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
130 MLX5_CMD_OP_CREATE_XRQ = 0x717,
131 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
132 MLX5_CMD_OP_QUERY_XRQ = 0x719,
133 MLX5_CMD_OP_ARM_XRQ = 0x71a,
134 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
135 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
136 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
137 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
138 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
139 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
140 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
141 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
142 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
143 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
144 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
145 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
146 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
147 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
148 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
149 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
150 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
151 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
152 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
153 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
154 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
155 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
156 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
157 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
158 MLX5_CMD_OP_ALLOC_PD = 0x800,
159 MLX5_CMD_OP_DEALLOC_PD = 0x801,
160 MLX5_CMD_OP_ALLOC_UAR = 0x802,
161 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
162 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
163 MLX5_CMD_OP_ACCESS_REG = 0x805,
164 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
165 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
166 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
167 MLX5_CMD_OP_MAD_IFC = 0x50d,
168 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
169 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
170 MLX5_CMD_OP_NOP = 0x80d,
171 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
172 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
173 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
174 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
175 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
176 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
177 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
178 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
179 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
180 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
181 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
182 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
183 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
184 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
185 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
186 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
187 MLX5_CMD_OP_CREATE_LAG = 0x840,
188 MLX5_CMD_OP_MODIFY_LAG = 0x841,
189 MLX5_CMD_OP_QUERY_LAG = 0x842,
190 MLX5_CMD_OP_DESTROY_LAG = 0x843,
191 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
192 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
193 MLX5_CMD_OP_CREATE_TIR = 0x900,
194 MLX5_CMD_OP_MODIFY_TIR = 0x901,
195 MLX5_CMD_OP_DESTROY_TIR = 0x902,
196 MLX5_CMD_OP_QUERY_TIR = 0x903,
197 MLX5_CMD_OP_CREATE_SQ = 0x904,
198 MLX5_CMD_OP_MODIFY_SQ = 0x905,
199 MLX5_CMD_OP_DESTROY_SQ = 0x906,
200 MLX5_CMD_OP_QUERY_SQ = 0x907,
201 MLX5_CMD_OP_CREATE_RQ = 0x908,
202 MLX5_CMD_OP_MODIFY_RQ = 0x909,
203 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
204 MLX5_CMD_OP_QUERY_RQ = 0x90b,
205 MLX5_CMD_OP_CREATE_RMP = 0x90c,
206 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
207 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
208 MLX5_CMD_OP_QUERY_RMP = 0x90f,
209 MLX5_CMD_OP_CREATE_TIS = 0x912,
210 MLX5_CMD_OP_MODIFY_TIS = 0x913,
211 MLX5_CMD_OP_DESTROY_TIS = 0x914,
212 MLX5_CMD_OP_QUERY_TIS = 0x915,
213 MLX5_CMD_OP_CREATE_RQT = 0x916,
214 MLX5_CMD_OP_MODIFY_RQT = 0x917,
215 MLX5_CMD_OP_DESTROY_RQT = 0x918,
216 MLX5_CMD_OP_QUERY_RQT = 0x919,
217 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
218 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
219 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
220 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
221 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
222 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
223 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
224 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
225 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
226 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
227 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
228 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
229 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
230 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
231 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
232 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
233 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
234 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
238 struct mlx5_ifc_flow_table_fields_supported_bits {
241 u8 outer_ether_type[0x1];
242 u8 outer_ip_version[0x1];
243 u8 outer_first_prio[0x1];
244 u8 outer_first_cfi[0x1];
245 u8 outer_first_vid[0x1];
246 u8 outer_ipv4_ttl[0x1];
247 u8 outer_second_prio[0x1];
248 u8 outer_second_cfi[0x1];
249 u8 outer_second_vid[0x1];
250 u8 reserved_at_b[0x1];
254 u8 outer_ip_protocol[0x1];
255 u8 outer_ip_ecn[0x1];
256 u8 outer_ip_dscp[0x1];
257 u8 outer_udp_sport[0x1];
258 u8 outer_udp_dport[0x1];
259 u8 outer_tcp_sport[0x1];
260 u8 outer_tcp_dport[0x1];
261 u8 outer_tcp_flags[0x1];
262 u8 outer_gre_protocol[0x1];
263 u8 outer_gre_key[0x1];
264 u8 outer_vxlan_vni[0x1];
265 u8 reserved_at_1a[0x5];
266 u8 source_eswitch_port[0x1];
270 u8 inner_ether_type[0x1];
271 u8 inner_ip_version[0x1];
272 u8 inner_first_prio[0x1];
273 u8 inner_first_cfi[0x1];
274 u8 inner_first_vid[0x1];
275 u8 reserved_at_27[0x1];
276 u8 inner_second_prio[0x1];
277 u8 inner_second_cfi[0x1];
278 u8 inner_second_vid[0x1];
279 u8 reserved_at_2b[0x1];
283 u8 inner_ip_protocol[0x1];
284 u8 inner_ip_ecn[0x1];
285 u8 inner_ip_dscp[0x1];
286 u8 inner_udp_sport[0x1];
287 u8 inner_udp_dport[0x1];
288 u8 inner_tcp_sport[0x1];
289 u8 inner_tcp_dport[0x1];
290 u8 inner_tcp_flags[0x1];
291 u8 reserved_at_37[0x9];
293 u8 reserved_at_40[0x40];
296 struct mlx5_ifc_flow_table_prop_layout_bits {
298 u8 reserved_at_1[0x1];
299 u8 flow_counter[0x1];
300 u8 flow_modify_en[0x1];
302 u8 identified_miss_table_mode[0x1];
303 u8 flow_table_modify[0x1];
306 u8 reserved_at_9[0x17];
308 u8 reserved_at_20[0x2];
309 u8 log_max_ft_size[0x6];
310 u8 log_max_modify_header_context[0x8];
311 u8 max_modify_header_actions[0x8];
312 u8 max_ft_level[0x8];
314 u8 reserved_at_40[0x20];
316 u8 reserved_at_60[0x18];
317 u8 log_max_ft_num[0x8];
319 u8 reserved_at_80[0x18];
320 u8 log_max_destination[0x8];
322 u8 reserved_at_a0[0x18];
323 u8 log_max_flow[0x8];
325 u8 reserved_at_c0[0x40];
327 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
329 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
332 struct mlx5_ifc_odp_per_transport_service_cap_bits {
339 u8 reserved_at_6[0x1a];
342 struct mlx5_ifc_ipv4_layout_bits {
343 u8 reserved_at_0[0x60];
348 struct mlx5_ifc_ipv6_layout_bits {
352 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
353 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
354 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
355 u8 reserved_at_0[0x80];
358 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
383 u8 reserved_at_c0[0x18];
384 u8 ttl_hoplimit[0x8];
389 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
391 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
394 struct mlx5_ifc_fte_match_set_misc_bits {
395 u8 reserved_at_0[0x8];
398 u8 reserved_at_20[0x10];
399 u8 source_port[0x10];
401 u8 outer_second_prio[0x3];
402 u8 outer_second_cfi[0x1];
403 u8 outer_second_vid[0xc];
404 u8 inner_second_prio[0x3];
405 u8 inner_second_cfi[0x1];
406 u8 inner_second_vid[0xc];
408 u8 outer_second_cvlan_tag[0x1];
409 u8 inner_second_cvlan_tag[0x1];
410 u8 outer_second_svlan_tag[0x1];
411 u8 inner_second_svlan_tag[0x1];
412 u8 reserved_at_64[0xc];
413 u8 gre_protocol[0x10];
419 u8 reserved_at_b8[0x8];
421 u8 reserved_at_c0[0x20];
423 u8 reserved_at_e0[0xc];
424 u8 outer_ipv6_flow_label[0x14];
426 u8 reserved_at_100[0xc];
427 u8 inner_ipv6_flow_label[0x14];
429 u8 reserved_at_120[0xe0];
432 struct mlx5_ifc_cmd_pas_bits {
436 u8 reserved_at_34[0xc];
439 struct mlx5_ifc_uint64_bits {
446 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
447 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
448 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
449 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
450 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
451 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
452 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
453 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
454 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
455 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
458 struct mlx5_ifc_ads_bits {
461 u8 reserved_at_2[0xe];
464 u8 reserved_at_20[0x8];
470 u8 reserved_at_45[0x3];
471 u8 src_addr_index[0x8];
472 u8 reserved_at_50[0x4];
476 u8 reserved_at_60[0x4];
480 u8 rgid_rip[16][0x8];
482 u8 reserved_at_100[0x4];
485 u8 reserved_at_106[0x1];
500 struct mlx5_ifc_flow_table_nic_cap_bits {
501 u8 nic_rx_multi_path_tirs[0x1];
502 u8 nic_rx_multi_path_tirs_fts[0x1];
503 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
504 u8 reserved_at_3[0x1fd];
506 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
508 u8 reserved_at_400[0x200];
510 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
512 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
514 u8 reserved_at_a00[0x200];
516 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
518 u8 reserved_at_e00[0x7200];
521 struct mlx5_ifc_flow_table_eswitch_cap_bits {
522 u8 reserved_at_0[0x200];
524 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
526 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
528 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
530 u8 reserved_at_800[0x7800];
533 struct mlx5_ifc_e_switch_cap_bits {
534 u8 vport_svlan_strip[0x1];
535 u8 vport_cvlan_strip[0x1];
536 u8 vport_svlan_insert[0x1];
537 u8 vport_cvlan_insert_if_not_exist[0x1];
538 u8 vport_cvlan_insert_overwrite[0x1];
539 u8 reserved_at_5[0x19];
540 u8 nic_vport_node_guid_modify[0x1];
541 u8 nic_vport_port_guid_modify[0x1];
543 u8 vxlan_encap_decap[0x1];
544 u8 nvgre_encap_decap[0x1];
545 u8 reserved_at_22[0x9];
546 u8 log_max_encap_headers[0x5];
548 u8 max_encap_header_size[0xa];
550 u8 reserved_40[0x7c0];
554 struct mlx5_ifc_qos_cap_bits {
555 u8 packet_pacing[0x1];
556 u8 esw_scheduling[0x1];
557 u8 esw_bw_share[0x1];
558 u8 esw_rate_limit[0x1];
559 u8 reserved_at_4[0x1c];
561 u8 reserved_at_20[0x20];
563 u8 packet_pacing_max_rate[0x20];
565 u8 packet_pacing_min_rate[0x20];
567 u8 reserved_at_80[0x10];
568 u8 packet_pacing_rate_table_size[0x10];
570 u8 esw_element_type[0x10];
571 u8 esw_tsar_type[0x10];
573 u8 reserved_at_c0[0x10];
574 u8 max_qos_para_vport[0x10];
576 u8 max_tsar_bw_share[0x20];
578 u8 reserved_at_100[0x700];
581 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
585 u8 lro_psh_flag[0x1];
586 u8 lro_time_stamp[0x1];
587 u8 reserved_at_5[0x2];
588 u8 wqe_vlan_insert[0x1];
589 u8 self_lb_en_modifiable[0x1];
590 u8 reserved_at_9[0x2];
592 u8 multi_pkt_send_wqe[0x2];
593 u8 wqe_inline_mode[0x2];
594 u8 rss_ind_tbl_cap[0x4];
597 u8 reserved_at_1a[0x1];
598 u8 tunnel_lso_const_out_ip_id[0x1];
599 u8 reserved_at_1c[0x2];
600 u8 tunnel_statless_gre[0x1];
601 u8 tunnel_stateless_vxlan[0x1];
603 u8 reserved_at_20[0x20];
605 u8 reserved_at_40[0x10];
606 u8 lro_min_mss_size[0x10];
608 u8 reserved_at_60[0x120];
610 u8 lro_timer_supported_periods[4][0x20];
612 u8 reserved_at_200[0x600];
615 struct mlx5_ifc_roce_cap_bits {
617 u8 reserved_at_1[0x1f];
619 u8 reserved_at_20[0x60];
621 u8 reserved_at_80[0xc];
623 u8 reserved_at_90[0x8];
624 u8 roce_version[0x8];
626 u8 reserved_at_a0[0x10];
627 u8 r_roce_dest_udp_port[0x10];
629 u8 r_roce_max_src_udp_port[0x10];
630 u8 r_roce_min_src_udp_port[0x10];
632 u8 reserved_at_e0[0x10];
633 u8 roce_address_table_size[0x10];
635 u8 reserved_at_100[0x700];
639 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
640 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
641 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
642 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
643 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
644 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
645 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
646 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
647 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
651 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
652 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
653 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
654 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
655 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
656 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
657 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
658 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
659 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
662 struct mlx5_ifc_atomic_caps_bits {
663 u8 reserved_at_0[0x40];
665 u8 atomic_req_8B_endianness_mode[0x2];
666 u8 reserved_at_42[0x4];
667 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
669 u8 reserved_at_47[0x19];
671 u8 reserved_at_60[0x20];
673 u8 reserved_at_80[0x10];
674 u8 atomic_operations[0x10];
676 u8 reserved_at_a0[0x10];
677 u8 atomic_size_qp[0x10];
679 u8 reserved_at_c0[0x10];
680 u8 atomic_size_dc[0x10];
682 u8 reserved_at_e0[0x720];
685 struct mlx5_ifc_odp_cap_bits {
686 u8 reserved_at_0[0x40];
689 u8 reserved_at_41[0x1f];
691 u8 reserved_at_60[0x20];
693 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
695 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
697 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
699 u8 reserved_at_e0[0x720];
702 struct mlx5_ifc_calc_op {
703 u8 reserved_at_0[0x10];
704 u8 reserved_at_10[0x9];
705 u8 op_swap_endianness[0x1];
714 struct mlx5_ifc_vector_calc_cap_bits {
716 u8 reserved_at_1[0x1f];
717 u8 reserved_at_20[0x8];
718 u8 max_vec_count[0x8];
719 u8 reserved_at_30[0xd];
720 u8 max_chunk_size[0x3];
721 struct mlx5_ifc_calc_op calc0;
722 struct mlx5_ifc_calc_op calc1;
723 struct mlx5_ifc_calc_op calc2;
724 struct mlx5_ifc_calc_op calc3;
726 u8 reserved_at_e0[0x720];
730 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
731 MLX5_WQ_TYPE_CYCLIC = 0x1,
732 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
736 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
737 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
741 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
742 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
743 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
744 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
745 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
749 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
750 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
751 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
752 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
753 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
754 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
758 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
759 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
763 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
764 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
765 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
769 MLX5_CAP_PORT_TYPE_IB = 0x0,
770 MLX5_CAP_PORT_TYPE_ETH = 0x1,
774 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
775 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
776 MLX5_CAP_UMR_FENCE_NONE = 0x2,
779 struct mlx5_ifc_cmd_hca_cap_bits {
780 u8 reserved_at_0[0x80];
782 u8 log_max_srq_sz[0x8];
783 u8 log_max_qp_sz[0x8];
784 u8 reserved_at_90[0xb];
787 u8 reserved_at_a0[0xb];
789 u8 reserved_at_b0[0x10];
791 u8 reserved_at_c0[0x8];
792 u8 log_max_cq_sz[0x8];
793 u8 reserved_at_d0[0xb];
796 u8 log_max_eq_sz[0x8];
797 u8 reserved_at_e8[0x2];
798 u8 log_max_mkey[0x6];
799 u8 reserved_at_f0[0xc];
802 u8 max_indirection[0x8];
803 u8 fixed_buffer_size[0x1];
804 u8 log_max_mrw_sz[0x7];
805 u8 force_teardown[0x1];
806 u8 reserved_at_111[0x1];
807 u8 log_max_bsf_list_size[0x6];
808 u8 umr_extended_translation_offset[0x1];
810 u8 log_max_klm_list_size[0x6];
812 u8 reserved_at_120[0xa];
813 u8 log_max_ra_req_dc[0x6];
814 u8 reserved_at_130[0xa];
815 u8 log_max_ra_res_dc[0x6];
817 u8 reserved_at_140[0xa];
818 u8 log_max_ra_req_qp[0x6];
819 u8 reserved_at_150[0xa];
820 u8 log_max_ra_res_qp[0x6];
823 u8 cc_query_allowed[0x1];
824 u8 cc_modify_allowed[0x1];
826 u8 cache_line_128byte[0x1];
827 u8 reserved_at_163[0xb];
828 u8 gid_table_size[0x10];
830 u8 out_of_seq_cnt[0x1];
831 u8 vport_counters[0x1];
832 u8 retransmission_q_counters[0x1];
833 u8 reserved_at_183[0x1];
834 u8 modify_rq_counter_set_id[0x1];
835 u8 reserved_at_185[0x1];
837 u8 pkey_table_size[0x10];
839 u8 vport_group_manager[0x1];
840 u8 vhca_group_manager[0x1];
843 u8 reserved_at_1a4[0x1];
845 u8 nic_flow_table[0x1];
846 u8 eswitch_flow_table[0x1];
847 u8 early_vf_enable[0x1];
850 u8 local_ca_ack_delay[0x5];
851 u8 port_module_event[0x1];
852 u8 reserved_at_1b1[0x1];
854 u8 reserved_at_1b3[0x1];
855 u8 disable_link_up[0x1];
860 u8 reserved_at_1c0[0x1];
864 u8 reserved_at_1c8[0x4];
866 u8 reserved_at_1d0[0x1];
868 u8 reserved_at_1d2[0x3];
872 u8 reserved_at_1d8[0x1];
881 u8 stat_rate_support[0x10];
882 u8 reserved_at_1f0[0xc];
885 u8 compact_address_vector[0x1];
887 u8 reserved_at_202[0x1];
888 u8 ipoib_enhanced_offloads[0x1];
889 u8 ipoib_basic_offloads[0x1];
890 u8 reserved_at_205[0x5];
892 u8 reserved_at_20c[0x3];
893 u8 drain_sigerr[0x1];
894 u8 cmdif_checksum[0x2];
896 u8 reserved_at_213[0x1];
897 u8 wq_signature[0x1];
898 u8 sctr_data_cqe[0x1];
899 u8 reserved_at_216[0x1];
905 u8 eth_net_offloads[0x1];
908 u8 reserved_at_21f[0x1];
912 u8 cq_moderation[0x1];
913 u8 reserved_at_223[0x3];
917 u8 reserved_at_229[0x1];
918 u8 scqe_break_moderation[0x1];
919 u8 cq_period_start_from_cqe[0x1];
921 u8 reserved_at_22d[0x1];
924 u8 umr_ptr_rlky[0x1];
926 u8 reserved_at_232[0x4];
929 u8 set_deth_sqpn[0x1];
930 u8 reserved_at_239[0x3];
937 u8 reserved_at_241[0x9];
939 u8 reserved_at_250[0x8];
943 u8 driver_version[0x1];
944 u8 pad_tx_eth_packet[0x1];
945 u8 reserved_at_263[0x8];
946 u8 log_bf_reg_size[0x5];
948 u8 reserved_at_270[0xb];
950 u8 num_lag_ports[0x4];
952 u8 reserved_at_280[0x10];
953 u8 max_wqe_sz_sq[0x10];
955 u8 reserved_at_2a0[0x10];
956 u8 max_wqe_sz_rq[0x10];
958 u8 reserved_at_2c0[0x10];
959 u8 max_wqe_sz_sq_dc[0x10];
961 u8 reserved_at_2e0[0x7];
964 u8 reserved_at_300[0x18];
967 u8 reserved_at_320[0x3];
968 u8 log_max_transport_domain[0x5];
969 u8 reserved_at_328[0x3];
971 u8 reserved_at_330[0xb];
972 u8 log_max_xrcd[0x5];
974 u8 reserved_at_340[0x8];
975 u8 log_max_flow_counter_bulk[0x8];
976 u8 max_flow_counter[0x10];
979 u8 reserved_at_360[0x3];
981 u8 reserved_at_368[0x3];
983 u8 reserved_at_370[0x3];
985 u8 reserved_at_378[0x3];
988 u8 basic_cyclic_rcv_wqe[0x1];
989 u8 reserved_at_381[0x2];
991 u8 reserved_at_388[0x3];
993 u8 reserved_at_390[0x3];
994 u8 log_max_rqt_size[0x5];
995 u8 reserved_at_398[0x3];
996 u8 log_max_tis_per_sq[0x5];
998 u8 reserved_at_3a0[0x3];
999 u8 log_max_stride_sz_rq[0x5];
1000 u8 reserved_at_3a8[0x3];
1001 u8 log_min_stride_sz_rq[0x5];
1002 u8 reserved_at_3b0[0x3];
1003 u8 log_max_stride_sz_sq[0x5];
1004 u8 reserved_at_3b8[0x3];
1005 u8 log_min_stride_sz_sq[0x5];
1007 u8 reserved_at_3c0[0x1b];
1008 u8 log_max_wq_sz[0x5];
1010 u8 nic_vport_change_event[0x1];
1011 u8 reserved_at_3e1[0xa];
1012 u8 log_max_vlan_list[0x5];
1013 u8 reserved_at_3f0[0x3];
1014 u8 log_max_current_mc_list[0x5];
1015 u8 reserved_at_3f8[0x3];
1016 u8 log_max_current_uc_list[0x5];
1018 u8 reserved_at_400[0x80];
1020 u8 reserved_at_480[0x3];
1021 u8 log_max_l2_table[0x5];
1022 u8 reserved_at_488[0x8];
1023 u8 log_uar_page_sz[0x10];
1025 u8 reserved_at_4a0[0x20];
1026 u8 device_frequency_mhz[0x20];
1027 u8 device_frequency_khz[0x20];
1029 u8 reserved_at_500[0x20];
1030 u8 num_of_uars_per_page[0x20];
1031 u8 reserved_at_540[0x40];
1033 u8 reserved_at_580[0x3f];
1034 u8 cqe_compression[0x1];
1036 u8 cqe_compression_timeout[0x10];
1037 u8 cqe_compression_max_num[0x10];
1039 u8 reserved_at_5e0[0x10];
1040 u8 tag_matching[0x1];
1041 u8 rndv_offload_rc[0x1];
1042 u8 rndv_offload_dc[0x1];
1043 u8 log_tag_matching_list_sz[0x5];
1044 u8 reserved_at_5f8[0x3];
1045 u8 log_max_xrq[0x5];
1047 u8 reserved_at_600[0x200];
1050 enum mlx5_flow_destination_type {
1051 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1052 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1053 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1055 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1058 struct mlx5_ifc_dest_format_struct_bits {
1059 u8 destination_type[0x8];
1060 u8 destination_id[0x18];
1062 u8 reserved_at_20[0x20];
1065 struct mlx5_ifc_flow_counter_list_bits {
1067 u8 num_of_counters[0xf];
1068 u8 flow_counter_id[0x10];
1070 u8 reserved_at_20[0x20];
1073 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1074 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1075 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1076 u8 reserved_at_0[0x40];
1079 struct mlx5_ifc_fte_match_param_bits {
1080 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1082 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1084 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1086 u8 reserved_at_600[0xa00];
1090 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1091 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1092 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1093 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1094 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1097 struct mlx5_ifc_rx_hash_field_select_bits {
1098 u8 l3_prot_type[0x1];
1099 u8 l4_prot_type[0x1];
1100 u8 selected_fields[0x1e];
1104 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1105 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1109 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1110 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1113 struct mlx5_ifc_wq_bits {
1115 u8 wq_signature[0x1];
1116 u8 end_padding_mode[0x2];
1118 u8 reserved_at_8[0x18];
1120 u8 hds_skip_first_sge[0x1];
1121 u8 log2_hds_buf_size[0x3];
1122 u8 reserved_at_24[0x7];
1123 u8 page_offset[0x5];
1126 u8 reserved_at_40[0x8];
1129 u8 reserved_at_60[0x8];
1134 u8 hw_counter[0x20];
1136 u8 sw_counter[0x20];
1138 u8 reserved_at_100[0xc];
1139 u8 log_wq_stride[0x4];
1140 u8 reserved_at_110[0x3];
1141 u8 log_wq_pg_sz[0x5];
1142 u8 reserved_at_118[0x3];
1145 u8 reserved_at_120[0x15];
1146 u8 log_wqe_num_of_strides[0x3];
1147 u8 two_byte_shift_en[0x1];
1148 u8 reserved_at_139[0x4];
1149 u8 log_wqe_stride_size[0x3];
1151 u8 reserved_at_140[0x4c0];
1153 struct mlx5_ifc_cmd_pas_bits pas[0];
1156 struct mlx5_ifc_rq_num_bits {
1157 u8 reserved_at_0[0x8];
1161 struct mlx5_ifc_mac_address_layout_bits {
1162 u8 reserved_at_0[0x10];
1163 u8 mac_addr_47_32[0x10];
1165 u8 mac_addr_31_0[0x20];
1168 struct mlx5_ifc_vlan_layout_bits {
1169 u8 reserved_at_0[0x14];
1172 u8 reserved_at_20[0x20];
1175 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1176 u8 reserved_at_0[0xa0];
1178 u8 min_time_between_cnps[0x20];
1180 u8 reserved_at_c0[0x12];
1182 u8 reserved_at_d8[0x5];
1183 u8 cnp_802p_prio[0x3];
1185 u8 reserved_at_e0[0x720];
1188 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1189 u8 reserved_at_0[0x60];
1191 u8 reserved_at_60[0x4];
1192 u8 clamp_tgt_rate[0x1];
1193 u8 reserved_at_65[0x3];
1194 u8 clamp_tgt_rate_after_time_inc[0x1];
1195 u8 reserved_at_69[0x17];
1197 u8 reserved_at_80[0x20];
1199 u8 rpg_time_reset[0x20];
1201 u8 rpg_byte_reset[0x20];
1203 u8 rpg_threshold[0x20];
1205 u8 rpg_max_rate[0x20];
1207 u8 rpg_ai_rate[0x20];
1209 u8 rpg_hai_rate[0x20];
1213 u8 rpg_min_dec_fac[0x20];
1215 u8 rpg_min_rate[0x20];
1217 u8 reserved_at_1c0[0xe0];
1219 u8 rate_to_set_on_first_cnp[0x20];
1223 u8 dce_tcp_rtt[0x20];
1225 u8 rate_reduce_monitor_period[0x20];
1227 u8 reserved_at_320[0x20];
1229 u8 initial_alpha_value[0x20];
1231 u8 reserved_at_360[0x4a0];
1234 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1235 u8 reserved_at_0[0x80];
1237 u8 rppp_max_rps[0x20];
1239 u8 rpg_time_reset[0x20];
1241 u8 rpg_byte_reset[0x20];
1243 u8 rpg_threshold[0x20];
1245 u8 rpg_max_rate[0x20];
1247 u8 rpg_ai_rate[0x20];
1249 u8 rpg_hai_rate[0x20];
1253 u8 rpg_min_dec_fac[0x20];
1255 u8 rpg_min_rate[0x20];
1257 u8 reserved_at_1c0[0x640];
1261 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1262 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1263 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1266 struct mlx5_ifc_resize_field_select_bits {
1267 u8 resize_field_select[0x20];
1271 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1272 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1273 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1274 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1277 struct mlx5_ifc_modify_field_select_bits {
1278 u8 modify_field_select[0x20];
1281 struct mlx5_ifc_field_select_r_roce_np_bits {
1282 u8 field_select_r_roce_np[0x20];
1285 struct mlx5_ifc_field_select_r_roce_rp_bits {
1286 u8 field_select_r_roce_rp[0x20];
1290 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1291 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1292 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1293 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1294 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1295 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1296 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1297 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1298 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1299 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1302 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1303 u8 field_select_8021qaurp[0x20];
1306 struct mlx5_ifc_phys_layer_cntrs_bits {
1307 u8 time_since_last_clear_high[0x20];
1309 u8 time_since_last_clear_low[0x20];
1311 u8 symbol_errors_high[0x20];
1313 u8 symbol_errors_low[0x20];
1315 u8 sync_headers_errors_high[0x20];
1317 u8 sync_headers_errors_low[0x20];
1319 u8 edpl_bip_errors_lane0_high[0x20];
1321 u8 edpl_bip_errors_lane0_low[0x20];
1323 u8 edpl_bip_errors_lane1_high[0x20];
1325 u8 edpl_bip_errors_lane1_low[0x20];
1327 u8 edpl_bip_errors_lane2_high[0x20];
1329 u8 edpl_bip_errors_lane2_low[0x20];
1331 u8 edpl_bip_errors_lane3_high[0x20];
1333 u8 edpl_bip_errors_lane3_low[0x20];
1335 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1337 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1339 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1341 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1343 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1345 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1347 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1349 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1351 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1353 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1355 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1357 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1359 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1361 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1363 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1365 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1367 u8 rs_fec_corrected_blocks_high[0x20];
1369 u8 rs_fec_corrected_blocks_low[0x20];
1371 u8 rs_fec_uncorrectable_blocks_high[0x20];
1373 u8 rs_fec_uncorrectable_blocks_low[0x20];
1375 u8 rs_fec_no_errors_blocks_high[0x20];
1377 u8 rs_fec_no_errors_blocks_low[0x20];
1379 u8 rs_fec_single_error_blocks_high[0x20];
1381 u8 rs_fec_single_error_blocks_low[0x20];
1383 u8 rs_fec_corrected_symbols_total_high[0x20];
1385 u8 rs_fec_corrected_symbols_total_low[0x20];
1387 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1389 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1391 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1393 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1395 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1397 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1399 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1401 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1403 u8 link_down_events[0x20];
1405 u8 successful_recovery_events[0x20];
1407 u8 reserved_at_640[0x180];
1410 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1411 u8 time_since_last_clear_high[0x20];
1413 u8 time_since_last_clear_low[0x20];
1415 u8 phy_received_bits_high[0x20];
1417 u8 phy_received_bits_low[0x20];
1419 u8 phy_symbol_errors_high[0x20];
1421 u8 phy_symbol_errors_low[0x20];
1423 u8 phy_corrected_bits_high[0x20];
1425 u8 phy_corrected_bits_low[0x20];
1427 u8 phy_corrected_bits_lane0_high[0x20];
1429 u8 phy_corrected_bits_lane0_low[0x20];
1431 u8 phy_corrected_bits_lane1_high[0x20];
1433 u8 phy_corrected_bits_lane1_low[0x20];
1435 u8 phy_corrected_bits_lane2_high[0x20];
1437 u8 phy_corrected_bits_lane2_low[0x20];
1439 u8 phy_corrected_bits_lane3_high[0x20];
1441 u8 phy_corrected_bits_lane3_low[0x20];
1443 u8 reserved_at_200[0x5c0];
1446 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1447 u8 symbol_error_counter[0x10];
1449 u8 link_error_recovery_counter[0x8];
1451 u8 link_downed_counter[0x8];
1453 u8 port_rcv_errors[0x10];
1455 u8 port_rcv_remote_physical_errors[0x10];
1457 u8 port_rcv_switch_relay_errors[0x10];
1459 u8 port_xmit_discards[0x10];
1461 u8 port_xmit_constraint_errors[0x8];
1463 u8 port_rcv_constraint_errors[0x8];
1465 u8 reserved_at_70[0x8];
1467 u8 link_overrun_errors[0x8];
1469 u8 reserved_at_80[0x10];
1471 u8 vl_15_dropped[0x10];
1473 u8 reserved_at_a0[0x80];
1475 u8 port_xmit_wait[0x20];
1478 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1479 u8 transmit_queue_high[0x20];
1481 u8 transmit_queue_low[0x20];
1483 u8 reserved_at_40[0x780];
1486 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1487 u8 rx_octets_high[0x20];
1489 u8 rx_octets_low[0x20];
1491 u8 reserved_at_40[0xc0];
1493 u8 rx_frames_high[0x20];
1495 u8 rx_frames_low[0x20];
1497 u8 tx_octets_high[0x20];
1499 u8 tx_octets_low[0x20];
1501 u8 reserved_at_180[0xc0];
1503 u8 tx_frames_high[0x20];
1505 u8 tx_frames_low[0x20];
1507 u8 rx_pause_high[0x20];
1509 u8 rx_pause_low[0x20];
1511 u8 rx_pause_duration_high[0x20];
1513 u8 rx_pause_duration_low[0x20];
1515 u8 tx_pause_high[0x20];
1517 u8 tx_pause_low[0x20];
1519 u8 tx_pause_duration_high[0x20];
1521 u8 tx_pause_duration_low[0x20];
1523 u8 rx_pause_transition_high[0x20];
1525 u8 rx_pause_transition_low[0x20];
1527 u8 reserved_at_3c0[0x400];
1530 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1531 u8 port_transmit_wait_high[0x20];
1533 u8 port_transmit_wait_low[0x20];
1535 u8 reserved_at_40[0x780];
1538 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1539 u8 dot3stats_alignment_errors_high[0x20];
1541 u8 dot3stats_alignment_errors_low[0x20];
1543 u8 dot3stats_fcs_errors_high[0x20];
1545 u8 dot3stats_fcs_errors_low[0x20];
1547 u8 dot3stats_single_collision_frames_high[0x20];
1549 u8 dot3stats_single_collision_frames_low[0x20];
1551 u8 dot3stats_multiple_collision_frames_high[0x20];
1553 u8 dot3stats_multiple_collision_frames_low[0x20];
1555 u8 dot3stats_sqe_test_errors_high[0x20];
1557 u8 dot3stats_sqe_test_errors_low[0x20];
1559 u8 dot3stats_deferred_transmissions_high[0x20];
1561 u8 dot3stats_deferred_transmissions_low[0x20];
1563 u8 dot3stats_late_collisions_high[0x20];
1565 u8 dot3stats_late_collisions_low[0x20];
1567 u8 dot3stats_excessive_collisions_high[0x20];
1569 u8 dot3stats_excessive_collisions_low[0x20];
1571 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1573 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1575 u8 dot3stats_carrier_sense_errors_high[0x20];
1577 u8 dot3stats_carrier_sense_errors_low[0x20];
1579 u8 dot3stats_frame_too_longs_high[0x20];
1581 u8 dot3stats_frame_too_longs_low[0x20];
1583 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1585 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1587 u8 dot3stats_symbol_errors_high[0x20];
1589 u8 dot3stats_symbol_errors_low[0x20];
1591 u8 dot3control_in_unknown_opcodes_high[0x20];
1593 u8 dot3control_in_unknown_opcodes_low[0x20];
1595 u8 dot3in_pause_frames_high[0x20];
1597 u8 dot3in_pause_frames_low[0x20];
1599 u8 dot3out_pause_frames_high[0x20];
1601 u8 dot3out_pause_frames_low[0x20];
1603 u8 reserved_at_400[0x3c0];
1606 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1607 u8 ether_stats_drop_events_high[0x20];
1609 u8 ether_stats_drop_events_low[0x20];
1611 u8 ether_stats_octets_high[0x20];
1613 u8 ether_stats_octets_low[0x20];
1615 u8 ether_stats_pkts_high[0x20];
1617 u8 ether_stats_pkts_low[0x20];
1619 u8 ether_stats_broadcast_pkts_high[0x20];
1621 u8 ether_stats_broadcast_pkts_low[0x20];
1623 u8 ether_stats_multicast_pkts_high[0x20];
1625 u8 ether_stats_multicast_pkts_low[0x20];
1627 u8 ether_stats_crc_align_errors_high[0x20];
1629 u8 ether_stats_crc_align_errors_low[0x20];
1631 u8 ether_stats_undersize_pkts_high[0x20];
1633 u8 ether_stats_undersize_pkts_low[0x20];
1635 u8 ether_stats_oversize_pkts_high[0x20];
1637 u8 ether_stats_oversize_pkts_low[0x20];
1639 u8 ether_stats_fragments_high[0x20];
1641 u8 ether_stats_fragments_low[0x20];
1643 u8 ether_stats_jabbers_high[0x20];
1645 u8 ether_stats_jabbers_low[0x20];
1647 u8 ether_stats_collisions_high[0x20];
1649 u8 ether_stats_collisions_low[0x20];
1651 u8 ether_stats_pkts64octets_high[0x20];
1653 u8 ether_stats_pkts64octets_low[0x20];
1655 u8 ether_stats_pkts65to127octets_high[0x20];
1657 u8 ether_stats_pkts65to127octets_low[0x20];
1659 u8 ether_stats_pkts128to255octets_high[0x20];
1661 u8 ether_stats_pkts128to255octets_low[0x20];
1663 u8 ether_stats_pkts256to511octets_high[0x20];
1665 u8 ether_stats_pkts256to511octets_low[0x20];
1667 u8 ether_stats_pkts512to1023octets_high[0x20];
1669 u8 ether_stats_pkts512to1023octets_low[0x20];
1671 u8 ether_stats_pkts1024to1518octets_high[0x20];
1673 u8 ether_stats_pkts1024to1518octets_low[0x20];
1675 u8 ether_stats_pkts1519to2047octets_high[0x20];
1677 u8 ether_stats_pkts1519to2047octets_low[0x20];
1679 u8 ether_stats_pkts2048to4095octets_high[0x20];
1681 u8 ether_stats_pkts2048to4095octets_low[0x20];
1683 u8 ether_stats_pkts4096to8191octets_high[0x20];
1685 u8 ether_stats_pkts4096to8191octets_low[0x20];
1687 u8 ether_stats_pkts8192to10239octets_high[0x20];
1689 u8 ether_stats_pkts8192to10239octets_low[0x20];
1691 u8 reserved_at_540[0x280];
1694 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1695 u8 if_in_octets_high[0x20];
1697 u8 if_in_octets_low[0x20];
1699 u8 if_in_ucast_pkts_high[0x20];
1701 u8 if_in_ucast_pkts_low[0x20];
1703 u8 if_in_discards_high[0x20];
1705 u8 if_in_discards_low[0x20];
1707 u8 if_in_errors_high[0x20];
1709 u8 if_in_errors_low[0x20];
1711 u8 if_in_unknown_protos_high[0x20];
1713 u8 if_in_unknown_protos_low[0x20];
1715 u8 if_out_octets_high[0x20];
1717 u8 if_out_octets_low[0x20];
1719 u8 if_out_ucast_pkts_high[0x20];
1721 u8 if_out_ucast_pkts_low[0x20];
1723 u8 if_out_discards_high[0x20];
1725 u8 if_out_discards_low[0x20];
1727 u8 if_out_errors_high[0x20];
1729 u8 if_out_errors_low[0x20];
1731 u8 if_in_multicast_pkts_high[0x20];
1733 u8 if_in_multicast_pkts_low[0x20];
1735 u8 if_in_broadcast_pkts_high[0x20];
1737 u8 if_in_broadcast_pkts_low[0x20];
1739 u8 if_out_multicast_pkts_high[0x20];
1741 u8 if_out_multicast_pkts_low[0x20];
1743 u8 if_out_broadcast_pkts_high[0x20];
1745 u8 if_out_broadcast_pkts_low[0x20];
1747 u8 reserved_at_340[0x480];
1750 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1751 u8 a_frames_transmitted_ok_high[0x20];
1753 u8 a_frames_transmitted_ok_low[0x20];
1755 u8 a_frames_received_ok_high[0x20];
1757 u8 a_frames_received_ok_low[0x20];
1759 u8 a_frame_check_sequence_errors_high[0x20];
1761 u8 a_frame_check_sequence_errors_low[0x20];
1763 u8 a_alignment_errors_high[0x20];
1765 u8 a_alignment_errors_low[0x20];
1767 u8 a_octets_transmitted_ok_high[0x20];
1769 u8 a_octets_transmitted_ok_low[0x20];
1771 u8 a_octets_received_ok_high[0x20];
1773 u8 a_octets_received_ok_low[0x20];
1775 u8 a_multicast_frames_xmitted_ok_high[0x20];
1777 u8 a_multicast_frames_xmitted_ok_low[0x20];
1779 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1781 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1783 u8 a_multicast_frames_received_ok_high[0x20];
1785 u8 a_multicast_frames_received_ok_low[0x20];
1787 u8 a_broadcast_frames_received_ok_high[0x20];
1789 u8 a_broadcast_frames_received_ok_low[0x20];
1791 u8 a_in_range_length_errors_high[0x20];
1793 u8 a_in_range_length_errors_low[0x20];
1795 u8 a_out_of_range_length_field_high[0x20];
1797 u8 a_out_of_range_length_field_low[0x20];
1799 u8 a_frame_too_long_errors_high[0x20];
1801 u8 a_frame_too_long_errors_low[0x20];
1803 u8 a_symbol_error_during_carrier_high[0x20];
1805 u8 a_symbol_error_during_carrier_low[0x20];
1807 u8 a_mac_control_frames_transmitted_high[0x20];
1809 u8 a_mac_control_frames_transmitted_low[0x20];
1811 u8 a_mac_control_frames_received_high[0x20];
1813 u8 a_mac_control_frames_received_low[0x20];
1815 u8 a_unsupported_opcodes_received_high[0x20];
1817 u8 a_unsupported_opcodes_received_low[0x20];
1819 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1821 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1823 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1825 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1827 u8 reserved_at_4c0[0x300];
1830 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1831 u8 life_time_counter_high[0x20];
1833 u8 life_time_counter_low[0x20];
1839 u8 l0_to_recovery_eieos[0x20];
1841 u8 l0_to_recovery_ts[0x20];
1843 u8 l0_to_recovery_framing[0x20];
1845 u8 l0_to_recovery_retrain[0x20];
1847 u8 crc_error_dllp[0x20];
1849 u8 crc_error_tlp[0x20];
1851 u8 reserved_at_140[0x680];
1854 struct mlx5_ifc_cmd_inter_comp_event_bits {
1855 u8 command_completion_vector[0x20];
1857 u8 reserved_at_20[0xc0];
1860 struct mlx5_ifc_stall_vl_event_bits {
1861 u8 reserved_at_0[0x18];
1863 u8 reserved_at_19[0x3];
1866 u8 reserved_at_20[0xa0];
1869 struct mlx5_ifc_db_bf_congestion_event_bits {
1870 u8 event_subtype[0x8];
1871 u8 reserved_at_8[0x8];
1872 u8 congestion_level[0x8];
1873 u8 reserved_at_18[0x8];
1875 u8 reserved_at_20[0xa0];
1878 struct mlx5_ifc_gpio_event_bits {
1879 u8 reserved_at_0[0x60];
1881 u8 gpio_event_hi[0x20];
1883 u8 gpio_event_lo[0x20];
1885 u8 reserved_at_a0[0x40];
1888 struct mlx5_ifc_port_state_change_event_bits {
1889 u8 reserved_at_0[0x40];
1892 u8 reserved_at_44[0x1c];
1894 u8 reserved_at_60[0x80];
1897 struct mlx5_ifc_dropped_packet_logged_bits {
1898 u8 reserved_at_0[0xe0];
1902 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1903 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1906 struct mlx5_ifc_cq_error_bits {
1907 u8 reserved_at_0[0x8];
1910 u8 reserved_at_20[0x20];
1912 u8 reserved_at_40[0x18];
1915 u8 reserved_at_60[0x80];
1918 struct mlx5_ifc_rdma_page_fault_event_bits {
1919 u8 bytes_committed[0x20];
1923 u8 reserved_at_40[0x10];
1924 u8 packet_len[0x10];
1926 u8 rdma_op_len[0x20];
1930 u8 reserved_at_c0[0x5];
1937 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1938 u8 bytes_committed[0x20];
1940 u8 reserved_at_20[0x10];
1943 u8 reserved_at_40[0x10];
1946 u8 reserved_at_60[0x60];
1948 u8 reserved_at_c0[0x5];
1955 struct mlx5_ifc_qp_events_bits {
1956 u8 reserved_at_0[0xa0];
1959 u8 reserved_at_a8[0x18];
1961 u8 reserved_at_c0[0x8];
1962 u8 qpn_rqn_sqn[0x18];
1965 struct mlx5_ifc_dct_events_bits {
1966 u8 reserved_at_0[0xc0];
1968 u8 reserved_at_c0[0x8];
1969 u8 dct_number[0x18];
1972 struct mlx5_ifc_comp_event_bits {
1973 u8 reserved_at_0[0xc0];
1975 u8 reserved_at_c0[0x8];
1980 MLX5_QPC_STATE_RST = 0x0,
1981 MLX5_QPC_STATE_INIT = 0x1,
1982 MLX5_QPC_STATE_RTR = 0x2,
1983 MLX5_QPC_STATE_RTS = 0x3,
1984 MLX5_QPC_STATE_SQER = 0x4,
1985 MLX5_QPC_STATE_ERR = 0x6,
1986 MLX5_QPC_STATE_SQD = 0x7,
1987 MLX5_QPC_STATE_SUSPENDED = 0x9,
1991 MLX5_QPC_ST_RC = 0x0,
1992 MLX5_QPC_ST_UC = 0x1,
1993 MLX5_QPC_ST_UD = 0x2,
1994 MLX5_QPC_ST_XRC = 0x3,
1995 MLX5_QPC_ST_DCI = 0x5,
1996 MLX5_QPC_ST_QP0 = 0x7,
1997 MLX5_QPC_ST_QP1 = 0x8,
1998 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1999 MLX5_QPC_ST_REG_UMR = 0xc,
2003 MLX5_QPC_PM_STATE_ARMED = 0x0,
2004 MLX5_QPC_PM_STATE_REARM = 0x1,
2005 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2006 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2010 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2011 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2015 MLX5_QPC_MTU_256_BYTES = 0x1,
2016 MLX5_QPC_MTU_512_BYTES = 0x2,
2017 MLX5_QPC_MTU_1K_BYTES = 0x3,
2018 MLX5_QPC_MTU_2K_BYTES = 0x4,
2019 MLX5_QPC_MTU_4K_BYTES = 0x5,
2020 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2024 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2025 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2026 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2027 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2028 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2029 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2030 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2031 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2035 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2036 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2037 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2041 MLX5_QPC_CS_RES_DISABLE = 0x0,
2042 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2043 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2046 struct mlx5_ifc_qpc_bits {
2048 u8 lag_tx_port_affinity[0x4];
2050 u8 reserved_at_10[0x3];
2052 u8 reserved_at_15[0x7];
2053 u8 end_padding_mode[0x2];
2054 u8 reserved_at_1e[0x2];
2056 u8 wq_signature[0x1];
2057 u8 block_lb_mc[0x1];
2058 u8 atomic_like_write_en[0x1];
2059 u8 latency_sensitive[0x1];
2060 u8 reserved_at_24[0x1];
2061 u8 drain_sigerr[0x1];
2062 u8 reserved_at_26[0x2];
2066 u8 log_msg_max[0x5];
2067 u8 reserved_at_48[0x1];
2068 u8 log_rq_size[0x4];
2069 u8 log_rq_stride[0x3];
2071 u8 log_sq_size[0x4];
2072 u8 reserved_at_55[0x6];
2074 u8 ulp_stateless_offload_mode[0x4];
2076 u8 counter_set_id[0x8];
2079 u8 reserved_at_80[0x8];
2080 u8 user_index[0x18];
2082 u8 reserved_at_a0[0x3];
2083 u8 log_page_size[0x5];
2084 u8 remote_qpn[0x18];
2086 struct mlx5_ifc_ads_bits primary_address_path;
2088 struct mlx5_ifc_ads_bits secondary_address_path;
2090 u8 log_ack_req_freq[0x4];
2091 u8 reserved_at_384[0x4];
2092 u8 log_sra_max[0x3];
2093 u8 reserved_at_38b[0x2];
2094 u8 retry_count[0x3];
2096 u8 reserved_at_393[0x1];
2098 u8 cur_rnr_retry[0x3];
2099 u8 cur_retry_count[0x3];
2100 u8 reserved_at_39b[0x5];
2102 u8 reserved_at_3a0[0x20];
2104 u8 reserved_at_3c0[0x8];
2105 u8 next_send_psn[0x18];
2107 u8 reserved_at_3e0[0x8];
2110 u8 reserved_at_400[0x8];
2113 u8 reserved_at_420[0x20];
2115 u8 reserved_at_440[0x8];
2116 u8 last_acked_psn[0x18];
2118 u8 reserved_at_460[0x8];
2121 u8 reserved_at_480[0x8];
2122 u8 log_rra_max[0x3];
2123 u8 reserved_at_48b[0x1];
2124 u8 atomic_mode[0x4];
2128 u8 reserved_at_493[0x1];
2129 u8 page_offset[0x6];
2130 u8 reserved_at_49a[0x3];
2131 u8 cd_slave_receive[0x1];
2132 u8 cd_slave_send[0x1];
2135 u8 reserved_at_4a0[0x3];
2136 u8 min_rnr_nak[0x5];
2137 u8 next_rcv_psn[0x18];
2139 u8 reserved_at_4c0[0x8];
2142 u8 reserved_at_4e0[0x8];
2149 u8 reserved_at_560[0x5];
2151 u8 srqn_rmpn_xrqn[0x18];
2153 u8 reserved_at_580[0x8];
2156 u8 hw_sq_wqebb_counter[0x10];
2157 u8 sw_sq_wqebb_counter[0x10];
2159 u8 hw_rq_counter[0x20];
2161 u8 sw_rq_counter[0x20];
2163 u8 reserved_at_600[0x20];
2165 u8 reserved_at_620[0xf];
2170 u8 dc_access_key[0x40];
2172 u8 reserved_at_680[0xc0];
2175 struct mlx5_ifc_roce_addr_layout_bits {
2176 u8 source_l3_address[16][0x8];
2178 u8 reserved_at_80[0x3];
2181 u8 source_mac_47_32[0x10];
2183 u8 source_mac_31_0[0x20];
2185 u8 reserved_at_c0[0x14];
2186 u8 roce_l3_type[0x4];
2187 u8 roce_version[0x8];
2189 u8 reserved_at_e0[0x20];
2192 union mlx5_ifc_hca_cap_union_bits {
2193 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2194 struct mlx5_ifc_odp_cap_bits odp_cap;
2195 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2196 struct mlx5_ifc_roce_cap_bits roce_cap;
2197 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2198 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2199 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2200 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2201 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2202 struct mlx5_ifc_qos_cap_bits qos_cap;
2203 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2204 u8 reserved_at_0[0x8000];
2208 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2209 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2210 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2211 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2212 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2213 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2214 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2217 struct mlx5_ifc_flow_context_bits {
2218 u8 reserved_at_0[0x20];
2222 u8 reserved_at_40[0x8];
2225 u8 reserved_at_60[0x10];
2228 u8 reserved_at_80[0x8];
2229 u8 destination_list_size[0x18];
2231 u8 reserved_at_a0[0x8];
2232 u8 flow_counter_list_size[0x18];
2236 u8 modify_header_id[0x20];
2238 u8 reserved_at_100[0x100];
2240 struct mlx5_ifc_fte_match_param_bits match_value;
2242 u8 reserved_at_1200[0x600];
2244 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2248 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2249 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2252 struct mlx5_ifc_xrc_srqc_bits {
2254 u8 log_xrc_srq_size[0x4];
2255 u8 reserved_at_8[0x18];
2257 u8 wq_signature[0x1];
2259 u8 reserved_at_22[0x1];
2261 u8 basic_cyclic_rcv_wqe[0x1];
2262 u8 log_rq_stride[0x3];
2265 u8 page_offset[0x6];
2266 u8 reserved_at_46[0x2];
2269 u8 reserved_at_60[0x20];
2271 u8 user_index_equal_xrc_srqn[0x1];
2272 u8 reserved_at_81[0x1];
2273 u8 log_page_size[0x6];
2274 u8 user_index[0x18];
2276 u8 reserved_at_a0[0x20];
2278 u8 reserved_at_c0[0x8];
2284 u8 reserved_at_100[0x40];
2286 u8 db_record_addr_h[0x20];
2288 u8 db_record_addr_l[0x1e];
2289 u8 reserved_at_17e[0x2];
2291 u8 reserved_at_180[0x80];
2294 struct mlx5_ifc_traffic_counter_bits {
2300 struct mlx5_ifc_tisc_bits {
2301 u8 strict_lag_tx_port_affinity[0x1];
2302 u8 reserved_at_1[0x3];
2303 u8 lag_tx_port_affinity[0x04];
2305 u8 reserved_at_8[0x4];
2307 u8 reserved_at_10[0x10];
2309 u8 reserved_at_20[0x100];
2311 u8 reserved_at_120[0x8];
2312 u8 transport_domain[0x18];
2314 u8 reserved_at_140[0x8];
2315 u8 underlay_qpn[0x18];
2316 u8 reserved_at_160[0x3a0];
2320 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2321 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2325 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2326 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2330 MLX5_RX_HASH_FN_NONE = 0x0,
2331 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2332 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2336 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2337 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2340 struct mlx5_ifc_tirc_bits {
2341 u8 reserved_at_0[0x20];
2344 u8 reserved_at_24[0x1c];
2346 u8 reserved_at_40[0x40];
2348 u8 reserved_at_80[0x4];
2349 u8 lro_timeout_period_usecs[0x10];
2350 u8 lro_enable_mask[0x4];
2351 u8 lro_max_ip_payload_size[0x8];
2353 u8 reserved_at_a0[0x40];
2355 u8 reserved_at_e0[0x8];
2356 u8 inline_rqn[0x18];
2358 u8 rx_hash_symmetric[0x1];
2359 u8 reserved_at_101[0x1];
2360 u8 tunneled_offload_en[0x1];
2361 u8 reserved_at_103[0x5];
2362 u8 indirect_table[0x18];
2365 u8 reserved_at_124[0x2];
2366 u8 self_lb_block[0x2];
2367 u8 transport_domain[0x18];
2369 u8 rx_hash_toeplitz_key[10][0x20];
2371 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2373 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2375 u8 reserved_at_2c0[0x4c0];
2379 MLX5_SRQC_STATE_GOOD = 0x0,
2380 MLX5_SRQC_STATE_ERROR = 0x1,
2383 struct mlx5_ifc_srqc_bits {
2385 u8 log_srq_size[0x4];
2386 u8 reserved_at_8[0x18];
2388 u8 wq_signature[0x1];
2390 u8 reserved_at_22[0x1];
2392 u8 reserved_at_24[0x1];
2393 u8 log_rq_stride[0x3];
2396 u8 page_offset[0x6];
2397 u8 reserved_at_46[0x2];
2400 u8 reserved_at_60[0x20];
2402 u8 reserved_at_80[0x2];
2403 u8 log_page_size[0x6];
2404 u8 reserved_at_88[0x18];
2406 u8 reserved_at_a0[0x20];
2408 u8 reserved_at_c0[0x8];
2414 u8 reserved_at_100[0x40];
2418 u8 reserved_at_180[0x80];
2422 MLX5_SQC_STATE_RST = 0x0,
2423 MLX5_SQC_STATE_RDY = 0x1,
2424 MLX5_SQC_STATE_ERR = 0x3,
2427 struct mlx5_ifc_sqc_bits {
2431 u8 flush_in_error_en[0x1];
2432 u8 reserved_at_4[0x1];
2433 u8 min_wqe_inline_mode[0x3];
2436 u8 reserved_at_d[0x13];
2438 u8 reserved_at_20[0x8];
2439 u8 user_index[0x18];
2441 u8 reserved_at_40[0x8];
2444 u8 reserved_at_60[0x90];
2446 u8 packet_pacing_rate_limit_index[0x10];
2447 u8 tis_lst_sz[0x10];
2448 u8 reserved_at_110[0x10];
2450 u8 reserved_at_120[0x40];
2452 u8 reserved_at_160[0x8];
2455 struct mlx5_ifc_wq_bits wq;
2459 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2460 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2461 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2462 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2465 struct mlx5_ifc_scheduling_context_bits {
2466 u8 element_type[0x8];
2467 u8 reserved_at_8[0x18];
2469 u8 element_attributes[0x20];
2471 u8 parent_element_id[0x20];
2473 u8 reserved_at_60[0x40];
2477 u8 max_average_bw[0x20];
2479 u8 reserved_at_e0[0x120];
2482 struct mlx5_ifc_rqtc_bits {
2483 u8 reserved_at_0[0xa0];
2485 u8 reserved_at_a0[0x10];
2486 u8 rqt_max_size[0x10];
2488 u8 reserved_at_c0[0x10];
2489 u8 rqt_actual_size[0x10];
2491 u8 reserved_at_e0[0x6a0];
2493 struct mlx5_ifc_rq_num_bits rq_num[0];
2497 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2498 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2502 MLX5_RQC_STATE_RST = 0x0,
2503 MLX5_RQC_STATE_RDY = 0x1,
2504 MLX5_RQC_STATE_ERR = 0x3,
2507 struct mlx5_ifc_rqc_bits {
2509 u8 reserved_at_1[0x1];
2510 u8 scatter_fcs[0x1];
2512 u8 mem_rq_type[0x4];
2514 u8 reserved_at_c[0x1];
2515 u8 flush_in_error_en[0x1];
2516 u8 reserved_at_e[0x12];
2518 u8 reserved_at_20[0x8];
2519 u8 user_index[0x18];
2521 u8 reserved_at_40[0x8];
2524 u8 counter_set_id[0x8];
2525 u8 reserved_at_68[0x18];
2527 u8 reserved_at_80[0x8];
2530 u8 reserved_at_a0[0xe0];
2532 struct mlx5_ifc_wq_bits wq;
2536 MLX5_RMPC_STATE_RDY = 0x1,
2537 MLX5_RMPC_STATE_ERR = 0x3,
2540 struct mlx5_ifc_rmpc_bits {
2541 u8 reserved_at_0[0x8];
2543 u8 reserved_at_c[0x14];
2545 u8 basic_cyclic_rcv_wqe[0x1];
2546 u8 reserved_at_21[0x1f];
2548 u8 reserved_at_40[0x140];
2550 struct mlx5_ifc_wq_bits wq;
2553 struct mlx5_ifc_nic_vport_context_bits {
2554 u8 reserved_at_0[0x5];
2555 u8 min_wqe_inline_mode[0x3];
2556 u8 reserved_at_8[0x17];
2559 u8 arm_change_event[0x1];
2560 u8 reserved_at_21[0x1a];
2561 u8 event_on_mtu[0x1];
2562 u8 event_on_promisc_change[0x1];
2563 u8 event_on_vlan_change[0x1];
2564 u8 event_on_mc_address_change[0x1];
2565 u8 event_on_uc_address_change[0x1];
2567 u8 reserved_at_40[0xf0];
2571 u8 system_image_guid[0x40];
2575 u8 reserved_at_200[0x140];
2576 u8 qkey_violation_counter[0x10];
2577 u8 reserved_at_350[0x430];
2581 u8 promisc_all[0x1];
2582 u8 reserved_at_783[0x2];
2583 u8 allowed_list_type[0x3];
2584 u8 reserved_at_788[0xc];
2585 u8 allowed_list_size[0xc];
2587 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2589 u8 reserved_at_7e0[0x20];
2591 u8 current_uc_mac_address[0][0x40];
2595 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2596 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2597 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2598 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
2601 struct mlx5_ifc_mkc_bits {
2602 u8 reserved_at_0[0x1];
2604 u8 reserved_at_2[0xd];
2605 u8 small_fence_on_rdma_read_response[0x1];
2612 u8 access_mode[0x2];
2613 u8 reserved_at_18[0x8];
2618 u8 reserved_at_40[0x20];
2623 u8 reserved_at_63[0x2];
2624 u8 expected_sigerr_count[0x1];
2625 u8 reserved_at_66[0x1];
2629 u8 start_addr[0x40];
2633 u8 bsf_octword_size[0x20];
2635 u8 reserved_at_120[0x80];
2637 u8 translations_octword_size[0x20];
2639 u8 reserved_at_1c0[0x1b];
2640 u8 log_page_size[0x5];
2642 u8 reserved_at_1e0[0x20];
2645 struct mlx5_ifc_pkey_bits {
2646 u8 reserved_at_0[0x10];
2650 struct mlx5_ifc_array128_auto_bits {
2651 u8 array128_auto[16][0x8];
2654 struct mlx5_ifc_hca_vport_context_bits {
2655 u8 field_select[0x20];
2657 u8 reserved_at_20[0xe0];
2659 u8 sm_virt_aware[0x1];
2662 u8 grh_required[0x1];
2663 u8 reserved_at_104[0xc];
2664 u8 port_physical_state[0x4];
2665 u8 vport_state_policy[0x4];
2667 u8 vport_state[0x4];
2669 u8 reserved_at_120[0x20];
2671 u8 system_image_guid[0x40];
2679 u8 cap_mask1_field_select[0x20];
2683 u8 cap_mask2_field_select[0x20];
2685 u8 reserved_at_280[0x80];
2688 u8 reserved_at_310[0x4];
2689 u8 init_type_reply[0x4];
2691 u8 subnet_timeout[0x5];
2695 u8 reserved_at_334[0xc];
2697 u8 qkey_violation_counter[0x10];
2698 u8 pkey_violation_counter[0x10];
2700 u8 reserved_at_360[0xca0];
2703 struct mlx5_ifc_esw_vport_context_bits {
2704 u8 reserved_at_0[0x3];
2705 u8 vport_svlan_strip[0x1];
2706 u8 vport_cvlan_strip[0x1];
2707 u8 vport_svlan_insert[0x1];
2708 u8 vport_cvlan_insert[0x2];
2709 u8 reserved_at_8[0x18];
2711 u8 reserved_at_20[0x20];
2720 u8 reserved_at_60[0x7a0];
2724 MLX5_EQC_STATUS_OK = 0x0,
2725 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2729 MLX5_EQC_ST_ARMED = 0x9,
2730 MLX5_EQC_ST_FIRED = 0xa,
2733 struct mlx5_ifc_eqc_bits {
2735 u8 reserved_at_4[0x9];
2738 u8 reserved_at_f[0x5];
2740 u8 reserved_at_18[0x8];
2742 u8 reserved_at_20[0x20];
2744 u8 reserved_at_40[0x14];
2745 u8 page_offset[0x6];
2746 u8 reserved_at_5a[0x6];
2748 u8 reserved_at_60[0x3];
2749 u8 log_eq_size[0x5];
2752 u8 reserved_at_80[0x20];
2754 u8 reserved_at_a0[0x18];
2757 u8 reserved_at_c0[0x3];
2758 u8 log_page_size[0x5];
2759 u8 reserved_at_c8[0x18];
2761 u8 reserved_at_e0[0x60];
2763 u8 reserved_at_140[0x8];
2764 u8 consumer_counter[0x18];
2766 u8 reserved_at_160[0x8];
2767 u8 producer_counter[0x18];
2769 u8 reserved_at_180[0x80];
2773 MLX5_DCTC_STATE_ACTIVE = 0x0,
2774 MLX5_DCTC_STATE_DRAINING = 0x1,
2775 MLX5_DCTC_STATE_DRAINED = 0x2,
2779 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2780 MLX5_DCTC_CS_RES_NA = 0x1,
2781 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2785 MLX5_DCTC_MTU_256_BYTES = 0x1,
2786 MLX5_DCTC_MTU_512_BYTES = 0x2,
2787 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2788 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2789 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2792 struct mlx5_ifc_dctc_bits {
2793 u8 reserved_at_0[0x4];
2795 u8 reserved_at_8[0x18];
2797 u8 reserved_at_20[0x8];
2798 u8 user_index[0x18];
2800 u8 reserved_at_40[0x8];
2803 u8 counter_set_id[0x8];
2804 u8 atomic_mode[0x4];
2808 u8 atomic_like_write_en[0x1];
2809 u8 latency_sensitive[0x1];
2812 u8 reserved_at_73[0xd];
2814 u8 reserved_at_80[0x8];
2816 u8 reserved_at_90[0x3];
2817 u8 min_rnr_nak[0x5];
2818 u8 reserved_at_98[0x8];
2820 u8 reserved_at_a0[0x8];
2823 u8 reserved_at_c0[0x8];
2827 u8 reserved_at_e8[0x4];
2828 u8 flow_label[0x14];
2830 u8 dc_access_key[0x40];
2832 u8 reserved_at_140[0x5];
2835 u8 pkey_index[0x10];
2837 u8 reserved_at_160[0x8];
2838 u8 my_addr_index[0x8];
2839 u8 reserved_at_170[0x8];
2842 u8 dc_access_key_violation_count[0x20];
2844 u8 reserved_at_1a0[0x14];
2850 u8 reserved_at_1c0[0x40];
2854 MLX5_CQC_STATUS_OK = 0x0,
2855 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2856 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2860 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2861 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2865 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2866 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2867 MLX5_CQC_ST_FIRED = 0xa,
2871 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2872 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2873 MLX5_CQ_PERIOD_NUM_MODES
2876 struct mlx5_ifc_cqc_bits {
2878 u8 reserved_at_4[0x4];
2881 u8 reserved_at_c[0x1];
2882 u8 scqe_break_moderation_en[0x1];
2884 u8 cq_period_mode[0x2];
2885 u8 cqe_comp_en[0x1];
2886 u8 mini_cqe_res_format[0x2];
2888 u8 reserved_at_18[0x8];
2890 u8 reserved_at_20[0x20];
2892 u8 reserved_at_40[0x14];
2893 u8 page_offset[0x6];
2894 u8 reserved_at_5a[0x6];
2896 u8 reserved_at_60[0x3];
2897 u8 log_cq_size[0x5];
2900 u8 reserved_at_80[0x4];
2902 u8 cq_max_count[0x10];
2904 u8 reserved_at_a0[0x18];
2907 u8 reserved_at_c0[0x3];
2908 u8 log_page_size[0x5];
2909 u8 reserved_at_c8[0x18];
2911 u8 reserved_at_e0[0x20];
2913 u8 reserved_at_100[0x8];
2914 u8 last_notified_index[0x18];
2916 u8 reserved_at_120[0x8];
2917 u8 last_solicit_index[0x18];
2919 u8 reserved_at_140[0x8];
2920 u8 consumer_counter[0x18];
2922 u8 reserved_at_160[0x8];
2923 u8 producer_counter[0x18];
2925 u8 reserved_at_180[0x40];
2930 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2931 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2932 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2933 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2934 u8 reserved_at_0[0x800];
2937 struct mlx5_ifc_query_adapter_param_block_bits {
2938 u8 reserved_at_0[0xc0];
2940 u8 reserved_at_c0[0x8];
2941 u8 ieee_vendor_id[0x18];
2943 u8 reserved_at_e0[0x10];
2944 u8 vsd_vendor_id[0x10];
2948 u8 vsd_contd_psid[16][0x8];
2952 MLX5_XRQC_STATE_GOOD = 0x0,
2953 MLX5_XRQC_STATE_ERROR = 0x1,
2957 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2958 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
2962 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2965 struct mlx5_ifc_tag_matching_topology_context_bits {
2966 u8 log_matching_list_sz[0x4];
2967 u8 reserved_at_4[0xc];
2968 u8 append_next_index[0x10];
2970 u8 sw_phase_cnt[0x10];
2971 u8 hw_phase_cnt[0x10];
2973 u8 reserved_at_40[0x40];
2976 struct mlx5_ifc_xrqc_bits {
2979 u8 reserved_at_5[0xf];
2981 u8 reserved_at_18[0x4];
2984 u8 reserved_at_20[0x8];
2985 u8 user_index[0x18];
2987 u8 reserved_at_40[0x8];
2990 u8 reserved_at_60[0xa0];
2992 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2994 u8 reserved_at_180[0x880];
2996 struct mlx5_ifc_wq_bits wq;
2999 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3000 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3001 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3002 u8 reserved_at_0[0x20];
3005 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3006 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3007 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3008 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3009 u8 reserved_at_0[0x20];
3012 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3013 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3014 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3015 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3016 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3017 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3018 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3019 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3020 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3021 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3022 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3023 u8 reserved_at_0[0x7c0];
3026 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3027 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3028 u8 reserved_at_0[0x7c0];
3031 union mlx5_ifc_event_auto_bits {
3032 struct mlx5_ifc_comp_event_bits comp_event;
3033 struct mlx5_ifc_dct_events_bits dct_events;
3034 struct mlx5_ifc_qp_events_bits qp_events;
3035 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3036 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3037 struct mlx5_ifc_cq_error_bits cq_error;
3038 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3039 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3040 struct mlx5_ifc_gpio_event_bits gpio_event;
3041 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3042 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3043 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3044 u8 reserved_at_0[0xe0];
3047 struct mlx5_ifc_health_buffer_bits {
3048 u8 reserved_at_0[0x100];
3050 u8 assert_existptr[0x20];
3052 u8 assert_callra[0x20];
3054 u8 reserved_at_140[0x40];
3056 u8 fw_version[0x20];
3060 u8 reserved_at_1c0[0x20];
3062 u8 irisc_index[0x8];
3067 struct mlx5_ifc_register_loopback_control_bits {
3069 u8 reserved_at_1[0x7];
3071 u8 reserved_at_10[0x10];
3073 u8 reserved_at_20[0x60];
3076 struct mlx5_ifc_vport_tc_element_bits {
3077 u8 traffic_class[0x4];
3078 u8 reserved_at_4[0xc];
3079 u8 vport_number[0x10];
3082 struct mlx5_ifc_vport_element_bits {
3083 u8 reserved_at_0[0x10];
3084 u8 vport_number[0x10];
3088 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3089 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3090 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3093 struct mlx5_ifc_tsar_element_bits {
3094 u8 reserved_at_0[0x8];
3096 u8 reserved_at_10[0x10];
3100 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3101 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3104 struct mlx5_ifc_teardown_hca_out_bits {
3106 u8 reserved_at_8[0x18];
3110 u8 reserved_at_40[0x3f];
3112 u8 force_state[0x1];
3116 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3117 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3120 struct mlx5_ifc_teardown_hca_in_bits {
3122 u8 reserved_at_10[0x10];
3124 u8 reserved_at_20[0x10];
3127 u8 reserved_at_40[0x10];
3130 u8 reserved_at_60[0x20];
3133 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3135 u8 reserved_at_8[0x18];
3139 u8 reserved_at_40[0x40];
3142 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3144 u8 reserved_at_10[0x10];
3146 u8 reserved_at_20[0x10];
3149 u8 reserved_at_40[0x8];
3152 u8 reserved_at_60[0x20];
3154 u8 opt_param_mask[0x20];
3156 u8 reserved_at_a0[0x20];
3158 struct mlx5_ifc_qpc_bits qpc;
3160 u8 reserved_at_800[0x80];
3163 struct mlx5_ifc_sqd2rts_qp_out_bits {
3165 u8 reserved_at_8[0x18];
3169 u8 reserved_at_40[0x40];
3172 struct mlx5_ifc_sqd2rts_qp_in_bits {
3174 u8 reserved_at_10[0x10];
3176 u8 reserved_at_20[0x10];
3179 u8 reserved_at_40[0x8];
3182 u8 reserved_at_60[0x20];
3184 u8 opt_param_mask[0x20];
3186 u8 reserved_at_a0[0x20];
3188 struct mlx5_ifc_qpc_bits qpc;
3190 u8 reserved_at_800[0x80];
3193 struct mlx5_ifc_set_roce_address_out_bits {
3195 u8 reserved_at_8[0x18];
3199 u8 reserved_at_40[0x40];
3202 struct mlx5_ifc_set_roce_address_in_bits {
3204 u8 reserved_at_10[0x10];
3206 u8 reserved_at_20[0x10];
3209 u8 roce_address_index[0x10];
3210 u8 reserved_at_50[0x10];
3212 u8 reserved_at_60[0x20];
3214 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3217 struct mlx5_ifc_set_mad_demux_out_bits {
3219 u8 reserved_at_8[0x18];
3223 u8 reserved_at_40[0x40];
3227 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3228 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3231 struct mlx5_ifc_set_mad_demux_in_bits {
3233 u8 reserved_at_10[0x10];
3235 u8 reserved_at_20[0x10];
3238 u8 reserved_at_40[0x20];
3240 u8 reserved_at_60[0x6];
3242 u8 reserved_at_68[0x18];
3245 struct mlx5_ifc_set_l2_table_entry_out_bits {
3247 u8 reserved_at_8[0x18];
3251 u8 reserved_at_40[0x40];
3254 struct mlx5_ifc_set_l2_table_entry_in_bits {
3256 u8 reserved_at_10[0x10];
3258 u8 reserved_at_20[0x10];
3261 u8 reserved_at_40[0x60];
3263 u8 reserved_at_a0[0x8];
3264 u8 table_index[0x18];
3266 u8 reserved_at_c0[0x20];
3268 u8 reserved_at_e0[0x13];
3272 struct mlx5_ifc_mac_address_layout_bits mac_address;
3274 u8 reserved_at_140[0xc0];
3277 struct mlx5_ifc_set_issi_out_bits {
3279 u8 reserved_at_8[0x18];
3283 u8 reserved_at_40[0x40];
3286 struct mlx5_ifc_set_issi_in_bits {
3288 u8 reserved_at_10[0x10];
3290 u8 reserved_at_20[0x10];
3293 u8 reserved_at_40[0x10];
3294 u8 current_issi[0x10];
3296 u8 reserved_at_60[0x20];
3299 struct mlx5_ifc_set_hca_cap_out_bits {
3301 u8 reserved_at_8[0x18];
3305 u8 reserved_at_40[0x40];
3308 struct mlx5_ifc_set_hca_cap_in_bits {
3310 u8 reserved_at_10[0x10];
3312 u8 reserved_at_20[0x10];
3315 u8 reserved_at_40[0x40];
3317 union mlx5_ifc_hca_cap_union_bits capability;
3321 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3322 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3323 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3324 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3327 struct mlx5_ifc_set_fte_out_bits {
3329 u8 reserved_at_8[0x18];
3333 u8 reserved_at_40[0x40];
3336 struct mlx5_ifc_set_fte_in_bits {
3338 u8 reserved_at_10[0x10];
3340 u8 reserved_at_20[0x10];
3343 u8 other_vport[0x1];
3344 u8 reserved_at_41[0xf];
3345 u8 vport_number[0x10];
3347 u8 reserved_at_60[0x20];
3350 u8 reserved_at_88[0x18];
3352 u8 reserved_at_a0[0x8];
3355 u8 reserved_at_c0[0x18];
3356 u8 modify_enable_mask[0x8];
3358 u8 reserved_at_e0[0x20];
3360 u8 flow_index[0x20];
3362 u8 reserved_at_120[0xe0];
3364 struct mlx5_ifc_flow_context_bits flow_context;
3367 struct mlx5_ifc_rts2rts_qp_out_bits {
3369 u8 reserved_at_8[0x18];
3373 u8 reserved_at_40[0x40];
3376 struct mlx5_ifc_rts2rts_qp_in_bits {
3378 u8 reserved_at_10[0x10];
3380 u8 reserved_at_20[0x10];
3383 u8 reserved_at_40[0x8];
3386 u8 reserved_at_60[0x20];
3388 u8 opt_param_mask[0x20];
3390 u8 reserved_at_a0[0x20];
3392 struct mlx5_ifc_qpc_bits qpc;
3394 u8 reserved_at_800[0x80];
3397 struct mlx5_ifc_rtr2rts_qp_out_bits {
3399 u8 reserved_at_8[0x18];
3403 u8 reserved_at_40[0x40];
3406 struct mlx5_ifc_rtr2rts_qp_in_bits {
3408 u8 reserved_at_10[0x10];
3410 u8 reserved_at_20[0x10];
3413 u8 reserved_at_40[0x8];
3416 u8 reserved_at_60[0x20];
3418 u8 opt_param_mask[0x20];
3420 u8 reserved_at_a0[0x20];
3422 struct mlx5_ifc_qpc_bits qpc;
3424 u8 reserved_at_800[0x80];
3427 struct mlx5_ifc_rst2init_qp_out_bits {
3429 u8 reserved_at_8[0x18];
3433 u8 reserved_at_40[0x40];
3436 struct mlx5_ifc_rst2init_qp_in_bits {
3438 u8 reserved_at_10[0x10];
3440 u8 reserved_at_20[0x10];
3443 u8 reserved_at_40[0x8];
3446 u8 reserved_at_60[0x20];
3448 u8 opt_param_mask[0x20];
3450 u8 reserved_at_a0[0x20];
3452 struct mlx5_ifc_qpc_bits qpc;
3454 u8 reserved_at_800[0x80];
3457 struct mlx5_ifc_query_xrq_out_bits {
3459 u8 reserved_at_8[0x18];
3463 u8 reserved_at_40[0x40];
3465 struct mlx5_ifc_xrqc_bits xrq_context;
3468 struct mlx5_ifc_query_xrq_in_bits {
3470 u8 reserved_at_10[0x10];
3472 u8 reserved_at_20[0x10];
3475 u8 reserved_at_40[0x8];
3478 u8 reserved_at_60[0x20];
3481 struct mlx5_ifc_query_xrc_srq_out_bits {
3483 u8 reserved_at_8[0x18];
3487 u8 reserved_at_40[0x40];
3489 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3491 u8 reserved_at_280[0x600];
3496 struct mlx5_ifc_query_xrc_srq_in_bits {
3498 u8 reserved_at_10[0x10];
3500 u8 reserved_at_20[0x10];
3503 u8 reserved_at_40[0x8];
3506 u8 reserved_at_60[0x20];
3510 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3511 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3514 struct mlx5_ifc_query_vport_state_out_bits {
3516 u8 reserved_at_8[0x18];
3520 u8 reserved_at_40[0x20];
3522 u8 reserved_at_60[0x18];
3523 u8 admin_state[0x4];
3528 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3529 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3532 struct mlx5_ifc_query_vport_state_in_bits {
3534 u8 reserved_at_10[0x10];
3536 u8 reserved_at_20[0x10];
3539 u8 other_vport[0x1];
3540 u8 reserved_at_41[0xf];
3541 u8 vport_number[0x10];
3543 u8 reserved_at_60[0x20];
3546 struct mlx5_ifc_query_vport_counter_out_bits {
3548 u8 reserved_at_8[0x18];
3552 u8 reserved_at_40[0x40];
3554 struct mlx5_ifc_traffic_counter_bits received_errors;
3556 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3558 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3560 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3562 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3564 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3566 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3568 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3570 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3572 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3574 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3576 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3578 u8 reserved_at_680[0xa00];
3582 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3585 struct mlx5_ifc_query_vport_counter_in_bits {
3587 u8 reserved_at_10[0x10];
3589 u8 reserved_at_20[0x10];
3592 u8 other_vport[0x1];
3593 u8 reserved_at_41[0xb];
3595 u8 vport_number[0x10];
3597 u8 reserved_at_60[0x60];
3600 u8 reserved_at_c1[0x1f];
3602 u8 reserved_at_e0[0x20];
3605 struct mlx5_ifc_query_tis_out_bits {
3607 u8 reserved_at_8[0x18];
3611 u8 reserved_at_40[0x40];
3613 struct mlx5_ifc_tisc_bits tis_context;
3616 struct mlx5_ifc_query_tis_in_bits {
3618 u8 reserved_at_10[0x10];
3620 u8 reserved_at_20[0x10];
3623 u8 reserved_at_40[0x8];
3626 u8 reserved_at_60[0x20];
3629 struct mlx5_ifc_query_tir_out_bits {
3631 u8 reserved_at_8[0x18];
3635 u8 reserved_at_40[0xc0];
3637 struct mlx5_ifc_tirc_bits tir_context;
3640 struct mlx5_ifc_query_tir_in_bits {
3642 u8 reserved_at_10[0x10];
3644 u8 reserved_at_20[0x10];
3647 u8 reserved_at_40[0x8];
3650 u8 reserved_at_60[0x20];
3653 struct mlx5_ifc_query_srq_out_bits {
3655 u8 reserved_at_8[0x18];
3659 u8 reserved_at_40[0x40];
3661 struct mlx5_ifc_srqc_bits srq_context_entry;
3663 u8 reserved_at_280[0x600];
3668 struct mlx5_ifc_query_srq_in_bits {
3670 u8 reserved_at_10[0x10];
3672 u8 reserved_at_20[0x10];
3675 u8 reserved_at_40[0x8];
3678 u8 reserved_at_60[0x20];
3681 struct mlx5_ifc_query_sq_out_bits {
3683 u8 reserved_at_8[0x18];
3687 u8 reserved_at_40[0xc0];
3689 struct mlx5_ifc_sqc_bits sq_context;
3692 struct mlx5_ifc_query_sq_in_bits {
3694 u8 reserved_at_10[0x10];
3696 u8 reserved_at_20[0x10];
3699 u8 reserved_at_40[0x8];
3702 u8 reserved_at_60[0x20];
3705 struct mlx5_ifc_query_special_contexts_out_bits {
3707 u8 reserved_at_8[0x18];
3711 u8 dump_fill_mkey[0x20];
3717 u8 reserved_at_a0[0x60];
3720 struct mlx5_ifc_query_special_contexts_in_bits {
3722 u8 reserved_at_10[0x10];
3724 u8 reserved_at_20[0x10];
3727 u8 reserved_at_40[0x40];
3730 struct mlx5_ifc_query_scheduling_element_out_bits {
3732 u8 reserved_at_10[0x10];
3734 u8 reserved_at_20[0x10];
3737 u8 reserved_at_40[0xc0];
3739 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3741 u8 reserved_at_300[0x100];
3745 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3748 struct mlx5_ifc_query_scheduling_element_in_bits {
3750 u8 reserved_at_10[0x10];
3752 u8 reserved_at_20[0x10];
3755 u8 scheduling_hierarchy[0x8];
3756 u8 reserved_at_48[0x18];
3758 u8 scheduling_element_id[0x20];
3760 u8 reserved_at_80[0x180];
3763 struct mlx5_ifc_query_rqt_out_bits {
3765 u8 reserved_at_8[0x18];
3769 u8 reserved_at_40[0xc0];
3771 struct mlx5_ifc_rqtc_bits rqt_context;
3774 struct mlx5_ifc_query_rqt_in_bits {
3776 u8 reserved_at_10[0x10];
3778 u8 reserved_at_20[0x10];
3781 u8 reserved_at_40[0x8];
3784 u8 reserved_at_60[0x20];
3787 struct mlx5_ifc_query_rq_out_bits {
3789 u8 reserved_at_8[0x18];
3793 u8 reserved_at_40[0xc0];
3795 struct mlx5_ifc_rqc_bits rq_context;
3798 struct mlx5_ifc_query_rq_in_bits {
3800 u8 reserved_at_10[0x10];
3802 u8 reserved_at_20[0x10];
3805 u8 reserved_at_40[0x8];
3808 u8 reserved_at_60[0x20];
3811 struct mlx5_ifc_query_roce_address_out_bits {
3813 u8 reserved_at_8[0x18];
3817 u8 reserved_at_40[0x40];
3819 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3822 struct mlx5_ifc_query_roce_address_in_bits {
3824 u8 reserved_at_10[0x10];
3826 u8 reserved_at_20[0x10];
3829 u8 roce_address_index[0x10];
3830 u8 reserved_at_50[0x10];
3832 u8 reserved_at_60[0x20];
3835 struct mlx5_ifc_query_rmp_out_bits {
3837 u8 reserved_at_8[0x18];
3841 u8 reserved_at_40[0xc0];
3843 struct mlx5_ifc_rmpc_bits rmp_context;
3846 struct mlx5_ifc_query_rmp_in_bits {
3848 u8 reserved_at_10[0x10];
3850 u8 reserved_at_20[0x10];
3853 u8 reserved_at_40[0x8];
3856 u8 reserved_at_60[0x20];
3859 struct mlx5_ifc_query_qp_out_bits {
3861 u8 reserved_at_8[0x18];
3865 u8 reserved_at_40[0x40];
3867 u8 opt_param_mask[0x20];
3869 u8 reserved_at_a0[0x20];
3871 struct mlx5_ifc_qpc_bits qpc;
3873 u8 reserved_at_800[0x80];
3878 struct mlx5_ifc_query_qp_in_bits {
3880 u8 reserved_at_10[0x10];
3882 u8 reserved_at_20[0x10];
3885 u8 reserved_at_40[0x8];
3888 u8 reserved_at_60[0x20];
3891 struct mlx5_ifc_query_q_counter_out_bits {
3893 u8 reserved_at_8[0x18];
3897 u8 reserved_at_40[0x40];
3899 u8 rx_write_requests[0x20];
3901 u8 reserved_at_a0[0x20];
3903 u8 rx_read_requests[0x20];
3905 u8 reserved_at_e0[0x20];
3907 u8 rx_atomic_requests[0x20];
3909 u8 reserved_at_120[0x20];
3911 u8 rx_dct_connect[0x20];
3913 u8 reserved_at_160[0x20];
3915 u8 out_of_buffer[0x20];
3917 u8 reserved_at_1a0[0x20];
3919 u8 out_of_sequence[0x20];
3921 u8 reserved_at_1e0[0x20];
3923 u8 duplicate_request[0x20];
3925 u8 reserved_at_220[0x20];
3927 u8 rnr_nak_retry_err[0x20];
3929 u8 reserved_at_260[0x20];
3931 u8 packet_seq_err[0x20];
3933 u8 reserved_at_2a0[0x20];
3935 u8 implied_nak_seq_err[0x20];
3937 u8 reserved_at_2e0[0x20];
3939 u8 local_ack_timeout_err[0x20];
3941 u8 reserved_at_320[0x4e0];
3944 struct mlx5_ifc_query_q_counter_in_bits {
3946 u8 reserved_at_10[0x10];
3948 u8 reserved_at_20[0x10];
3951 u8 reserved_at_40[0x80];
3954 u8 reserved_at_c1[0x1f];
3956 u8 reserved_at_e0[0x18];
3957 u8 counter_set_id[0x8];
3960 struct mlx5_ifc_query_pages_out_bits {
3962 u8 reserved_at_8[0x18];
3966 u8 reserved_at_40[0x10];
3967 u8 function_id[0x10];
3973 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3974 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3975 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3978 struct mlx5_ifc_query_pages_in_bits {
3980 u8 reserved_at_10[0x10];
3982 u8 reserved_at_20[0x10];
3985 u8 reserved_at_40[0x10];
3986 u8 function_id[0x10];
3988 u8 reserved_at_60[0x20];
3991 struct mlx5_ifc_query_nic_vport_context_out_bits {
3993 u8 reserved_at_8[0x18];
3997 u8 reserved_at_40[0x40];
3999 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4002 struct mlx5_ifc_query_nic_vport_context_in_bits {
4004 u8 reserved_at_10[0x10];
4006 u8 reserved_at_20[0x10];
4009 u8 other_vport[0x1];
4010 u8 reserved_at_41[0xf];
4011 u8 vport_number[0x10];
4013 u8 reserved_at_60[0x5];
4014 u8 allowed_list_type[0x3];
4015 u8 reserved_at_68[0x18];
4018 struct mlx5_ifc_query_mkey_out_bits {
4020 u8 reserved_at_8[0x18];
4024 u8 reserved_at_40[0x40];
4026 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4028 u8 reserved_at_280[0x600];
4030 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4032 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4035 struct mlx5_ifc_query_mkey_in_bits {
4037 u8 reserved_at_10[0x10];
4039 u8 reserved_at_20[0x10];
4042 u8 reserved_at_40[0x8];
4043 u8 mkey_index[0x18];
4046 u8 reserved_at_61[0x1f];
4049 struct mlx5_ifc_query_mad_demux_out_bits {
4051 u8 reserved_at_8[0x18];
4055 u8 reserved_at_40[0x40];
4057 u8 mad_dumux_parameters_block[0x20];
4060 struct mlx5_ifc_query_mad_demux_in_bits {
4062 u8 reserved_at_10[0x10];
4064 u8 reserved_at_20[0x10];
4067 u8 reserved_at_40[0x40];
4070 struct mlx5_ifc_query_l2_table_entry_out_bits {
4072 u8 reserved_at_8[0x18];
4076 u8 reserved_at_40[0xa0];
4078 u8 reserved_at_e0[0x13];
4082 struct mlx5_ifc_mac_address_layout_bits mac_address;
4084 u8 reserved_at_140[0xc0];
4087 struct mlx5_ifc_query_l2_table_entry_in_bits {
4089 u8 reserved_at_10[0x10];
4091 u8 reserved_at_20[0x10];
4094 u8 reserved_at_40[0x60];
4096 u8 reserved_at_a0[0x8];
4097 u8 table_index[0x18];
4099 u8 reserved_at_c0[0x140];
4102 struct mlx5_ifc_query_issi_out_bits {
4104 u8 reserved_at_8[0x18];
4108 u8 reserved_at_40[0x10];
4109 u8 current_issi[0x10];
4111 u8 reserved_at_60[0xa0];
4113 u8 reserved_at_100[76][0x8];
4114 u8 supported_issi_dw0[0x20];
4117 struct mlx5_ifc_query_issi_in_bits {
4119 u8 reserved_at_10[0x10];
4121 u8 reserved_at_20[0x10];
4124 u8 reserved_at_40[0x40];
4127 struct mlx5_ifc_set_driver_version_out_bits {
4129 u8 reserved_0[0x18];
4132 u8 reserved_1[0x40];
4135 struct mlx5_ifc_set_driver_version_in_bits {
4137 u8 reserved_0[0x10];
4139 u8 reserved_1[0x10];
4142 u8 reserved_2[0x40];
4143 u8 driver_version[64][0x8];
4146 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4148 u8 reserved_at_8[0x18];
4152 u8 reserved_at_40[0x40];
4154 struct mlx5_ifc_pkey_bits pkey[0];
4157 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4159 u8 reserved_at_10[0x10];
4161 u8 reserved_at_20[0x10];
4164 u8 other_vport[0x1];
4165 u8 reserved_at_41[0xb];
4167 u8 vport_number[0x10];
4169 u8 reserved_at_60[0x10];
4170 u8 pkey_index[0x10];
4174 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4175 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4176 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4179 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4181 u8 reserved_at_8[0x18];
4185 u8 reserved_at_40[0x20];
4188 u8 reserved_at_70[0x10];
4190 struct mlx5_ifc_array128_auto_bits gid[0];
4193 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4195 u8 reserved_at_10[0x10];
4197 u8 reserved_at_20[0x10];
4200 u8 other_vport[0x1];
4201 u8 reserved_at_41[0xb];
4203 u8 vport_number[0x10];
4205 u8 reserved_at_60[0x10];
4209 struct mlx5_ifc_query_hca_vport_context_out_bits {
4211 u8 reserved_at_8[0x18];
4215 u8 reserved_at_40[0x40];
4217 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4220 struct mlx5_ifc_query_hca_vport_context_in_bits {
4222 u8 reserved_at_10[0x10];
4224 u8 reserved_at_20[0x10];
4227 u8 other_vport[0x1];
4228 u8 reserved_at_41[0xb];
4230 u8 vport_number[0x10];
4232 u8 reserved_at_60[0x20];
4235 struct mlx5_ifc_query_hca_cap_out_bits {
4237 u8 reserved_at_8[0x18];
4241 u8 reserved_at_40[0x40];
4243 union mlx5_ifc_hca_cap_union_bits capability;
4246 struct mlx5_ifc_query_hca_cap_in_bits {
4248 u8 reserved_at_10[0x10];
4250 u8 reserved_at_20[0x10];
4253 u8 reserved_at_40[0x40];
4256 struct mlx5_ifc_query_flow_table_out_bits {
4258 u8 reserved_at_8[0x18];
4262 u8 reserved_at_40[0x80];
4264 u8 reserved_at_c0[0x8];
4266 u8 reserved_at_d0[0x8];
4269 u8 reserved_at_e0[0x120];
4272 struct mlx5_ifc_query_flow_table_in_bits {
4274 u8 reserved_at_10[0x10];
4276 u8 reserved_at_20[0x10];
4279 u8 reserved_at_40[0x40];
4282 u8 reserved_at_88[0x18];
4284 u8 reserved_at_a0[0x8];
4287 u8 reserved_at_c0[0x140];
4290 struct mlx5_ifc_query_fte_out_bits {
4292 u8 reserved_at_8[0x18];
4296 u8 reserved_at_40[0x1c0];
4298 struct mlx5_ifc_flow_context_bits flow_context;
4301 struct mlx5_ifc_query_fte_in_bits {
4303 u8 reserved_at_10[0x10];
4305 u8 reserved_at_20[0x10];
4308 u8 reserved_at_40[0x40];
4311 u8 reserved_at_88[0x18];
4313 u8 reserved_at_a0[0x8];
4316 u8 reserved_at_c0[0x40];
4318 u8 flow_index[0x20];
4320 u8 reserved_at_120[0xe0];
4324 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4325 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4326 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4329 struct mlx5_ifc_query_flow_group_out_bits {
4331 u8 reserved_at_8[0x18];
4335 u8 reserved_at_40[0xa0];
4337 u8 start_flow_index[0x20];
4339 u8 reserved_at_100[0x20];
4341 u8 end_flow_index[0x20];
4343 u8 reserved_at_140[0xa0];
4345 u8 reserved_at_1e0[0x18];
4346 u8 match_criteria_enable[0x8];
4348 struct mlx5_ifc_fte_match_param_bits match_criteria;
4350 u8 reserved_at_1200[0xe00];
4353 struct mlx5_ifc_query_flow_group_in_bits {
4355 u8 reserved_at_10[0x10];
4357 u8 reserved_at_20[0x10];
4360 u8 reserved_at_40[0x40];
4363 u8 reserved_at_88[0x18];
4365 u8 reserved_at_a0[0x8];
4370 u8 reserved_at_e0[0x120];
4373 struct mlx5_ifc_query_flow_counter_out_bits {
4375 u8 reserved_at_8[0x18];
4379 u8 reserved_at_40[0x40];
4381 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4384 struct mlx5_ifc_query_flow_counter_in_bits {
4386 u8 reserved_at_10[0x10];
4388 u8 reserved_at_20[0x10];
4391 u8 reserved_at_40[0x80];
4394 u8 reserved_at_c1[0xf];
4395 u8 num_of_counters[0x10];
4397 u8 reserved_at_e0[0x10];
4398 u8 flow_counter_id[0x10];
4401 struct mlx5_ifc_query_esw_vport_context_out_bits {
4403 u8 reserved_at_8[0x18];
4407 u8 reserved_at_40[0x40];
4409 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4412 struct mlx5_ifc_query_esw_vport_context_in_bits {
4414 u8 reserved_at_10[0x10];
4416 u8 reserved_at_20[0x10];
4419 u8 other_vport[0x1];
4420 u8 reserved_at_41[0xf];
4421 u8 vport_number[0x10];
4423 u8 reserved_at_60[0x20];
4426 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4428 u8 reserved_at_8[0x18];
4432 u8 reserved_at_40[0x40];
4435 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4436 u8 reserved_at_0[0x1c];
4437 u8 vport_cvlan_insert[0x1];
4438 u8 vport_svlan_insert[0x1];
4439 u8 vport_cvlan_strip[0x1];
4440 u8 vport_svlan_strip[0x1];
4443 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4445 u8 reserved_at_10[0x10];
4447 u8 reserved_at_20[0x10];
4450 u8 other_vport[0x1];
4451 u8 reserved_at_41[0xf];
4452 u8 vport_number[0x10];
4454 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4456 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4459 struct mlx5_ifc_query_eq_out_bits {
4461 u8 reserved_at_8[0x18];
4465 u8 reserved_at_40[0x40];
4467 struct mlx5_ifc_eqc_bits eq_context_entry;
4469 u8 reserved_at_280[0x40];
4471 u8 event_bitmask[0x40];
4473 u8 reserved_at_300[0x580];
4478 struct mlx5_ifc_query_eq_in_bits {
4480 u8 reserved_at_10[0x10];
4482 u8 reserved_at_20[0x10];
4485 u8 reserved_at_40[0x18];
4488 u8 reserved_at_60[0x20];
4491 struct mlx5_ifc_encap_header_in_bits {
4492 u8 reserved_at_0[0x5];
4493 u8 header_type[0x3];
4494 u8 reserved_at_8[0xe];
4495 u8 encap_header_size[0xa];
4497 u8 reserved_at_20[0x10];
4498 u8 encap_header[2][0x8];
4500 u8 more_encap_header[0][0x8];
4503 struct mlx5_ifc_query_encap_header_out_bits {
4505 u8 reserved_at_8[0x18];
4509 u8 reserved_at_40[0xa0];
4511 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4514 struct mlx5_ifc_query_encap_header_in_bits {
4516 u8 reserved_at_10[0x10];
4518 u8 reserved_at_20[0x10];
4523 u8 reserved_at_60[0xa0];
4526 struct mlx5_ifc_alloc_encap_header_out_bits {
4528 u8 reserved_at_8[0x18];
4534 u8 reserved_at_60[0x20];
4537 struct mlx5_ifc_alloc_encap_header_in_bits {
4539 u8 reserved_at_10[0x10];
4541 u8 reserved_at_20[0x10];
4544 u8 reserved_at_40[0xa0];
4546 struct mlx5_ifc_encap_header_in_bits encap_header;
4549 struct mlx5_ifc_dealloc_encap_header_out_bits {
4551 u8 reserved_at_8[0x18];
4555 u8 reserved_at_40[0x40];
4558 struct mlx5_ifc_dealloc_encap_header_in_bits {
4560 u8 reserved_at_10[0x10];
4562 u8 reserved_20[0x10];
4567 u8 reserved_60[0x20];
4570 struct mlx5_ifc_set_action_in_bits {
4571 u8 action_type[0x4];
4573 u8 reserved_at_10[0x3];
4575 u8 reserved_at_18[0x3];
4581 struct mlx5_ifc_add_action_in_bits {
4582 u8 action_type[0x4];
4584 u8 reserved_at_10[0x10];
4589 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4590 struct mlx5_ifc_set_action_in_bits set_action_in;
4591 struct mlx5_ifc_add_action_in_bits add_action_in;
4592 u8 reserved_at_0[0x40];
4596 MLX5_ACTION_TYPE_SET = 0x1,
4597 MLX5_ACTION_TYPE_ADD = 0x2,
4601 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4602 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4603 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4604 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4605 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4606 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4607 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4608 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4609 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4610 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4611 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4612 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4613 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4614 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4615 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4616 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4617 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4618 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4619 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4620 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4621 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4622 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
4623 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4626 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4628 u8 reserved_at_8[0x18];
4632 u8 modify_header_id[0x20];
4634 u8 reserved_at_60[0x20];
4637 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4639 u8 reserved_at_10[0x10];
4641 u8 reserved_at_20[0x10];
4644 u8 reserved_at_40[0x20];
4647 u8 reserved_at_68[0x10];
4648 u8 num_of_actions[0x8];
4650 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4653 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4655 u8 reserved_at_8[0x18];
4659 u8 reserved_at_40[0x40];
4662 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4664 u8 reserved_at_10[0x10];
4666 u8 reserved_at_20[0x10];
4669 u8 modify_header_id[0x20];
4671 u8 reserved_at_60[0x20];
4674 struct mlx5_ifc_query_dct_out_bits {
4676 u8 reserved_at_8[0x18];
4680 u8 reserved_at_40[0x40];
4682 struct mlx5_ifc_dctc_bits dct_context_entry;
4684 u8 reserved_at_280[0x180];
4687 struct mlx5_ifc_query_dct_in_bits {
4689 u8 reserved_at_10[0x10];
4691 u8 reserved_at_20[0x10];
4694 u8 reserved_at_40[0x8];
4697 u8 reserved_at_60[0x20];
4700 struct mlx5_ifc_query_cq_out_bits {
4702 u8 reserved_at_8[0x18];
4706 u8 reserved_at_40[0x40];
4708 struct mlx5_ifc_cqc_bits cq_context;
4710 u8 reserved_at_280[0x600];
4715 struct mlx5_ifc_query_cq_in_bits {
4717 u8 reserved_at_10[0x10];
4719 u8 reserved_at_20[0x10];
4722 u8 reserved_at_40[0x8];
4725 u8 reserved_at_60[0x20];
4728 struct mlx5_ifc_query_cong_status_out_bits {
4730 u8 reserved_at_8[0x18];
4734 u8 reserved_at_40[0x20];
4738 u8 reserved_at_62[0x1e];
4741 struct mlx5_ifc_query_cong_status_in_bits {
4743 u8 reserved_at_10[0x10];
4745 u8 reserved_at_20[0x10];
4748 u8 reserved_at_40[0x18];
4750 u8 cong_protocol[0x4];
4752 u8 reserved_at_60[0x20];
4755 struct mlx5_ifc_query_cong_statistics_out_bits {
4757 u8 reserved_at_8[0x18];
4761 u8 reserved_at_40[0x40];
4763 u8 rp_cur_flows[0x20];
4767 u8 rp_cnp_ignored_high[0x20];
4769 u8 rp_cnp_ignored_low[0x20];
4771 u8 rp_cnp_handled_high[0x20];
4773 u8 rp_cnp_handled_low[0x20];
4775 u8 reserved_at_140[0x100];
4777 u8 time_stamp_high[0x20];
4779 u8 time_stamp_low[0x20];
4781 u8 accumulators_period[0x20];
4783 u8 np_ecn_marked_roce_packets_high[0x20];
4785 u8 np_ecn_marked_roce_packets_low[0x20];
4787 u8 np_cnp_sent_high[0x20];
4789 u8 np_cnp_sent_low[0x20];
4791 u8 reserved_at_320[0x560];
4794 struct mlx5_ifc_query_cong_statistics_in_bits {
4796 u8 reserved_at_10[0x10];
4798 u8 reserved_at_20[0x10];
4802 u8 reserved_at_41[0x1f];
4804 u8 reserved_at_60[0x20];
4807 struct mlx5_ifc_query_cong_params_out_bits {
4809 u8 reserved_at_8[0x18];
4813 u8 reserved_at_40[0x40];
4815 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4818 struct mlx5_ifc_query_cong_params_in_bits {
4820 u8 reserved_at_10[0x10];
4822 u8 reserved_at_20[0x10];
4825 u8 reserved_at_40[0x1c];
4826 u8 cong_protocol[0x4];
4828 u8 reserved_at_60[0x20];
4831 struct mlx5_ifc_query_adapter_out_bits {
4833 u8 reserved_at_8[0x18];
4837 u8 reserved_at_40[0x40];
4839 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4842 struct mlx5_ifc_query_adapter_in_bits {
4844 u8 reserved_at_10[0x10];
4846 u8 reserved_at_20[0x10];
4849 u8 reserved_at_40[0x40];
4852 struct mlx5_ifc_qp_2rst_out_bits {
4854 u8 reserved_at_8[0x18];
4858 u8 reserved_at_40[0x40];
4861 struct mlx5_ifc_qp_2rst_in_bits {
4863 u8 reserved_at_10[0x10];
4865 u8 reserved_at_20[0x10];
4868 u8 reserved_at_40[0x8];
4871 u8 reserved_at_60[0x20];
4874 struct mlx5_ifc_qp_2err_out_bits {
4876 u8 reserved_at_8[0x18];
4880 u8 reserved_at_40[0x40];
4883 struct mlx5_ifc_qp_2err_in_bits {
4885 u8 reserved_at_10[0x10];
4887 u8 reserved_at_20[0x10];
4890 u8 reserved_at_40[0x8];
4893 u8 reserved_at_60[0x20];
4896 struct mlx5_ifc_page_fault_resume_out_bits {
4898 u8 reserved_at_8[0x18];
4902 u8 reserved_at_40[0x40];
4905 struct mlx5_ifc_page_fault_resume_in_bits {
4907 u8 reserved_at_10[0x10];
4909 u8 reserved_at_20[0x10];
4913 u8 reserved_at_41[0x4];
4914 u8 page_fault_type[0x3];
4917 u8 reserved_at_60[0x8];
4921 struct mlx5_ifc_nop_out_bits {
4923 u8 reserved_at_8[0x18];
4927 u8 reserved_at_40[0x40];
4930 struct mlx5_ifc_nop_in_bits {
4932 u8 reserved_at_10[0x10];
4934 u8 reserved_at_20[0x10];
4937 u8 reserved_at_40[0x40];
4940 struct mlx5_ifc_modify_vport_state_out_bits {
4942 u8 reserved_at_8[0x18];
4946 u8 reserved_at_40[0x40];
4949 struct mlx5_ifc_modify_vport_state_in_bits {
4951 u8 reserved_at_10[0x10];
4953 u8 reserved_at_20[0x10];
4956 u8 other_vport[0x1];
4957 u8 reserved_at_41[0xf];
4958 u8 vport_number[0x10];
4960 u8 reserved_at_60[0x18];
4961 u8 admin_state[0x4];
4962 u8 reserved_at_7c[0x4];
4965 struct mlx5_ifc_modify_tis_out_bits {
4967 u8 reserved_at_8[0x18];
4971 u8 reserved_at_40[0x40];
4974 struct mlx5_ifc_modify_tis_bitmask_bits {
4975 u8 reserved_at_0[0x20];
4977 u8 reserved_at_20[0x1d];
4978 u8 lag_tx_port_affinity[0x1];
4979 u8 strict_lag_tx_port_affinity[0x1];
4983 struct mlx5_ifc_modify_tis_in_bits {
4985 u8 reserved_at_10[0x10];
4987 u8 reserved_at_20[0x10];
4990 u8 reserved_at_40[0x8];
4993 u8 reserved_at_60[0x20];
4995 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4997 u8 reserved_at_c0[0x40];
4999 struct mlx5_ifc_tisc_bits ctx;
5002 struct mlx5_ifc_modify_tir_bitmask_bits {
5003 u8 reserved_at_0[0x20];
5005 u8 reserved_at_20[0x1b];
5007 u8 reserved_at_3c[0x1];
5009 u8 reserved_at_3e[0x1];
5013 struct mlx5_ifc_modify_tir_out_bits {
5015 u8 reserved_at_8[0x18];
5019 u8 reserved_at_40[0x40];
5022 struct mlx5_ifc_modify_tir_in_bits {
5024 u8 reserved_at_10[0x10];
5026 u8 reserved_at_20[0x10];
5029 u8 reserved_at_40[0x8];
5032 u8 reserved_at_60[0x20];
5034 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5036 u8 reserved_at_c0[0x40];
5038 struct mlx5_ifc_tirc_bits ctx;
5041 struct mlx5_ifc_modify_sq_out_bits {
5043 u8 reserved_at_8[0x18];
5047 u8 reserved_at_40[0x40];
5050 struct mlx5_ifc_modify_sq_in_bits {
5052 u8 reserved_at_10[0x10];
5054 u8 reserved_at_20[0x10];
5058 u8 reserved_at_44[0x4];
5061 u8 reserved_at_60[0x20];
5063 u8 modify_bitmask[0x40];
5065 u8 reserved_at_c0[0x40];
5067 struct mlx5_ifc_sqc_bits ctx;
5070 struct mlx5_ifc_modify_scheduling_element_out_bits {
5072 u8 reserved_at_8[0x18];
5076 u8 reserved_at_40[0x1c0];
5080 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5081 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5084 struct mlx5_ifc_modify_scheduling_element_in_bits {
5086 u8 reserved_at_10[0x10];
5088 u8 reserved_at_20[0x10];
5091 u8 scheduling_hierarchy[0x8];
5092 u8 reserved_at_48[0x18];
5094 u8 scheduling_element_id[0x20];
5096 u8 reserved_at_80[0x20];
5098 u8 modify_bitmask[0x20];
5100 u8 reserved_at_c0[0x40];
5102 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5104 u8 reserved_at_300[0x100];
5107 struct mlx5_ifc_modify_rqt_out_bits {
5109 u8 reserved_at_8[0x18];
5113 u8 reserved_at_40[0x40];
5116 struct mlx5_ifc_rqt_bitmask_bits {
5117 u8 reserved_at_0[0x20];
5119 u8 reserved_at_20[0x1f];
5123 struct mlx5_ifc_modify_rqt_in_bits {
5125 u8 reserved_at_10[0x10];
5127 u8 reserved_at_20[0x10];
5130 u8 reserved_at_40[0x8];
5133 u8 reserved_at_60[0x20];
5135 struct mlx5_ifc_rqt_bitmask_bits bitmask;
5137 u8 reserved_at_c0[0x40];
5139 struct mlx5_ifc_rqtc_bits ctx;
5142 struct mlx5_ifc_modify_rq_out_bits {
5144 u8 reserved_at_8[0x18];
5148 u8 reserved_at_40[0x40];
5152 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5153 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5154 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5157 struct mlx5_ifc_modify_rq_in_bits {
5159 u8 reserved_at_10[0x10];
5161 u8 reserved_at_20[0x10];
5165 u8 reserved_at_44[0x4];
5168 u8 reserved_at_60[0x20];
5170 u8 modify_bitmask[0x40];
5172 u8 reserved_at_c0[0x40];
5174 struct mlx5_ifc_rqc_bits ctx;
5177 struct mlx5_ifc_modify_rmp_out_bits {
5179 u8 reserved_at_8[0x18];
5183 u8 reserved_at_40[0x40];
5186 struct mlx5_ifc_rmp_bitmask_bits {
5187 u8 reserved_at_0[0x20];
5189 u8 reserved_at_20[0x1f];
5193 struct mlx5_ifc_modify_rmp_in_bits {
5195 u8 reserved_at_10[0x10];
5197 u8 reserved_at_20[0x10];
5201 u8 reserved_at_44[0x4];
5204 u8 reserved_at_60[0x20];
5206 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5208 u8 reserved_at_c0[0x40];
5210 struct mlx5_ifc_rmpc_bits ctx;
5213 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5215 u8 reserved_at_8[0x18];
5219 u8 reserved_at_40[0x40];
5222 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5223 u8 reserved_at_0[0x16];
5228 u8 change_event[0x1];
5230 u8 permanent_address[0x1];
5231 u8 addresses_list[0x1];
5233 u8 reserved_at_1f[0x1];
5236 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5238 u8 reserved_at_10[0x10];
5240 u8 reserved_at_20[0x10];
5243 u8 other_vport[0x1];
5244 u8 reserved_at_41[0xf];
5245 u8 vport_number[0x10];
5247 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5249 u8 reserved_at_80[0x780];
5251 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5254 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5256 u8 reserved_at_8[0x18];
5260 u8 reserved_at_40[0x40];
5263 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5265 u8 reserved_at_10[0x10];
5267 u8 reserved_at_20[0x10];
5270 u8 other_vport[0x1];
5271 u8 reserved_at_41[0xb];
5273 u8 vport_number[0x10];
5275 u8 reserved_at_60[0x20];
5277 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5280 struct mlx5_ifc_modify_cq_out_bits {
5282 u8 reserved_at_8[0x18];
5286 u8 reserved_at_40[0x40];
5290 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5291 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5294 struct mlx5_ifc_modify_cq_in_bits {
5296 u8 reserved_at_10[0x10];
5298 u8 reserved_at_20[0x10];
5301 u8 reserved_at_40[0x8];
5304 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5306 struct mlx5_ifc_cqc_bits cq_context;
5308 u8 reserved_at_280[0x600];
5313 struct mlx5_ifc_modify_cong_status_out_bits {
5315 u8 reserved_at_8[0x18];
5319 u8 reserved_at_40[0x40];
5322 struct mlx5_ifc_modify_cong_status_in_bits {
5324 u8 reserved_at_10[0x10];
5326 u8 reserved_at_20[0x10];
5329 u8 reserved_at_40[0x18];
5331 u8 cong_protocol[0x4];
5335 u8 reserved_at_62[0x1e];
5338 struct mlx5_ifc_modify_cong_params_out_bits {
5340 u8 reserved_at_8[0x18];
5344 u8 reserved_at_40[0x40];
5347 struct mlx5_ifc_modify_cong_params_in_bits {
5349 u8 reserved_at_10[0x10];
5351 u8 reserved_at_20[0x10];
5354 u8 reserved_at_40[0x1c];
5355 u8 cong_protocol[0x4];
5357 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5359 u8 reserved_at_80[0x80];
5361 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5364 struct mlx5_ifc_manage_pages_out_bits {
5366 u8 reserved_at_8[0x18];
5370 u8 output_num_entries[0x20];
5372 u8 reserved_at_60[0x20];
5378 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5379 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5380 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5383 struct mlx5_ifc_manage_pages_in_bits {
5385 u8 reserved_at_10[0x10];
5387 u8 reserved_at_20[0x10];
5390 u8 reserved_at_40[0x10];
5391 u8 function_id[0x10];
5393 u8 input_num_entries[0x20];
5398 struct mlx5_ifc_mad_ifc_out_bits {
5400 u8 reserved_at_8[0x18];
5404 u8 reserved_at_40[0x40];
5406 u8 response_mad_packet[256][0x8];
5409 struct mlx5_ifc_mad_ifc_in_bits {
5411 u8 reserved_at_10[0x10];
5413 u8 reserved_at_20[0x10];
5416 u8 remote_lid[0x10];
5417 u8 reserved_at_50[0x8];
5420 u8 reserved_at_60[0x20];
5425 struct mlx5_ifc_init_hca_out_bits {
5427 u8 reserved_at_8[0x18];
5431 u8 reserved_at_40[0x40];
5434 struct mlx5_ifc_init_hca_in_bits {
5436 u8 reserved_at_10[0x10];
5438 u8 reserved_at_20[0x10];
5441 u8 reserved_at_40[0x40];
5444 struct mlx5_ifc_init2rtr_qp_out_bits {
5446 u8 reserved_at_8[0x18];
5450 u8 reserved_at_40[0x40];
5453 struct mlx5_ifc_init2rtr_qp_in_bits {
5455 u8 reserved_at_10[0x10];
5457 u8 reserved_at_20[0x10];
5460 u8 reserved_at_40[0x8];
5463 u8 reserved_at_60[0x20];
5465 u8 opt_param_mask[0x20];
5467 u8 reserved_at_a0[0x20];
5469 struct mlx5_ifc_qpc_bits qpc;
5471 u8 reserved_at_800[0x80];
5474 struct mlx5_ifc_init2init_qp_out_bits {
5476 u8 reserved_at_8[0x18];
5480 u8 reserved_at_40[0x40];
5483 struct mlx5_ifc_init2init_qp_in_bits {
5485 u8 reserved_at_10[0x10];
5487 u8 reserved_at_20[0x10];
5490 u8 reserved_at_40[0x8];
5493 u8 reserved_at_60[0x20];
5495 u8 opt_param_mask[0x20];
5497 u8 reserved_at_a0[0x20];
5499 struct mlx5_ifc_qpc_bits qpc;
5501 u8 reserved_at_800[0x80];
5504 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5506 u8 reserved_at_8[0x18];
5510 u8 reserved_at_40[0x40];
5512 u8 packet_headers_log[128][0x8];
5514 u8 packet_syndrome[64][0x8];
5517 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5519 u8 reserved_at_10[0x10];
5521 u8 reserved_at_20[0x10];
5524 u8 reserved_at_40[0x40];
5527 struct mlx5_ifc_gen_eqe_in_bits {
5529 u8 reserved_at_10[0x10];
5531 u8 reserved_at_20[0x10];
5534 u8 reserved_at_40[0x18];
5537 u8 reserved_at_60[0x20];
5542 struct mlx5_ifc_gen_eq_out_bits {
5544 u8 reserved_at_8[0x18];
5548 u8 reserved_at_40[0x40];
5551 struct mlx5_ifc_enable_hca_out_bits {
5553 u8 reserved_at_8[0x18];
5557 u8 reserved_at_40[0x20];
5560 struct mlx5_ifc_enable_hca_in_bits {
5562 u8 reserved_at_10[0x10];
5564 u8 reserved_at_20[0x10];
5567 u8 reserved_at_40[0x10];
5568 u8 function_id[0x10];
5570 u8 reserved_at_60[0x20];
5573 struct mlx5_ifc_drain_dct_out_bits {
5575 u8 reserved_at_8[0x18];
5579 u8 reserved_at_40[0x40];
5582 struct mlx5_ifc_drain_dct_in_bits {
5584 u8 reserved_at_10[0x10];
5586 u8 reserved_at_20[0x10];
5589 u8 reserved_at_40[0x8];
5592 u8 reserved_at_60[0x20];
5595 struct mlx5_ifc_disable_hca_out_bits {
5597 u8 reserved_at_8[0x18];
5601 u8 reserved_at_40[0x20];
5604 struct mlx5_ifc_disable_hca_in_bits {
5606 u8 reserved_at_10[0x10];
5608 u8 reserved_at_20[0x10];
5611 u8 reserved_at_40[0x10];
5612 u8 function_id[0x10];
5614 u8 reserved_at_60[0x20];
5617 struct mlx5_ifc_detach_from_mcg_out_bits {
5619 u8 reserved_at_8[0x18];
5623 u8 reserved_at_40[0x40];
5626 struct mlx5_ifc_detach_from_mcg_in_bits {
5628 u8 reserved_at_10[0x10];
5630 u8 reserved_at_20[0x10];
5633 u8 reserved_at_40[0x8];
5636 u8 reserved_at_60[0x20];
5638 u8 multicast_gid[16][0x8];
5641 struct mlx5_ifc_destroy_xrq_out_bits {
5643 u8 reserved_at_8[0x18];
5647 u8 reserved_at_40[0x40];
5650 struct mlx5_ifc_destroy_xrq_in_bits {
5652 u8 reserved_at_10[0x10];
5654 u8 reserved_at_20[0x10];
5657 u8 reserved_at_40[0x8];
5660 u8 reserved_at_60[0x20];
5663 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5665 u8 reserved_at_8[0x18];
5669 u8 reserved_at_40[0x40];
5672 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5674 u8 reserved_at_10[0x10];
5676 u8 reserved_at_20[0x10];
5679 u8 reserved_at_40[0x8];
5682 u8 reserved_at_60[0x20];
5685 struct mlx5_ifc_destroy_tis_out_bits {
5687 u8 reserved_at_8[0x18];
5691 u8 reserved_at_40[0x40];
5694 struct mlx5_ifc_destroy_tis_in_bits {
5696 u8 reserved_at_10[0x10];
5698 u8 reserved_at_20[0x10];
5701 u8 reserved_at_40[0x8];
5704 u8 reserved_at_60[0x20];
5707 struct mlx5_ifc_destroy_tir_out_bits {
5709 u8 reserved_at_8[0x18];
5713 u8 reserved_at_40[0x40];
5716 struct mlx5_ifc_destroy_tir_in_bits {
5718 u8 reserved_at_10[0x10];
5720 u8 reserved_at_20[0x10];
5723 u8 reserved_at_40[0x8];
5726 u8 reserved_at_60[0x20];
5729 struct mlx5_ifc_destroy_srq_out_bits {
5731 u8 reserved_at_8[0x18];
5735 u8 reserved_at_40[0x40];
5738 struct mlx5_ifc_destroy_srq_in_bits {
5740 u8 reserved_at_10[0x10];
5742 u8 reserved_at_20[0x10];
5745 u8 reserved_at_40[0x8];
5748 u8 reserved_at_60[0x20];
5751 struct mlx5_ifc_destroy_sq_out_bits {
5753 u8 reserved_at_8[0x18];
5757 u8 reserved_at_40[0x40];
5760 struct mlx5_ifc_destroy_sq_in_bits {
5762 u8 reserved_at_10[0x10];
5764 u8 reserved_at_20[0x10];
5767 u8 reserved_at_40[0x8];
5770 u8 reserved_at_60[0x20];
5773 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5775 u8 reserved_at_8[0x18];
5779 u8 reserved_at_40[0x1c0];
5782 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5784 u8 reserved_at_10[0x10];
5786 u8 reserved_at_20[0x10];
5789 u8 scheduling_hierarchy[0x8];
5790 u8 reserved_at_48[0x18];
5792 u8 scheduling_element_id[0x20];
5794 u8 reserved_at_80[0x180];
5797 struct mlx5_ifc_destroy_rqt_out_bits {
5799 u8 reserved_at_8[0x18];
5803 u8 reserved_at_40[0x40];
5806 struct mlx5_ifc_destroy_rqt_in_bits {
5808 u8 reserved_at_10[0x10];
5810 u8 reserved_at_20[0x10];
5813 u8 reserved_at_40[0x8];
5816 u8 reserved_at_60[0x20];
5819 struct mlx5_ifc_destroy_rq_out_bits {
5821 u8 reserved_at_8[0x18];
5825 u8 reserved_at_40[0x40];
5828 struct mlx5_ifc_destroy_rq_in_bits {
5830 u8 reserved_at_10[0x10];
5832 u8 reserved_at_20[0x10];
5835 u8 reserved_at_40[0x8];
5838 u8 reserved_at_60[0x20];
5841 struct mlx5_ifc_destroy_rmp_out_bits {
5843 u8 reserved_at_8[0x18];
5847 u8 reserved_at_40[0x40];
5850 struct mlx5_ifc_destroy_rmp_in_bits {
5852 u8 reserved_at_10[0x10];
5854 u8 reserved_at_20[0x10];
5857 u8 reserved_at_40[0x8];
5860 u8 reserved_at_60[0x20];
5863 struct mlx5_ifc_destroy_qp_out_bits {
5865 u8 reserved_at_8[0x18];
5869 u8 reserved_at_40[0x40];
5872 struct mlx5_ifc_destroy_qp_in_bits {
5874 u8 reserved_at_10[0x10];
5876 u8 reserved_at_20[0x10];
5879 u8 reserved_at_40[0x8];
5882 u8 reserved_at_60[0x20];
5885 struct mlx5_ifc_destroy_psv_out_bits {
5887 u8 reserved_at_8[0x18];
5891 u8 reserved_at_40[0x40];
5894 struct mlx5_ifc_destroy_psv_in_bits {
5896 u8 reserved_at_10[0x10];
5898 u8 reserved_at_20[0x10];
5901 u8 reserved_at_40[0x8];
5904 u8 reserved_at_60[0x20];
5907 struct mlx5_ifc_destroy_mkey_out_bits {
5909 u8 reserved_at_8[0x18];
5913 u8 reserved_at_40[0x40];
5916 struct mlx5_ifc_destroy_mkey_in_bits {
5918 u8 reserved_at_10[0x10];
5920 u8 reserved_at_20[0x10];
5923 u8 reserved_at_40[0x8];
5924 u8 mkey_index[0x18];
5926 u8 reserved_at_60[0x20];
5929 struct mlx5_ifc_destroy_flow_table_out_bits {
5931 u8 reserved_at_8[0x18];
5935 u8 reserved_at_40[0x40];
5938 struct mlx5_ifc_destroy_flow_table_in_bits {
5940 u8 reserved_at_10[0x10];
5942 u8 reserved_at_20[0x10];
5945 u8 other_vport[0x1];
5946 u8 reserved_at_41[0xf];
5947 u8 vport_number[0x10];
5949 u8 reserved_at_60[0x20];
5952 u8 reserved_at_88[0x18];
5954 u8 reserved_at_a0[0x8];
5957 u8 reserved_at_c0[0x140];
5960 struct mlx5_ifc_destroy_flow_group_out_bits {
5962 u8 reserved_at_8[0x18];
5966 u8 reserved_at_40[0x40];
5969 struct mlx5_ifc_destroy_flow_group_in_bits {
5971 u8 reserved_at_10[0x10];
5973 u8 reserved_at_20[0x10];
5976 u8 other_vport[0x1];
5977 u8 reserved_at_41[0xf];
5978 u8 vport_number[0x10];
5980 u8 reserved_at_60[0x20];
5983 u8 reserved_at_88[0x18];
5985 u8 reserved_at_a0[0x8];
5990 u8 reserved_at_e0[0x120];
5993 struct mlx5_ifc_destroy_eq_out_bits {
5995 u8 reserved_at_8[0x18];
5999 u8 reserved_at_40[0x40];
6002 struct mlx5_ifc_destroy_eq_in_bits {
6004 u8 reserved_at_10[0x10];
6006 u8 reserved_at_20[0x10];
6009 u8 reserved_at_40[0x18];
6012 u8 reserved_at_60[0x20];
6015 struct mlx5_ifc_destroy_dct_out_bits {
6017 u8 reserved_at_8[0x18];
6021 u8 reserved_at_40[0x40];
6024 struct mlx5_ifc_destroy_dct_in_bits {
6026 u8 reserved_at_10[0x10];
6028 u8 reserved_at_20[0x10];
6031 u8 reserved_at_40[0x8];
6034 u8 reserved_at_60[0x20];
6037 struct mlx5_ifc_destroy_cq_out_bits {
6039 u8 reserved_at_8[0x18];
6043 u8 reserved_at_40[0x40];
6046 struct mlx5_ifc_destroy_cq_in_bits {
6048 u8 reserved_at_10[0x10];
6050 u8 reserved_at_20[0x10];
6053 u8 reserved_at_40[0x8];
6056 u8 reserved_at_60[0x20];
6059 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6061 u8 reserved_at_8[0x18];
6065 u8 reserved_at_40[0x40];
6068 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6070 u8 reserved_at_10[0x10];
6072 u8 reserved_at_20[0x10];
6075 u8 reserved_at_40[0x20];
6077 u8 reserved_at_60[0x10];
6078 u8 vxlan_udp_port[0x10];
6081 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6083 u8 reserved_at_8[0x18];
6087 u8 reserved_at_40[0x40];
6090 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6092 u8 reserved_at_10[0x10];
6094 u8 reserved_at_20[0x10];
6097 u8 reserved_at_40[0x60];
6099 u8 reserved_at_a0[0x8];
6100 u8 table_index[0x18];
6102 u8 reserved_at_c0[0x140];
6105 struct mlx5_ifc_delete_fte_out_bits {
6107 u8 reserved_at_8[0x18];
6111 u8 reserved_at_40[0x40];
6114 struct mlx5_ifc_delete_fte_in_bits {
6116 u8 reserved_at_10[0x10];
6118 u8 reserved_at_20[0x10];
6121 u8 other_vport[0x1];
6122 u8 reserved_at_41[0xf];
6123 u8 vport_number[0x10];
6125 u8 reserved_at_60[0x20];
6128 u8 reserved_at_88[0x18];
6130 u8 reserved_at_a0[0x8];
6133 u8 reserved_at_c0[0x40];
6135 u8 flow_index[0x20];
6137 u8 reserved_at_120[0xe0];
6140 struct mlx5_ifc_dealloc_xrcd_out_bits {
6142 u8 reserved_at_8[0x18];
6146 u8 reserved_at_40[0x40];
6149 struct mlx5_ifc_dealloc_xrcd_in_bits {
6151 u8 reserved_at_10[0x10];
6153 u8 reserved_at_20[0x10];
6156 u8 reserved_at_40[0x8];
6159 u8 reserved_at_60[0x20];
6162 struct mlx5_ifc_dealloc_uar_out_bits {
6164 u8 reserved_at_8[0x18];
6168 u8 reserved_at_40[0x40];
6171 struct mlx5_ifc_dealloc_uar_in_bits {
6173 u8 reserved_at_10[0x10];
6175 u8 reserved_at_20[0x10];
6178 u8 reserved_at_40[0x8];
6181 u8 reserved_at_60[0x20];
6184 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6186 u8 reserved_at_8[0x18];
6190 u8 reserved_at_40[0x40];
6193 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6195 u8 reserved_at_10[0x10];
6197 u8 reserved_at_20[0x10];
6200 u8 reserved_at_40[0x8];
6201 u8 transport_domain[0x18];
6203 u8 reserved_at_60[0x20];
6206 struct mlx5_ifc_dealloc_q_counter_out_bits {
6208 u8 reserved_at_8[0x18];
6212 u8 reserved_at_40[0x40];
6215 struct mlx5_ifc_dealloc_q_counter_in_bits {
6217 u8 reserved_at_10[0x10];
6219 u8 reserved_at_20[0x10];
6222 u8 reserved_at_40[0x18];
6223 u8 counter_set_id[0x8];
6225 u8 reserved_at_60[0x20];
6228 struct mlx5_ifc_dealloc_pd_out_bits {
6230 u8 reserved_at_8[0x18];
6234 u8 reserved_at_40[0x40];
6237 struct mlx5_ifc_dealloc_pd_in_bits {
6239 u8 reserved_at_10[0x10];
6241 u8 reserved_at_20[0x10];
6244 u8 reserved_at_40[0x8];
6247 u8 reserved_at_60[0x20];
6250 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6252 u8 reserved_at_8[0x18];
6256 u8 reserved_at_40[0x40];
6259 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6261 u8 reserved_at_10[0x10];
6263 u8 reserved_at_20[0x10];
6266 u8 reserved_at_40[0x10];
6267 u8 flow_counter_id[0x10];
6269 u8 reserved_at_60[0x20];
6272 struct mlx5_ifc_create_xrq_out_bits {
6274 u8 reserved_at_8[0x18];
6278 u8 reserved_at_40[0x8];
6281 u8 reserved_at_60[0x20];
6284 struct mlx5_ifc_create_xrq_in_bits {
6286 u8 reserved_at_10[0x10];
6288 u8 reserved_at_20[0x10];
6291 u8 reserved_at_40[0x40];
6293 struct mlx5_ifc_xrqc_bits xrq_context;
6296 struct mlx5_ifc_create_xrc_srq_out_bits {
6298 u8 reserved_at_8[0x18];
6302 u8 reserved_at_40[0x8];
6305 u8 reserved_at_60[0x20];
6308 struct mlx5_ifc_create_xrc_srq_in_bits {
6310 u8 reserved_at_10[0x10];
6312 u8 reserved_at_20[0x10];
6315 u8 reserved_at_40[0x40];
6317 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6319 u8 reserved_at_280[0x600];
6324 struct mlx5_ifc_create_tis_out_bits {
6326 u8 reserved_at_8[0x18];
6330 u8 reserved_at_40[0x8];
6333 u8 reserved_at_60[0x20];
6336 struct mlx5_ifc_create_tis_in_bits {
6338 u8 reserved_at_10[0x10];
6340 u8 reserved_at_20[0x10];
6343 u8 reserved_at_40[0xc0];
6345 struct mlx5_ifc_tisc_bits ctx;
6348 struct mlx5_ifc_create_tir_out_bits {
6350 u8 reserved_at_8[0x18];
6354 u8 reserved_at_40[0x8];
6357 u8 reserved_at_60[0x20];
6360 struct mlx5_ifc_create_tir_in_bits {
6362 u8 reserved_at_10[0x10];
6364 u8 reserved_at_20[0x10];
6367 u8 reserved_at_40[0xc0];
6369 struct mlx5_ifc_tirc_bits ctx;
6372 struct mlx5_ifc_create_srq_out_bits {
6374 u8 reserved_at_8[0x18];
6378 u8 reserved_at_40[0x8];
6381 u8 reserved_at_60[0x20];
6384 struct mlx5_ifc_create_srq_in_bits {
6386 u8 reserved_at_10[0x10];
6388 u8 reserved_at_20[0x10];
6391 u8 reserved_at_40[0x40];
6393 struct mlx5_ifc_srqc_bits srq_context_entry;
6395 u8 reserved_at_280[0x600];
6400 struct mlx5_ifc_create_sq_out_bits {
6402 u8 reserved_at_8[0x18];
6406 u8 reserved_at_40[0x8];
6409 u8 reserved_at_60[0x20];
6412 struct mlx5_ifc_create_sq_in_bits {
6414 u8 reserved_at_10[0x10];
6416 u8 reserved_at_20[0x10];
6419 u8 reserved_at_40[0xc0];
6421 struct mlx5_ifc_sqc_bits ctx;
6424 struct mlx5_ifc_create_scheduling_element_out_bits {
6426 u8 reserved_at_8[0x18];
6430 u8 reserved_at_40[0x40];
6432 u8 scheduling_element_id[0x20];
6434 u8 reserved_at_a0[0x160];
6437 struct mlx5_ifc_create_scheduling_element_in_bits {
6439 u8 reserved_at_10[0x10];
6441 u8 reserved_at_20[0x10];
6444 u8 scheduling_hierarchy[0x8];
6445 u8 reserved_at_48[0x18];
6447 u8 reserved_at_60[0xa0];
6449 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6451 u8 reserved_at_300[0x100];
6454 struct mlx5_ifc_create_rqt_out_bits {
6456 u8 reserved_at_8[0x18];
6460 u8 reserved_at_40[0x8];
6463 u8 reserved_at_60[0x20];
6466 struct mlx5_ifc_create_rqt_in_bits {
6468 u8 reserved_at_10[0x10];
6470 u8 reserved_at_20[0x10];
6473 u8 reserved_at_40[0xc0];
6475 struct mlx5_ifc_rqtc_bits rqt_context;
6478 struct mlx5_ifc_create_rq_out_bits {
6480 u8 reserved_at_8[0x18];
6484 u8 reserved_at_40[0x8];
6487 u8 reserved_at_60[0x20];
6490 struct mlx5_ifc_create_rq_in_bits {
6492 u8 reserved_at_10[0x10];
6494 u8 reserved_at_20[0x10];
6497 u8 reserved_at_40[0xc0];
6499 struct mlx5_ifc_rqc_bits ctx;
6502 struct mlx5_ifc_create_rmp_out_bits {
6504 u8 reserved_at_8[0x18];
6508 u8 reserved_at_40[0x8];
6511 u8 reserved_at_60[0x20];
6514 struct mlx5_ifc_create_rmp_in_bits {
6516 u8 reserved_at_10[0x10];
6518 u8 reserved_at_20[0x10];
6521 u8 reserved_at_40[0xc0];
6523 struct mlx5_ifc_rmpc_bits ctx;
6526 struct mlx5_ifc_create_qp_out_bits {
6528 u8 reserved_at_8[0x18];
6532 u8 reserved_at_40[0x8];
6535 u8 reserved_at_60[0x20];
6538 struct mlx5_ifc_create_qp_in_bits {
6540 u8 reserved_at_10[0x10];
6542 u8 reserved_at_20[0x10];
6545 u8 reserved_at_40[0x40];
6547 u8 opt_param_mask[0x20];
6549 u8 reserved_at_a0[0x20];
6551 struct mlx5_ifc_qpc_bits qpc;
6553 u8 reserved_at_800[0x80];
6558 struct mlx5_ifc_create_psv_out_bits {
6560 u8 reserved_at_8[0x18];
6564 u8 reserved_at_40[0x40];
6566 u8 reserved_at_80[0x8];
6567 u8 psv0_index[0x18];
6569 u8 reserved_at_a0[0x8];
6570 u8 psv1_index[0x18];
6572 u8 reserved_at_c0[0x8];
6573 u8 psv2_index[0x18];
6575 u8 reserved_at_e0[0x8];
6576 u8 psv3_index[0x18];
6579 struct mlx5_ifc_create_psv_in_bits {
6581 u8 reserved_at_10[0x10];
6583 u8 reserved_at_20[0x10];
6587 u8 reserved_at_44[0x4];
6590 u8 reserved_at_60[0x20];
6593 struct mlx5_ifc_create_mkey_out_bits {
6595 u8 reserved_at_8[0x18];
6599 u8 reserved_at_40[0x8];
6600 u8 mkey_index[0x18];
6602 u8 reserved_at_60[0x20];
6605 struct mlx5_ifc_create_mkey_in_bits {
6607 u8 reserved_at_10[0x10];
6609 u8 reserved_at_20[0x10];
6612 u8 reserved_at_40[0x20];
6615 u8 reserved_at_61[0x1f];
6617 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6619 u8 reserved_at_280[0x80];
6621 u8 translations_octword_actual_size[0x20];
6623 u8 reserved_at_320[0x560];
6625 u8 klm_pas_mtt[0][0x20];
6628 struct mlx5_ifc_create_flow_table_out_bits {
6630 u8 reserved_at_8[0x18];
6634 u8 reserved_at_40[0x8];
6637 u8 reserved_at_60[0x20];
6640 struct mlx5_ifc_flow_table_context_bits {
6643 u8 reserved_at_2[0x2];
6644 u8 table_miss_action[0x4];
6646 u8 reserved_at_10[0x8];
6649 u8 reserved_at_20[0x8];
6650 u8 table_miss_id[0x18];
6652 u8 reserved_at_40[0x8];
6653 u8 lag_master_next_table_id[0x18];
6655 u8 reserved_at_60[0xe0];
6658 struct mlx5_ifc_create_flow_table_in_bits {
6660 u8 reserved_at_10[0x10];
6662 u8 reserved_at_20[0x10];
6665 u8 other_vport[0x1];
6666 u8 reserved_at_41[0xf];
6667 u8 vport_number[0x10];
6669 u8 reserved_at_60[0x20];
6672 u8 reserved_at_88[0x18];
6674 u8 reserved_at_a0[0x20];
6676 struct mlx5_ifc_flow_table_context_bits flow_table_context;
6679 struct mlx5_ifc_create_flow_group_out_bits {
6681 u8 reserved_at_8[0x18];
6685 u8 reserved_at_40[0x8];
6688 u8 reserved_at_60[0x20];
6692 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6693 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6694 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6697 struct mlx5_ifc_create_flow_group_in_bits {
6699 u8 reserved_at_10[0x10];
6701 u8 reserved_at_20[0x10];
6704 u8 other_vport[0x1];
6705 u8 reserved_at_41[0xf];
6706 u8 vport_number[0x10];
6708 u8 reserved_at_60[0x20];
6711 u8 reserved_at_88[0x18];
6713 u8 reserved_at_a0[0x8];
6716 u8 reserved_at_c0[0x20];
6718 u8 start_flow_index[0x20];
6720 u8 reserved_at_100[0x20];
6722 u8 end_flow_index[0x20];
6724 u8 reserved_at_140[0xa0];
6726 u8 reserved_at_1e0[0x18];
6727 u8 match_criteria_enable[0x8];
6729 struct mlx5_ifc_fte_match_param_bits match_criteria;
6731 u8 reserved_at_1200[0xe00];
6734 struct mlx5_ifc_create_eq_out_bits {
6736 u8 reserved_at_8[0x18];
6740 u8 reserved_at_40[0x18];
6743 u8 reserved_at_60[0x20];
6746 struct mlx5_ifc_create_eq_in_bits {
6748 u8 reserved_at_10[0x10];
6750 u8 reserved_at_20[0x10];
6753 u8 reserved_at_40[0x40];
6755 struct mlx5_ifc_eqc_bits eq_context_entry;
6757 u8 reserved_at_280[0x40];
6759 u8 event_bitmask[0x40];
6761 u8 reserved_at_300[0x580];
6766 struct mlx5_ifc_create_dct_out_bits {
6768 u8 reserved_at_8[0x18];
6772 u8 reserved_at_40[0x8];
6775 u8 reserved_at_60[0x20];
6778 struct mlx5_ifc_create_dct_in_bits {
6780 u8 reserved_at_10[0x10];
6782 u8 reserved_at_20[0x10];
6785 u8 reserved_at_40[0x40];
6787 struct mlx5_ifc_dctc_bits dct_context_entry;
6789 u8 reserved_at_280[0x180];
6792 struct mlx5_ifc_create_cq_out_bits {
6794 u8 reserved_at_8[0x18];
6798 u8 reserved_at_40[0x8];
6801 u8 reserved_at_60[0x20];
6804 struct mlx5_ifc_create_cq_in_bits {
6806 u8 reserved_at_10[0x10];
6808 u8 reserved_at_20[0x10];
6811 u8 reserved_at_40[0x40];
6813 struct mlx5_ifc_cqc_bits cq_context;
6815 u8 reserved_at_280[0x600];
6820 struct mlx5_ifc_config_int_moderation_out_bits {
6822 u8 reserved_at_8[0x18];
6826 u8 reserved_at_40[0x4];
6828 u8 int_vector[0x10];
6830 u8 reserved_at_60[0x20];
6834 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6835 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6838 struct mlx5_ifc_config_int_moderation_in_bits {
6840 u8 reserved_at_10[0x10];
6842 u8 reserved_at_20[0x10];
6845 u8 reserved_at_40[0x4];
6847 u8 int_vector[0x10];
6849 u8 reserved_at_60[0x20];
6852 struct mlx5_ifc_attach_to_mcg_out_bits {
6854 u8 reserved_at_8[0x18];
6858 u8 reserved_at_40[0x40];
6861 struct mlx5_ifc_attach_to_mcg_in_bits {
6863 u8 reserved_at_10[0x10];
6865 u8 reserved_at_20[0x10];
6868 u8 reserved_at_40[0x8];
6871 u8 reserved_at_60[0x20];
6873 u8 multicast_gid[16][0x8];
6876 struct mlx5_ifc_arm_xrq_out_bits {
6878 u8 reserved_at_8[0x18];
6882 u8 reserved_at_40[0x40];
6885 struct mlx5_ifc_arm_xrq_in_bits {
6887 u8 reserved_at_10[0x10];
6889 u8 reserved_at_20[0x10];
6892 u8 reserved_at_40[0x8];
6895 u8 reserved_at_60[0x10];
6899 struct mlx5_ifc_arm_xrc_srq_out_bits {
6901 u8 reserved_at_8[0x18];
6905 u8 reserved_at_40[0x40];
6909 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6912 struct mlx5_ifc_arm_xrc_srq_in_bits {
6914 u8 reserved_at_10[0x10];
6916 u8 reserved_at_20[0x10];
6919 u8 reserved_at_40[0x8];
6922 u8 reserved_at_60[0x10];
6926 struct mlx5_ifc_arm_rq_out_bits {
6928 u8 reserved_at_8[0x18];
6932 u8 reserved_at_40[0x40];
6936 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6937 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6940 struct mlx5_ifc_arm_rq_in_bits {
6942 u8 reserved_at_10[0x10];
6944 u8 reserved_at_20[0x10];
6947 u8 reserved_at_40[0x8];
6948 u8 srq_number[0x18];
6950 u8 reserved_at_60[0x10];
6954 struct mlx5_ifc_arm_dct_out_bits {
6956 u8 reserved_at_8[0x18];
6960 u8 reserved_at_40[0x40];
6963 struct mlx5_ifc_arm_dct_in_bits {
6965 u8 reserved_at_10[0x10];
6967 u8 reserved_at_20[0x10];
6970 u8 reserved_at_40[0x8];
6971 u8 dct_number[0x18];
6973 u8 reserved_at_60[0x20];
6976 struct mlx5_ifc_alloc_xrcd_out_bits {
6978 u8 reserved_at_8[0x18];
6982 u8 reserved_at_40[0x8];
6985 u8 reserved_at_60[0x20];
6988 struct mlx5_ifc_alloc_xrcd_in_bits {
6990 u8 reserved_at_10[0x10];
6992 u8 reserved_at_20[0x10];
6995 u8 reserved_at_40[0x40];
6998 struct mlx5_ifc_alloc_uar_out_bits {
7000 u8 reserved_at_8[0x18];
7004 u8 reserved_at_40[0x8];
7007 u8 reserved_at_60[0x20];
7010 struct mlx5_ifc_alloc_uar_in_bits {
7012 u8 reserved_at_10[0x10];
7014 u8 reserved_at_20[0x10];
7017 u8 reserved_at_40[0x40];
7020 struct mlx5_ifc_alloc_transport_domain_out_bits {
7022 u8 reserved_at_8[0x18];
7026 u8 reserved_at_40[0x8];
7027 u8 transport_domain[0x18];
7029 u8 reserved_at_60[0x20];
7032 struct mlx5_ifc_alloc_transport_domain_in_bits {
7034 u8 reserved_at_10[0x10];
7036 u8 reserved_at_20[0x10];
7039 u8 reserved_at_40[0x40];
7042 struct mlx5_ifc_alloc_q_counter_out_bits {
7044 u8 reserved_at_8[0x18];
7048 u8 reserved_at_40[0x18];
7049 u8 counter_set_id[0x8];
7051 u8 reserved_at_60[0x20];
7054 struct mlx5_ifc_alloc_q_counter_in_bits {
7056 u8 reserved_at_10[0x10];
7058 u8 reserved_at_20[0x10];
7061 u8 reserved_at_40[0x40];
7064 struct mlx5_ifc_alloc_pd_out_bits {
7066 u8 reserved_at_8[0x18];
7070 u8 reserved_at_40[0x8];
7073 u8 reserved_at_60[0x20];
7076 struct mlx5_ifc_alloc_pd_in_bits {
7078 u8 reserved_at_10[0x10];
7080 u8 reserved_at_20[0x10];
7083 u8 reserved_at_40[0x40];
7086 struct mlx5_ifc_alloc_flow_counter_out_bits {
7088 u8 reserved_at_8[0x18];
7092 u8 reserved_at_40[0x10];
7093 u8 flow_counter_id[0x10];
7095 u8 reserved_at_60[0x20];
7098 struct mlx5_ifc_alloc_flow_counter_in_bits {
7100 u8 reserved_at_10[0x10];
7102 u8 reserved_at_20[0x10];
7105 u8 reserved_at_40[0x40];
7108 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7110 u8 reserved_at_8[0x18];
7114 u8 reserved_at_40[0x40];
7117 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7119 u8 reserved_at_10[0x10];
7121 u8 reserved_at_20[0x10];
7124 u8 reserved_at_40[0x20];
7126 u8 reserved_at_60[0x10];
7127 u8 vxlan_udp_port[0x10];
7130 struct mlx5_ifc_set_rate_limit_out_bits {
7132 u8 reserved_at_8[0x18];
7136 u8 reserved_at_40[0x40];
7139 struct mlx5_ifc_set_rate_limit_in_bits {
7141 u8 reserved_at_10[0x10];
7143 u8 reserved_at_20[0x10];
7146 u8 reserved_at_40[0x10];
7147 u8 rate_limit_index[0x10];
7149 u8 reserved_at_60[0x20];
7151 u8 rate_limit[0x20];
7154 struct mlx5_ifc_access_register_out_bits {
7156 u8 reserved_at_8[0x18];
7160 u8 reserved_at_40[0x40];
7162 u8 register_data[0][0x20];
7166 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7167 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7170 struct mlx5_ifc_access_register_in_bits {
7172 u8 reserved_at_10[0x10];
7174 u8 reserved_at_20[0x10];
7177 u8 reserved_at_40[0x10];
7178 u8 register_id[0x10];
7182 u8 register_data[0][0x20];
7185 struct mlx5_ifc_sltp_reg_bits {
7190 u8 reserved_at_12[0x2];
7192 u8 reserved_at_18[0x8];
7194 u8 reserved_at_20[0x20];
7196 u8 reserved_at_40[0x7];
7202 u8 reserved_at_60[0xc];
7203 u8 ob_preemp_mode[0x4];
7207 u8 reserved_at_80[0x20];
7210 struct mlx5_ifc_slrg_reg_bits {
7215 u8 reserved_at_12[0x2];
7217 u8 reserved_at_18[0x8];
7219 u8 time_to_link_up[0x10];
7220 u8 reserved_at_30[0xc];
7221 u8 grade_lane_speed[0x4];
7223 u8 grade_version[0x8];
7226 u8 reserved_at_60[0x4];
7227 u8 height_grade_type[0x4];
7228 u8 height_grade[0x18];
7233 u8 reserved_at_a0[0x10];
7234 u8 height_sigma[0x10];
7236 u8 reserved_at_c0[0x20];
7238 u8 reserved_at_e0[0x4];
7239 u8 phase_grade_type[0x4];
7240 u8 phase_grade[0x18];
7242 u8 reserved_at_100[0x8];
7243 u8 phase_eo_pos[0x8];
7244 u8 reserved_at_110[0x8];
7245 u8 phase_eo_neg[0x8];
7247 u8 ffe_set_tested[0x10];
7248 u8 test_errors_per_lane[0x10];
7251 struct mlx5_ifc_pvlc_reg_bits {
7252 u8 reserved_at_0[0x8];
7254 u8 reserved_at_10[0x10];
7256 u8 reserved_at_20[0x1c];
7259 u8 reserved_at_40[0x1c];
7262 u8 reserved_at_60[0x1c];
7263 u8 vl_operational[0x4];
7266 struct mlx5_ifc_pude_reg_bits {
7269 u8 reserved_at_10[0x4];
7270 u8 admin_status[0x4];
7271 u8 reserved_at_18[0x4];
7272 u8 oper_status[0x4];
7274 u8 reserved_at_20[0x60];
7277 struct mlx5_ifc_ptys_reg_bits {
7278 u8 reserved_at_0[0x1];
7279 u8 an_disable_admin[0x1];
7280 u8 an_disable_cap[0x1];
7281 u8 reserved_at_3[0x5];
7283 u8 reserved_at_10[0xd];
7287 u8 reserved_at_24[0x3c];
7289 u8 eth_proto_capability[0x20];
7291 u8 ib_link_width_capability[0x10];
7292 u8 ib_proto_capability[0x10];
7294 u8 reserved_at_a0[0x20];
7296 u8 eth_proto_admin[0x20];
7298 u8 ib_link_width_admin[0x10];
7299 u8 ib_proto_admin[0x10];
7301 u8 reserved_at_100[0x20];
7303 u8 eth_proto_oper[0x20];
7305 u8 ib_link_width_oper[0x10];
7306 u8 ib_proto_oper[0x10];
7308 u8 reserved_at_160[0x1c];
7309 u8 connector_type[0x4];
7311 u8 eth_proto_lp_advertise[0x20];
7313 u8 reserved_at_1a0[0x60];
7316 struct mlx5_ifc_mlcr_reg_bits {
7317 u8 reserved_at_0[0x8];
7319 u8 reserved_at_10[0x20];
7321 u8 beacon_duration[0x10];
7322 u8 reserved_at_40[0x10];
7324 u8 beacon_remain[0x10];
7327 struct mlx5_ifc_ptas_reg_bits {
7328 u8 reserved_at_0[0x20];
7330 u8 algorithm_options[0x10];
7331 u8 reserved_at_30[0x4];
7332 u8 repetitions_mode[0x4];
7333 u8 num_of_repetitions[0x8];
7335 u8 grade_version[0x8];
7336 u8 height_grade_type[0x4];
7337 u8 phase_grade_type[0x4];
7338 u8 height_grade_weight[0x8];
7339 u8 phase_grade_weight[0x8];
7341 u8 gisim_measure_bits[0x10];
7342 u8 adaptive_tap_measure_bits[0x10];
7344 u8 ber_bath_high_error_threshold[0x10];
7345 u8 ber_bath_mid_error_threshold[0x10];
7347 u8 ber_bath_low_error_threshold[0x10];
7348 u8 one_ratio_high_threshold[0x10];
7350 u8 one_ratio_high_mid_threshold[0x10];
7351 u8 one_ratio_low_mid_threshold[0x10];
7353 u8 one_ratio_low_threshold[0x10];
7354 u8 ndeo_error_threshold[0x10];
7356 u8 mixer_offset_step_size[0x10];
7357 u8 reserved_at_110[0x8];
7358 u8 mix90_phase_for_voltage_bath[0x8];
7360 u8 mixer_offset_start[0x10];
7361 u8 mixer_offset_end[0x10];
7363 u8 reserved_at_140[0x15];
7364 u8 ber_test_time[0xb];
7367 struct mlx5_ifc_pspa_reg_bits {
7371 u8 reserved_at_18[0x8];
7373 u8 reserved_at_20[0x20];
7376 struct mlx5_ifc_pqdr_reg_bits {
7377 u8 reserved_at_0[0x8];
7379 u8 reserved_at_10[0x5];
7381 u8 reserved_at_18[0x6];
7384 u8 reserved_at_20[0x20];
7386 u8 reserved_at_40[0x10];
7387 u8 min_threshold[0x10];
7389 u8 reserved_at_60[0x10];
7390 u8 max_threshold[0x10];
7392 u8 reserved_at_80[0x10];
7393 u8 mark_probability_denominator[0x10];
7395 u8 reserved_at_a0[0x60];
7398 struct mlx5_ifc_ppsc_reg_bits {
7399 u8 reserved_at_0[0x8];
7401 u8 reserved_at_10[0x10];
7403 u8 reserved_at_20[0x60];
7405 u8 reserved_at_80[0x1c];
7408 u8 reserved_at_a0[0x1c];
7409 u8 wrps_status[0x4];
7411 u8 reserved_at_c0[0x8];
7412 u8 up_threshold[0x8];
7413 u8 reserved_at_d0[0x8];
7414 u8 down_threshold[0x8];
7416 u8 reserved_at_e0[0x20];
7418 u8 reserved_at_100[0x1c];
7421 u8 reserved_at_120[0x1c];
7422 u8 srps_status[0x4];
7424 u8 reserved_at_140[0x40];
7427 struct mlx5_ifc_pplr_reg_bits {
7428 u8 reserved_at_0[0x8];
7430 u8 reserved_at_10[0x10];
7432 u8 reserved_at_20[0x8];
7434 u8 reserved_at_30[0x8];
7438 struct mlx5_ifc_pplm_reg_bits {
7439 u8 reserved_at_0[0x8];
7441 u8 reserved_at_10[0x10];
7443 u8 reserved_at_20[0x20];
7445 u8 port_profile_mode[0x8];
7446 u8 static_port_profile[0x8];
7447 u8 active_port_profile[0x8];
7448 u8 reserved_at_58[0x8];
7450 u8 retransmission_active[0x8];
7451 u8 fec_mode_active[0x18];
7453 u8 reserved_at_80[0x20];
7456 struct mlx5_ifc_ppcnt_reg_bits {
7460 u8 reserved_at_12[0x8];
7464 u8 reserved_at_21[0x1c];
7467 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7470 struct mlx5_ifc_mpcnt_reg_bits {
7471 u8 reserved_at_0[0x8];
7473 u8 reserved_at_10[0xa];
7477 u8 reserved_at_21[0x1f];
7479 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7482 struct mlx5_ifc_ppad_reg_bits {
7483 u8 reserved_at_0[0x3];
7485 u8 reserved_at_4[0x4];
7491 u8 reserved_at_40[0x40];
7494 struct mlx5_ifc_pmtu_reg_bits {
7495 u8 reserved_at_0[0x8];
7497 u8 reserved_at_10[0x10];
7500 u8 reserved_at_30[0x10];
7503 u8 reserved_at_50[0x10];
7506 u8 reserved_at_70[0x10];
7509 struct mlx5_ifc_pmpr_reg_bits {
7510 u8 reserved_at_0[0x8];
7512 u8 reserved_at_10[0x10];
7514 u8 reserved_at_20[0x18];
7515 u8 attenuation_5g[0x8];
7517 u8 reserved_at_40[0x18];
7518 u8 attenuation_7g[0x8];
7520 u8 reserved_at_60[0x18];
7521 u8 attenuation_12g[0x8];
7524 struct mlx5_ifc_pmpe_reg_bits {
7525 u8 reserved_at_0[0x8];
7527 u8 reserved_at_10[0xc];
7528 u8 module_status[0x4];
7530 u8 reserved_at_20[0x60];
7533 struct mlx5_ifc_pmpc_reg_bits {
7534 u8 module_state_updated[32][0x8];
7537 struct mlx5_ifc_pmlpn_reg_bits {
7538 u8 reserved_at_0[0x4];
7539 u8 mlpn_status[0x4];
7541 u8 reserved_at_10[0x10];
7544 u8 reserved_at_21[0x1f];
7547 struct mlx5_ifc_pmlp_reg_bits {
7549 u8 reserved_at_1[0x7];
7551 u8 reserved_at_10[0x8];
7554 u8 lane0_module_mapping[0x20];
7556 u8 lane1_module_mapping[0x20];
7558 u8 lane2_module_mapping[0x20];
7560 u8 lane3_module_mapping[0x20];
7562 u8 reserved_at_a0[0x160];
7565 struct mlx5_ifc_pmaos_reg_bits {
7566 u8 reserved_at_0[0x8];
7568 u8 reserved_at_10[0x4];
7569 u8 admin_status[0x4];
7570 u8 reserved_at_18[0x4];
7571 u8 oper_status[0x4];
7575 u8 reserved_at_22[0x1c];
7578 u8 reserved_at_40[0x40];
7581 struct mlx5_ifc_plpc_reg_bits {
7582 u8 reserved_at_0[0x4];
7584 u8 reserved_at_10[0x4];
7586 u8 reserved_at_18[0x8];
7588 u8 reserved_at_20[0x10];
7589 u8 lane_speed[0x10];
7591 u8 reserved_at_40[0x17];
7593 u8 fec_mode_policy[0x8];
7595 u8 retransmission_capability[0x8];
7596 u8 fec_mode_capability[0x18];
7598 u8 retransmission_support_admin[0x8];
7599 u8 fec_mode_support_admin[0x18];
7601 u8 retransmission_request_admin[0x8];
7602 u8 fec_mode_request_admin[0x18];
7604 u8 reserved_at_c0[0x80];
7607 struct mlx5_ifc_plib_reg_bits {
7608 u8 reserved_at_0[0x8];
7610 u8 reserved_at_10[0x8];
7613 u8 reserved_at_20[0x60];
7616 struct mlx5_ifc_plbf_reg_bits {
7617 u8 reserved_at_0[0x8];
7619 u8 reserved_at_10[0xd];
7622 u8 reserved_at_20[0x20];
7625 struct mlx5_ifc_pipg_reg_bits {
7626 u8 reserved_at_0[0x8];
7628 u8 reserved_at_10[0x10];
7631 u8 reserved_at_21[0x19];
7633 u8 reserved_at_3e[0x2];
7636 struct mlx5_ifc_pifr_reg_bits {
7637 u8 reserved_at_0[0x8];
7639 u8 reserved_at_10[0x10];
7641 u8 reserved_at_20[0xe0];
7643 u8 port_filter[8][0x20];
7645 u8 port_filter_update_en[8][0x20];
7648 struct mlx5_ifc_pfcc_reg_bits {
7649 u8 reserved_at_0[0x8];
7651 u8 reserved_at_10[0x10];
7654 u8 reserved_at_24[0x4];
7655 u8 prio_mask_tx[0x8];
7656 u8 reserved_at_30[0x8];
7657 u8 prio_mask_rx[0x8];
7661 u8 reserved_at_42[0x6];
7663 u8 reserved_at_50[0x10];
7667 u8 reserved_at_62[0x6];
7669 u8 reserved_at_70[0x10];
7671 u8 reserved_at_80[0x80];
7674 struct mlx5_ifc_pelc_reg_bits {
7676 u8 reserved_at_4[0x4];
7678 u8 reserved_at_10[0x10];
7681 u8 op_capability[0x8];
7687 u8 capability[0x40];
7693 u8 reserved_at_140[0x80];
7696 struct mlx5_ifc_peir_reg_bits {
7697 u8 reserved_at_0[0x8];
7699 u8 reserved_at_10[0x10];
7701 u8 reserved_at_20[0xc];
7702 u8 error_count[0x4];
7703 u8 reserved_at_30[0x10];
7705 u8 reserved_at_40[0xc];
7707 u8 reserved_at_50[0x8];
7711 struct mlx5_ifc_pcam_enhanced_features_bits {
7712 u8 reserved_at_0[0x7c];
7714 u8 ptys_connector_type[0x1];
7715 u8 reserved_at_7d[0x1];
7716 u8 ppcnt_discard_group[0x1];
7717 u8 ppcnt_statistical_group[0x1];
7720 struct mlx5_ifc_pcam_reg_bits {
7721 u8 reserved_at_0[0x8];
7722 u8 feature_group[0x8];
7723 u8 reserved_at_10[0x8];
7724 u8 access_reg_group[0x8];
7726 u8 reserved_at_20[0x20];
7729 u8 reserved_at_0[0x80];
7730 } port_access_reg_cap_mask;
7732 u8 reserved_at_c0[0x80];
7735 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7736 u8 reserved_at_0[0x80];
7739 u8 reserved_at_1c0[0xc0];
7742 struct mlx5_ifc_mcam_enhanced_features_bits {
7743 u8 reserved_at_0[0x7f];
7745 u8 pcie_performance_group[0x1];
7748 struct mlx5_ifc_mcam_reg_bits {
7749 u8 reserved_at_0[0x8];
7750 u8 feature_group[0x8];
7751 u8 reserved_at_10[0x8];
7752 u8 access_reg_group[0x8];
7754 u8 reserved_at_20[0x20];
7757 u8 reserved_at_0[0x80];
7758 } mng_access_reg_cap_mask;
7760 u8 reserved_at_c0[0x80];
7763 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7764 u8 reserved_at_0[0x80];
7765 } mng_feature_cap_mask;
7767 u8 reserved_at_1c0[0x80];
7770 struct mlx5_ifc_pcap_reg_bits {
7771 u8 reserved_at_0[0x8];
7773 u8 reserved_at_10[0x10];
7775 u8 port_capability_mask[4][0x20];
7778 struct mlx5_ifc_paos_reg_bits {
7781 u8 reserved_at_10[0x4];
7782 u8 admin_status[0x4];
7783 u8 reserved_at_18[0x4];
7784 u8 oper_status[0x4];
7788 u8 reserved_at_22[0x1c];
7791 u8 reserved_at_40[0x40];
7794 struct mlx5_ifc_pamp_reg_bits {
7795 u8 reserved_at_0[0x8];
7796 u8 opamp_group[0x8];
7797 u8 reserved_at_10[0xc];
7798 u8 opamp_group_type[0x4];
7800 u8 start_index[0x10];
7801 u8 reserved_at_30[0x4];
7802 u8 num_of_indices[0xc];
7804 u8 index_data[18][0x10];
7807 struct mlx5_ifc_pcmr_reg_bits {
7808 u8 reserved_at_0[0x8];
7810 u8 reserved_at_10[0x2e];
7812 u8 reserved_at_3f[0x1f];
7814 u8 reserved_at_5f[0x1];
7817 struct mlx5_ifc_lane_2_module_mapping_bits {
7818 u8 reserved_at_0[0x6];
7820 u8 reserved_at_8[0x6];
7822 u8 reserved_at_10[0x8];
7826 struct mlx5_ifc_bufferx_reg_bits {
7827 u8 reserved_at_0[0x6];
7830 u8 reserved_at_8[0xc];
7833 u8 xoff_threshold[0x10];
7834 u8 xon_threshold[0x10];
7837 struct mlx5_ifc_set_node_in_bits {
7838 u8 node_description[64][0x8];
7841 struct mlx5_ifc_register_power_settings_bits {
7842 u8 reserved_at_0[0x18];
7843 u8 power_settings_level[0x8];
7845 u8 reserved_at_20[0x60];
7848 struct mlx5_ifc_register_host_endianness_bits {
7850 u8 reserved_at_1[0x1f];
7852 u8 reserved_at_20[0x60];
7855 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7856 u8 reserved_at_0[0x20];
7860 u8 addressh_63_32[0x20];
7862 u8 addressl_31_0[0x20];
7865 struct mlx5_ifc_ud_adrs_vector_bits {
7869 u8 reserved_at_41[0x7];
7870 u8 destination_qp_dct[0x18];
7872 u8 static_rate[0x4];
7873 u8 sl_eth_prio[0x4];
7876 u8 rlid_udp_sport[0x10];
7878 u8 reserved_at_80[0x20];
7880 u8 rmac_47_16[0x20];
7886 u8 reserved_at_e0[0x1];
7888 u8 reserved_at_e2[0x2];
7889 u8 src_addr_index[0x8];
7890 u8 flow_label[0x14];
7892 u8 rgid_rip[16][0x8];
7895 struct mlx5_ifc_pages_req_event_bits {
7896 u8 reserved_at_0[0x10];
7897 u8 function_id[0x10];
7901 u8 reserved_at_40[0xa0];
7904 struct mlx5_ifc_eqe_bits {
7905 u8 reserved_at_0[0x8];
7907 u8 reserved_at_10[0x8];
7908 u8 event_sub_type[0x8];
7910 u8 reserved_at_20[0xe0];
7912 union mlx5_ifc_event_auto_bits event_data;
7914 u8 reserved_at_1e0[0x10];
7916 u8 reserved_at_1f8[0x7];
7921 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7924 struct mlx5_ifc_cmd_queue_entry_bits {
7926 u8 reserved_at_8[0x18];
7928 u8 input_length[0x20];
7930 u8 input_mailbox_pointer_63_32[0x20];
7932 u8 input_mailbox_pointer_31_9[0x17];
7933 u8 reserved_at_77[0x9];
7935 u8 command_input_inline_data[16][0x8];
7937 u8 command_output_inline_data[16][0x8];
7939 u8 output_mailbox_pointer_63_32[0x20];
7941 u8 output_mailbox_pointer_31_9[0x17];
7942 u8 reserved_at_1b7[0x9];
7944 u8 output_length[0x20];
7948 u8 reserved_at_1f0[0x8];
7953 struct mlx5_ifc_cmd_out_bits {
7955 u8 reserved_at_8[0x18];
7959 u8 command_output[0x20];
7962 struct mlx5_ifc_cmd_in_bits {
7964 u8 reserved_at_10[0x10];
7966 u8 reserved_at_20[0x10];
7969 u8 command[0][0x20];
7972 struct mlx5_ifc_cmd_if_box_bits {
7973 u8 mailbox_data[512][0x8];
7975 u8 reserved_at_1000[0x180];
7977 u8 next_pointer_63_32[0x20];
7979 u8 next_pointer_31_10[0x16];
7980 u8 reserved_at_11b6[0xa];
7982 u8 block_number[0x20];
7984 u8 reserved_at_11e0[0x8];
7986 u8 ctrl_signature[0x8];
7990 struct mlx5_ifc_mtt_bits {
7991 u8 ptag_63_32[0x20];
7994 u8 reserved_at_38[0x6];
7999 struct mlx5_ifc_query_wol_rol_out_bits {
8001 u8 reserved_at_8[0x18];
8005 u8 reserved_at_40[0x10];
8009 u8 reserved_at_60[0x20];
8012 struct mlx5_ifc_query_wol_rol_in_bits {
8014 u8 reserved_at_10[0x10];
8016 u8 reserved_at_20[0x10];
8019 u8 reserved_at_40[0x40];
8022 struct mlx5_ifc_set_wol_rol_out_bits {
8024 u8 reserved_at_8[0x18];
8028 u8 reserved_at_40[0x40];
8031 struct mlx5_ifc_set_wol_rol_in_bits {
8033 u8 reserved_at_10[0x10];
8035 u8 reserved_at_20[0x10];
8038 u8 rol_mode_valid[0x1];
8039 u8 wol_mode_valid[0x1];
8040 u8 reserved_at_42[0xe];
8044 u8 reserved_at_60[0x20];
8048 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8049 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8050 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8054 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8055 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8056 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8060 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8061 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8062 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8063 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8064 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8065 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8066 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8067 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8068 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8069 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8070 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8073 struct mlx5_ifc_initial_seg_bits {
8074 u8 fw_rev_minor[0x10];
8075 u8 fw_rev_major[0x10];
8077 u8 cmd_interface_rev[0x10];
8078 u8 fw_rev_subminor[0x10];
8080 u8 reserved_at_40[0x40];
8082 u8 cmdq_phy_addr_63_32[0x20];
8084 u8 cmdq_phy_addr_31_12[0x14];
8085 u8 reserved_at_b4[0x2];
8086 u8 nic_interface[0x2];
8087 u8 log_cmdq_size[0x4];
8088 u8 log_cmdq_stride[0x4];
8090 u8 command_doorbell_vector[0x20];
8092 u8 reserved_at_e0[0xf00];
8094 u8 initializing[0x1];
8095 u8 reserved_at_fe1[0x4];
8096 u8 nic_interface_supported[0x3];
8097 u8 reserved_at_fe8[0x18];
8099 struct mlx5_ifc_health_buffer_bits health_buffer;
8101 u8 no_dram_nic_offset[0x20];
8103 u8 reserved_at_1220[0x6e40];
8105 u8 reserved_at_8060[0x1f];
8108 u8 health_syndrome[0x8];
8109 u8 health_counter[0x18];
8111 u8 reserved_at_80a0[0x17fc0];
8114 struct mlx5_ifc_mtpps_reg_bits {
8115 u8 reserved_at_0[0xc];
8116 u8 cap_number_of_pps_pins[0x4];
8117 u8 reserved_at_10[0x4];
8118 u8 cap_max_num_of_pps_in_pins[0x4];
8119 u8 reserved_at_18[0x4];
8120 u8 cap_max_num_of_pps_out_pins[0x4];
8122 u8 reserved_at_20[0x24];
8123 u8 cap_pin_3_mode[0x4];
8124 u8 reserved_at_48[0x4];
8125 u8 cap_pin_2_mode[0x4];
8126 u8 reserved_at_50[0x4];
8127 u8 cap_pin_1_mode[0x4];
8128 u8 reserved_at_58[0x4];
8129 u8 cap_pin_0_mode[0x4];
8131 u8 reserved_at_60[0x4];
8132 u8 cap_pin_7_mode[0x4];
8133 u8 reserved_at_68[0x4];
8134 u8 cap_pin_6_mode[0x4];
8135 u8 reserved_at_70[0x4];
8136 u8 cap_pin_5_mode[0x4];
8137 u8 reserved_at_78[0x4];
8138 u8 cap_pin_4_mode[0x4];
8140 u8 reserved_at_80[0x80];
8143 u8 reserved_at_101[0xb];
8145 u8 reserved_at_110[0x4];
8149 u8 reserved_at_120[0x20];
8151 u8 time_stamp[0x40];
8153 u8 out_pulse_duration[0x10];
8154 u8 out_periodic_adjustment[0x10];
8156 u8 reserved_at_1a0[0x60];
8159 struct mlx5_ifc_mtppse_reg_bits {
8160 u8 reserved_at_0[0x18];
8163 u8 reserved_at_21[0x1b];
8164 u8 event_generation_mode[0x4];
8165 u8 reserved_at_40[0x40];
8168 struct mlx5_ifc_mcqi_cap_bits {
8169 u8 supported_info_bitmask[0x20];
8171 u8 component_size[0x20];
8173 u8 max_component_size[0x20];
8175 u8 log_mcda_word_size[0x4];
8176 u8 reserved_at_64[0xc];
8177 u8 mcda_max_write_size[0x10];
8180 u8 reserved_at_81[0x1];
8181 u8 match_chip_id[0x1];
8183 u8 check_user_timestamp[0x1];
8184 u8 match_base_guid_mac[0x1];
8185 u8 reserved_at_86[0x1a];
8188 struct mlx5_ifc_mcqi_reg_bits {
8189 u8 read_pending_component[0x1];
8190 u8 reserved_at_1[0xf];
8191 u8 component_index[0x10];
8193 u8 reserved_at_20[0x20];
8195 u8 reserved_at_40[0x1b];
8202 u8 reserved_at_a0[0x10];
8208 struct mlx5_ifc_mcc_reg_bits {
8209 u8 reserved_at_0[0x4];
8210 u8 time_elapsed_since_last_cmd[0xc];
8211 u8 reserved_at_10[0x8];
8212 u8 instruction[0x8];
8214 u8 reserved_at_20[0x10];
8215 u8 component_index[0x10];
8217 u8 reserved_at_40[0x8];
8218 u8 update_handle[0x18];
8220 u8 handle_owner_type[0x4];
8221 u8 handle_owner_host_id[0x4];
8222 u8 reserved_at_68[0x1];
8223 u8 control_progress[0x7];
8225 u8 reserved_at_78[0x4];
8226 u8 control_state[0x4];
8228 u8 component_size[0x20];
8230 u8 reserved_at_a0[0x60];
8233 struct mlx5_ifc_mcda_reg_bits {
8234 u8 reserved_at_0[0x8];
8235 u8 update_handle[0x18];
8239 u8 reserved_at_40[0x10];
8242 u8 reserved_at_60[0x20];
8247 union mlx5_ifc_ports_control_registers_document_bits {
8248 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8249 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8250 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8251 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8252 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8253 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8254 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8255 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8256 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8257 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8258 struct mlx5_ifc_paos_reg_bits paos_reg;
8259 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8260 struct mlx5_ifc_peir_reg_bits peir_reg;
8261 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8262 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8263 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8264 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8265 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8266 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8267 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8268 struct mlx5_ifc_plib_reg_bits plib_reg;
8269 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8270 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8271 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8272 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8273 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8274 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8275 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8276 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8277 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8278 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8279 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8280 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8281 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8282 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8283 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8284 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8285 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8286 struct mlx5_ifc_ptys_reg_bits ptys_reg;
8287 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8288 struct mlx5_ifc_pude_reg_bits pude_reg;
8289 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8290 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8291 struct mlx5_ifc_sltp_reg_bits sltp_reg;
8292 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8293 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8294 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8295 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8296 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8297 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8298 struct mlx5_ifc_mcda_reg_bits mcda_reg;
8299 u8 reserved_at_0[0x60e0];
8302 union mlx5_ifc_debug_enhancements_document_bits {
8303 struct mlx5_ifc_health_buffer_bits health_buffer;
8304 u8 reserved_at_0[0x200];
8307 union mlx5_ifc_uplink_pci_interface_document_bits {
8308 struct mlx5_ifc_initial_seg_bits initial_seg;
8309 u8 reserved_at_0[0x20060];
8312 struct mlx5_ifc_set_flow_table_root_out_bits {
8314 u8 reserved_at_8[0x18];
8318 u8 reserved_at_40[0x40];
8321 struct mlx5_ifc_set_flow_table_root_in_bits {
8323 u8 reserved_at_10[0x10];
8325 u8 reserved_at_20[0x10];
8328 u8 other_vport[0x1];
8329 u8 reserved_at_41[0xf];
8330 u8 vport_number[0x10];
8332 u8 reserved_at_60[0x20];
8335 u8 reserved_at_88[0x18];
8337 u8 reserved_at_a0[0x8];
8340 u8 reserved_at_c0[0x8];
8341 u8 underlay_qpn[0x18];
8342 u8 reserved_at_e0[0x120];
8346 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8347 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8350 struct mlx5_ifc_modify_flow_table_out_bits {
8352 u8 reserved_at_8[0x18];
8356 u8 reserved_at_40[0x40];
8359 struct mlx5_ifc_modify_flow_table_in_bits {
8361 u8 reserved_at_10[0x10];
8363 u8 reserved_at_20[0x10];
8366 u8 other_vport[0x1];
8367 u8 reserved_at_41[0xf];
8368 u8 vport_number[0x10];
8370 u8 reserved_at_60[0x10];
8371 u8 modify_field_select[0x10];
8374 u8 reserved_at_88[0x18];
8376 u8 reserved_at_a0[0x8];
8379 struct mlx5_ifc_flow_table_context_bits flow_table_context;
8382 struct mlx5_ifc_ets_tcn_config_reg_bits {
8386 u8 reserved_at_3[0x9];
8388 u8 reserved_at_10[0x9];
8389 u8 bw_allocation[0x7];
8391 u8 reserved_at_20[0xc];
8392 u8 max_bw_units[0x4];
8393 u8 reserved_at_30[0x8];
8394 u8 max_bw_value[0x8];
8397 struct mlx5_ifc_ets_global_config_reg_bits {
8398 u8 reserved_at_0[0x2];
8400 u8 reserved_at_3[0x1d];
8402 u8 reserved_at_20[0xc];
8403 u8 max_bw_units[0x4];
8404 u8 reserved_at_30[0x8];
8405 u8 max_bw_value[0x8];
8408 struct mlx5_ifc_qetc_reg_bits {
8409 u8 reserved_at_0[0x8];
8410 u8 port_number[0x8];
8411 u8 reserved_at_10[0x30];
8413 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8414 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8417 struct mlx5_ifc_qtct_reg_bits {
8418 u8 reserved_at_0[0x8];
8419 u8 port_number[0x8];
8420 u8 reserved_at_10[0xd];
8423 u8 reserved_at_20[0x1d];
8427 struct mlx5_ifc_mcia_reg_bits {
8429 u8 reserved_at_1[0x7];
8431 u8 reserved_at_10[0x8];
8434 u8 i2c_device_address[0x8];
8435 u8 page_number[0x8];
8436 u8 device_address[0x10];
8438 u8 reserved_at_40[0x10];
8441 u8 reserved_at_60[0x20];
8457 struct mlx5_ifc_dcbx_param_bits {
8458 u8 dcbx_cee_cap[0x1];
8459 u8 dcbx_ieee_cap[0x1];
8460 u8 dcbx_standby_cap[0x1];
8461 u8 reserved_at_0[0x5];
8462 u8 port_number[0x8];
8463 u8 reserved_at_10[0xa];
8464 u8 max_application_table_size[6];
8465 u8 reserved_at_20[0x15];
8466 u8 version_oper[0x3];
8467 u8 reserved_at_38[5];
8468 u8 version_admin[0x3];
8469 u8 willing_admin[0x1];
8470 u8 reserved_at_41[0x3];
8471 u8 pfc_cap_oper[0x4];
8472 u8 reserved_at_48[0x4];
8473 u8 pfc_cap_admin[0x4];
8474 u8 reserved_at_50[0x4];
8475 u8 num_of_tc_oper[0x4];
8476 u8 reserved_at_58[0x4];
8477 u8 num_of_tc_admin[0x4];
8478 u8 remote_willing[0x1];
8479 u8 reserved_at_61[3];
8480 u8 remote_pfc_cap[4];
8481 u8 reserved_at_68[0x14];
8482 u8 remote_num_of_tc[0x4];
8483 u8 reserved_at_80[0x18];
8485 u8 reserved_at_a0[0x160];
8488 struct mlx5_ifc_lagc_bits {
8489 u8 reserved_at_0[0x1d];
8492 u8 reserved_at_20[0x14];
8493 u8 tx_remap_affinity_2[0x4];
8494 u8 reserved_at_38[0x4];
8495 u8 tx_remap_affinity_1[0x4];
8498 struct mlx5_ifc_create_lag_out_bits {
8500 u8 reserved_at_8[0x18];
8504 u8 reserved_at_40[0x40];
8507 struct mlx5_ifc_create_lag_in_bits {
8509 u8 reserved_at_10[0x10];
8511 u8 reserved_at_20[0x10];
8514 struct mlx5_ifc_lagc_bits ctx;
8517 struct mlx5_ifc_modify_lag_out_bits {
8519 u8 reserved_at_8[0x18];
8523 u8 reserved_at_40[0x40];
8526 struct mlx5_ifc_modify_lag_in_bits {
8528 u8 reserved_at_10[0x10];
8530 u8 reserved_at_20[0x10];
8533 u8 reserved_at_40[0x20];
8534 u8 field_select[0x20];
8536 struct mlx5_ifc_lagc_bits ctx;
8539 struct mlx5_ifc_query_lag_out_bits {
8541 u8 reserved_at_8[0x18];
8545 u8 reserved_at_40[0x40];
8547 struct mlx5_ifc_lagc_bits ctx;
8550 struct mlx5_ifc_query_lag_in_bits {
8552 u8 reserved_at_10[0x10];
8554 u8 reserved_at_20[0x10];
8557 u8 reserved_at_40[0x40];
8560 struct mlx5_ifc_destroy_lag_out_bits {
8562 u8 reserved_at_8[0x18];
8566 u8 reserved_at_40[0x40];
8569 struct mlx5_ifc_destroy_lag_in_bits {
8571 u8 reserved_at_10[0x10];
8573 u8 reserved_at_20[0x10];
8576 u8 reserved_at_40[0x40];
8579 struct mlx5_ifc_create_vport_lag_out_bits {
8581 u8 reserved_at_8[0x18];
8585 u8 reserved_at_40[0x40];
8588 struct mlx5_ifc_create_vport_lag_in_bits {
8590 u8 reserved_at_10[0x10];
8592 u8 reserved_at_20[0x10];
8595 u8 reserved_at_40[0x40];
8598 struct mlx5_ifc_destroy_vport_lag_out_bits {
8600 u8 reserved_at_8[0x18];
8604 u8 reserved_at_40[0x40];
8607 struct mlx5_ifc_destroy_vport_lag_in_bits {
8609 u8 reserved_at_10[0x10];
8611 u8 reserved_at_20[0x10];
8614 u8 reserved_at_40[0x40];
8617 #endif /* MLX5_IFC_H */