include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 enum {
  36         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  37         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  38         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  39         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  40         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  41         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  42         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  43         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  44         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  45         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  46         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  47         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  48         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  49         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  50         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  51         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  52         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  53         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  54         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  56         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  57         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  58         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  59         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
  60 };
  61
  62 enum {
  63         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  64         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  65         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  66         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  67 };
  68
  69 enum {
  70         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  71         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  72 };
  73
  74 enum {
  75         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  76         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  77         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  78         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  79         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  80         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  81         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  82         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  83         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  84         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  85         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  86         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  87         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  88         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  89         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  90         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  91         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  92         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  93         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  94         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  95         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  96         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
  97         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
  98         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
  99         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 100         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 101         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 102         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 103         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 104         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 105         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 106         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 107         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 108         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 109         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 110         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 111         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 112         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 113         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 114         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 115         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 116         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 117         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 118         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 119         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 120         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 121         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 122         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 123         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 124         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 125         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 126         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 127         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 128         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 129         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 130         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 131         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 132         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 133         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 134         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 135         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 136         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 137         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 138         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 139         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 140         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 141         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 142         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 143         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 144         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 145         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 146         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 147         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 148         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 149         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 150         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 151         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 152         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 153         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 154         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 155         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 156         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 157         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 158         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 159         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 160         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 161         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 162         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 163         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 164         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 165         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 166         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 167         MLX5_CMD_OP_NOP                           = 0x80d,
 168         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 169         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 170         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 171         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 172         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 173         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 174         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 175         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 176         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 177         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 178         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 179         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 180         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 181         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 182         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 183         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 184         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 185         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 186         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 187         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 188         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 189         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 190         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 191         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 192         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 193         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 194         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 195         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 196         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 197         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 198         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 199         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 200         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 201         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 202         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 203         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 204         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 205         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 206         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 207         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 208         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 209         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 210         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 211         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 212         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 213         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 214         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 215         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 216         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 217         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 218         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 219         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 220         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 221         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 222         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 223         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 224         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 225         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 226         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 227         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 228         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 229         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 230         MLX5_CMD_OP_MAX
 231 };
 232
 233 struct mlx5_ifc_flow_table_fields_supported_bits {
 234         u8         outer_dmac[0x1];
 235         u8         outer_smac[0x1];
 236         u8         outer_ether_type[0x1];
 237         u8         reserved_at_3[0x1];
 238         u8         outer_first_prio[0x1];
 239         u8         outer_first_cfi[0x1];
 240         u8         outer_first_vid[0x1];
 241         u8         reserved_at_7[0x1];
 242         u8         outer_second_prio[0x1];
 243         u8         outer_second_cfi[0x1];
 244         u8         outer_second_vid[0x1];
 245         u8         reserved_at_b[0x1];
 246         u8         outer_sip[0x1];
 247         u8         outer_dip[0x1];
 248         u8         outer_frag[0x1];
 249         u8         outer_ip_protocol[0x1];
 250         u8         outer_ip_ecn[0x1];
 251         u8         outer_ip_dscp[0x1];
 252         u8         outer_udp_sport[0x1];
 253         u8         outer_udp_dport[0x1];
 254         u8         outer_tcp_sport[0x1];
 255         u8         outer_tcp_dport[0x1];
 256         u8         outer_tcp_flags[0x1];
 257         u8         outer_gre_protocol[0x1];
 258         u8         outer_gre_key[0x1];
 259         u8         outer_vxlan_vni[0x1];
 260         u8         reserved_at_1a[0x5];
 261         u8         source_eswitch_port[0x1];
 262
 263         u8         inner_dmac[0x1];
 264         u8         inner_smac[0x1];
 265         u8         inner_ether_type[0x1];
 266         u8         reserved_at_23[0x1];
 267         u8         inner_first_prio[0x1];
 268         u8         inner_first_cfi[0x1];
 269         u8         inner_first_vid[0x1];
 270         u8         reserved_at_27[0x1];
 271         u8         inner_second_prio[0x1];
 272         u8         inner_second_cfi[0x1];
 273         u8         inner_second_vid[0x1];
 274         u8         reserved_at_2b[0x1];
 275         u8         inner_sip[0x1];
 276         u8         inner_dip[0x1];
 277         u8         inner_frag[0x1];
 278         u8         inner_ip_protocol[0x1];
 279         u8         inner_ip_ecn[0x1];
 280         u8         inner_ip_dscp[0x1];
 281         u8         inner_udp_sport[0x1];
 282         u8         inner_udp_dport[0x1];
 283         u8         inner_tcp_sport[0x1];
 284         u8         inner_tcp_dport[0x1];
 285         u8         inner_tcp_flags[0x1];
 286         u8         reserved_at_37[0x9];
 287
 288         u8         reserved_at_40[0x40];
 289 };
 290
 291 struct mlx5_ifc_flow_table_prop_layout_bits {
 292         u8         ft_support[0x1];
 293         u8         reserved_at_1[0x1];
 294         u8         flow_counter[0x1];
 295         u8         flow_modify_en[0x1];
 296         u8         modify_root[0x1];
 297         u8         identified_miss_table_mode[0x1];
 298         u8         flow_table_modify[0x1];
 299         u8         encap[0x1];
 300         u8         decap[0x1];
 301         u8         reserved_at_9[0x17];
 302
 303         u8         reserved_at_20[0x2];
 304         u8         log_max_ft_size[0x6];
 305         u8         reserved_at_28[0x10];
 306         u8         max_ft_level[0x8];
 307
 308         u8         reserved_at_40[0x20];
 309
 310         u8         reserved_at_60[0x18];
 311         u8         log_max_ft_num[0x8];
 312
 313         u8         reserved_at_80[0x18];
 314         u8         log_max_destination[0x8];
 315
 316         u8         reserved_at_a0[0x18];
 317         u8         log_max_flow[0x8];
 318
 319         u8         reserved_at_c0[0x40];
 320
 321         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 322
 323         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 324 };
 325
 326 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 327         u8         send[0x1];
 328         u8         receive[0x1];
 329         u8         write[0x1];
 330         u8         read[0x1];
 331         u8         atomic[0x1];
 332         u8         srq_receive[0x1];
 333         u8         reserved_at_6[0x1a];
 334 };
 335
 336 struct mlx5_ifc_ipv4_layout_bits {
 337         u8         reserved_at_0[0x60];
 338
 339         u8         ipv4[0x20];
 340 };
 341
 342 struct mlx5_ifc_ipv6_layout_bits {
 343         u8         ipv6[16][0x8];
 344 };
 345
 346 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 347         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 348         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 349         u8         reserved_at_0[0x80];
 350 };
 351
 352 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 353         u8         smac_47_16[0x20];
 354
 355         u8         smac_15_0[0x10];
 356         u8         ethertype[0x10];
 357
 358         u8         dmac_47_16[0x20];
 359
 360         u8         dmac_15_0[0x10];
 361         u8         first_prio[0x3];
 362         u8         first_cfi[0x1];
 363         u8         first_vid[0xc];
 364
 365         u8         ip_protocol[0x8];
 366         u8         ip_dscp[0x6];
 367         u8         ip_ecn[0x2];
 368         u8         vlan_tag[0x1];
 369         u8         reserved_at_91[0x1];
 370         u8         frag[0x1];
 371         u8         reserved_at_93[0x4];
 372         u8         tcp_flags[0x9];
 373
 374         u8         tcp_sport[0x10];
 375         u8         tcp_dport[0x10];
 376
 377         u8         reserved_at_c0[0x20];
 378
 379         u8         udp_sport[0x10];
 380         u8         udp_dport[0x10];
 381
 382         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 383
 384         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 385 };
 386
 387 struct mlx5_ifc_fte_match_set_misc_bits {
 388         u8         reserved_at_0[0x8];
 389         u8         source_sqn[0x18];
 390
 391         u8         reserved_at_20[0x10];
 392         u8         source_port[0x10];
 393
 394         u8         outer_second_prio[0x3];
 395         u8         outer_second_cfi[0x1];
 396         u8         outer_second_vid[0xc];
 397         u8         inner_second_prio[0x3];
 398         u8         inner_second_cfi[0x1];
 399         u8         inner_second_vid[0xc];
 400
 401         u8         outer_second_vlan_tag[0x1];
 402         u8         inner_second_vlan_tag[0x1];
 403         u8         reserved_at_62[0xe];
 404         u8         gre_protocol[0x10];
 405
 406         u8         gre_key_h[0x18];
 407         u8         gre_key_l[0x8];
 408
 409         u8         vxlan_vni[0x18];
 410         u8         reserved_at_b8[0x8];
 411
 412         u8         reserved_at_c0[0x20];
 413
 414         u8         reserved_at_e0[0xc];
 415         u8         outer_ipv6_flow_label[0x14];
 416
 417         u8         reserved_at_100[0xc];
 418         u8         inner_ipv6_flow_label[0x14];
 419
 420         u8         reserved_at_120[0xe0];
 421 };
 422
 423 struct mlx5_ifc_cmd_pas_bits {
 424         u8         pa_h[0x20];
 425
 426         u8         pa_l[0x14];
 427         u8         reserved_at_34[0xc];
 428 };
 429
 430 struct mlx5_ifc_uint64_bits {
 431         u8         hi[0x20];
 432
 433         u8         lo[0x20];
 434 };
 435
 436 enum {
 437         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 438         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 439         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 440         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 441         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 442         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 443         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 444         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 445         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 446         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 447 };
 448
 449 struct mlx5_ifc_ads_bits {
 450         u8         fl[0x1];
 451         u8         free_ar[0x1];
 452         u8         reserved_at_2[0xe];
 453         u8         pkey_index[0x10];
 454
 455         u8         reserved_at_20[0x8];
 456         u8         grh[0x1];
 457         u8         mlid[0x7];
 458         u8         rlid[0x10];
 459
 460         u8         ack_timeout[0x5];
 461         u8         reserved_at_45[0x3];
 462         u8         src_addr_index[0x8];
 463         u8         reserved_at_50[0x4];
 464         u8         stat_rate[0x4];
 465         u8         hop_limit[0x8];
 466
 467         u8         reserved_at_60[0x4];
 468         u8         tclass[0x8];
 469         u8         flow_label[0x14];
 470
 471         u8         rgid_rip[16][0x8];
 472
 473         u8         reserved_at_100[0x4];
 474         u8         f_dscp[0x1];
 475         u8         f_ecn[0x1];
 476         u8         reserved_at_106[0x1];
 477         u8         f_eth_prio[0x1];
 478         u8         ecn[0x2];
 479         u8         dscp[0x6];
 480         u8         udp_sport[0x10];
 481
 482         u8         dei_cfi[0x1];
 483         u8         eth_prio[0x3];
 484         u8         sl[0x4];
 485         u8         port[0x8];
 486         u8         rmac_47_32[0x10];
 487
 488         u8         rmac_31_0[0x20];
 489 };
 490
 491 struct mlx5_ifc_flow_table_nic_cap_bits {
 492         u8         nic_rx_multi_path_tirs[0x1];
 493         u8         nic_rx_multi_path_tirs_fts[0x1];
 494         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 495         u8         reserved_at_3[0x1fd];
 496
 497         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 498
 499         u8         reserved_at_400[0x200];
 500
 501         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 502
 503         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 504
 505         u8         reserved_at_a00[0x200];
 506
 507         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 508
 509         u8         reserved_at_e00[0x7200];
 510 };
 511
 512 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 513         u8     reserved_at_0[0x200];
 514
 515         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 516
 517         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 518
 519         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 520
 521         u8      reserved_at_800[0x7800];
 522 };
 523
 524 struct mlx5_ifc_e_switch_cap_bits {
 525         u8         vport_svlan_strip[0x1];
 526         u8         vport_cvlan_strip[0x1];
 527         u8         vport_svlan_insert[0x1];
 528         u8         vport_cvlan_insert_if_not_exist[0x1];
 529         u8         vport_cvlan_insert_overwrite[0x1];
 530         u8         reserved_at_5[0x19];
 531         u8         nic_vport_node_guid_modify[0x1];
 532         u8         nic_vport_port_guid_modify[0x1];
 533
 534         u8         vxlan_encap_decap[0x1];
 535         u8         nvgre_encap_decap[0x1];
 536         u8         reserved_at_22[0x9];
 537         u8         log_max_encap_headers[0x5];
 538         u8         reserved_2b[0x6];
 539         u8         max_encap_header_size[0xa];
 540
 541         u8         reserved_40[0x7c0];
 542
 543 };
 544
 545 struct mlx5_ifc_qos_cap_bits {
 546         u8         packet_pacing[0x1];
 547         u8         esw_scheduling[0x1];
 548         u8         reserved_at_2[0x1e];
 549
 550         u8         reserved_at_20[0x20];
 551
 552         u8         packet_pacing_max_rate[0x20];
 553
 554         u8         packet_pacing_min_rate[0x20];
 555
 556         u8         reserved_at_80[0x10];
 557         u8         packet_pacing_rate_table_size[0x10];
 558
 559         u8         esw_element_type[0x10];
 560         u8         esw_tsar_type[0x10];
 561
 562         u8         reserved_at_c0[0x10];
 563         u8         max_qos_para_vport[0x10];
 564
 565         u8         max_tsar_bw_share[0x20];
 566
 567         u8         reserved_at_100[0x700];
 568 };
 569
 570 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 571         u8         csum_cap[0x1];
 572         u8         vlan_cap[0x1];
 573         u8         lro_cap[0x1];
 574         u8         lro_psh_flag[0x1];
 575         u8         lro_time_stamp[0x1];
 576         u8         reserved_at_5[0x3];
 577         u8         self_lb_en_modifiable[0x1];
 578         u8         reserved_at_9[0x2];
 579         u8         max_lso_cap[0x5];
 580         u8         multi_pkt_send_wqe[0x2];
 581         u8         wqe_inline_mode[0x2];
 582         u8         rss_ind_tbl_cap[0x4];
 583         u8         reg_umr_sq[0x1];
 584         u8         scatter_fcs[0x1];
 585         u8         reserved_at_1a[0x1];
 586         u8         tunnel_lso_const_out_ip_id[0x1];
 587         u8         reserved_at_1c[0x2];
 588         u8         tunnel_statless_gre[0x1];
 589         u8         tunnel_stateless_vxlan[0x1];
 590
 591         u8         reserved_at_20[0x20];
 592
 593         u8         reserved_at_40[0x10];
 594         u8         lro_min_mss_size[0x10];
 595
 596         u8         reserved_at_60[0x120];
 597
 598         u8         lro_timer_supported_periods[4][0x20];
 599
 600         u8         reserved_at_200[0x600];
 601 };
 602
 603 struct mlx5_ifc_roce_cap_bits {
 604         u8         roce_apm[0x1];
 605         u8         reserved_at_1[0x1f];
 606
 607         u8         reserved_at_20[0x60];
 608
 609         u8         reserved_at_80[0xc];
 610         u8         l3_type[0x4];
 611         u8         reserved_at_90[0x8];
 612         u8         roce_version[0x8];
 613
 614         u8         reserved_at_a0[0x10];
 615         u8         r_roce_dest_udp_port[0x10];
 616
 617         u8         r_roce_max_src_udp_port[0x10];
 618         u8         r_roce_min_src_udp_port[0x10];
 619
 620         u8         reserved_at_e0[0x10];
 621         u8         roce_address_table_size[0x10];
 622
 623         u8         reserved_at_100[0x700];
 624 };
 625
 626 enum {
 627         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 628         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 629         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 630         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 631         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 632         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 633         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 634         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 635         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 636 };
 637
 638 enum {
 639         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 640         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 641         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 642         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 643         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 644         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 645         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 646         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 647         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 648 };
 649
 650 struct mlx5_ifc_atomic_caps_bits {
 651         u8         reserved_at_0[0x40];
 652
 653         u8         atomic_req_8B_endianess_mode[0x2];
 654         u8         reserved_at_42[0x4];
 655         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 656
 657         u8         reserved_at_47[0x19];
 658
 659         u8         reserved_at_60[0x20];
 660
 661         u8         reserved_at_80[0x10];
 662         u8         atomic_operations[0x10];
 663
 664         u8         reserved_at_a0[0x10];
 665         u8         atomic_size_qp[0x10];
 666
 667         u8         reserved_at_c0[0x10];
 668         u8         atomic_size_dc[0x10];
 669
 670         u8         reserved_at_e0[0x720];
 671 };
 672
 673 struct mlx5_ifc_odp_cap_bits {
 674         u8         reserved_at_0[0x40];
 675
 676         u8         sig[0x1];
 677         u8         reserved_at_41[0x1f];
 678
 679         u8         reserved_at_60[0x20];
 680
 681         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 682
 683         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 684
 685         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 686
 687         u8         reserved_at_e0[0x720];
 688 };
 689
 690 struct mlx5_ifc_calc_op {
 691         u8        reserved_at_0[0x10];
 692         u8        reserved_at_10[0x9];
 693         u8        op_swap_endianness[0x1];
 694         u8        op_min[0x1];
 695         u8        op_xor[0x1];
 696         u8        op_or[0x1];
 697         u8        op_and[0x1];
 698         u8        op_max[0x1];
 699         u8        op_add[0x1];
 700 };
 701
 702 struct mlx5_ifc_vector_calc_cap_bits {
 703         u8         calc_matrix[0x1];
 704         u8         reserved_at_1[0x1f];
 705         u8         reserved_at_20[0x8];
 706         u8         max_vec_count[0x8];
 707         u8         reserved_at_30[0xd];
 708         u8         max_chunk_size[0x3];
 709         struct mlx5_ifc_calc_op calc0;
 710         struct mlx5_ifc_calc_op calc1;
 711         struct mlx5_ifc_calc_op calc2;
 712         struct mlx5_ifc_calc_op calc3;
 713
 714         u8         reserved_at_e0[0x720];
 715 };
 716
 717 enum {
 718         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 719         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 720         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 721 };
 722
 723 enum {
 724         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 725         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 726 };
 727
 728 enum {
 729         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 730         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 731         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 732         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 733         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 734 };
 735
 736 enum {
 737         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 738         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 739         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 740         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 741         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 742         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 743 };
 744
 745 enum {
 746         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 747         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 748 };
 749
 750 enum {
 751         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 752         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 753         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 754 };
 755
 756 enum {
 757         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 758         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 759 };
 760
 761 struct mlx5_ifc_cmd_hca_cap_bits {
 762         u8         reserved_at_0[0x80];
 763
 764         u8         log_max_srq_sz[0x8];
 765         u8         log_max_qp_sz[0x8];
 766         u8         reserved_at_90[0xb];
 767         u8         log_max_qp[0x5];
 768
 769         u8         reserved_at_a0[0xb];
 770         u8         log_max_srq[0x5];
 771         u8         reserved_at_b0[0x10];
 772
 773         u8         reserved_at_c0[0x8];
 774         u8         log_max_cq_sz[0x8];
 775         u8         reserved_at_d0[0xb];
 776         u8         log_max_cq[0x5];
 777
 778         u8         log_max_eq_sz[0x8];
 779         u8         reserved_at_e8[0x2];
 780         u8         log_max_mkey[0x6];
 781         u8         reserved_at_f0[0xc];
 782         u8         log_max_eq[0x4];
 783
 784         u8         max_indirection[0x8];
 785         u8         fixed_buffer_size[0x1];
 786         u8         log_max_mrw_sz[0x7];
 787         u8         reserved_at_110[0x2];
 788         u8         log_max_bsf_list_size[0x6];
 789         u8         umr_extended_translation_offset[0x1];
 790         u8         null_mkey[0x1];
 791         u8         log_max_klm_list_size[0x6];
 792
 793         u8         reserved_at_120[0xa];
 794         u8         log_max_ra_req_dc[0x6];
 795         u8         reserved_at_130[0xa];
 796         u8         log_max_ra_res_dc[0x6];
 797
 798         u8         reserved_at_140[0xa];
 799         u8         log_max_ra_req_qp[0x6];
 800         u8         reserved_at_150[0xa];
 801         u8         log_max_ra_res_qp[0x6];
 802
 803         u8         pad_cap[0x1];
 804         u8         cc_query_allowed[0x1];
 805         u8         cc_modify_allowed[0x1];
 806         u8         reserved_at_163[0xd];
 807         u8         gid_table_size[0x10];
 808
 809         u8         out_of_seq_cnt[0x1];
 810         u8         vport_counters[0x1];
 811         u8         retransmission_q_counters[0x1];
 812         u8         reserved_at_183[0x1];
 813         u8         modify_rq_counter_set_id[0x1];
 814         u8         reserved_at_185[0x1];
 815         u8         max_qp_cnt[0xa];
 816         u8         pkey_table_size[0x10];
 817
 818         u8         vport_group_manager[0x1];
 819         u8         vhca_group_manager[0x1];
 820         u8         ib_virt[0x1];
 821         u8         eth_virt[0x1];
 822         u8         reserved_at_1a4[0x1];
 823         u8         ets[0x1];
 824         u8         nic_flow_table[0x1];
 825         u8         eswitch_flow_table[0x1];
 826         u8         early_vf_enable[0x1];
 827         u8         reserved_at_1a9[0x2];
 828         u8         local_ca_ack_delay[0x5];
 829         u8         port_module_event[0x1];
 830         u8         reserved_at_1b1[0x1];
 831         u8         ports_check[0x1];
 832         u8         reserved_at_1b3[0x1];
 833         u8         disable_link_up[0x1];
 834         u8         beacon_led[0x1];
 835         u8         port_type[0x2];
 836         u8         num_ports[0x8];
 837
 838         u8         reserved_at_1c0[0x3];
 839         u8         log_max_msg[0x5];
 840         u8         reserved_at_1c8[0x4];
 841         u8         max_tc[0x4];
 842         u8         reserved_at_1d0[0x1];
 843         u8         dcbx[0x1];
 844         u8         reserved_at_1d2[0x4];
 845         u8         rol_s[0x1];
 846         u8         rol_g[0x1];
 847         u8         reserved_at_1d8[0x1];
 848         u8         wol_s[0x1];
 849         u8         wol_g[0x1];
 850         u8         wol_a[0x1];
 851         u8         wol_b[0x1];
 852         u8         wol_m[0x1];
 853         u8         wol_u[0x1];
 854         u8         wol_p[0x1];
 855
 856         u8         stat_rate_support[0x10];
 857         u8         reserved_at_1f0[0xc];
 858         u8         cqe_version[0x4];
 859
 860         u8         compact_address_vector[0x1];
 861         u8         striding_rq[0x1];
 862         u8         reserved_at_202[0x2];
 863         u8         ipoib_basic_offloads[0x1];
 864         u8         reserved_at_205[0xa];
 865         u8         drain_sigerr[0x1];
 866         u8         cmdif_checksum[0x2];
 867         u8         sigerr_cqe[0x1];
 868         u8         reserved_at_213[0x1];
 869         u8         wq_signature[0x1];
 870         u8         sctr_data_cqe[0x1];
 871         u8         reserved_at_216[0x1];
 872         u8         sho[0x1];
 873         u8         tph[0x1];
 874         u8         rf[0x1];
 875         u8         dct[0x1];
 876         u8         qos[0x1];
 877         u8         eth_net_offloads[0x1];
 878         u8         roce[0x1];
 879         u8         atomic[0x1];
 880         u8         reserved_at_21f[0x1];
 881
 882         u8         cq_oi[0x1];
 883         u8         cq_resize[0x1];
 884         u8         cq_moderation[0x1];
 885         u8         reserved_at_223[0x3];
 886         u8         cq_eq_remap[0x1];
 887         u8         pg[0x1];
 888         u8         block_lb_mc[0x1];
 889         u8         reserved_at_229[0x1];
 890         u8         scqe_break_moderation[0x1];
 891         u8         cq_period_start_from_cqe[0x1];
 892         u8         cd[0x1];
 893         u8         reserved_at_22d[0x1];
 894         u8         apm[0x1];
 895         u8         vector_calc[0x1];
 896         u8         umr_ptr_rlky[0x1];
 897         u8         imaicl[0x1];
 898         u8         reserved_at_232[0x4];
 899         u8         qkv[0x1];
 900         u8         pkv[0x1];
 901         u8         set_deth_sqpn[0x1];
 902         u8         reserved_at_239[0x3];
 903         u8         xrc[0x1];
 904         u8         ud[0x1];
 905         u8         uc[0x1];
 906         u8         rc[0x1];
 907
 908         u8         uar_4k[0x1];
 909         u8         reserved_at_241[0x9];
 910         u8         uar_sz[0x6];
 911         u8         reserved_at_250[0x8];
 912         u8         log_pg_sz[0x8];
 913
 914         u8         bf[0x1];
 915         u8         driver_version[0x1];
 916         u8         pad_tx_eth_packet[0x1];
 917         u8         reserved_at_263[0x8];
 918         u8         log_bf_reg_size[0x5];
 919
 920         u8         reserved_at_270[0xb];
 921         u8         lag_master[0x1];
 922         u8         num_lag_ports[0x4];
 923
 924         u8         reserved_at_280[0x10];
 925         u8         max_wqe_sz_sq[0x10];
 926
 927         u8         reserved_at_2a0[0x10];
 928         u8         max_wqe_sz_rq[0x10];
 929
 930         u8         reserved_at_2c0[0x10];
 931         u8         max_wqe_sz_sq_dc[0x10];
 932
 933         u8         reserved_at_2e0[0x7];
 934         u8         max_qp_mcg[0x19];
 935
 936         u8         reserved_at_300[0x18];
 937         u8         log_max_mcg[0x8];
 938
 939         u8         reserved_at_320[0x3];
 940         u8         log_max_transport_domain[0x5];
 941         u8         reserved_at_328[0x3];
 942         u8         log_max_pd[0x5];
 943         u8         reserved_at_330[0xb];
 944         u8         log_max_xrcd[0x5];
 945
 946         u8         reserved_at_340[0x8];
 947         u8         log_max_flow_counter_bulk[0x8];
 948         u8         max_flow_counter[0x10];
 949
 950
 951         u8         reserved_at_360[0x3];
 952         u8         log_max_rq[0x5];
 953         u8         reserved_at_368[0x3];
 954         u8         log_max_sq[0x5];
 955         u8         reserved_at_370[0x3];
 956         u8         log_max_tir[0x5];
 957         u8         reserved_at_378[0x3];
 958         u8         log_max_tis[0x5];
 959
 960         u8         basic_cyclic_rcv_wqe[0x1];
 961         u8         reserved_at_381[0x2];
 962         u8         log_max_rmp[0x5];
 963         u8         reserved_at_388[0x3];
 964         u8         log_max_rqt[0x5];
 965         u8         reserved_at_390[0x3];
 966         u8         log_max_rqt_size[0x5];
 967         u8         reserved_at_398[0x3];
 968         u8         log_max_tis_per_sq[0x5];
 969
 970         u8         reserved_at_3a0[0x3];
 971         u8         log_max_stride_sz_rq[0x5];
 972         u8         reserved_at_3a8[0x3];
 973         u8         log_min_stride_sz_rq[0x5];
 974         u8         reserved_at_3b0[0x3];
 975         u8         log_max_stride_sz_sq[0x5];
 976         u8         reserved_at_3b8[0x3];
 977         u8         log_min_stride_sz_sq[0x5];
 978
 979         u8         reserved_at_3c0[0x1b];
 980         u8         log_max_wq_sz[0x5];
 981
 982         u8         nic_vport_change_event[0x1];
 983         u8         reserved_at_3e1[0xa];
 984         u8         log_max_vlan_list[0x5];
 985         u8         reserved_at_3f0[0x3];
 986         u8         log_max_current_mc_list[0x5];
 987         u8         reserved_at_3f8[0x3];
 988         u8         log_max_current_uc_list[0x5];
 989
 990         u8         reserved_at_400[0x80];
 991
 992         u8         reserved_at_480[0x3];
 993         u8         log_max_l2_table[0x5];
 994         u8         reserved_at_488[0x8];
 995         u8         log_uar_page_sz[0x10];
 996
 997         u8         reserved_at_4a0[0x20];
 998         u8         device_frequency_mhz[0x20];
 999         u8         device_frequency_khz[0x20];
1000
1001         u8         reserved_at_500[0x20];
1002         u8         num_of_uars_per_page[0x20];
1003         u8         reserved_at_540[0x40];
1004
1005         u8         reserved_at_580[0x3f];
1006         u8         cqe_compression[0x1];
1007
1008         u8         cqe_compression_timeout[0x10];
1009         u8         cqe_compression_max_num[0x10];
1010
1011         u8         reserved_at_5e0[0x10];
1012         u8         tag_matching[0x1];
1013         u8         rndv_offload_rc[0x1];
1014         u8         rndv_offload_dc[0x1];
1015         u8         log_tag_matching_list_sz[0x5];
1016         u8         reserved_at_5f8[0x3];
1017         u8         log_max_xrq[0x5];
1018
1019         u8         reserved_at_600[0x200];
1020 };
1021
1022 enum mlx5_flow_destination_type {
1023         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1024         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1025         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1026
1027         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1028 };
1029
1030 struct mlx5_ifc_dest_format_struct_bits {
1031         u8         destination_type[0x8];
1032         u8         destination_id[0x18];
1033
1034         u8         reserved_at_20[0x20];
1035 };
1036
1037 struct mlx5_ifc_flow_counter_list_bits {
1038         u8         clear[0x1];
1039         u8         num_of_counters[0xf];
1040         u8         flow_counter_id[0x10];
1041
1042         u8         reserved_at_20[0x20];
1043 };
1044
1045 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1046         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1047         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1048         u8         reserved_at_0[0x40];
1049 };
1050
1051 struct mlx5_ifc_fte_match_param_bits {
1052         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1053
1054         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1055
1056         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1057
1058         u8         reserved_at_600[0xa00];
1059 };
1060
1061 enum {
1062         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1063         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1064         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1065         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1066         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1067 };
1068
1069 struct mlx5_ifc_rx_hash_field_select_bits {
1070         u8         l3_prot_type[0x1];
1071         u8         l4_prot_type[0x1];
1072         u8         selected_fields[0x1e];
1073 };
1074
1075 enum {
1076         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1077         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1078 };
1079
1080 enum {
1081         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1082         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1083 };
1084
1085 struct mlx5_ifc_wq_bits {
1086         u8         wq_type[0x4];
1087         u8         wq_signature[0x1];
1088         u8         end_padding_mode[0x2];
1089         u8         cd_slave[0x1];
1090         u8         reserved_at_8[0x18];
1091
1092         u8         hds_skip_first_sge[0x1];
1093         u8         log2_hds_buf_size[0x3];
1094         u8         reserved_at_24[0x7];
1095         u8         page_offset[0x5];
1096         u8         lwm[0x10];
1097
1098         u8         reserved_at_40[0x8];
1099         u8         pd[0x18];
1100
1101         u8         reserved_at_60[0x8];
1102         u8         uar_page[0x18];
1103
1104         u8         dbr_addr[0x40];
1105
1106         u8         hw_counter[0x20];
1107
1108         u8         sw_counter[0x20];
1109
1110         u8         reserved_at_100[0xc];
1111         u8         log_wq_stride[0x4];
1112         u8         reserved_at_110[0x3];
1113         u8         log_wq_pg_sz[0x5];
1114         u8         reserved_at_118[0x3];
1115         u8         log_wq_sz[0x5];
1116
1117         u8         reserved_at_120[0x15];
1118         u8         log_wqe_num_of_strides[0x3];
1119         u8         two_byte_shift_en[0x1];
1120         u8         reserved_at_139[0x4];
1121         u8         log_wqe_stride_size[0x3];
1122
1123         u8         reserved_at_140[0x4c0];
1124
1125         struct mlx5_ifc_cmd_pas_bits pas[0];
1126 };
1127
1128 struct mlx5_ifc_rq_num_bits {
1129         u8         reserved_at_0[0x8];
1130         u8         rq_num[0x18];
1131 };
1132
1133 struct mlx5_ifc_mac_address_layout_bits {
1134         u8         reserved_at_0[0x10];
1135         u8         mac_addr_47_32[0x10];
1136
1137         u8         mac_addr_31_0[0x20];
1138 };
1139
1140 struct mlx5_ifc_vlan_layout_bits {
1141         u8         reserved_at_0[0x14];
1142         u8         vlan[0x0c];
1143
1144         u8         reserved_at_20[0x20];
1145 };
1146
1147 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1148         u8         reserved_at_0[0xa0];
1149
1150         u8         min_time_between_cnps[0x20];
1151
1152         u8         reserved_at_c0[0x12];
1153         u8         cnp_dscp[0x6];
1154         u8         reserved_at_d8[0x5];
1155         u8         cnp_802p_prio[0x3];
1156
1157         u8         reserved_at_e0[0x720];
1158 };
1159
1160 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1161         u8         reserved_at_0[0x60];
1162
1163         u8         reserved_at_60[0x4];
1164         u8         clamp_tgt_rate[0x1];
1165         u8         reserved_at_65[0x3];
1166         u8         clamp_tgt_rate_after_time_inc[0x1];
1167         u8         reserved_at_69[0x17];
1168
1169         u8         reserved_at_80[0x20];
1170
1171         u8         rpg_time_reset[0x20];
1172
1173         u8         rpg_byte_reset[0x20];
1174
1175         u8         rpg_threshold[0x20];
1176
1177         u8         rpg_max_rate[0x20];
1178
1179         u8         rpg_ai_rate[0x20];
1180
1181         u8         rpg_hai_rate[0x20];
1182
1183         u8         rpg_gd[0x20];
1184
1185         u8         rpg_min_dec_fac[0x20];
1186
1187         u8         rpg_min_rate[0x20];
1188
1189         u8         reserved_at_1c0[0xe0];
1190
1191         u8         rate_to_set_on_first_cnp[0x20];
1192
1193         u8         dce_tcp_g[0x20];
1194
1195         u8         dce_tcp_rtt[0x20];
1196
1197         u8         rate_reduce_monitor_period[0x20];
1198
1199         u8         reserved_at_320[0x20];
1200
1201         u8         initial_alpha_value[0x20];
1202
1203         u8         reserved_at_360[0x4a0];
1204 };
1205
1206 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1207         u8         reserved_at_0[0x80];
1208
1209         u8         rppp_max_rps[0x20];
1210
1211         u8         rpg_time_reset[0x20];
1212
1213         u8         rpg_byte_reset[0x20];
1214
1215         u8         rpg_threshold[0x20];
1216
1217         u8         rpg_max_rate[0x20];
1218
1219         u8         rpg_ai_rate[0x20];
1220
1221         u8         rpg_hai_rate[0x20];
1222
1223         u8         rpg_gd[0x20];
1224
1225         u8         rpg_min_dec_fac[0x20];
1226
1227         u8         rpg_min_rate[0x20];
1228
1229         u8         reserved_at_1c0[0x640];
1230 };
1231
1232 enum {
1233         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1234         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1235         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1236 };
1237
1238 struct mlx5_ifc_resize_field_select_bits {
1239         u8         resize_field_select[0x20];
1240 };
1241
1242 enum {
1243         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1244         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1245         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1246         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1247 };
1248
1249 struct mlx5_ifc_modify_field_select_bits {
1250         u8         modify_field_select[0x20];
1251 };
1252
1253 struct mlx5_ifc_field_select_r_roce_np_bits {
1254         u8         field_select_r_roce_np[0x20];
1255 };
1256
1257 struct mlx5_ifc_field_select_r_roce_rp_bits {
1258         u8         field_select_r_roce_rp[0x20];
1259 };
1260
1261 enum {
1262         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1263         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1264         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1265         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1266         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1267         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1268         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1269         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1270         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1271         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1272 };
1273
1274 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1275         u8         field_select_8021qaurp[0x20];
1276 };
1277
1278 struct mlx5_ifc_phys_layer_cntrs_bits {
1279         u8         time_since_last_clear_high[0x20];
1280
1281         u8         time_since_last_clear_low[0x20];
1282
1283         u8         symbol_errors_high[0x20];
1284
1285         u8         symbol_errors_low[0x20];
1286
1287         u8         sync_headers_errors_high[0x20];
1288
1289         u8         sync_headers_errors_low[0x20];
1290
1291         u8         edpl_bip_errors_lane0_high[0x20];
1292
1293         u8         edpl_bip_errors_lane0_low[0x20];
1294
1295         u8         edpl_bip_errors_lane1_high[0x20];
1296
1297         u8         edpl_bip_errors_lane1_low[0x20];
1298
1299         u8         edpl_bip_errors_lane2_high[0x20];
1300
1301         u8         edpl_bip_errors_lane2_low[0x20];
1302
1303         u8         edpl_bip_errors_lane3_high[0x20];
1304
1305         u8         edpl_bip_errors_lane3_low[0x20];
1306
1307         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1308
1309         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1310
1311         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1312
1313         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1314
1315         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1316
1317         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1318
1319         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1320
1321         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1322
1323         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1324
1325         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1326
1327         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1328
1329         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1330
1331         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1332
1333         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1334
1335         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1336
1337         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1338
1339         u8         rs_fec_corrected_blocks_high[0x20];
1340
1341         u8         rs_fec_corrected_blocks_low[0x20];
1342
1343         u8         rs_fec_uncorrectable_blocks_high[0x20];
1344
1345         u8         rs_fec_uncorrectable_blocks_low[0x20];
1346
1347         u8         rs_fec_no_errors_blocks_high[0x20];
1348
1349         u8         rs_fec_no_errors_blocks_low[0x20];
1350
1351         u8         rs_fec_single_error_blocks_high[0x20];
1352
1353         u8         rs_fec_single_error_blocks_low[0x20];
1354
1355         u8         rs_fec_corrected_symbols_total_high[0x20];
1356
1357         u8         rs_fec_corrected_symbols_total_low[0x20];
1358
1359         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1360
1361         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1362
1363         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1364
1365         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1366
1367         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1368
1369         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1370
1371         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1372
1373         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1374
1375         u8         link_down_events[0x20];
1376
1377         u8         successful_recovery_events[0x20];
1378
1379         u8         reserved_at_640[0x180];
1380 };
1381
1382 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1383         u8         symbol_error_counter[0x10];
1384
1385         u8         link_error_recovery_counter[0x8];
1386
1387         u8         link_downed_counter[0x8];
1388
1389         u8         port_rcv_errors[0x10];
1390
1391         u8         port_rcv_remote_physical_errors[0x10];
1392
1393         u8         port_rcv_switch_relay_errors[0x10];
1394
1395         u8         port_xmit_discards[0x10];
1396
1397         u8         port_xmit_constraint_errors[0x8];
1398
1399         u8         port_rcv_constraint_errors[0x8];
1400
1401         u8         reserved_at_70[0x8];
1402
1403         u8         link_overrun_errors[0x8];
1404
1405         u8         reserved_at_80[0x10];
1406
1407         u8         vl_15_dropped[0x10];
1408
1409         u8         reserved_at_a0[0xa0];
1410 };
1411
1412 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1413         u8         transmit_queue_high[0x20];
1414
1415         u8         transmit_queue_low[0x20];
1416
1417         u8         reserved_at_40[0x780];
1418 };
1419
1420 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1421         u8         rx_octets_high[0x20];
1422
1423         u8         rx_octets_low[0x20];
1424
1425         u8         reserved_at_40[0xc0];
1426
1427         u8         rx_frames_high[0x20];
1428
1429         u8         rx_frames_low[0x20];
1430
1431         u8         tx_octets_high[0x20];
1432
1433         u8         tx_octets_low[0x20];
1434
1435         u8         reserved_at_180[0xc0];
1436
1437         u8         tx_frames_high[0x20];
1438
1439         u8         tx_frames_low[0x20];
1440
1441         u8         rx_pause_high[0x20];
1442
1443         u8         rx_pause_low[0x20];
1444
1445         u8         rx_pause_duration_high[0x20];
1446
1447         u8         rx_pause_duration_low[0x20];
1448
1449         u8         tx_pause_high[0x20];
1450
1451         u8         tx_pause_low[0x20];
1452
1453         u8         tx_pause_duration_high[0x20];
1454
1455         u8         tx_pause_duration_low[0x20];
1456
1457         u8         rx_pause_transition_high[0x20];
1458
1459         u8         rx_pause_transition_low[0x20];
1460
1461         u8         reserved_at_3c0[0x400];
1462 };
1463
1464 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1465         u8         port_transmit_wait_high[0x20];
1466
1467         u8         port_transmit_wait_low[0x20];
1468
1469         u8         reserved_at_40[0x780];
1470 };
1471
1472 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1473         u8         dot3stats_alignment_errors_high[0x20];
1474
1475         u8         dot3stats_alignment_errors_low[0x20];
1476
1477         u8         dot3stats_fcs_errors_high[0x20];
1478
1479         u8         dot3stats_fcs_errors_low[0x20];
1480
1481         u8         dot3stats_single_collision_frames_high[0x20];
1482
1483         u8         dot3stats_single_collision_frames_low[0x20];
1484
1485         u8         dot3stats_multiple_collision_frames_high[0x20];
1486
1487         u8         dot3stats_multiple_collision_frames_low[0x20];
1488
1489         u8         dot3stats_sqe_test_errors_high[0x20];
1490
1491         u8         dot3stats_sqe_test_errors_low[0x20];
1492
1493         u8         dot3stats_deferred_transmissions_high[0x20];
1494
1495         u8         dot3stats_deferred_transmissions_low[0x20];
1496
1497         u8         dot3stats_late_collisions_high[0x20];
1498
1499         u8         dot3stats_late_collisions_low[0x20];
1500
1501         u8         dot3stats_excessive_collisions_high[0x20];
1502
1503         u8         dot3stats_excessive_collisions_low[0x20];
1504
1505         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1506
1507         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1508
1509         u8         dot3stats_carrier_sense_errors_high[0x20];
1510
1511         u8         dot3stats_carrier_sense_errors_low[0x20];
1512
1513         u8         dot3stats_frame_too_longs_high[0x20];
1514
1515         u8         dot3stats_frame_too_longs_low[0x20];
1516
1517         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1518
1519         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1520
1521         u8         dot3stats_symbol_errors_high[0x20];
1522
1523         u8         dot3stats_symbol_errors_low[0x20];
1524
1525         u8         dot3control_in_unknown_opcodes_high[0x20];
1526
1527         u8         dot3control_in_unknown_opcodes_low[0x20];
1528
1529         u8         dot3in_pause_frames_high[0x20];
1530
1531         u8         dot3in_pause_frames_low[0x20];
1532
1533         u8         dot3out_pause_frames_high[0x20];
1534
1535         u8         dot3out_pause_frames_low[0x20];
1536
1537         u8         reserved_at_400[0x3c0];
1538 };
1539
1540 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1541         u8         ether_stats_drop_events_high[0x20];
1542
1543         u8         ether_stats_drop_events_low[0x20];
1544
1545         u8         ether_stats_octets_high[0x20];
1546
1547         u8         ether_stats_octets_low[0x20];
1548
1549         u8         ether_stats_pkts_high[0x20];
1550
1551         u8         ether_stats_pkts_low[0x20];
1552
1553         u8         ether_stats_broadcast_pkts_high[0x20];
1554
1555         u8         ether_stats_broadcast_pkts_low[0x20];
1556
1557         u8         ether_stats_multicast_pkts_high[0x20];
1558
1559         u8         ether_stats_multicast_pkts_low[0x20];
1560
1561         u8         ether_stats_crc_align_errors_high[0x20];
1562
1563         u8         ether_stats_crc_align_errors_low[0x20];
1564
1565         u8         ether_stats_undersize_pkts_high[0x20];
1566
1567         u8         ether_stats_undersize_pkts_low[0x20];
1568
1569         u8         ether_stats_oversize_pkts_high[0x20];
1570
1571         u8         ether_stats_oversize_pkts_low[0x20];
1572
1573         u8         ether_stats_fragments_high[0x20];
1574
1575         u8         ether_stats_fragments_low[0x20];
1576
1577         u8         ether_stats_jabbers_high[0x20];
1578
1579         u8         ether_stats_jabbers_low[0x20];
1580
1581         u8         ether_stats_collisions_high[0x20];
1582
1583         u8         ether_stats_collisions_low[0x20];
1584
1585         u8         ether_stats_pkts64octets_high[0x20];
1586
1587         u8         ether_stats_pkts64octets_low[0x20];
1588
1589         u8         ether_stats_pkts65to127octets_high[0x20];
1590
1591         u8         ether_stats_pkts65to127octets_low[0x20];
1592
1593         u8         ether_stats_pkts128to255octets_high[0x20];
1594
1595         u8         ether_stats_pkts128to255octets_low[0x20];
1596
1597         u8         ether_stats_pkts256to511octets_high[0x20];
1598
1599         u8         ether_stats_pkts256to511octets_low[0x20];
1600
1601         u8         ether_stats_pkts512to1023octets_high[0x20];
1602
1603         u8         ether_stats_pkts512to1023octets_low[0x20];
1604
1605         u8         ether_stats_pkts1024to1518octets_high[0x20];
1606
1607         u8         ether_stats_pkts1024to1518octets_low[0x20];
1608
1609         u8         ether_stats_pkts1519to2047octets_high[0x20];
1610
1611         u8         ether_stats_pkts1519to2047octets_low[0x20];
1612
1613         u8         ether_stats_pkts2048to4095octets_high[0x20];
1614
1615         u8         ether_stats_pkts2048to4095octets_low[0x20];
1616
1617         u8         ether_stats_pkts4096to8191octets_high[0x20];
1618
1619         u8         ether_stats_pkts4096to8191octets_low[0x20];
1620
1621         u8         ether_stats_pkts8192to10239octets_high[0x20];
1622
1623         u8         ether_stats_pkts8192to10239octets_low[0x20];
1624
1625         u8         reserved_at_540[0x280];
1626 };
1627
1628 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1629         u8         if_in_octets_high[0x20];
1630
1631         u8         if_in_octets_low[0x20];
1632
1633         u8         if_in_ucast_pkts_high[0x20];
1634
1635         u8         if_in_ucast_pkts_low[0x20];
1636
1637         u8         if_in_discards_high[0x20];
1638
1639         u8         if_in_discards_low[0x20];
1640
1641         u8         if_in_errors_high[0x20];
1642
1643         u8         if_in_errors_low[0x20];
1644
1645         u8         if_in_unknown_protos_high[0x20];
1646
1647         u8         if_in_unknown_protos_low[0x20];
1648
1649         u8         if_out_octets_high[0x20];
1650
1651         u8         if_out_octets_low[0x20];
1652
1653         u8         if_out_ucast_pkts_high[0x20];
1654
1655         u8         if_out_ucast_pkts_low[0x20];
1656
1657         u8         if_out_discards_high[0x20];
1658
1659         u8         if_out_discards_low[0x20];
1660
1661         u8         if_out_errors_high[0x20];
1662
1663         u8         if_out_errors_low[0x20];
1664
1665         u8         if_in_multicast_pkts_high[0x20];
1666
1667         u8         if_in_multicast_pkts_low[0x20];
1668
1669         u8         if_in_broadcast_pkts_high[0x20];
1670
1671         u8         if_in_broadcast_pkts_low[0x20];
1672
1673         u8         if_out_multicast_pkts_high[0x20];
1674
1675         u8         if_out_multicast_pkts_low[0x20];
1676
1677         u8         if_out_broadcast_pkts_high[0x20];
1678
1679         u8         if_out_broadcast_pkts_low[0x20];
1680
1681         u8         reserved_at_340[0x480];
1682 };
1683
1684 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1685         u8         a_frames_transmitted_ok_high[0x20];
1686
1687         u8         a_frames_transmitted_ok_low[0x20];
1688
1689         u8         a_frames_received_ok_high[0x20];
1690
1691         u8         a_frames_received_ok_low[0x20];
1692
1693         u8         a_frame_check_sequence_errors_high[0x20];
1694
1695         u8         a_frame_check_sequence_errors_low[0x20];
1696
1697         u8         a_alignment_errors_high[0x20];
1698
1699         u8         a_alignment_errors_low[0x20];
1700
1701         u8         a_octets_transmitted_ok_high[0x20];
1702
1703         u8         a_octets_transmitted_ok_low[0x20];
1704
1705         u8         a_octets_received_ok_high[0x20];
1706
1707         u8         a_octets_received_ok_low[0x20];
1708
1709         u8         a_multicast_frames_xmitted_ok_high[0x20];
1710
1711         u8         a_multicast_frames_xmitted_ok_low[0x20];
1712
1713         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1714
1715         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1716
1717         u8         a_multicast_frames_received_ok_high[0x20];
1718
1719         u8         a_multicast_frames_received_ok_low[0x20];
1720
1721         u8         a_broadcast_frames_received_ok_high[0x20];
1722
1723         u8         a_broadcast_frames_received_ok_low[0x20];
1724
1725         u8         a_in_range_length_errors_high[0x20];
1726
1727         u8         a_in_range_length_errors_low[0x20];
1728
1729         u8         a_out_of_range_length_field_high[0x20];
1730
1731         u8         a_out_of_range_length_field_low[0x20];
1732
1733         u8         a_frame_too_long_errors_high[0x20];
1734
1735         u8         a_frame_too_long_errors_low[0x20];
1736
1737         u8         a_symbol_error_during_carrier_high[0x20];
1738
1739         u8         a_symbol_error_during_carrier_low[0x20];
1740
1741         u8         a_mac_control_frames_transmitted_high[0x20];
1742
1743         u8         a_mac_control_frames_transmitted_low[0x20];
1744
1745         u8         a_mac_control_frames_received_high[0x20];
1746
1747         u8         a_mac_control_frames_received_low[0x20];
1748
1749         u8         a_unsupported_opcodes_received_high[0x20];
1750
1751         u8         a_unsupported_opcodes_received_low[0x20];
1752
1753         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1754
1755         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1756
1757         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1758
1759         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1760
1761         u8         reserved_at_4c0[0x300];
1762 };
1763
1764 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1765         u8         life_time_counter_high[0x20];
1766
1767         u8         life_time_counter_low[0x20];
1768
1769         u8         rx_errors[0x20];
1770
1771         u8         tx_errors[0x20];
1772
1773         u8         l0_to_recovery_eieos[0x20];
1774
1775         u8         l0_to_recovery_ts[0x20];
1776
1777         u8         l0_to_recovery_framing[0x20];
1778
1779         u8         l0_to_recovery_retrain[0x20];
1780
1781         u8         crc_error_dllp[0x20];
1782
1783         u8         crc_error_tlp[0x20];
1784
1785         u8         reserved_at_140[0x680];
1786 };
1787
1788 struct mlx5_ifc_pcie_tas_cntrs_grp_data_layout_bits {
1789         u8         life_time_counter_high[0x20];
1790
1791         u8         life_time_counter_low[0x20];
1792
1793         u8         time_to_boot_image_start[0x20];
1794
1795         u8         time_to_link_image[0x20];
1796
1797         u8         calibration_time[0x20];
1798
1799         u8         time_to_first_perst[0x20];
1800
1801         u8         time_to_detect_state[0x20];
1802
1803         u8         time_to_l0[0x20];
1804
1805         u8         time_to_crs_en[0x20];
1806
1807         u8         time_to_plastic_image_start[0x20];
1808
1809         u8         time_to_iron_image_start[0x20];
1810
1811         u8         perst_handler[0x20];
1812
1813         u8         times_in_l1[0x20];
1814
1815         u8         times_in_l23[0x20];
1816
1817         u8         dl_down[0x20];
1818
1819         u8         config_cycle1usec[0x20];
1820
1821         u8         config_cycle2to7usec[0x20];
1822
1823         u8         config_cycle_8to15usec[0x20];
1824
1825         u8         config_cycle_16_to_63usec[0x20];
1826
1827         u8         config_cycle_64usec[0x20];
1828
1829         u8         correctable_err_msg_sent[0x20];
1830
1831         u8         non_fatal_err_msg_sent[0x20];
1832
1833         u8         fatal_err_msg_sent[0x20];
1834
1835         u8         reserved_at_2e0[0x4e0];
1836 };
1837
1838 struct mlx5_ifc_cmd_inter_comp_event_bits {
1839         u8         command_completion_vector[0x20];
1840
1841         u8         reserved_at_20[0xc0];
1842 };
1843
1844 struct mlx5_ifc_stall_vl_event_bits {
1845         u8         reserved_at_0[0x18];
1846         u8         port_num[0x1];
1847         u8         reserved_at_19[0x3];
1848         u8         vl[0x4];
1849
1850         u8         reserved_at_20[0xa0];
1851 };
1852
1853 struct mlx5_ifc_db_bf_congestion_event_bits {
1854         u8         event_subtype[0x8];
1855         u8         reserved_at_8[0x8];
1856         u8         congestion_level[0x8];
1857         u8         reserved_at_18[0x8];
1858
1859         u8         reserved_at_20[0xa0];
1860 };
1861
1862 struct mlx5_ifc_gpio_event_bits {
1863         u8         reserved_at_0[0x60];
1864
1865         u8         gpio_event_hi[0x20];
1866
1867         u8         gpio_event_lo[0x20];
1868
1869         u8         reserved_at_a0[0x40];
1870 };
1871
1872 struct mlx5_ifc_port_state_change_event_bits {
1873         u8         reserved_at_0[0x40];
1874
1875         u8         port_num[0x4];
1876         u8         reserved_at_44[0x1c];
1877
1878         u8         reserved_at_60[0x80];
1879 };
1880
1881 struct mlx5_ifc_dropped_packet_logged_bits {
1882         u8         reserved_at_0[0xe0];
1883 };
1884
1885 enum {
1886         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1887         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1888 };
1889
1890 struct mlx5_ifc_cq_error_bits {
1891         u8         reserved_at_0[0x8];
1892         u8         cqn[0x18];
1893
1894         u8         reserved_at_20[0x20];
1895
1896         u8         reserved_at_40[0x18];
1897         u8         syndrome[0x8];
1898
1899         u8         reserved_at_60[0x80];
1900 };
1901
1902 struct mlx5_ifc_rdma_page_fault_event_bits {
1903         u8         bytes_committed[0x20];
1904
1905         u8         r_key[0x20];
1906
1907         u8         reserved_at_40[0x10];
1908         u8         packet_len[0x10];
1909
1910         u8         rdma_op_len[0x20];
1911
1912         u8         rdma_va[0x40];
1913
1914         u8         reserved_at_c0[0x5];
1915         u8         rdma[0x1];
1916         u8         write[0x1];
1917         u8         requestor[0x1];
1918         u8         qp_number[0x18];
1919 };
1920
1921 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1922         u8         bytes_committed[0x20];
1923
1924         u8         reserved_at_20[0x10];
1925         u8         wqe_index[0x10];
1926
1927         u8         reserved_at_40[0x10];
1928         u8         len[0x10];
1929
1930         u8         reserved_at_60[0x60];
1931
1932         u8         reserved_at_c0[0x5];
1933         u8         rdma[0x1];
1934         u8         write_read[0x1];
1935         u8         requestor[0x1];
1936         u8         qpn[0x18];
1937 };
1938
1939 struct mlx5_ifc_qp_events_bits {
1940         u8         reserved_at_0[0xa0];
1941
1942         u8         type[0x8];
1943         u8         reserved_at_a8[0x18];
1944
1945         u8         reserved_at_c0[0x8];
1946         u8         qpn_rqn_sqn[0x18];
1947 };
1948
1949 struct mlx5_ifc_dct_events_bits {
1950         u8         reserved_at_0[0xc0];
1951
1952         u8         reserved_at_c0[0x8];
1953         u8         dct_number[0x18];
1954 };
1955
1956 struct mlx5_ifc_comp_event_bits {
1957         u8         reserved_at_0[0xc0];
1958
1959         u8         reserved_at_c0[0x8];
1960         u8         cq_number[0x18];
1961 };
1962
1963 enum {
1964         MLX5_QPC_STATE_RST        = 0x0,
1965         MLX5_QPC_STATE_INIT       = 0x1,
1966         MLX5_QPC_STATE_RTR        = 0x2,
1967         MLX5_QPC_STATE_RTS        = 0x3,
1968         MLX5_QPC_STATE_SQER       = 0x4,
1969         MLX5_QPC_STATE_ERR        = 0x6,
1970         MLX5_QPC_STATE_SQD        = 0x7,
1971         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1972 };
1973
1974 enum {
1975         MLX5_QPC_ST_RC            = 0x0,
1976         MLX5_QPC_ST_UC            = 0x1,
1977         MLX5_QPC_ST_UD            = 0x2,
1978         MLX5_QPC_ST_XRC           = 0x3,
1979         MLX5_QPC_ST_DCI           = 0x5,
1980         MLX5_QPC_ST_QP0           = 0x7,
1981         MLX5_QPC_ST_QP1           = 0x8,
1982         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1983         MLX5_QPC_ST_REG_UMR       = 0xc,
1984 };
1985
1986 enum {
1987         MLX5_QPC_PM_STATE_ARMED     = 0x0,
1988         MLX5_QPC_PM_STATE_REARM     = 0x1,
1989         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1990         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1991 };
1992
1993 enum {
1994         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1995         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1996 };
1997
1998 enum {
1999         MLX5_QPC_MTU_256_BYTES        = 0x1,
2000         MLX5_QPC_MTU_512_BYTES        = 0x2,
2001         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2002         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2003         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2004         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2005 };
2006
2007 enum {
2008         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2009         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2010         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2011         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2012         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2013         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2014         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2015         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2016 };
2017
2018 enum {
2019         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2020         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2021         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2022 };
2023
2024 enum {
2025         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2026         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2027         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2028 };
2029
2030 struct mlx5_ifc_qpc_bits {
2031         u8         state[0x4];
2032         u8         lag_tx_port_affinity[0x4];
2033         u8         st[0x8];
2034         u8         reserved_at_10[0x3];
2035         u8         pm_state[0x2];
2036         u8         reserved_at_15[0x7];
2037         u8         end_padding_mode[0x2];
2038         u8         reserved_at_1e[0x2];
2039
2040         u8         wq_signature[0x1];
2041         u8         block_lb_mc[0x1];
2042         u8         atomic_like_write_en[0x1];
2043         u8         latency_sensitive[0x1];
2044         u8         reserved_at_24[0x1];
2045         u8         drain_sigerr[0x1];
2046         u8         reserved_at_26[0x2];
2047         u8         pd[0x18];
2048
2049         u8         mtu[0x3];
2050         u8         log_msg_max[0x5];
2051         u8         reserved_at_48[0x1];
2052         u8         log_rq_size[0x4];
2053         u8         log_rq_stride[0x3];
2054         u8         no_sq[0x1];
2055         u8         log_sq_size[0x4];
2056         u8         reserved_at_55[0x6];
2057         u8         rlky[0x1];
2058         u8         ulp_stateless_offload_mode[0x4];
2059
2060         u8         counter_set_id[0x8];
2061         u8         uar_page[0x18];
2062
2063         u8         reserved_at_80[0x8];
2064         u8         user_index[0x18];
2065
2066         u8         reserved_at_a0[0x3];
2067         u8         log_page_size[0x5];
2068         u8         remote_qpn[0x18];
2069
2070         struct mlx5_ifc_ads_bits primary_address_path;
2071
2072         struct mlx5_ifc_ads_bits secondary_address_path;
2073
2074         u8         log_ack_req_freq[0x4];
2075         u8         reserved_at_384[0x4];
2076         u8         log_sra_max[0x3];
2077         u8         reserved_at_38b[0x2];
2078         u8         retry_count[0x3];
2079         u8         rnr_retry[0x3];
2080         u8         reserved_at_393[0x1];
2081         u8         fre[0x1];
2082         u8         cur_rnr_retry[0x3];
2083         u8         cur_retry_count[0x3];
2084         u8         reserved_at_39b[0x5];
2085
2086         u8         reserved_at_3a0[0x20];
2087
2088         u8         reserved_at_3c0[0x8];
2089         u8         next_send_psn[0x18];
2090
2091         u8         reserved_at_3e0[0x8];
2092         u8         cqn_snd[0x18];
2093
2094         u8         reserved_at_400[0x8];
2095         u8         deth_sqpn[0x18];
2096
2097         u8         reserved_at_420[0x20];
2098
2099         u8         reserved_at_440[0x8];
2100         u8         last_acked_psn[0x18];
2101
2102         u8         reserved_at_460[0x8];
2103         u8         ssn[0x18];
2104
2105         u8         reserved_at_480[0x8];
2106         u8         log_rra_max[0x3];
2107         u8         reserved_at_48b[0x1];
2108         u8         atomic_mode[0x4];
2109         u8         rre[0x1];
2110         u8         rwe[0x1];
2111         u8         rae[0x1];
2112         u8         reserved_at_493[0x1];
2113         u8         page_offset[0x6];
2114         u8         reserved_at_49a[0x3];
2115         u8         cd_slave_receive[0x1];
2116         u8         cd_slave_send[0x1];
2117         u8         cd_master[0x1];
2118
2119         u8         reserved_at_4a0[0x3];
2120         u8         min_rnr_nak[0x5];
2121         u8         next_rcv_psn[0x18];
2122
2123         u8         reserved_at_4c0[0x8];
2124         u8         xrcd[0x18];
2125
2126         u8         reserved_at_4e0[0x8];
2127         u8         cqn_rcv[0x18];
2128
2129         u8         dbr_addr[0x40];
2130
2131         u8         q_key[0x20];
2132
2133         u8         reserved_at_560[0x5];
2134         u8         rq_type[0x3];
2135         u8         srqn_rmpn_xrqn[0x18];
2136
2137         u8         reserved_at_580[0x8];
2138         u8         rmsn[0x18];
2139
2140         u8         hw_sq_wqebb_counter[0x10];
2141         u8         sw_sq_wqebb_counter[0x10];
2142
2143         u8         hw_rq_counter[0x20];
2144
2145         u8         sw_rq_counter[0x20];
2146
2147         u8         reserved_at_600[0x20];
2148
2149         u8         reserved_at_620[0xf];
2150         u8         cgs[0x1];
2151         u8         cs_req[0x8];
2152         u8         cs_res[0x8];
2153
2154         u8         dc_access_key[0x40];
2155
2156         u8         reserved_at_680[0xc0];
2157 };
2158
2159 struct mlx5_ifc_roce_addr_layout_bits {
2160         u8         source_l3_address[16][0x8];
2161
2162         u8         reserved_at_80[0x3];
2163         u8         vlan_valid[0x1];
2164         u8         vlan_id[0xc];
2165         u8         source_mac_47_32[0x10];
2166
2167         u8         source_mac_31_0[0x20];
2168
2169         u8         reserved_at_c0[0x14];
2170         u8         roce_l3_type[0x4];
2171         u8         roce_version[0x8];
2172
2173         u8         reserved_at_e0[0x20];
2174 };
2175
2176 union mlx5_ifc_hca_cap_union_bits {
2177         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2178         struct mlx5_ifc_odp_cap_bits odp_cap;
2179         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2180         struct mlx5_ifc_roce_cap_bits roce_cap;
2181         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2182         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2183         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2184         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2185         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2186         struct mlx5_ifc_qos_cap_bits qos_cap;
2187         u8         reserved_at_0[0x8000];
2188 };
2189
2190 enum {
2191         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2192         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2193         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2194         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2195         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2196         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2197 };
2198
2199 struct mlx5_ifc_flow_context_bits {
2200         u8         reserved_at_0[0x20];
2201
2202         u8         group_id[0x20];
2203
2204         u8         reserved_at_40[0x8];
2205         u8         flow_tag[0x18];
2206
2207         u8         reserved_at_60[0x10];
2208         u8         action[0x10];
2209
2210         u8         reserved_at_80[0x8];
2211         u8         destination_list_size[0x18];
2212
2213         u8         reserved_at_a0[0x8];
2214         u8         flow_counter_list_size[0x18];
2215
2216         u8         encap_id[0x20];
2217
2218         u8         reserved_at_e0[0x120];
2219
2220         struct mlx5_ifc_fte_match_param_bits match_value;
2221
2222         u8         reserved_at_1200[0x600];
2223
2224         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2225 };
2226
2227 enum {
2228         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2229         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2230 };
2231
2232 struct mlx5_ifc_xrc_srqc_bits {
2233         u8         state[0x4];
2234         u8         log_xrc_srq_size[0x4];
2235         u8         reserved_at_8[0x18];
2236
2237         u8         wq_signature[0x1];
2238         u8         cont_srq[0x1];
2239         u8         reserved_at_22[0x1];
2240         u8         rlky[0x1];
2241         u8         basic_cyclic_rcv_wqe[0x1];
2242         u8         log_rq_stride[0x3];
2243         u8         xrcd[0x18];
2244
2245         u8         page_offset[0x6];
2246         u8         reserved_at_46[0x2];
2247         u8         cqn[0x18];
2248
2249         u8         reserved_at_60[0x20];
2250
2251         u8         user_index_equal_xrc_srqn[0x1];
2252         u8         reserved_at_81[0x1];
2253         u8         log_page_size[0x6];
2254         u8         user_index[0x18];
2255
2256         u8         reserved_at_a0[0x20];
2257
2258         u8         reserved_at_c0[0x8];
2259         u8         pd[0x18];
2260
2261         u8         lwm[0x10];
2262         u8         wqe_cnt[0x10];
2263
2264         u8         reserved_at_100[0x40];
2265
2266         u8         db_record_addr_h[0x20];
2267
2268         u8         db_record_addr_l[0x1e];
2269         u8         reserved_at_17e[0x2];
2270
2271         u8         reserved_at_180[0x80];
2272 };
2273
2274 struct mlx5_ifc_traffic_counter_bits {
2275         u8         packets[0x40];
2276
2277         u8         octets[0x40];
2278 };
2279
2280 struct mlx5_ifc_tisc_bits {
2281         u8         strict_lag_tx_port_affinity[0x1];
2282         u8         reserved_at_1[0x3];
2283         u8         lag_tx_port_affinity[0x04];
2284
2285         u8         reserved_at_8[0x4];
2286         u8         prio[0x4];
2287         u8         reserved_at_10[0x10];
2288
2289         u8         reserved_at_20[0x100];
2290
2291         u8         reserved_at_120[0x8];
2292         u8         transport_domain[0x18];
2293
2294         u8         reserved_at_140[0x3c0];
2295 };
2296
2297 enum {
2298         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2299         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2300 };
2301
2302 enum {
2303         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2304         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2305 };
2306
2307 enum {
2308         MLX5_RX_HASH_FN_NONE           = 0x0,
2309         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2310         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2311 };
2312
2313 enum {
2314         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2315         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2316 };
2317
2318 struct mlx5_ifc_tirc_bits {
2319         u8         reserved_at_0[0x20];
2320
2321         u8         disp_type[0x4];
2322         u8         reserved_at_24[0x1c];
2323
2324         u8         reserved_at_40[0x40];
2325
2326         u8         reserved_at_80[0x4];
2327         u8         lro_timeout_period_usecs[0x10];
2328         u8         lro_enable_mask[0x4];
2329         u8         lro_max_ip_payload_size[0x8];
2330
2331         u8         reserved_at_a0[0x40];
2332
2333         u8         reserved_at_e0[0x8];
2334         u8         inline_rqn[0x18];
2335
2336         u8         rx_hash_symmetric[0x1];
2337         u8         reserved_at_101[0x1];
2338         u8         tunneled_offload_en[0x1];
2339         u8         reserved_at_103[0x5];
2340         u8         indirect_table[0x18];
2341
2342         u8         rx_hash_fn[0x4];
2343         u8         reserved_at_124[0x2];
2344         u8         self_lb_block[0x2];
2345         u8         transport_domain[0x18];
2346
2347         u8         rx_hash_toeplitz_key[10][0x20];
2348
2349         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2350
2351         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2352
2353         u8         reserved_at_2c0[0x4c0];
2354 };
2355
2356 enum {
2357         MLX5_SRQC_STATE_GOOD   = 0x0,
2358         MLX5_SRQC_STATE_ERROR  = 0x1,
2359 };
2360
2361 struct mlx5_ifc_srqc_bits {
2362         u8         state[0x4];
2363         u8         log_srq_size[0x4];
2364         u8         reserved_at_8[0x18];
2365
2366         u8         wq_signature[0x1];
2367         u8         cont_srq[0x1];
2368         u8         reserved_at_22[0x1];
2369         u8         rlky[0x1];
2370         u8         reserved_at_24[0x1];
2371         u8         log_rq_stride[0x3];
2372         u8         xrcd[0x18];
2373
2374         u8         page_offset[0x6];
2375         u8         reserved_at_46[0x2];
2376         u8         cqn[0x18];
2377
2378         u8         reserved_at_60[0x20];
2379
2380         u8         reserved_at_80[0x2];
2381         u8         log_page_size[0x6];
2382         u8         reserved_at_88[0x18];
2383
2384         u8         reserved_at_a0[0x20];
2385
2386         u8         reserved_at_c0[0x8];
2387         u8         pd[0x18];
2388
2389         u8         lwm[0x10];
2390         u8         wqe_cnt[0x10];
2391
2392         u8         reserved_at_100[0x40];
2393
2394         u8         dbr_addr[0x40];
2395
2396         u8         reserved_at_180[0x80];
2397 };
2398
2399 enum {
2400         MLX5_SQC_STATE_RST  = 0x0,
2401         MLX5_SQC_STATE_RDY  = 0x1,
2402         MLX5_SQC_STATE_ERR  = 0x3,
2403 };
2404
2405 struct mlx5_ifc_sqc_bits {
2406         u8         rlky[0x1];
2407         u8         cd_master[0x1];
2408         u8         fre[0x1];
2409         u8         flush_in_error_en[0x1];
2410         u8         reserved_at_4[0x1];
2411         u8         min_wqe_inline_mode[0x3];
2412         u8         state[0x4];
2413         u8         reg_umr[0x1];
2414         u8         reserved_at_d[0x13];
2415
2416         u8         reserved_at_20[0x8];
2417         u8         user_index[0x18];
2418
2419         u8         reserved_at_40[0x8];
2420         u8         cqn[0x18];
2421
2422         u8         reserved_at_60[0x90];
2423
2424         u8         packet_pacing_rate_limit_index[0x10];
2425         u8         tis_lst_sz[0x10];
2426         u8         reserved_at_110[0x10];
2427
2428         u8         reserved_at_120[0x40];
2429
2430         u8         reserved_at_160[0x8];
2431         u8         tis_num_0[0x18];
2432
2433         struct mlx5_ifc_wq_bits wq;
2434 };
2435
2436 enum {
2437         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2438         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2439         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2440         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2441 };
2442
2443 struct mlx5_ifc_scheduling_context_bits {
2444         u8         element_type[0x8];
2445         u8         reserved_at_8[0x18];
2446
2447         u8         element_attributes[0x20];
2448
2449         u8         parent_element_id[0x20];
2450
2451         u8         reserved_at_60[0x40];
2452
2453         u8         bw_share[0x20];
2454
2455         u8         max_average_bw[0x20];
2456
2457         u8         reserved_at_e0[0x120];
2458 };
2459
2460 struct mlx5_ifc_rqtc_bits {
2461         u8         reserved_at_0[0xa0];
2462
2463         u8         reserved_at_a0[0x10];
2464         u8         rqt_max_size[0x10];
2465
2466         u8         reserved_at_c0[0x10];
2467         u8         rqt_actual_size[0x10];
2468
2469         u8         reserved_at_e0[0x6a0];
2470
2471         struct mlx5_ifc_rq_num_bits rq_num[0];
2472 };
2473
2474 enum {
2475         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2476         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2477 };
2478
2479 enum {
2480         MLX5_RQC_STATE_RST  = 0x0,
2481         MLX5_RQC_STATE_RDY  = 0x1,
2482         MLX5_RQC_STATE_ERR  = 0x3,
2483 };
2484
2485 struct mlx5_ifc_rqc_bits {
2486         u8         rlky[0x1];
2487         u8         reserved_at_1[0x1];
2488         u8         scatter_fcs[0x1];
2489         u8         vsd[0x1];
2490         u8         mem_rq_type[0x4];
2491         u8         state[0x4];
2492         u8         reserved_at_c[0x1];
2493         u8         flush_in_error_en[0x1];
2494         u8         reserved_at_e[0x12];
2495
2496         u8         reserved_at_20[0x8];
2497         u8         user_index[0x18];
2498
2499         u8         reserved_at_40[0x8];
2500         u8         cqn[0x18];
2501
2502         u8         counter_set_id[0x8];
2503         u8         reserved_at_68[0x18];
2504
2505         u8         reserved_at_80[0x8];
2506         u8         rmpn[0x18];
2507
2508         u8         reserved_at_a0[0xe0];
2509
2510         struct mlx5_ifc_wq_bits wq;
2511 };
2512
2513 enum {
2514         MLX5_RMPC_STATE_RDY  = 0x1,
2515         MLX5_RMPC_STATE_ERR  = 0x3,
2516 };
2517
2518 struct mlx5_ifc_rmpc_bits {
2519         u8         reserved_at_0[0x8];
2520         u8         state[0x4];
2521         u8         reserved_at_c[0x14];
2522
2523         u8         basic_cyclic_rcv_wqe[0x1];
2524         u8         reserved_at_21[0x1f];
2525
2526         u8         reserved_at_40[0x140];
2527
2528         struct mlx5_ifc_wq_bits wq;
2529 };
2530
2531 struct mlx5_ifc_nic_vport_context_bits {
2532         u8         reserved_at_0[0x5];
2533         u8         min_wqe_inline_mode[0x3];
2534         u8         reserved_at_8[0x17];
2535         u8         roce_en[0x1];
2536
2537         u8         arm_change_event[0x1];
2538         u8         reserved_at_21[0x1a];
2539         u8         event_on_mtu[0x1];
2540         u8         event_on_promisc_change[0x1];
2541         u8         event_on_vlan_change[0x1];
2542         u8         event_on_mc_address_change[0x1];
2543         u8         event_on_uc_address_change[0x1];
2544
2545         u8         reserved_at_40[0xf0];
2546
2547         u8         mtu[0x10];
2548
2549         u8         system_image_guid[0x40];
2550         u8         port_guid[0x40];
2551         u8         node_guid[0x40];
2552
2553         u8         reserved_at_200[0x140];
2554         u8         qkey_violation_counter[0x10];
2555         u8         reserved_at_350[0x430];
2556
2557         u8         promisc_uc[0x1];
2558         u8         promisc_mc[0x1];
2559         u8         promisc_all[0x1];
2560         u8         reserved_at_783[0x2];
2561         u8         allowed_list_type[0x3];
2562         u8         reserved_at_788[0xc];
2563         u8         allowed_list_size[0xc];
2564
2565         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2566
2567         u8         reserved_at_7e0[0x20];
2568
2569         u8         current_uc_mac_address[0][0x40];
2570 };
2571
2572 enum {
2573         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2574         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2575         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2576         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2577 };
2578
2579 struct mlx5_ifc_mkc_bits {
2580         u8         reserved_at_0[0x1];
2581         u8         free[0x1];
2582         u8         reserved_at_2[0xd];
2583         u8         small_fence_on_rdma_read_response[0x1];
2584         u8         umr_en[0x1];
2585         u8         a[0x1];
2586         u8         rw[0x1];
2587         u8         rr[0x1];
2588         u8         lw[0x1];
2589         u8         lr[0x1];
2590         u8         access_mode[0x2];
2591         u8         reserved_at_18[0x8];
2592
2593         u8         qpn[0x18];
2594         u8         mkey_7_0[0x8];
2595
2596         u8         reserved_at_40[0x20];
2597
2598         u8         length64[0x1];
2599         u8         bsf_en[0x1];
2600         u8         sync_umr[0x1];
2601         u8         reserved_at_63[0x2];
2602         u8         expected_sigerr_count[0x1];
2603         u8         reserved_at_66[0x1];
2604         u8         en_rinval[0x1];
2605         u8         pd[0x18];
2606
2607         u8         start_addr[0x40];
2608
2609         u8         len[0x40];
2610
2611         u8         bsf_octword_size[0x20];
2612
2613         u8         reserved_at_120[0x80];
2614
2615         u8         translations_octword_size[0x20];
2616
2617         u8         reserved_at_1c0[0x1b];
2618         u8         log_page_size[0x5];
2619
2620         u8         reserved_at_1e0[0x20];
2621 };
2622
2623 struct mlx5_ifc_pkey_bits {
2624         u8         reserved_at_0[0x10];
2625         u8         pkey[0x10];
2626 };
2627
2628 struct mlx5_ifc_array128_auto_bits {
2629         u8         array128_auto[16][0x8];
2630 };
2631
2632 struct mlx5_ifc_hca_vport_context_bits {
2633         u8         field_select[0x20];
2634
2635         u8         reserved_at_20[0xe0];
2636
2637         u8         sm_virt_aware[0x1];
2638         u8         has_smi[0x1];
2639         u8         has_raw[0x1];
2640         u8         grh_required[0x1];
2641         u8         reserved_at_104[0xc];
2642         u8         port_physical_state[0x4];
2643         u8         vport_state_policy[0x4];
2644         u8         port_state[0x4];
2645         u8         vport_state[0x4];
2646
2647         u8         reserved_at_120[0x20];
2648
2649         u8         system_image_guid[0x40];
2650
2651         u8         port_guid[0x40];
2652
2653         u8         node_guid[0x40];
2654
2655         u8         cap_mask1[0x20];
2656
2657         u8         cap_mask1_field_select[0x20];
2658
2659         u8         cap_mask2[0x20];
2660
2661         u8         cap_mask2_field_select[0x20];
2662
2663         u8         reserved_at_280[0x80];
2664
2665         u8         lid[0x10];
2666         u8         reserved_at_310[0x4];
2667         u8         init_type_reply[0x4];
2668         u8         lmc[0x3];
2669         u8         subnet_timeout[0x5];
2670
2671         u8         sm_lid[0x10];
2672         u8         sm_sl[0x4];
2673         u8         reserved_at_334[0xc];
2674
2675         u8         qkey_violation_counter[0x10];
2676         u8         pkey_violation_counter[0x10];
2677
2678         u8         reserved_at_360[0xca0];
2679 };
2680
2681 struct mlx5_ifc_esw_vport_context_bits {
2682         u8         reserved_at_0[0x3];
2683         u8         vport_svlan_strip[0x1];
2684         u8         vport_cvlan_strip[0x1];
2685         u8         vport_svlan_insert[0x1];
2686         u8         vport_cvlan_insert[0x2];
2687         u8         reserved_at_8[0x18];
2688
2689         u8         reserved_at_20[0x20];
2690
2691         u8         svlan_cfi[0x1];
2692         u8         svlan_pcp[0x3];
2693         u8         svlan_id[0xc];
2694         u8         cvlan_cfi[0x1];
2695         u8         cvlan_pcp[0x3];
2696         u8         cvlan_id[0xc];
2697
2698         u8         reserved_at_60[0x7a0];
2699 };
2700
2701 enum {
2702         MLX5_EQC_STATUS_OK                = 0x0,
2703         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2704 };
2705
2706 enum {
2707         MLX5_EQC_ST_ARMED  = 0x9,
2708         MLX5_EQC_ST_FIRED  = 0xa,
2709 };
2710
2711 struct mlx5_ifc_eqc_bits {
2712         u8         status[0x4];
2713         u8         reserved_at_4[0x9];
2714         u8         ec[0x1];
2715         u8         oi[0x1];
2716         u8         reserved_at_f[0x5];
2717         u8         st[0x4];
2718         u8         reserved_at_18[0x8];
2719
2720         u8         reserved_at_20[0x20];
2721
2722         u8         reserved_at_40[0x14];
2723         u8         page_offset[0x6];
2724         u8         reserved_at_5a[0x6];
2725
2726         u8         reserved_at_60[0x3];
2727         u8         log_eq_size[0x5];
2728         u8         uar_page[0x18];
2729
2730         u8         reserved_at_80[0x20];
2731
2732         u8         reserved_at_a0[0x18];
2733         u8         intr[0x8];
2734
2735         u8         reserved_at_c0[0x3];
2736         u8         log_page_size[0x5];
2737         u8         reserved_at_c8[0x18];
2738
2739         u8         reserved_at_e0[0x60];
2740
2741         u8         reserved_at_140[0x8];
2742         u8         consumer_counter[0x18];
2743
2744         u8         reserved_at_160[0x8];
2745         u8         producer_counter[0x18];
2746
2747         u8         reserved_at_180[0x80];
2748 };
2749
2750 enum {
2751         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2752         MLX5_DCTC_STATE_DRAINING  = 0x1,
2753         MLX5_DCTC_STATE_DRAINED   = 0x2,
2754 };
2755
2756 enum {
2757         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2758         MLX5_DCTC_CS_RES_NA         = 0x1,
2759         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2760 };
2761
2762 enum {
2763         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2764         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2765         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2766         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2767         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2768 };
2769
2770 struct mlx5_ifc_dctc_bits {
2771         u8         reserved_at_0[0x4];
2772         u8         state[0x4];
2773         u8         reserved_at_8[0x18];
2774
2775         u8         reserved_at_20[0x8];
2776         u8         user_index[0x18];
2777
2778         u8         reserved_at_40[0x8];
2779         u8         cqn[0x18];
2780
2781         u8         counter_set_id[0x8];
2782         u8         atomic_mode[0x4];
2783         u8         rre[0x1];
2784         u8         rwe[0x1];
2785         u8         rae[0x1];
2786         u8         atomic_like_write_en[0x1];
2787         u8         latency_sensitive[0x1];
2788         u8         rlky[0x1];
2789         u8         free_ar[0x1];
2790         u8         reserved_at_73[0xd];
2791
2792         u8         reserved_at_80[0x8];
2793         u8         cs_res[0x8];
2794         u8         reserved_at_90[0x3];
2795         u8         min_rnr_nak[0x5];
2796         u8         reserved_at_98[0x8];
2797
2798         u8         reserved_at_a0[0x8];
2799         u8         srqn_xrqn[0x18];
2800
2801         u8         reserved_at_c0[0x8];
2802         u8         pd[0x18];
2803
2804         u8         tclass[0x8];
2805         u8         reserved_at_e8[0x4];
2806         u8         flow_label[0x14];
2807
2808         u8         dc_access_key[0x40];
2809
2810         u8         reserved_at_140[0x5];
2811         u8         mtu[0x3];
2812         u8         port[0x8];
2813         u8         pkey_index[0x10];
2814
2815         u8         reserved_at_160[0x8];
2816         u8         my_addr_index[0x8];
2817         u8         reserved_at_170[0x8];
2818         u8         hop_limit[0x8];
2819
2820         u8         dc_access_key_violation_count[0x20];
2821
2822         u8         reserved_at_1a0[0x14];
2823         u8         dei_cfi[0x1];
2824         u8         eth_prio[0x3];
2825         u8         ecn[0x2];
2826         u8         dscp[0x6];
2827
2828         u8         reserved_at_1c0[0x40];
2829 };
2830
2831 enum {
2832         MLX5_CQC_STATUS_OK             = 0x0,
2833         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2834         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2835 };
2836
2837 enum {
2838         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2839         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2840 };
2841
2842 enum {
2843         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2844         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2845         MLX5_CQC_ST_FIRED                                 = 0xa,
2846 };
2847
2848 enum {
2849         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2850         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2851         MLX5_CQ_PERIOD_NUM_MODES
2852 };
2853
2854 struct mlx5_ifc_cqc_bits {
2855         u8         status[0x4];
2856         u8         reserved_at_4[0x4];
2857         u8         cqe_sz[0x3];
2858         u8         cc[0x1];
2859         u8         reserved_at_c[0x1];
2860         u8         scqe_break_moderation_en[0x1];
2861         u8         oi[0x1];
2862         u8         cq_period_mode[0x2];
2863         u8         cqe_comp_en[0x1];
2864         u8         mini_cqe_res_format[0x2];
2865         u8         st[0x4];
2866         u8         reserved_at_18[0x8];
2867
2868         u8         reserved_at_20[0x20];
2869
2870         u8         reserved_at_40[0x14];
2871         u8         page_offset[0x6];
2872         u8         reserved_at_5a[0x6];
2873
2874         u8         reserved_at_60[0x3];
2875         u8         log_cq_size[0x5];
2876         u8         uar_page[0x18];
2877
2878         u8         reserved_at_80[0x4];
2879         u8         cq_period[0xc];
2880         u8         cq_max_count[0x10];
2881
2882         u8         reserved_at_a0[0x18];
2883         u8         c_eqn[0x8];
2884
2885         u8         reserved_at_c0[0x3];
2886         u8         log_page_size[0x5];
2887         u8         reserved_at_c8[0x18];
2888
2889         u8         reserved_at_e0[0x20];
2890
2891         u8         reserved_at_100[0x8];
2892         u8         last_notified_index[0x18];
2893
2894         u8         reserved_at_120[0x8];
2895         u8         last_solicit_index[0x18];
2896
2897         u8         reserved_at_140[0x8];
2898         u8         consumer_counter[0x18];
2899
2900         u8         reserved_at_160[0x8];
2901         u8         producer_counter[0x18];
2902
2903         u8         reserved_at_180[0x40];
2904
2905         u8         dbr_addr[0x40];
2906 };
2907
2908 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2909         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2910         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2911         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2912         u8         reserved_at_0[0x800];
2913 };
2914
2915 struct mlx5_ifc_query_adapter_param_block_bits {
2916         u8         reserved_at_0[0xc0];
2917
2918         u8         reserved_at_c0[0x8];
2919         u8         ieee_vendor_id[0x18];
2920
2921         u8         reserved_at_e0[0x10];
2922         u8         vsd_vendor_id[0x10];
2923
2924         u8         vsd[208][0x8];
2925
2926         u8         vsd_contd_psid[16][0x8];
2927 };
2928
2929 enum {
2930         MLX5_XRQC_STATE_GOOD   = 0x0,
2931         MLX5_XRQC_STATE_ERROR  = 0x1,
2932 };
2933
2934 enum {
2935         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2936         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
2937 };
2938
2939 enum {
2940         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2941 };
2942
2943 struct mlx5_ifc_tag_matching_topology_context_bits {
2944         u8         log_matching_list_sz[0x4];
2945         u8         reserved_at_4[0xc];
2946         u8         append_next_index[0x10];
2947
2948         u8         sw_phase_cnt[0x10];
2949         u8         hw_phase_cnt[0x10];
2950
2951         u8         reserved_at_40[0x40];
2952 };
2953
2954 struct mlx5_ifc_xrqc_bits {
2955         u8         state[0x4];
2956         u8         rlkey[0x1];
2957         u8         reserved_at_5[0xf];
2958         u8         topology[0x4];
2959         u8         reserved_at_18[0x4];
2960         u8         offload[0x4];
2961
2962         u8         reserved_at_20[0x8];
2963         u8         user_index[0x18];
2964
2965         u8         reserved_at_40[0x8];
2966         u8         cqn[0x18];
2967
2968         u8         reserved_at_60[0xa0];
2969
2970         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2971
2972         u8         reserved_at_180[0x880];
2973
2974         struct mlx5_ifc_wq_bits wq;
2975 };
2976
2977 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2978         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2979         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2980         u8         reserved_at_0[0x20];
2981 };
2982
2983 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2984         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2985         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2986         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2987         u8         reserved_at_0[0x20];
2988 };
2989
2990 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2991         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2992         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2993         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2994         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2995         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2996         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2997         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2998         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2999         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3000         u8         reserved_at_0[0x7c0];
3001 };
3002
3003 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3004         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3005         struct mlx5_ifc_pcie_tas_cntrs_grp_data_layout_bits pcie_tas_cntrs_grp_data_layout;
3006         u8         reserved_at_0[0x7c0];
3007 };
3008
3009 union mlx5_ifc_event_auto_bits {
3010         struct mlx5_ifc_comp_event_bits comp_event;
3011         struct mlx5_ifc_dct_events_bits dct_events;
3012         struct mlx5_ifc_qp_events_bits qp_events;
3013         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3014         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3015         struct mlx5_ifc_cq_error_bits cq_error;
3016         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3017         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3018         struct mlx5_ifc_gpio_event_bits gpio_event;
3019         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3020         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3021         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3022         u8         reserved_at_0[0xe0];
3023 };
3024
3025 struct mlx5_ifc_health_buffer_bits {
3026         u8         reserved_at_0[0x100];
3027
3028         u8         assert_existptr[0x20];
3029
3030         u8         assert_callra[0x20];
3031
3032         u8         reserved_at_140[0x40];
3033
3034         u8         fw_version[0x20];
3035
3036         u8         hw_id[0x20];
3037
3038         u8         reserved_at_1c0[0x20];
3039
3040         u8         irisc_index[0x8];
3041         u8         synd[0x8];
3042         u8         ext_synd[0x10];
3043 };
3044
3045 struct mlx5_ifc_register_loopback_control_bits {
3046         u8         no_lb[0x1];
3047         u8         reserved_at_1[0x7];
3048         u8         port[0x8];
3049         u8         reserved_at_10[0x10];
3050
3051         u8         reserved_at_20[0x60];
3052 };
3053
3054 struct mlx5_ifc_vport_tc_element_bits {
3055         u8         traffic_class[0x4];
3056         u8         reserved_at_4[0xc];
3057         u8         vport_number[0x10];
3058 };
3059
3060 struct mlx5_ifc_vport_element_bits {
3061         u8         reserved_at_0[0x10];
3062         u8         vport_number[0x10];
3063 };
3064
3065 enum {
3066         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3067         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3068         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3069 };
3070
3071 struct mlx5_ifc_tsar_element_bits {
3072         u8         reserved_at_0[0x8];
3073         u8         tsar_type[0x8];
3074         u8         reserved_at_10[0x10];
3075 };
3076
3077 struct mlx5_ifc_teardown_hca_out_bits {
3078         u8         status[0x8];
3079         u8         reserved_at_8[0x18];
3080
3081         u8         syndrome[0x20];
3082
3083         u8         reserved_at_40[0x40];
3084 };
3085
3086 enum {
3087         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3088         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
3089 };
3090
3091 struct mlx5_ifc_teardown_hca_in_bits {
3092         u8         opcode[0x10];
3093         u8         reserved_at_10[0x10];
3094
3095         u8         reserved_at_20[0x10];
3096         u8         op_mod[0x10];
3097
3098         u8         reserved_at_40[0x10];
3099         u8         profile[0x10];
3100
3101         u8         reserved_at_60[0x20];
3102 };
3103
3104 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3105         u8         status[0x8];
3106         u8         reserved_at_8[0x18];
3107
3108         u8         syndrome[0x20];
3109
3110         u8         reserved_at_40[0x40];
3111 };
3112
3113 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3114         u8         opcode[0x10];
3115         u8         reserved_at_10[0x10];
3116
3117         u8         reserved_at_20[0x10];
3118         u8         op_mod[0x10];
3119
3120         u8         reserved_at_40[0x8];
3121         u8         qpn[0x18];
3122
3123         u8         reserved_at_60[0x20];
3124
3125         u8         opt_param_mask[0x20];
3126
3127         u8         reserved_at_a0[0x20];
3128
3129         struct mlx5_ifc_qpc_bits qpc;
3130
3131         u8         reserved_at_800[0x80];
3132 };
3133
3134 struct mlx5_ifc_sqd2rts_qp_out_bits {
3135         u8         status[0x8];
3136         u8         reserved_at_8[0x18];
3137
3138         u8         syndrome[0x20];
3139
3140         u8         reserved_at_40[0x40];
3141 };
3142
3143 struct mlx5_ifc_sqd2rts_qp_in_bits {
3144         u8         opcode[0x10];
3145         u8         reserved_at_10[0x10];
3146
3147         u8         reserved_at_20[0x10];
3148         u8         op_mod[0x10];
3149
3150         u8         reserved_at_40[0x8];
3151         u8         qpn[0x18];
3152
3153         u8         reserved_at_60[0x20];
3154
3155         u8         opt_param_mask[0x20];
3156
3157         u8         reserved_at_a0[0x20];
3158
3159         struct mlx5_ifc_qpc_bits qpc;
3160
3161         u8         reserved_at_800[0x80];
3162 };
3163
3164 struct mlx5_ifc_set_roce_address_out_bits {
3165         u8         status[0x8];
3166         u8         reserved_at_8[0x18];
3167
3168         u8         syndrome[0x20];
3169
3170         u8         reserved_at_40[0x40];
3171 };
3172
3173 struct mlx5_ifc_set_roce_address_in_bits {
3174         u8         opcode[0x10];
3175         u8         reserved_at_10[0x10];
3176
3177         u8         reserved_at_20[0x10];
3178         u8         op_mod[0x10];
3179
3180         u8         roce_address_index[0x10];
3181         u8         reserved_at_50[0x10];
3182
3183         u8         reserved_at_60[0x20];
3184
3185         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3186 };
3187
3188 struct mlx5_ifc_set_mad_demux_out_bits {
3189         u8         status[0x8];
3190         u8         reserved_at_8[0x18];
3191
3192         u8         syndrome[0x20];
3193
3194         u8         reserved_at_40[0x40];
3195 };
3196
3197 enum {
3198         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3199         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3200 };
3201
3202 struct mlx5_ifc_set_mad_demux_in_bits {
3203         u8         opcode[0x10];
3204         u8         reserved_at_10[0x10];
3205
3206         u8         reserved_at_20[0x10];
3207         u8         op_mod[0x10];
3208
3209         u8         reserved_at_40[0x20];
3210
3211         u8         reserved_at_60[0x6];
3212         u8         demux_mode[0x2];
3213         u8         reserved_at_68[0x18];
3214 };
3215
3216 struct mlx5_ifc_set_l2_table_entry_out_bits {
3217         u8         status[0x8];
3218         u8         reserved_at_8[0x18];
3219
3220         u8         syndrome[0x20];
3221
3222         u8         reserved_at_40[0x40];
3223 };
3224
3225 struct mlx5_ifc_set_l2_table_entry_in_bits {
3226         u8         opcode[0x10];
3227         u8         reserved_at_10[0x10];
3228
3229         u8         reserved_at_20[0x10];
3230         u8         op_mod[0x10];
3231
3232         u8         reserved_at_40[0x60];
3233
3234         u8         reserved_at_a0[0x8];
3235         u8         table_index[0x18];
3236
3237         u8         reserved_at_c0[0x20];
3238
3239         u8         reserved_at_e0[0x13];
3240         u8         vlan_valid[0x1];
3241         u8         vlan[0xc];
3242
3243         struct mlx5_ifc_mac_address_layout_bits mac_address;
3244
3245         u8         reserved_at_140[0xc0];
3246 };
3247
3248 struct mlx5_ifc_set_issi_out_bits {
3249         u8         status[0x8];
3250         u8         reserved_at_8[0x18];
3251
3252         u8         syndrome[0x20];
3253
3254         u8         reserved_at_40[0x40];
3255 };
3256
3257 struct mlx5_ifc_set_issi_in_bits {
3258         u8         opcode[0x10];
3259         u8         reserved_at_10[0x10];
3260
3261         u8         reserved_at_20[0x10];
3262         u8         op_mod[0x10];
3263
3264         u8         reserved_at_40[0x10];
3265         u8         current_issi[0x10];
3266
3267         u8         reserved_at_60[0x20];
3268 };
3269
3270 struct mlx5_ifc_set_hca_cap_out_bits {
3271         u8         status[0x8];
3272         u8         reserved_at_8[0x18];
3273
3274         u8         syndrome[0x20];
3275
3276         u8         reserved_at_40[0x40];
3277 };
3278
3279 struct mlx5_ifc_set_hca_cap_in_bits {
3280         u8         opcode[0x10];
3281         u8         reserved_at_10[0x10];
3282
3283         u8         reserved_at_20[0x10];
3284         u8         op_mod[0x10];
3285
3286         u8         reserved_at_40[0x40];
3287
3288         union mlx5_ifc_hca_cap_union_bits capability;
3289 };
3290
3291 enum {
3292         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3293         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3294         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3295         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3296 };
3297
3298 struct mlx5_ifc_set_fte_out_bits {
3299         u8         status[0x8];
3300         u8         reserved_at_8[0x18];
3301
3302         u8         syndrome[0x20];
3303
3304         u8         reserved_at_40[0x40];
3305 };
3306
3307 struct mlx5_ifc_set_fte_in_bits {
3308         u8         opcode[0x10];
3309         u8         reserved_at_10[0x10];
3310
3311         u8         reserved_at_20[0x10];
3312         u8         op_mod[0x10];
3313
3314         u8         other_vport[0x1];
3315         u8         reserved_at_41[0xf];
3316         u8         vport_number[0x10];
3317
3318         u8         reserved_at_60[0x20];
3319
3320         u8         table_type[0x8];
3321         u8         reserved_at_88[0x18];
3322
3323         u8         reserved_at_a0[0x8];
3324         u8         table_id[0x18];
3325
3326         u8         reserved_at_c0[0x18];
3327         u8         modify_enable_mask[0x8];
3328
3329         u8         reserved_at_e0[0x20];
3330
3331         u8         flow_index[0x20];
3332
3333         u8         reserved_at_120[0xe0];
3334
3335         struct mlx5_ifc_flow_context_bits flow_context;
3336 };
3337
3338 struct mlx5_ifc_rts2rts_qp_out_bits {
3339         u8         status[0x8];
3340         u8         reserved_at_8[0x18];
3341
3342         u8         syndrome[0x20];
3343
3344         u8         reserved_at_40[0x40];
3345 };
3346
3347 struct mlx5_ifc_rts2rts_qp_in_bits {
3348         u8         opcode[0x10];
3349         u8         reserved_at_10[0x10];
3350
3351         u8         reserved_at_20[0x10];
3352         u8         op_mod[0x10];
3353
3354         u8         reserved_at_40[0x8];
3355         u8         qpn[0x18];
3356
3357         u8         reserved_at_60[0x20];
3358
3359         u8         opt_param_mask[0x20];
3360
3361         u8         reserved_at_a0[0x20];
3362
3363         struct mlx5_ifc_qpc_bits qpc;
3364
3365         u8         reserved_at_800[0x80];
3366 };
3367
3368 struct mlx5_ifc_rtr2rts_qp_out_bits {
3369         u8         status[0x8];
3370         u8         reserved_at_8[0x18];
3371
3372         u8         syndrome[0x20];
3373
3374         u8         reserved_at_40[0x40];
3375 };
3376
3377 struct mlx5_ifc_rtr2rts_qp_in_bits {
3378         u8         opcode[0x10];
3379         u8         reserved_at_10[0x10];
3380
3381         u8         reserved_at_20[0x10];
3382         u8         op_mod[0x10];
3383
3384         u8         reserved_at_40[0x8];
3385         u8         qpn[0x18];
3386
3387         u8         reserved_at_60[0x20];
3388
3389         u8         opt_param_mask[0x20];
3390
3391         u8         reserved_at_a0[0x20];
3392
3393         struct mlx5_ifc_qpc_bits qpc;
3394
3395         u8         reserved_at_800[0x80];
3396 };
3397
3398 struct mlx5_ifc_rst2init_qp_out_bits {
3399         u8         status[0x8];
3400         u8         reserved_at_8[0x18];
3401
3402         u8         syndrome[0x20];
3403
3404         u8         reserved_at_40[0x40];
3405 };
3406
3407 struct mlx5_ifc_rst2init_qp_in_bits {
3408         u8         opcode[0x10];
3409         u8         reserved_at_10[0x10];
3410
3411         u8         reserved_at_20[0x10];
3412         u8         op_mod[0x10];
3413
3414         u8         reserved_at_40[0x8];
3415         u8         qpn[0x18];
3416
3417         u8         reserved_at_60[0x20];
3418
3419         u8         opt_param_mask[0x20];
3420
3421         u8         reserved_at_a0[0x20];
3422
3423         struct mlx5_ifc_qpc_bits qpc;
3424
3425         u8         reserved_at_800[0x80];
3426 };
3427
3428 struct mlx5_ifc_query_xrq_out_bits {
3429         u8         status[0x8];
3430         u8         reserved_at_8[0x18];
3431
3432         u8         syndrome[0x20];
3433
3434         u8         reserved_at_40[0x40];
3435
3436         struct mlx5_ifc_xrqc_bits xrq_context;
3437 };
3438
3439 struct mlx5_ifc_query_xrq_in_bits {
3440         u8         opcode[0x10];
3441         u8         reserved_at_10[0x10];
3442
3443         u8         reserved_at_20[0x10];
3444         u8         op_mod[0x10];
3445
3446         u8         reserved_at_40[0x8];
3447         u8         xrqn[0x18];
3448
3449         u8         reserved_at_60[0x20];
3450 };
3451
3452 struct mlx5_ifc_query_xrc_srq_out_bits {
3453         u8         status[0x8];
3454         u8         reserved_at_8[0x18];
3455
3456         u8         syndrome[0x20];
3457
3458         u8         reserved_at_40[0x40];
3459
3460         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3461
3462         u8         reserved_at_280[0x600];
3463
3464         u8         pas[0][0x40];
3465 };
3466
3467 struct mlx5_ifc_query_xrc_srq_in_bits {
3468         u8         opcode[0x10];
3469         u8         reserved_at_10[0x10];
3470
3471         u8         reserved_at_20[0x10];
3472         u8         op_mod[0x10];
3473
3474         u8         reserved_at_40[0x8];
3475         u8         xrc_srqn[0x18];
3476
3477         u8         reserved_at_60[0x20];
3478 };
3479
3480 enum {
3481         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3482         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3483 };
3484
3485 struct mlx5_ifc_query_vport_state_out_bits {
3486         u8         status[0x8];
3487         u8         reserved_at_8[0x18];
3488
3489         u8         syndrome[0x20];
3490
3491         u8         reserved_at_40[0x20];
3492
3493         u8         reserved_at_60[0x18];
3494         u8         admin_state[0x4];
3495         u8         state[0x4];
3496 };
3497
3498 enum {
3499         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3500         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3501 };
3502
3503 struct mlx5_ifc_query_vport_state_in_bits {
3504         u8         opcode[0x10];
3505         u8         reserved_at_10[0x10];
3506
3507         u8         reserved_at_20[0x10];
3508         u8         op_mod[0x10];
3509
3510         u8         other_vport[0x1];
3511         u8         reserved_at_41[0xf];
3512         u8         vport_number[0x10];
3513
3514         u8         reserved_at_60[0x20];
3515 };
3516
3517 struct mlx5_ifc_query_vport_counter_out_bits {
3518         u8         status[0x8];
3519         u8         reserved_at_8[0x18];
3520
3521         u8         syndrome[0x20];
3522
3523         u8         reserved_at_40[0x40];
3524
3525         struct mlx5_ifc_traffic_counter_bits received_errors;
3526
3527         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3528
3529         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3530
3531         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3532
3533         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3534
3535         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3536
3537         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3538
3539         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3540
3541         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3542
3543         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3544
3545         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3546
3547         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3548
3549         u8         reserved_at_680[0xa00];
3550 };
3551
3552 enum {
3553         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3554 };
3555
3556 struct mlx5_ifc_query_vport_counter_in_bits {
3557         u8         opcode[0x10];
3558         u8         reserved_at_10[0x10];
3559
3560         u8         reserved_at_20[0x10];
3561         u8         op_mod[0x10];
3562
3563         u8         other_vport[0x1];
3564         u8         reserved_at_41[0xb];
3565         u8         port_num[0x4];
3566         u8         vport_number[0x10];
3567
3568         u8         reserved_at_60[0x60];
3569
3570         u8         clear[0x1];
3571         u8         reserved_at_c1[0x1f];
3572
3573         u8         reserved_at_e0[0x20];
3574 };
3575
3576 struct mlx5_ifc_query_tis_out_bits {
3577         u8         status[0x8];
3578         u8         reserved_at_8[0x18];
3579
3580         u8         syndrome[0x20];
3581
3582         u8         reserved_at_40[0x40];
3583
3584         struct mlx5_ifc_tisc_bits tis_context;
3585 };
3586
3587 struct mlx5_ifc_query_tis_in_bits {
3588         u8         opcode[0x10];
3589         u8         reserved_at_10[0x10];
3590
3591         u8         reserved_at_20[0x10];
3592         u8         op_mod[0x10];
3593
3594         u8         reserved_at_40[0x8];
3595         u8         tisn[0x18];
3596
3597         u8         reserved_at_60[0x20];
3598 };
3599
3600 struct mlx5_ifc_query_tir_out_bits {
3601         u8         status[0x8];
3602         u8         reserved_at_8[0x18];
3603
3604         u8         syndrome[0x20];
3605
3606         u8         reserved_at_40[0xc0];
3607
3608         struct mlx5_ifc_tirc_bits tir_context;
3609 };
3610
3611 struct mlx5_ifc_query_tir_in_bits {
3612         u8         opcode[0x10];
3613         u8         reserved_at_10[0x10];
3614
3615         u8         reserved_at_20[0x10];
3616         u8         op_mod[0x10];
3617
3618         u8         reserved_at_40[0x8];
3619         u8         tirn[0x18];
3620
3621         u8         reserved_at_60[0x20];
3622 };
3623
3624 struct mlx5_ifc_query_srq_out_bits {
3625         u8         status[0x8];
3626         u8         reserved_at_8[0x18];
3627
3628         u8         syndrome[0x20];
3629
3630         u8         reserved_at_40[0x40];
3631
3632         struct mlx5_ifc_srqc_bits srq_context_entry;
3633
3634         u8         reserved_at_280[0x600];
3635
3636         u8         pas[0][0x40];
3637 };
3638
3639 struct mlx5_ifc_query_srq_in_bits {
3640         u8         opcode[0x10];
3641         u8         reserved_at_10[0x10];
3642
3643         u8         reserved_at_20[0x10];
3644         u8         op_mod[0x10];
3645
3646         u8         reserved_at_40[0x8];
3647         u8         srqn[0x18];
3648
3649         u8         reserved_at_60[0x20];
3650 };
3651
3652 struct mlx5_ifc_query_sq_out_bits {
3653         u8         status[0x8];
3654         u8         reserved_at_8[0x18];
3655
3656         u8         syndrome[0x20];
3657
3658         u8         reserved_at_40[0xc0];
3659
3660         struct mlx5_ifc_sqc_bits sq_context;
3661 };
3662
3663 struct mlx5_ifc_query_sq_in_bits {
3664         u8         opcode[0x10];
3665         u8         reserved_at_10[0x10];
3666
3667         u8         reserved_at_20[0x10];
3668         u8         op_mod[0x10];
3669
3670         u8         reserved_at_40[0x8];
3671         u8         sqn[0x18];
3672
3673         u8         reserved_at_60[0x20];
3674 };
3675
3676 struct mlx5_ifc_query_special_contexts_out_bits {
3677         u8         status[0x8];
3678         u8         reserved_at_8[0x18];
3679
3680         u8         syndrome[0x20];
3681
3682         u8         dump_fill_mkey[0x20];
3683
3684         u8         resd_lkey[0x20];
3685
3686         u8         null_mkey[0x20];
3687
3688         u8         reserved_at_a0[0x60];
3689 };
3690
3691 struct mlx5_ifc_query_special_contexts_in_bits {
3692         u8         opcode[0x10];
3693         u8         reserved_at_10[0x10];
3694
3695         u8         reserved_at_20[0x10];
3696         u8         op_mod[0x10];
3697
3698         u8         reserved_at_40[0x40];
3699 };
3700
3701 struct mlx5_ifc_query_scheduling_element_out_bits {
3702         u8         opcode[0x10];
3703         u8         reserved_at_10[0x10];
3704
3705         u8         reserved_at_20[0x10];
3706         u8         op_mod[0x10];
3707
3708         u8         reserved_at_40[0xc0];
3709
3710         struct mlx5_ifc_scheduling_context_bits scheduling_context;
3711
3712         u8         reserved_at_300[0x100];
3713 };
3714
3715 enum {
3716         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3717 };
3718
3719 struct mlx5_ifc_query_scheduling_element_in_bits {
3720         u8         opcode[0x10];
3721         u8         reserved_at_10[0x10];
3722
3723         u8         reserved_at_20[0x10];
3724         u8         op_mod[0x10];
3725
3726         u8         scheduling_hierarchy[0x8];
3727         u8         reserved_at_48[0x18];
3728
3729         u8         scheduling_element_id[0x20];
3730
3731         u8         reserved_at_80[0x180];
3732 };
3733
3734 struct mlx5_ifc_query_rqt_out_bits {
3735         u8         status[0x8];
3736         u8         reserved_at_8[0x18];
3737
3738         u8         syndrome[0x20];
3739
3740         u8         reserved_at_40[0xc0];
3741
3742         struct mlx5_ifc_rqtc_bits rqt_context;
3743 };
3744
3745 struct mlx5_ifc_query_rqt_in_bits {
3746         u8         opcode[0x10];
3747         u8         reserved_at_10[0x10];
3748
3749         u8         reserved_at_20[0x10];
3750         u8         op_mod[0x10];
3751
3752         u8         reserved_at_40[0x8];
3753         u8         rqtn[0x18];
3754
3755         u8         reserved_at_60[0x20];
3756 };
3757
3758 struct mlx5_ifc_query_rq_out_bits {
3759         u8         status[0x8];
3760         u8         reserved_at_8[0x18];
3761
3762         u8         syndrome[0x20];
3763
3764         u8         reserved_at_40[0xc0];
3765
3766         struct mlx5_ifc_rqc_bits rq_context;
3767 };
3768
3769 struct mlx5_ifc_query_rq_in_bits {
3770         u8         opcode[0x10];
3771         u8         reserved_at_10[0x10];
3772
3773         u8         reserved_at_20[0x10];
3774         u8         op_mod[0x10];
3775
3776         u8         reserved_at_40[0x8];
3777         u8         rqn[0x18];
3778
3779         u8         reserved_at_60[0x20];
3780 };
3781
3782 struct mlx5_ifc_query_roce_address_out_bits {
3783         u8         status[0x8];
3784         u8         reserved_at_8[0x18];
3785
3786         u8         syndrome[0x20];
3787
3788         u8         reserved_at_40[0x40];
3789
3790         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3791 };
3792
3793 struct mlx5_ifc_query_roce_address_in_bits {
3794         u8         opcode[0x10];
3795         u8         reserved_at_10[0x10];
3796
3797         u8         reserved_at_20[0x10];
3798         u8         op_mod[0x10];
3799
3800         u8         roce_address_index[0x10];
3801         u8         reserved_at_50[0x10];
3802
3803         u8         reserved_at_60[0x20];
3804 };
3805
3806 struct mlx5_ifc_query_rmp_out_bits {
3807         u8         status[0x8];
3808         u8         reserved_at_8[0x18];
3809
3810         u8         syndrome[0x20];
3811
3812         u8         reserved_at_40[0xc0];
3813
3814         struct mlx5_ifc_rmpc_bits rmp_context;
3815 };
3816
3817 struct mlx5_ifc_query_rmp_in_bits {
3818         u8         opcode[0x10];
3819         u8         reserved_at_10[0x10];
3820
3821         u8         reserved_at_20[0x10];
3822         u8         op_mod[0x10];
3823
3824         u8         reserved_at_40[0x8];
3825         u8         rmpn[0x18];
3826
3827         u8         reserved_at_60[0x20];
3828 };
3829
3830 struct mlx5_ifc_query_qp_out_bits {
3831         u8         status[0x8];
3832         u8         reserved_at_8[0x18];
3833
3834         u8         syndrome[0x20];
3835
3836         u8         reserved_at_40[0x40];
3837
3838         u8         opt_param_mask[0x20];
3839
3840         u8         reserved_at_a0[0x20];
3841
3842         struct mlx5_ifc_qpc_bits qpc;
3843
3844         u8         reserved_at_800[0x80];
3845
3846         u8         pas[0][0x40];
3847 };
3848
3849 struct mlx5_ifc_query_qp_in_bits {
3850         u8         opcode[0x10];
3851         u8         reserved_at_10[0x10];
3852
3853         u8         reserved_at_20[0x10];
3854         u8         op_mod[0x10];
3855
3856         u8         reserved_at_40[0x8];
3857         u8         qpn[0x18];
3858
3859         u8         reserved_at_60[0x20];
3860 };
3861
3862 struct mlx5_ifc_query_q_counter_out_bits {
3863         u8         status[0x8];
3864         u8         reserved_at_8[0x18];
3865
3866         u8         syndrome[0x20];
3867
3868         u8         reserved_at_40[0x40];
3869
3870         u8         rx_write_requests[0x20];
3871
3872         u8         reserved_at_a0[0x20];
3873
3874         u8         rx_read_requests[0x20];
3875
3876         u8         reserved_at_e0[0x20];
3877
3878         u8         rx_atomic_requests[0x20];
3879
3880         u8         reserved_at_120[0x20];
3881
3882         u8         rx_dct_connect[0x20];
3883
3884         u8         reserved_at_160[0x20];
3885
3886         u8         out_of_buffer[0x20];
3887
3888         u8         reserved_at_1a0[0x20];
3889
3890         u8         out_of_sequence[0x20];
3891
3892         u8         reserved_at_1e0[0x20];
3893
3894         u8         duplicate_request[0x20];
3895
3896         u8         reserved_at_220[0x20];
3897
3898         u8         rnr_nak_retry_err[0x20];
3899
3900         u8         reserved_at_260[0x20];
3901
3902         u8         packet_seq_err[0x20];
3903
3904         u8         reserved_at_2a0[0x20];
3905
3906         u8         implied_nak_seq_err[0x20];
3907
3908         u8         reserved_at_2e0[0x20];
3909
3910         u8         local_ack_timeout_err[0x20];
3911
3912         u8         reserved_at_320[0x4e0];
3913 };
3914
3915 struct mlx5_ifc_query_q_counter_in_bits {
3916         u8         opcode[0x10];
3917         u8         reserved_at_10[0x10];
3918
3919         u8         reserved_at_20[0x10];
3920         u8         op_mod[0x10];
3921
3922         u8         reserved_at_40[0x80];
3923
3924         u8         clear[0x1];
3925         u8         reserved_at_c1[0x1f];
3926
3927         u8         reserved_at_e0[0x18];
3928         u8         counter_set_id[0x8];
3929 };
3930
3931 struct mlx5_ifc_query_pages_out_bits {
3932         u8         status[0x8];
3933         u8         reserved_at_8[0x18];
3934
3935         u8         syndrome[0x20];
3936
3937         u8         reserved_at_40[0x10];
3938         u8         function_id[0x10];
3939
3940         u8         num_pages[0x20];
3941 };
3942
3943 enum {
3944         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3945         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3946         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3947 };
3948
3949 struct mlx5_ifc_query_pages_in_bits {
3950         u8         opcode[0x10];
3951         u8         reserved_at_10[0x10];
3952
3953         u8         reserved_at_20[0x10];
3954         u8         op_mod[0x10];
3955
3956         u8         reserved_at_40[0x10];
3957         u8         function_id[0x10];
3958
3959         u8         reserved_at_60[0x20];
3960 };
3961
3962 struct mlx5_ifc_query_nic_vport_context_out_bits {
3963         u8         status[0x8];
3964         u8         reserved_at_8[0x18];
3965
3966         u8         syndrome[0x20];
3967
3968         u8         reserved_at_40[0x40];
3969
3970         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3971 };
3972
3973 struct mlx5_ifc_query_nic_vport_context_in_bits {
3974         u8         opcode[0x10];
3975         u8         reserved_at_10[0x10];
3976
3977         u8         reserved_at_20[0x10];
3978         u8         op_mod[0x10];
3979
3980         u8         other_vport[0x1];
3981         u8         reserved_at_41[0xf];
3982         u8         vport_number[0x10];
3983
3984         u8         reserved_at_60[0x5];
3985         u8         allowed_list_type[0x3];
3986         u8         reserved_at_68[0x18];
3987 };
3988
3989 struct mlx5_ifc_query_mkey_out_bits {
3990         u8         status[0x8];
3991         u8         reserved_at_8[0x18];
3992
3993         u8         syndrome[0x20];
3994
3995         u8         reserved_at_40[0x40];
3996
3997         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3998
3999         u8         reserved_at_280[0x600];
4000
4001         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4002
4003         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4004 };
4005
4006 struct mlx5_ifc_query_mkey_in_bits {
4007         u8         opcode[0x10];
4008         u8         reserved_at_10[0x10];
4009
4010         u8         reserved_at_20[0x10];
4011         u8         op_mod[0x10];
4012
4013         u8         reserved_at_40[0x8];
4014         u8         mkey_index[0x18];
4015
4016         u8         pg_access[0x1];
4017         u8         reserved_at_61[0x1f];
4018 };
4019
4020 struct mlx5_ifc_query_mad_demux_out_bits {
4021         u8         status[0x8];
4022         u8         reserved_at_8[0x18];
4023
4024         u8         syndrome[0x20];
4025
4026         u8         reserved_at_40[0x40];
4027
4028         u8         mad_dumux_parameters_block[0x20];
4029 };
4030
4031 struct mlx5_ifc_query_mad_demux_in_bits {
4032         u8         opcode[0x10];
4033         u8         reserved_at_10[0x10];
4034
4035         u8         reserved_at_20[0x10];
4036         u8         op_mod[0x10];
4037
4038         u8         reserved_at_40[0x40];
4039 };
4040
4041 struct mlx5_ifc_query_l2_table_entry_out_bits {
4042         u8         status[0x8];
4043         u8         reserved_at_8[0x18];
4044
4045         u8         syndrome[0x20];
4046
4047         u8         reserved_at_40[0xa0];
4048
4049         u8         reserved_at_e0[0x13];
4050         u8         vlan_valid[0x1];
4051         u8         vlan[0xc];
4052
4053         struct mlx5_ifc_mac_address_layout_bits mac_address;
4054
4055         u8         reserved_at_140[0xc0];
4056 };
4057
4058 struct mlx5_ifc_query_l2_table_entry_in_bits {
4059         u8         opcode[0x10];
4060         u8         reserved_at_10[0x10];
4061
4062         u8         reserved_at_20[0x10];
4063         u8         op_mod[0x10];
4064
4065         u8         reserved_at_40[0x60];
4066
4067         u8         reserved_at_a0[0x8];
4068         u8         table_index[0x18];
4069
4070         u8         reserved_at_c0[0x140];
4071 };
4072
4073 struct mlx5_ifc_query_issi_out_bits {
4074         u8         status[0x8];
4075         u8         reserved_at_8[0x18];
4076
4077         u8         syndrome[0x20];
4078
4079         u8         reserved_at_40[0x10];
4080         u8         current_issi[0x10];
4081
4082         u8         reserved_at_60[0xa0];
4083
4084         u8         reserved_at_100[76][0x8];
4085         u8         supported_issi_dw0[0x20];
4086 };
4087
4088 struct mlx5_ifc_query_issi_in_bits {
4089         u8         opcode[0x10];
4090         u8         reserved_at_10[0x10];
4091
4092         u8         reserved_at_20[0x10];
4093         u8         op_mod[0x10];
4094
4095         u8         reserved_at_40[0x40];
4096 };
4097
4098 struct mlx5_ifc_set_driver_version_out_bits {
4099         u8         status[0x8];
4100         u8         reserved_0[0x18];
4101
4102         u8         syndrome[0x20];
4103         u8         reserved_1[0x40];
4104 };
4105
4106 struct mlx5_ifc_set_driver_version_in_bits {
4107         u8         opcode[0x10];
4108         u8         reserved_0[0x10];
4109
4110         u8         reserved_1[0x10];
4111         u8         op_mod[0x10];
4112
4113         u8         reserved_2[0x40];
4114         u8         driver_version[64][0x8];
4115 };
4116
4117 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4118         u8         status[0x8];
4119         u8         reserved_at_8[0x18];
4120
4121         u8         syndrome[0x20];
4122
4123         u8         reserved_at_40[0x40];
4124
4125         struct mlx5_ifc_pkey_bits pkey[0];
4126 };
4127
4128 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4129         u8         opcode[0x10];
4130         u8         reserved_at_10[0x10];
4131
4132         u8         reserved_at_20[0x10];
4133         u8         op_mod[0x10];
4134
4135         u8         other_vport[0x1];
4136         u8         reserved_at_41[0xb];
4137         u8         port_num[0x4];
4138         u8         vport_number[0x10];
4139
4140         u8         reserved_at_60[0x10];
4141         u8         pkey_index[0x10];
4142 };
4143
4144 enum {
4145         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4146         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4147         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4148 };
4149
4150 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4151         u8         status[0x8];
4152         u8         reserved_at_8[0x18];
4153
4154         u8         syndrome[0x20];
4155
4156         u8         reserved_at_40[0x20];
4157
4158         u8         gids_num[0x10];
4159         u8         reserved_at_70[0x10];
4160
4161         struct mlx5_ifc_array128_auto_bits gid[0];
4162 };
4163
4164 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4165         u8         opcode[0x10];
4166         u8         reserved_at_10[0x10];
4167
4168         u8         reserved_at_20[0x10];
4169         u8         op_mod[0x10];
4170
4171         u8         other_vport[0x1];
4172         u8         reserved_at_41[0xb];
4173         u8         port_num[0x4];
4174         u8         vport_number[0x10];
4175
4176         u8         reserved_at_60[0x10];
4177         u8         gid_index[0x10];
4178 };
4179
4180 struct mlx5_ifc_query_hca_vport_context_out_bits {
4181         u8         status[0x8];
4182         u8         reserved_at_8[0x18];
4183
4184         u8         syndrome[0x20];
4185
4186         u8         reserved_at_40[0x40];
4187
4188         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4189 };
4190
4191 struct mlx5_ifc_query_hca_vport_context_in_bits {
4192         u8         opcode[0x10];
4193         u8         reserved_at_10[0x10];
4194
4195         u8         reserved_at_20[0x10];
4196         u8         op_mod[0x10];
4197
4198         u8         other_vport[0x1];
4199         u8         reserved_at_41[0xb];
4200         u8         port_num[0x4];
4201         u8         vport_number[0x10];
4202
4203         u8         reserved_at_60[0x20];
4204 };
4205
4206 struct mlx5_ifc_query_hca_cap_out_bits {
4207         u8         status[0x8];
4208         u8         reserved_at_8[0x18];
4209
4210         u8         syndrome[0x20];
4211
4212         u8         reserved_at_40[0x40];
4213
4214         union mlx5_ifc_hca_cap_union_bits capability;
4215 };
4216
4217 struct mlx5_ifc_query_hca_cap_in_bits {
4218         u8         opcode[0x10];
4219         u8         reserved_at_10[0x10];
4220
4221         u8         reserved_at_20[0x10];
4222         u8         op_mod[0x10];
4223
4224         u8         reserved_at_40[0x40];
4225 };
4226
4227 struct mlx5_ifc_query_flow_table_out_bits {
4228         u8         status[0x8];
4229         u8         reserved_at_8[0x18];
4230
4231         u8         syndrome[0x20];
4232
4233         u8         reserved_at_40[0x80];
4234
4235         u8         reserved_at_c0[0x8];
4236         u8         level[0x8];
4237         u8         reserved_at_d0[0x8];
4238         u8         log_size[0x8];
4239
4240         u8         reserved_at_e0[0x120];
4241 };
4242
4243 struct mlx5_ifc_query_flow_table_in_bits {
4244         u8         opcode[0x10];
4245         u8         reserved_at_10[0x10];
4246
4247         u8         reserved_at_20[0x10];
4248         u8         op_mod[0x10];
4249
4250         u8         reserved_at_40[0x40];
4251
4252         u8         table_type[0x8];
4253         u8         reserved_at_88[0x18];
4254
4255         u8         reserved_at_a0[0x8];
4256         u8         table_id[0x18];
4257
4258         u8         reserved_at_c0[0x140];
4259 };
4260
4261 struct mlx5_ifc_query_fte_out_bits {
4262         u8         status[0x8];
4263         u8         reserved_at_8[0x18];
4264
4265         u8         syndrome[0x20];
4266
4267         u8         reserved_at_40[0x1c0];
4268
4269         struct mlx5_ifc_flow_context_bits flow_context;
4270 };
4271
4272 struct mlx5_ifc_query_fte_in_bits {
4273         u8         opcode[0x10];
4274         u8         reserved_at_10[0x10];
4275
4276         u8         reserved_at_20[0x10];
4277         u8         op_mod[0x10];
4278
4279         u8         reserved_at_40[0x40];
4280
4281         u8         table_type[0x8];
4282         u8         reserved_at_88[0x18];
4283
4284         u8         reserved_at_a0[0x8];
4285         u8         table_id[0x18];
4286
4287         u8         reserved_at_c0[0x40];
4288
4289         u8         flow_index[0x20];
4290
4291         u8         reserved_at_120[0xe0];
4292 };
4293
4294 enum {
4295         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4296         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4297         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4298 };
4299
4300 struct mlx5_ifc_query_flow_group_out_bits {
4301         u8         status[0x8];
4302         u8         reserved_at_8[0x18];
4303
4304         u8         syndrome[0x20];
4305
4306         u8         reserved_at_40[0xa0];
4307
4308         u8         start_flow_index[0x20];
4309
4310         u8         reserved_at_100[0x20];
4311
4312         u8         end_flow_index[0x20];
4313
4314         u8         reserved_at_140[0xa0];
4315
4316         u8         reserved_at_1e0[0x18];
4317         u8         match_criteria_enable[0x8];
4318
4319         struct mlx5_ifc_fte_match_param_bits match_criteria;
4320
4321         u8         reserved_at_1200[0xe00];
4322 };
4323
4324 struct mlx5_ifc_query_flow_group_in_bits {
4325         u8         opcode[0x10];
4326         u8         reserved_at_10[0x10];
4327
4328         u8         reserved_at_20[0x10];
4329         u8         op_mod[0x10];
4330
4331         u8         reserved_at_40[0x40];
4332
4333         u8         table_type[0x8];
4334         u8         reserved_at_88[0x18];
4335
4336         u8         reserved_at_a0[0x8];
4337         u8         table_id[0x18];
4338
4339         u8         group_id[0x20];
4340
4341         u8         reserved_at_e0[0x120];
4342 };
4343
4344 struct mlx5_ifc_query_flow_counter_out_bits {
4345         u8         status[0x8];
4346         u8         reserved_at_8[0x18];
4347
4348         u8         syndrome[0x20];
4349
4350         u8         reserved_at_40[0x40];
4351
4352         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4353 };
4354
4355 struct mlx5_ifc_query_flow_counter_in_bits {
4356         u8         opcode[0x10];
4357         u8         reserved_at_10[0x10];
4358
4359         u8         reserved_at_20[0x10];
4360         u8         op_mod[0x10];
4361
4362         u8         reserved_at_40[0x80];
4363
4364         u8         clear[0x1];
4365         u8         reserved_at_c1[0xf];
4366         u8         num_of_counters[0x10];
4367
4368         u8         reserved_at_e0[0x10];
4369         u8         flow_counter_id[0x10];
4370 };
4371
4372 struct mlx5_ifc_query_esw_vport_context_out_bits {
4373         u8         status[0x8];
4374         u8         reserved_at_8[0x18];
4375
4376         u8         syndrome[0x20];
4377
4378         u8         reserved_at_40[0x40];
4379
4380         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4381 };
4382
4383 struct mlx5_ifc_query_esw_vport_context_in_bits {
4384         u8         opcode[0x10];
4385         u8         reserved_at_10[0x10];
4386
4387         u8         reserved_at_20[0x10];
4388         u8         op_mod[0x10];
4389
4390         u8         other_vport[0x1];
4391         u8         reserved_at_41[0xf];
4392         u8         vport_number[0x10];
4393
4394         u8         reserved_at_60[0x20];
4395 };
4396
4397 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4398         u8         status[0x8];
4399         u8         reserved_at_8[0x18];
4400
4401         u8         syndrome[0x20];
4402
4403         u8         reserved_at_40[0x40];
4404 };
4405
4406 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4407         u8         reserved_at_0[0x1c];
4408         u8         vport_cvlan_insert[0x1];
4409         u8         vport_svlan_insert[0x1];
4410         u8         vport_cvlan_strip[0x1];
4411         u8         vport_svlan_strip[0x1];
4412 };
4413
4414 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4415         u8         opcode[0x10];
4416         u8         reserved_at_10[0x10];
4417
4418         u8         reserved_at_20[0x10];
4419         u8         op_mod[0x10];
4420
4421         u8         other_vport[0x1];
4422         u8         reserved_at_41[0xf];
4423         u8         vport_number[0x10];
4424
4425         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4426
4427         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4428 };
4429
4430 struct mlx5_ifc_query_eq_out_bits {
4431         u8         status[0x8];
4432         u8         reserved_at_8[0x18];
4433
4434         u8         syndrome[0x20];
4435
4436         u8         reserved_at_40[0x40];
4437
4438         struct mlx5_ifc_eqc_bits eq_context_entry;
4439
4440         u8         reserved_at_280[0x40];
4441
4442         u8         event_bitmask[0x40];
4443
4444         u8         reserved_at_300[0x580];
4445
4446         u8         pas[0][0x40];
4447 };
4448
4449 struct mlx5_ifc_query_eq_in_bits {
4450         u8         opcode[0x10];
4451         u8         reserved_at_10[0x10];
4452
4453         u8         reserved_at_20[0x10];
4454         u8         op_mod[0x10];
4455
4456         u8         reserved_at_40[0x18];
4457         u8         eq_number[0x8];
4458
4459         u8         reserved_at_60[0x20];
4460 };
4461
4462 struct mlx5_ifc_encap_header_in_bits {
4463         u8         reserved_at_0[0x5];
4464         u8         header_type[0x3];
4465         u8         reserved_at_8[0xe];
4466         u8         encap_header_size[0xa];
4467
4468         u8         reserved_at_20[0x10];
4469         u8         encap_header[2][0x8];
4470
4471         u8         more_encap_header[0][0x8];
4472 };
4473
4474 struct mlx5_ifc_query_encap_header_out_bits {
4475         u8         status[0x8];
4476         u8         reserved_at_8[0x18];
4477
4478         u8         syndrome[0x20];
4479
4480         u8         reserved_at_40[0xa0];
4481
4482         struct mlx5_ifc_encap_header_in_bits encap_header[0];
4483 };
4484
4485 struct mlx5_ifc_query_encap_header_in_bits {
4486         u8         opcode[0x10];
4487         u8         reserved_at_10[0x10];
4488
4489         u8         reserved_at_20[0x10];
4490         u8         op_mod[0x10];
4491
4492         u8         encap_id[0x20];
4493
4494         u8         reserved_at_60[0xa0];
4495 };
4496
4497 struct mlx5_ifc_alloc_encap_header_out_bits {
4498         u8         status[0x8];
4499         u8         reserved_at_8[0x18];
4500
4501         u8         syndrome[0x20];
4502
4503         u8         encap_id[0x20];
4504
4505         u8         reserved_at_60[0x20];
4506 };
4507
4508 struct mlx5_ifc_alloc_encap_header_in_bits {
4509         u8         opcode[0x10];
4510         u8         reserved_at_10[0x10];
4511
4512         u8         reserved_at_20[0x10];
4513         u8         op_mod[0x10];
4514
4515         u8         reserved_at_40[0xa0];
4516
4517         struct mlx5_ifc_encap_header_in_bits encap_header;
4518 };
4519
4520 struct mlx5_ifc_dealloc_encap_header_out_bits {
4521         u8         status[0x8];
4522         u8         reserved_at_8[0x18];
4523
4524         u8         syndrome[0x20];
4525
4526         u8         reserved_at_40[0x40];
4527 };
4528
4529 struct mlx5_ifc_dealloc_encap_header_in_bits {
4530         u8         opcode[0x10];
4531         u8         reserved_at_10[0x10];
4532
4533         u8         reserved_20[0x10];
4534         u8         op_mod[0x10];
4535
4536         u8         encap_id[0x20];
4537
4538         u8         reserved_60[0x20];
4539 };
4540
4541 struct mlx5_ifc_query_dct_out_bits {
4542         u8         status[0x8];
4543         u8         reserved_at_8[0x18];
4544
4545         u8         syndrome[0x20];
4546
4547         u8         reserved_at_40[0x40];
4548
4549         struct mlx5_ifc_dctc_bits dct_context_entry;
4550
4551         u8         reserved_at_280[0x180];
4552 };
4553
4554 struct mlx5_ifc_query_dct_in_bits {
4555         u8         opcode[0x10];
4556         u8         reserved_at_10[0x10];
4557
4558         u8         reserved_at_20[0x10];
4559         u8         op_mod[0x10];
4560
4561         u8         reserved_at_40[0x8];
4562         u8         dctn[0x18];
4563
4564         u8         reserved_at_60[0x20];
4565 };
4566
4567 struct mlx5_ifc_query_cq_out_bits {
4568         u8         status[0x8];
4569         u8         reserved_at_8[0x18];
4570
4571         u8         syndrome[0x20];
4572
4573         u8         reserved_at_40[0x40];
4574
4575         struct mlx5_ifc_cqc_bits cq_context;
4576
4577         u8         reserved_at_280[0x600];
4578
4579         u8         pas[0][0x40];
4580 };
4581
4582 struct mlx5_ifc_query_cq_in_bits {
4583         u8         opcode[0x10];
4584         u8         reserved_at_10[0x10];
4585
4586         u8         reserved_at_20[0x10];
4587         u8         op_mod[0x10];
4588
4589         u8         reserved_at_40[0x8];
4590         u8         cqn[0x18];
4591
4592         u8         reserved_at_60[0x20];
4593 };
4594
4595 struct mlx5_ifc_query_cong_status_out_bits {
4596         u8         status[0x8];
4597         u8         reserved_at_8[0x18];
4598
4599         u8         syndrome[0x20];
4600
4601         u8         reserved_at_40[0x20];
4602
4603         u8         enable[0x1];
4604         u8         tag_enable[0x1];
4605         u8         reserved_at_62[0x1e];
4606 };
4607
4608 struct mlx5_ifc_query_cong_status_in_bits {
4609         u8         opcode[0x10];
4610         u8         reserved_at_10[0x10];
4611
4612         u8         reserved_at_20[0x10];
4613         u8         op_mod[0x10];
4614
4615         u8         reserved_at_40[0x18];
4616         u8         priority[0x4];
4617         u8         cong_protocol[0x4];
4618
4619         u8         reserved_at_60[0x20];
4620 };
4621
4622 struct mlx5_ifc_query_cong_statistics_out_bits {
4623         u8         status[0x8];
4624         u8         reserved_at_8[0x18];
4625
4626         u8         syndrome[0x20];
4627
4628         u8         reserved_at_40[0x40];
4629
4630         u8         cur_flows[0x20];
4631
4632         u8         sum_flows[0x20];
4633
4634         u8         cnp_ignored_high[0x20];
4635
4636         u8         cnp_ignored_low[0x20];
4637
4638         u8         cnp_handled_high[0x20];
4639
4640         u8         cnp_handled_low[0x20];
4641
4642         u8         reserved_at_140[0x100];
4643
4644         u8         time_stamp_high[0x20];
4645
4646         u8         time_stamp_low[0x20];
4647
4648         u8         accumulators_period[0x20];
4649
4650         u8         ecn_marked_roce_packets_high[0x20];
4651
4652         u8         ecn_marked_roce_packets_low[0x20];
4653
4654         u8         cnps_sent_high[0x20];
4655
4656         u8         cnps_sent_low[0x20];
4657
4658         u8         reserved_at_320[0x560];
4659 };
4660
4661 struct mlx5_ifc_query_cong_statistics_in_bits {
4662         u8         opcode[0x10];
4663         u8         reserved_at_10[0x10];
4664
4665         u8         reserved_at_20[0x10];
4666         u8         op_mod[0x10];
4667
4668         u8         clear[0x1];
4669         u8         reserved_at_41[0x1f];
4670
4671         u8         reserved_at_60[0x20];
4672 };
4673
4674 struct mlx5_ifc_query_cong_params_out_bits {
4675         u8         status[0x8];
4676         u8         reserved_at_8[0x18];
4677
4678         u8         syndrome[0x20];
4679
4680         u8         reserved_at_40[0x40];
4681
4682         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4683 };
4684
4685 struct mlx5_ifc_query_cong_params_in_bits {
4686         u8         opcode[0x10];
4687         u8         reserved_at_10[0x10];
4688
4689         u8         reserved_at_20[0x10];
4690         u8         op_mod[0x10];
4691
4692         u8         reserved_at_40[0x1c];
4693         u8         cong_protocol[0x4];
4694
4695         u8         reserved_at_60[0x20];
4696 };
4697
4698 struct mlx5_ifc_query_adapter_out_bits {
4699         u8         status[0x8];
4700         u8         reserved_at_8[0x18];
4701
4702         u8         syndrome[0x20];
4703
4704         u8         reserved_at_40[0x40];
4705
4706         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4707 };
4708
4709 struct mlx5_ifc_query_adapter_in_bits {
4710         u8         opcode[0x10];
4711         u8         reserved_at_10[0x10];
4712
4713         u8         reserved_at_20[0x10];
4714         u8         op_mod[0x10];
4715
4716         u8         reserved_at_40[0x40];
4717 };
4718
4719 struct mlx5_ifc_qp_2rst_out_bits {
4720         u8         status[0x8];
4721         u8         reserved_at_8[0x18];
4722
4723         u8         syndrome[0x20];
4724
4725         u8         reserved_at_40[0x40];
4726 };
4727
4728 struct mlx5_ifc_qp_2rst_in_bits {
4729         u8         opcode[0x10];
4730         u8         reserved_at_10[0x10];
4731
4732         u8         reserved_at_20[0x10];
4733         u8         op_mod[0x10];
4734
4735         u8         reserved_at_40[0x8];
4736         u8         qpn[0x18];
4737
4738         u8         reserved_at_60[0x20];
4739 };
4740
4741 struct mlx5_ifc_qp_2err_out_bits {
4742         u8         status[0x8];
4743         u8         reserved_at_8[0x18];
4744
4745         u8         syndrome[0x20];
4746
4747         u8         reserved_at_40[0x40];
4748 };
4749
4750 struct mlx5_ifc_qp_2err_in_bits {
4751         u8         opcode[0x10];
4752         u8         reserved_at_10[0x10];
4753
4754         u8         reserved_at_20[0x10];
4755         u8         op_mod[0x10];
4756
4757         u8         reserved_at_40[0x8];
4758         u8         qpn[0x18];
4759
4760         u8         reserved_at_60[0x20];
4761 };
4762
4763 struct mlx5_ifc_page_fault_resume_out_bits {
4764         u8         status[0x8];
4765         u8         reserved_at_8[0x18];
4766
4767         u8         syndrome[0x20];
4768
4769         u8         reserved_at_40[0x40];
4770 };
4771
4772 struct mlx5_ifc_page_fault_resume_in_bits {
4773         u8         opcode[0x10];
4774         u8         reserved_at_10[0x10];
4775
4776         u8         reserved_at_20[0x10];
4777         u8         op_mod[0x10];
4778
4779         u8         error[0x1];
4780         u8         reserved_at_41[0x4];
4781         u8         page_fault_type[0x3];
4782         u8         wq_number[0x18];
4783
4784         u8         reserved_at_60[0x8];
4785         u8         token[0x18];
4786 };
4787
4788 struct mlx5_ifc_nop_out_bits {
4789         u8         status[0x8];
4790         u8         reserved_at_8[0x18];
4791
4792         u8         syndrome[0x20];
4793
4794         u8         reserved_at_40[0x40];
4795 };
4796
4797 struct mlx5_ifc_nop_in_bits {
4798         u8         opcode[0x10];
4799         u8         reserved_at_10[0x10];
4800
4801         u8         reserved_at_20[0x10];
4802         u8         op_mod[0x10];
4803
4804         u8         reserved_at_40[0x40];
4805 };
4806
4807 struct mlx5_ifc_modify_vport_state_out_bits {
4808         u8         status[0x8];
4809         u8         reserved_at_8[0x18];
4810
4811         u8         syndrome[0x20];
4812
4813         u8         reserved_at_40[0x40];
4814 };
4815
4816 struct mlx5_ifc_modify_vport_state_in_bits {
4817         u8         opcode[0x10];
4818         u8         reserved_at_10[0x10];
4819
4820         u8         reserved_at_20[0x10];
4821         u8         op_mod[0x10];
4822
4823         u8         other_vport[0x1];
4824         u8         reserved_at_41[0xf];
4825         u8         vport_number[0x10];
4826
4827         u8         reserved_at_60[0x18];
4828         u8         admin_state[0x4];
4829         u8         reserved_at_7c[0x4];
4830 };
4831
4832 struct mlx5_ifc_modify_tis_out_bits {
4833         u8         status[0x8];
4834         u8         reserved_at_8[0x18];
4835
4836         u8         syndrome[0x20];
4837
4838         u8         reserved_at_40[0x40];
4839 };
4840
4841 struct mlx5_ifc_modify_tis_bitmask_bits {
4842         u8         reserved_at_0[0x20];
4843
4844         u8         reserved_at_20[0x1d];
4845         u8         lag_tx_port_affinity[0x1];
4846         u8         strict_lag_tx_port_affinity[0x1];
4847         u8         prio[0x1];
4848 };
4849
4850 struct mlx5_ifc_modify_tis_in_bits {
4851         u8         opcode[0x10];
4852         u8         reserved_at_10[0x10];
4853
4854         u8         reserved_at_20[0x10];
4855         u8         op_mod[0x10];
4856
4857         u8         reserved_at_40[0x8];
4858         u8         tisn[0x18];
4859
4860         u8         reserved_at_60[0x20];
4861
4862         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4863
4864         u8         reserved_at_c0[0x40];
4865
4866         struct mlx5_ifc_tisc_bits ctx;
4867 };
4868
4869 struct mlx5_ifc_modify_tir_bitmask_bits {
4870         u8         reserved_at_0[0x20];
4871
4872         u8         reserved_at_20[0x1b];
4873         u8         self_lb_en[0x1];
4874         u8         reserved_at_3c[0x1];
4875         u8         hash[0x1];
4876         u8         reserved_at_3e[0x1];
4877         u8         lro[0x1];
4878 };
4879
4880 struct mlx5_ifc_modify_tir_out_bits {
4881         u8         status[0x8];
4882         u8         reserved_at_8[0x18];
4883
4884         u8         syndrome[0x20];
4885
4886         u8         reserved_at_40[0x40];
4887 };
4888
4889 struct mlx5_ifc_modify_tir_in_bits {
4890         u8         opcode[0x10];
4891         u8         reserved_at_10[0x10];
4892
4893         u8         reserved_at_20[0x10];
4894         u8         op_mod[0x10];
4895
4896         u8         reserved_at_40[0x8];
4897         u8         tirn[0x18];
4898
4899         u8         reserved_at_60[0x20];
4900
4901         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4902
4903         u8         reserved_at_c0[0x40];
4904
4905         struct mlx5_ifc_tirc_bits ctx;
4906 };
4907
4908 struct mlx5_ifc_modify_sq_out_bits {
4909         u8         status[0x8];
4910         u8         reserved_at_8[0x18];
4911
4912         u8         syndrome[0x20];
4913
4914         u8         reserved_at_40[0x40];
4915 };
4916
4917 struct mlx5_ifc_modify_sq_in_bits {
4918         u8         opcode[0x10];
4919         u8         reserved_at_10[0x10];
4920
4921         u8         reserved_at_20[0x10];
4922         u8         op_mod[0x10];
4923
4924         u8         sq_state[0x4];
4925         u8         reserved_at_44[0x4];
4926         u8         sqn[0x18];
4927
4928         u8         reserved_at_60[0x20];
4929
4930         u8         modify_bitmask[0x40];
4931
4932         u8         reserved_at_c0[0x40];
4933
4934         struct mlx5_ifc_sqc_bits ctx;
4935 };
4936
4937 struct mlx5_ifc_modify_scheduling_element_out_bits {
4938         u8         status[0x8];
4939         u8         reserved_at_8[0x18];
4940
4941         u8         syndrome[0x20];
4942
4943         u8         reserved_at_40[0x1c0];
4944 };
4945
4946 enum {
4947         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
4948         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
4949 };
4950
4951 struct mlx5_ifc_modify_scheduling_element_in_bits {
4952         u8         opcode[0x10];
4953         u8         reserved_at_10[0x10];
4954
4955         u8         reserved_at_20[0x10];
4956         u8         op_mod[0x10];
4957
4958         u8         scheduling_hierarchy[0x8];
4959         u8         reserved_at_48[0x18];
4960
4961         u8         scheduling_element_id[0x20];
4962
4963         u8         reserved_at_80[0x20];
4964
4965         u8         modify_bitmask[0x20];
4966
4967         u8         reserved_at_c0[0x40];
4968
4969         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4970
4971         u8         reserved_at_300[0x100];
4972 };
4973
4974 struct mlx5_ifc_modify_rqt_out_bits {
4975         u8         status[0x8];
4976         u8         reserved_at_8[0x18];
4977
4978         u8         syndrome[0x20];
4979
4980         u8         reserved_at_40[0x40];
4981 };
4982
4983 struct mlx5_ifc_rqt_bitmask_bits {
4984         u8         reserved_at_0[0x20];
4985
4986         u8         reserved_at_20[0x1f];
4987         u8         rqn_list[0x1];
4988 };
4989
4990 struct mlx5_ifc_modify_rqt_in_bits {
4991         u8         opcode[0x10];
4992         u8         reserved_at_10[0x10];
4993
4994         u8         reserved_at_20[0x10];
4995         u8         op_mod[0x10];
4996
4997         u8         reserved_at_40[0x8];
4998         u8         rqtn[0x18];
4999
5000         u8         reserved_at_60[0x20];
5001
5002         struct mlx5_ifc_rqt_bitmask_bits bitmask;
5003
5004         u8         reserved_at_c0[0x40];
5005
5006         struct mlx5_ifc_rqtc_bits ctx;
5007 };
5008
5009 struct mlx5_ifc_modify_rq_out_bits {
5010         u8         status[0x8];
5011         u8         reserved_at_8[0x18];
5012
5013         u8         syndrome[0x20];
5014
5015         u8         reserved_at_40[0x40];
5016 };
5017
5018 enum {
5019         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5020         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
5021 };
5022
5023 struct mlx5_ifc_modify_rq_in_bits {
5024         u8         opcode[0x10];
5025         u8         reserved_at_10[0x10];
5026
5027         u8         reserved_at_20[0x10];
5028         u8         op_mod[0x10];
5029
5030         u8         rq_state[0x4];
5031         u8         reserved_at_44[0x4];
5032         u8         rqn[0x18];
5033
5034         u8         reserved_at_60[0x20];
5035
5036         u8         modify_bitmask[0x40];
5037
5038         u8         reserved_at_c0[0x40];
5039
5040         struct mlx5_ifc_rqc_bits ctx;
5041 };
5042
5043 struct mlx5_ifc_modify_rmp_out_bits {
5044         u8         status[0x8];
5045         u8         reserved_at_8[0x18];
5046
5047         u8         syndrome[0x20];
5048
5049         u8         reserved_at_40[0x40];
5050 };
5051
5052 struct mlx5_ifc_rmp_bitmask_bits {
5053         u8         reserved_at_0[0x20];
5054
5055         u8         reserved_at_20[0x1f];
5056         u8         lwm[0x1];
5057 };
5058
5059 struct mlx5_ifc_modify_rmp_in_bits {
5060         u8         opcode[0x10];
5061         u8         reserved_at_10[0x10];
5062
5063         u8         reserved_at_20[0x10];
5064         u8         op_mod[0x10];
5065
5066         u8         rmp_state[0x4];
5067         u8         reserved_at_44[0x4];
5068         u8         rmpn[0x18];
5069
5070         u8         reserved_at_60[0x20];
5071
5072         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5073
5074         u8         reserved_at_c0[0x40];
5075
5076         struct mlx5_ifc_rmpc_bits ctx;
5077 };
5078
5079 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5080         u8         status[0x8];
5081         u8         reserved_at_8[0x18];
5082
5083         u8         syndrome[0x20];
5084
5085         u8         reserved_at_40[0x40];
5086 };
5087
5088 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5089         u8         reserved_at_0[0x16];
5090         u8         node_guid[0x1];
5091         u8         port_guid[0x1];
5092         u8         min_inline[0x1];
5093         u8         mtu[0x1];
5094         u8         change_event[0x1];
5095         u8         promisc[0x1];
5096         u8         permanent_address[0x1];
5097         u8         addresses_list[0x1];
5098         u8         roce_en[0x1];
5099         u8         reserved_at_1f[0x1];
5100 };
5101
5102 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5103         u8         opcode[0x10];
5104         u8         reserved_at_10[0x10];
5105
5106         u8         reserved_at_20[0x10];
5107         u8         op_mod[0x10];
5108
5109         u8         other_vport[0x1];
5110         u8         reserved_at_41[0xf];
5111         u8         vport_number[0x10];
5112
5113         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5114
5115         u8         reserved_at_80[0x780];
5116
5117         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5118 };
5119
5120 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5121         u8         status[0x8];
5122         u8         reserved_at_8[0x18];
5123
5124         u8         syndrome[0x20];
5125
5126         u8         reserved_at_40[0x40];
5127 };
5128
5129 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5130         u8         opcode[0x10];
5131         u8         reserved_at_10[0x10];
5132
5133         u8         reserved_at_20[0x10];
5134         u8         op_mod[0x10];
5135
5136         u8         other_vport[0x1];
5137         u8         reserved_at_41[0xb];
5138         u8         port_num[0x4];
5139         u8         vport_number[0x10];
5140
5141         u8         reserved_at_60[0x20];
5142
5143         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5144 };
5145
5146 struct mlx5_ifc_modify_cq_out_bits {
5147         u8         status[0x8];
5148         u8         reserved_at_8[0x18];
5149
5150         u8         syndrome[0x20];
5151
5152         u8         reserved_at_40[0x40];
5153 };
5154
5155 enum {
5156         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5157         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5158 };
5159
5160 struct mlx5_ifc_modify_cq_in_bits {
5161         u8         opcode[0x10];
5162         u8         reserved_at_10[0x10];
5163
5164         u8         reserved_at_20[0x10];
5165         u8         op_mod[0x10];
5166
5167         u8         reserved_at_40[0x8];
5168         u8         cqn[0x18];
5169
5170         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5171
5172         struct mlx5_ifc_cqc_bits cq_context;
5173
5174         u8         reserved_at_280[0x600];
5175
5176         u8         pas[0][0x40];
5177 };
5178
5179 struct mlx5_ifc_modify_cong_status_out_bits {
5180         u8         status[0x8];
5181         u8         reserved_at_8[0x18];
5182
5183         u8         syndrome[0x20];
5184
5185         u8         reserved_at_40[0x40];
5186 };
5187
5188 struct mlx5_ifc_modify_cong_status_in_bits {
5189         u8         opcode[0x10];
5190         u8         reserved_at_10[0x10];
5191
5192         u8         reserved_at_20[0x10];
5193         u8         op_mod[0x10];
5194
5195         u8         reserved_at_40[0x18];
5196         u8         priority[0x4];
5197         u8         cong_protocol[0x4];
5198
5199         u8         enable[0x1];
5200         u8         tag_enable[0x1];
5201         u8         reserved_at_62[0x1e];
5202 };
5203
5204 struct mlx5_ifc_modify_cong_params_out_bits {
5205         u8         status[0x8];
5206         u8         reserved_at_8[0x18];
5207
5208         u8         syndrome[0x20];
5209
5210         u8         reserved_at_40[0x40];
5211 };
5212
5213 struct mlx5_ifc_modify_cong_params_in_bits {
5214         u8         opcode[0x10];
5215         u8         reserved_at_10[0x10];
5216
5217         u8         reserved_at_20[0x10];
5218         u8         op_mod[0x10];
5219
5220         u8         reserved_at_40[0x1c];
5221         u8         cong_protocol[0x4];
5222
5223         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5224
5225         u8         reserved_at_80[0x80];
5226
5227         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5228 };
5229
5230 struct mlx5_ifc_manage_pages_out_bits {
5231         u8         status[0x8];
5232         u8         reserved_at_8[0x18];
5233
5234         u8         syndrome[0x20];
5235
5236         u8         output_num_entries[0x20];
5237
5238         u8         reserved_at_60[0x20];
5239
5240         u8         pas[0][0x40];
5241 };
5242
5243 enum {
5244         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5245         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5246         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5247 };
5248
5249 struct mlx5_ifc_manage_pages_in_bits {
5250         u8         opcode[0x10];
5251         u8         reserved_at_10[0x10];
5252
5253         u8         reserved_at_20[0x10];
5254         u8         op_mod[0x10];
5255
5256         u8         reserved_at_40[0x10];
5257         u8         function_id[0x10];
5258
5259         u8         input_num_entries[0x20];
5260
5261         u8         pas[0][0x40];
5262 };
5263
5264 struct mlx5_ifc_mad_ifc_out_bits {
5265         u8         status[0x8];
5266         u8         reserved_at_8[0x18];
5267
5268         u8         syndrome[0x20];
5269
5270         u8         reserved_at_40[0x40];
5271
5272         u8         response_mad_packet[256][0x8];
5273 };
5274
5275 struct mlx5_ifc_mad_ifc_in_bits {
5276         u8         opcode[0x10];
5277         u8         reserved_at_10[0x10];
5278
5279         u8         reserved_at_20[0x10];
5280         u8         op_mod[0x10];
5281
5282         u8         remote_lid[0x10];
5283         u8         reserved_at_50[0x8];
5284         u8         port[0x8];
5285
5286         u8         reserved_at_60[0x20];
5287
5288         u8         mad[256][0x8];
5289 };
5290
5291 struct mlx5_ifc_init_hca_out_bits {
5292         u8         status[0x8];
5293         u8         reserved_at_8[0x18];
5294
5295         u8         syndrome[0x20];
5296
5297         u8         reserved_at_40[0x40];
5298 };
5299
5300 struct mlx5_ifc_init_hca_in_bits {
5301         u8         opcode[0x10];
5302         u8         reserved_at_10[0x10];
5303
5304         u8         reserved_at_20[0x10];
5305         u8         op_mod[0x10];
5306
5307         u8         reserved_at_40[0x40];
5308 };
5309
5310 struct mlx5_ifc_init2rtr_qp_out_bits {
5311         u8         status[0x8];
5312         u8         reserved_at_8[0x18];
5313
5314         u8         syndrome[0x20];
5315
5316         u8         reserved_at_40[0x40];
5317 };
5318
5319 struct mlx5_ifc_init2rtr_qp_in_bits {
5320         u8         opcode[0x10];
5321         u8         reserved_at_10[0x10];
5322
5323         u8         reserved_at_20[0x10];
5324         u8         op_mod[0x10];
5325
5326         u8         reserved_at_40[0x8];
5327         u8         qpn[0x18];
5328
5329         u8         reserved_at_60[0x20];
5330
5331         u8         opt_param_mask[0x20];
5332
5333         u8         reserved_at_a0[0x20];
5334
5335         struct mlx5_ifc_qpc_bits qpc;
5336
5337         u8         reserved_at_800[0x80];
5338 };
5339
5340 struct mlx5_ifc_init2init_qp_out_bits {
5341         u8         status[0x8];
5342         u8         reserved_at_8[0x18];
5343
5344         u8         syndrome[0x20];
5345
5346         u8         reserved_at_40[0x40];
5347 };
5348
5349 struct mlx5_ifc_init2init_qp_in_bits {
5350         u8         opcode[0x10];
5351         u8         reserved_at_10[0x10];
5352
5353         u8         reserved_at_20[0x10];
5354         u8         op_mod[0x10];
5355
5356         u8         reserved_at_40[0x8];
5357         u8         qpn[0x18];
5358
5359         u8         reserved_at_60[0x20];
5360
5361         u8         opt_param_mask[0x20];
5362
5363         u8         reserved_at_a0[0x20];
5364
5365         struct mlx5_ifc_qpc_bits qpc;
5366
5367         u8         reserved_at_800[0x80];
5368 };
5369
5370 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5371         u8         status[0x8];
5372         u8         reserved_at_8[0x18];
5373
5374         u8         syndrome[0x20];
5375
5376         u8         reserved_at_40[0x40];
5377
5378         u8         packet_headers_log[128][0x8];
5379
5380         u8         packet_syndrome[64][0x8];
5381 };
5382
5383 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5384         u8         opcode[0x10];
5385         u8         reserved_at_10[0x10];
5386
5387         u8         reserved_at_20[0x10];
5388         u8         op_mod[0x10];
5389
5390         u8         reserved_at_40[0x40];
5391 };
5392
5393 struct mlx5_ifc_gen_eqe_in_bits {
5394         u8         opcode[0x10];
5395         u8         reserved_at_10[0x10];
5396
5397         u8         reserved_at_20[0x10];
5398         u8         op_mod[0x10];
5399
5400         u8         reserved_at_40[0x18];
5401         u8         eq_number[0x8];
5402
5403         u8         reserved_at_60[0x20];
5404
5405         u8         eqe[64][0x8];
5406 };
5407
5408 struct mlx5_ifc_gen_eq_out_bits {
5409         u8         status[0x8];
5410         u8         reserved_at_8[0x18];
5411
5412         u8         syndrome[0x20];
5413
5414         u8         reserved_at_40[0x40];
5415 };
5416
5417 struct mlx5_ifc_enable_hca_out_bits {
5418         u8         status[0x8];
5419         u8         reserved_at_8[0x18];
5420
5421         u8         syndrome[0x20];
5422
5423         u8         reserved_at_40[0x20];
5424 };
5425
5426 struct mlx5_ifc_enable_hca_in_bits {
5427         u8         opcode[0x10];
5428         u8         reserved_at_10[0x10];
5429
5430         u8         reserved_at_20[0x10];
5431         u8         op_mod[0x10];
5432
5433         u8         reserved_at_40[0x10];
5434         u8         function_id[0x10];
5435
5436         u8         reserved_at_60[0x20];
5437 };
5438
5439 struct mlx5_ifc_drain_dct_out_bits {
5440         u8         status[0x8];
5441         u8         reserved_at_8[0x18];
5442
5443         u8         syndrome[0x20];
5444
5445         u8         reserved_at_40[0x40];
5446 };
5447
5448 struct mlx5_ifc_drain_dct_in_bits {
5449         u8         opcode[0x10];
5450         u8         reserved_at_10[0x10];
5451
5452         u8         reserved_at_20[0x10];
5453         u8         op_mod[0x10];
5454
5455         u8         reserved_at_40[0x8];
5456         u8         dctn[0x18];
5457
5458         u8         reserved_at_60[0x20];
5459 };
5460
5461 struct mlx5_ifc_disable_hca_out_bits {
5462         u8         status[0x8];
5463         u8         reserved_at_8[0x18];
5464
5465         u8         syndrome[0x20];
5466
5467         u8         reserved_at_40[0x20];
5468 };
5469
5470 struct mlx5_ifc_disable_hca_in_bits {
5471         u8         opcode[0x10];
5472         u8         reserved_at_10[0x10];
5473
5474         u8         reserved_at_20[0x10];
5475         u8         op_mod[0x10];
5476
5477         u8         reserved_at_40[0x10];
5478         u8         function_id[0x10];
5479
5480         u8         reserved_at_60[0x20];
5481 };
5482
5483 struct mlx5_ifc_detach_from_mcg_out_bits {
5484         u8         status[0x8];
5485         u8         reserved_at_8[0x18];
5486
5487         u8         syndrome[0x20];
5488
5489         u8         reserved_at_40[0x40];
5490 };
5491
5492 struct mlx5_ifc_detach_from_mcg_in_bits {
5493         u8         opcode[0x10];
5494         u8         reserved_at_10[0x10];
5495
5496         u8         reserved_at_20[0x10];
5497         u8         op_mod[0x10];
5498
5499         u8         reserved_at_40[0x8];
5500         u8         qpn[0x18];
5501
5502         u8         reserved_at_60[0x20];
5503
5504         u8         multicast_gid[16][0x8];
5505 };
5506
5507 struct mlx5_ifc_destroy_xrq_out_bits {
5508         u8         status[0x8];
5509         u8         reserved_at_8[0x18];
5510
5511         u8         syndrome[0x20];
5512
5513         u8         reserved_at_40[0x40];
5514 };
5515
5516 struct mlx5_ifc_destroy_xrq_in_bits {
5517         u8         opcode[0x10];
5518         u8         reserved_at_10[0x10];
5519
5520         u8         reserved_at_20[0x10];
5521         u8         op_mod[0x10];
5522
5523         u8         reserved_at_40[0x8];
5524         u8         xrqn[0x18];
5525
5526         u8         reserved_at_60[0x20];
5527 };
5528
5529 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5530         u8         status[0x8];
5531         u8         reserved_at_8[0x18];
5532
5533         u8         syndrome[0x20];
5534
5535         u8         reserved_at_40[0x40];
5536 };
5537
5538 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5539         u8         opcode[0x10];
5540         u8         reserved_at_10[0x10];
5541
5542         u8         reserved_at_20[0x10];
5543         u8         op_mod[0x10];
5544
5545         u8         reserved_at_40[0x8];
5546         u8         xrc_srqn[0x18];
5547
5548         u8         reserved_at_60[0x20];
5549 };
5550
5551 struct mlx5_ifc_destroy_tis_out_bits {
5552         u8         status[0x8];
5553         u8         reserved_at_8[0x18];
5554
5555         u8         syndrome[0x20];
5556
5557         u8         reserved_at_40[0x40];
5558 };
5559
5560 struct mlx5_ifc_destroy_tis_in_bits {
5561         u8         opcode[0x10];
5562         u8         reserved_at_10[0x10];
5563
5564         u8         reserved_at_20[0x10];
5565         u8         op_mod[0x10];
5566
5567         u8         reserved_at_40[0x8];
5568         u8         tisn[0x18];
5569
5570         u8         reserved_at_60[0x20];
5571 };
5572
5573 struct mlx5_ifc_destroy_tir_out_bits {
5574         u8         status[0x8];
5575         u8         reserved_at_8[0x18];
5576
5577         u8         syndrome[0x20];
5578
5579         u8         reserved_at_40[0x40];
5580 };
5581
5582 struct mlx5_ifc_destroy_tir_in_bits {
5583         u8         opcode[0x10];
5584         u8         reserved_at_10[0x10];
5585
5586         u8         reserved_at_20[0x10];
5587         u8         op_mod[0x10];
5588
5589         u8         reserved_at_40[0x8];
5590         u8         tirn[0x18];
5591
5592         u8         reserved_at_60[0x20];
5593 };
5594
5595 struct mlx5_ifc_destroy_srq_out_bits {
5596         u8         status[0x8];
5597         u8         reserved_at_8[0x18];
5598
5599         u8         syndrome[0x20];
5600
5601         u8         reserved_at_40[0x40];
5602 };
5603
5604 struct mlx5_ifc_destroy_srq_in_bits {
5605         u8         opcode[0x10];
5606         u8         reserved_at_10[0x10];
5607
5608         u8         reserved_at_20[0x10];
5609         u8         op_mod[0x10];
5610
5611         u8         reserved_at_40[0x8];
5612         u8         srqn[0x18];
5613
5614         u8         reserved_at_60[0x20];
5615 };
5616
5617 struct mlx5_ifc_destroy_sq_out_bits {
5618         u8         status[0x8];
5619         u8         reserved_at_8[0x18];
5620
5621         u8         syndrome[0x20];
5622
5623         u8         reserved_at_40[0x40];
5624 };
5625
5626 struct mlx5_ifc_destroy_sq_in_bits {
5627         u8         opcode[0x10];
5628         u8         reserved_at_10[0x10];
5629
5630         u8         reserved_at_20[0x10];
5631         u8         op_mod[0x10];
5632
5633         u8         reserved_at_40[0x8];
5634         u8         sqn[0x18];
5635
5636         u8         reserved_at_60[0x20];
5637 };
5638
5639 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5640         u8         status[0x8];
5641         u8         reserved_at_8[0x18];
5642
5643         u8         syndrome[0x20];
5644
5645         u8         reserved_at_40[0x1c0];
5646 };
5647
5648 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5649         u8         opcode[0x10];
5650         u8         reserved_at_10[0x10];
5651
5652         u8         reserved_at_20[0x10];
5653         u8         op_mod[0x10];
5654
5655         u8         scheduling_hierarchy[0x8];
5656         u8         reserved_at_48[0x18];
5657
5658         u8         scheduling_element_id[0x20];
5659
5660         u8         reserved_at_80[0x180];
5661 };
5662
5663 struct mlx5_ifc_destroy_rqt_out_bits {
5664         u8         status[0x8];
5665         u8         reserved_at_8[0x18];
5666
5667         u8         syndrome[0x20];
5668
5669         u8         reserved_at_40[0x40];
5670 };
5671
5672 struct mlx5_ifc_destroy_rqt_in_bits {
5673         u8         opcode[0x10];
5674         u8         reserved_at_10[0x10];
5675
5676         u8         reserved_at_20[0x10];
5677         u8         op_mod[0x10];
5678
5679         u8         reserved_at_40[0x8];
5680         u8         rqtn[0x18];
5681
5682         u8         reserved_at_60[0x20];
5683 };
5684
5685 struct mlx5_ifc_destroy_rq_out_bits {
5686         u8         status[0x8];
5687         u8         reserved_at_8[0x18];
5688
5689         u8         syndrome[0x20];
5690
5691         u8         reserved_at_40[0x40];
5692 };
5693
5694 struct mlx5_ifc_destroy_rq_in_bits {
5695         u8         opcode[0x10];
5696         u8         reserved_at_10[0x10];
5697
5698         u8         reserved_at_20[0x10];
5699         u8         op_mod[0x10];
5700
5701         u8         reserved_at_40[0x8];
5702         u8         rqn[0x18];
5703
5704         u8         reserved_at_60[0x20];
5705 };
5706
5707 struct mlx5_ifc_destroy_rmp_out_bits {
5708         u8         status[0x8];
5709         u8         reserved_at_8[0x18];
5710
5711         u8         syndrome[0x20];
5712
5713         u8         reserved_at_40[0x40];
5714 };
5715
5716 struct mlx5_ifc_destroy_rmp_in_bits {
5717         u8         opcode[0x10];
5718         u8         reserved_at_10[0x10];
5719
5720         u8         reserved_at_20[0x10];
5721         u8         op_mod[0x10];
5722
5723         u8         reserved_at_40[0x8];
5724         u8         rmpn[0x18];
5725
5726         u8         reserved_at_60[0x20];
5727 };
5728
5729 struct mlx5_ifc_destroy_qp_out_bits {
5730         u8         status[0x8];
5731         u8         reserved_at_8[0x18];
5732
5733         u8         syndrome[0x20];
5734
5735         u8         reserved_at_40[0x40];
5736 };
5737
5738 struct mlx5_ifc_destroy_qp_in_bits {
5739         u8         opcode[0x10];
5740         u8         reserved_at_10[0x10];
5741
5742         u8         reserved_at_20[0x10];
5743         u8         op_mod[0x10];
5744
5745         u8         reserved_at_40[0x8];
5746         u8         qpn[0x18];
5747
5748         u8         reserved_at_60[0x20];
5749 };
5750
5751 struct mlx5_ifc_destroy_psv_out_bits {
5752         u8         status[0x8];
5753         u8         reserved_at_8[0x18];
5754
5755         u8         syndrome[0x20];
5756
5757         u8         reserved_at_40[0x40];
5758 };
5759
5760 struct mlx5_ifc_destroy_psv_in_bits {
5761         u8         opcode[0x10];
5762         u8         reserved_at_10[0x10];
5763
5764         u8         reserved_at_20[0x10];
5765         u8         op_mod[0x10];
5766
5767         u8         reserved_at_40[0x8];
5768         u8         psvn[0x18];
5769
5770         u8         reserved_at_60[0x20];
5771 };
5772
5773 struct mlx5_ifc_destroy_mkey_out_bits {
5774         u8         status[0x8];
5775         u8         reserved_at_8[0x18];
5776
5777         u8         syndrome[0x20];
5778
5779         u8         reserved_at_40[0x40];
5780 };
5781
5782 struct mlx5_ifc_destroy_mkey_in_bits {
5783         u8         opcode[0x10];
5784         u8         reserved_at_10[0x10];
5785
5786         u8         reserved_at_20[0x10];
5787         u8         op_mod[0x10];
5788
5789         u8         reserved_at_40[0x8];
5790         u8         mkey_index[0x18];
5791
5792         u8         reserved_at_60[0x20];
5793 };
5794
5795 struct mlx5_ifc_destroy_flow_table_out_bits {
5796         u8         status[0x8];
5797         u8         reserved_at_8[0x18];
5798
5799         u8         syndrome[0x20];
5800
5801         u8         reserved_at_40[0x40];
5802 };
5803
5804 struct mlx5_ifc_destroy_flow_table_in_bits {
5805         u8         opcode[0x10];
5806         u8         reserved_at_10[0x10];
5807
5808         u8         reserved_at_20[0x10];
5809         u8         op_mod[0x10];
5810
5811         u8         other_vport[0x1];
5812         u8         reserved_at_41[0xf];
5813         u8         vport_number[0x10];
5814
5815         u8         reserved_at_60[0x20];
5816
5817         u8         table_type[0x8];
5818         u8         reserved_at_88[0x18];
5819
5820         u8         reserved_at_a0[0x8];
5821         u8         table_id[0x18];
5822
5823         u8         reserved_at_c0[0x140];
5824 };
5825
5826 struct mlx5_ifc_destroy_flow_group_out_bits {
5827         u8         status[0x8];
5828         u8         reserved_at_8[0x18];
5829
5830         u8         syndrome[0x20];
5831
5832         u8         reserved_at_40[0x40];
5833 };
5834
5835 struct mlx5_ifc_destroy_flow_group_in_bits {
5836         u8         opcode[0x10];
5837         u8         reserved_at_10[0x10];
5838
5839         u8         reserved_at_20[0x10];
5840         u8         op_mod[0x10];
5841
5842         u8         other_vport[0x1];
5843         u8         reserved_at_41[0xf];
5844         u8         vport_number[0x10];
5845
5846         u8         reserved_at_60[0x20];
5847
5848         u8         table_type[0x8];
5849         u8         reserved_at_88[0x18];
5850
5851         u8         reserved_at_a0[0x8];
5852         u8         table_id[0x18];
5853
5854         u8         group_id[0x20];
5855
5856         u8         reserved_at_e0[0x120];
5857 };
5858
5859 struct mlx5_ifc_destroy_eq_out_bits {
5860         u8         status[0x8];
5861         u8         reserved_at_8[0x18];
5862
5863         u8         syndrome[0x20];
5864
5865         u8         reserved_at_40[0x40];
5866 };
5867
5868 struct mlx5_ifc_destroy_eq_in_bits {
5869         u8         opcode[0x10];
5870         u8         reserved_at_10[0x10];
5871
5872         u8         reserved_at_20[0x10];
5873         u8         op_mod[0x10];
5874
5875         u8         reserved_at_40[0x18];
5876         u8         eq_number[0x8];
5877
5878         u8         reserved_at_60[0x20];
5879 };
5880
5881 struct mlx5_ifc_destroy_dct_out_bits {
5882         u8         status[0x8];
5883         u8         reserved_at_8[0x18];
5884
5885         u8         syndrome[0x20];
5886
5887         u8         reserved_at_40[0x40];
5888 };
5889
5890 struct mlx5_ifc_destroy_dct_in_bits {
5891         u8         opcode[0x10];
5892         u8         reserved_at_10[0x10];
5893
5894         u8         reserved_at_20[0x10];
5895         u8         op_mod[0x10];
5896
5897         u8         reserved_at_40[0x8];
5898         u8         dctn[0x18];
5899
5900         u8         reserved_at_60[0x20];
5901 };
5902
5903 struct mlx5_ifc_destroy_cq_out_bits {
5904         u8         status[0x8];
5905         u8         reserved_at_8[0x18];
5906
5907         u8         syndrome[0x20];
5908
5909         u8         reserved_at_40[0x40];
5910 };
5911
5912 struct mlx5_ifc_destroy_cq_in_bits {
5913         u8         opcode[0x10];
5914         u8         reserved_at_10[0x10];
5915
5916         u8         reserved_at_20[0x10];
5917         u8         op_mod[0x10];
5918
5919         u8         reserved_at_40[0x8];
5920         u8         cqn[0x18];
5921
5922         u8         reserved_at_60[0x20];
5923 };
5924
5925 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5926         u8         status[0x8];
5927         u8         reserved_at_8[0x18];
5928
5929         u8         syndrome[0x20];
5930
5931         u8         reserved_at_40[0x40];
5932 };
5933
5934 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5935         u8         opcode[0x10];
5936         u8         reserved_at_10[0x10];
5937
5938         u8         reserved_at_20[0x10];
5939         u8         op_mod[0x10];
5940
5941         u8         reserved_at_40[0x20];
5942
5943         u8         reserved_at_60[0x10];
5944         u8         vxlan_udp_port[0x10];
5945 };
5946
5947 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5948         u8         status[0x8];
5949         u8         reserved_at_8[0x18];
5950
5951         u8         syndrome[0x20];
5952
5953         u8         reserved_at_40[0x40];
5954 };
5955
5956 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5957         u8         opcode[0x10];
5958         u8         reserved_at_10[0x10];
5959
5960         u8         reserved_at_20[0x10];
5961         u8         op_mod[0x10];
5962
5963         u8         reserved_at_40[0x60];
5964
5965         u8         reserved_at_a0[0x8];
5966         u8         table_index[0x18];
5967
5968         u8         reserved_at_c0[0x140];
5969 };
5970
5971 struct mlx5_ifc_delete_fte_out_bits {
5972         u8         status[0x8];
5973         u8         reserved_at_8[0x18];
5974
5975         u8         syndrome[0x20];
5976
5977         u8         reserved_at_40[0x40];
5978 };
5979
5980 struct mlx5_ifc_delete_fte_in_bits {
5981         u8         opcode[0x10];
5982         u8         reserved_at_10[0x10];
5983
5984         u8         reserved_at_20[0x10];
5985         u8         op_mod[0x10];
5986
5987         u8         other_vport[0x1];
5988         u8         reserved_at_41[0xf];
5989         u8         vport_number[0x10];
5990
5991         u8         reserved_at_60[0x20];
5992
5993         u8         table_type[0x8];
5994         u8         reserved_at_88[0x18];
5995
5996         u8         reserved_at_a0[0x8];
5997         u8         table_id[0x18];
5998
5999         u8         reserved_at_c0[0x40];
6000
6001         u8         flow_index[0x20];
6002
6003         u8         reserved_at_120[0xe0];
6004 };
6005
6006 struct mlx5_ifc_dealloc_xrcd_out_bits {
6007         u8         status[0x8];
6008         u8         reserved_at_8[0x18];
6009
6010         u8         syndrome[0x20];
6011
6012         u8         reserved_at_40[0x40];
6013 };
6014
6015 struct mlx5_ifc_dealloc_xrcd_in_bits {
6016         u8         opcode[0x10];
6017         u8         reserved_at_10[0x10];
6018
6019         u8         reserved_at_20[0x10];
6020         u8         op_mod[0x10];
6021
6022         u8         reserved_at_40[0x8];
6023         u8         xrcd[0x18];
6024
6025         u8         reserved_at_60[0x20];
6026 };
6027
6028 struct mlx5_ifc_dealloc_uar_out_bits {
6029         u8         status[0x8];
6030         u8         reserved_at_8[0x18];
6031
6032         u8         syndrome[0x20];
6033
6034         u8         reserved_at_40[0x40];
6035 };
6036
6037 struct mlx5_ifc_dealloc_uar_in_bits {
6038         u8         opcode[0x10];
6039         u8         reserved_at_10[0x10];
6040
6041         u8         reserved_at_20[0x10];
6042         u8         op_mod[0x10];
6043
6044         u8         reserved_at_40[0x8];
6045         u8         uar[0x18];
6046
6047         u8         reserved_at_60[0x20];
6048 };
6049
6050 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6051         u8         status[0x8];
6052         u8         reserved_at_8[0x18];
6053
6054         u8         syndrome[0x20];
6055
6056         u8         reserved_at_40[0x40];
6057 };
6058
6059 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6060         u8         opcode[0x10];
6061         u8         reserved_at_10[0x10];
6062
6063         u8         reserved_at_20[0x10];
6064         u8         op_mod[0x10];
6065
6066         u8         reserved_at_40[0x8];
6067         u8         transport_domain[0x18];
6068
6069         u8         reserved_at_60[0x20];
6070 };
6071
6072 struct mlx5_ifc_dealloc_q_counter_out_bits {
6073         u8         status[0x8];
6074         u8         reserved_at_8[0x18];
6075
6076         u8         syndrome[0x20];
6077
6078         u8         reserved_at_40[0x40];
6079 };
6080
6081 struct mlx5_ifc_dealloc_q_counter_in_bits {
6082         u8         opcode[0x10];
6083         u8         reserved_at_10[0x10];
6084
6085         u8         reserved_at_20[0x10];
6086         u8         op_mod[0x10];
6087
6088         u8         reserved_at_40[0x18];
6089         u8         counter_set_id[0x8];
6090
6091         u8         reserved_at_60[0x20];
6092 };
6093
6094 struct mlx5_ifc_dealloc_pd_out_bits {
6095         u8         status[0x8];
6096         u8         reserved_at_8[0x18];
6097
6098         u8         syndrome[0x20];
6099
6100         u8         reserved_at_40[0x40];
6101 };
6102
6103 struct mlx5_ifc_dealloc_pd_in_bits {
6104         u8         opcode[0x10];
6105         u8         reserved_at_10[0x10];
6106
6107         u8         reserved_at_20[0x10];
6108         u8         op_mod[0x10];
6109
6110         u8         reserved_at_40[0x8];
6111         u8         pd[0x18];
6112
6113         u8         reserved_at_60[0x20];
6114 };
6115
6116 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6117         u8         status[0x8];
6118         u8         reserved_at_8[0x18];
6119
6120         u8         syndrome[0x20];
6121
6122         u8         reserved_at_40[0x40];
6123 };
6124
6125 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6126         u8         opcode[0x10];
6127         u8         reserved_at_10[0x10];
6128
6129         u8         reserved_at_20[0x10];
6130         u8         op_mod[0x10];
6131
6132         u8         reserved_at_40[0x10];
6133         u8         flow_counter_id[0x10];
6134
6135         u8         reserved_at_60[0x20];
6136 };
6137
6138 struct mlx5_ifc_create_xrq_out_bits {
6139         u8         status[0x8];
6140         u8         reserved_at_8[0x18];
6141
6142         u8         syndrome[0x20];
6143
6144         u8         reserved_at_40[0x8];
6145         u8         xrqn[0x18];
6146
6147         u8         reserved_at_60[0x20];
6148 };
6149
6150 struct mlx5_ifc_create_xrq_in_bits {
6151         u8         opcode[0x10];
6152         u8         reserved_at_10[0x10];
6153
6154         u8         reserved_at_20[0x10];
6155         u8         op_mod[0x10];
6156
6157         u8         reserved_at_40[0x40];
6158
6159         struct mlx5_ifc_xrqc_bits xrq_context;
6160 };
6161
6162 struct mlx5_ifc_create_xrc_srq_out_bits {
6163         u8         status[0x8];
6164         u8         reserved_at_8[0x18];
6165
6166         u8         syndrome[0x20];
6167
6168         u8         reserved_at_40[0x8];
6169         u8         xrc_srqn[0x18];
6170
6171         u8         reserved_at_60[0x20];
6172 };
6173
6174 struct mlx5_ifc_create_xrc_srq_in_bits {
6175         u8         opcode[0x10];
6176         u8         reserved_at_10[0x10];
6177
6178         u8         reserved_at_20[0x10];
6179         u8         op_mod[0x10];
6180
6181         u8         reserved_at_40[0x40];
6182
6183         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6184
6185         u8         reserved_at_280[0x600];
6186
6187         u8         pas[0][0x40];
6188 };
6189
6190 struct mlx5_ifc_create_tis_out_bits {
6191         u8         status[0x8];
6192         u8         reserved_at_8[0x18];
6193
6194         u8         syndrome[0x20];
6195
6196         u8         reserved_at_40[0x8];
6197         u8         tisn[0x18];
6198
6199         u8         reserved_at_60[0x20];
6200 };
6201
6202 struct mlx5_ifc_create_tis_in_bits {
6203         u8         opcode[0x10];
6204         u8         reserved_at_10[0x10];
6205
6206         u8         reserved_at_20[0x10];
6207         u8         op_mod[0x10];
6208
6209         u8         reserved_at_40[0xc0];
6210
6211         struct mlx5_ifc_tisc_bits ctx;
6212 };
6213
6214 struct mlx5_ifc_create_tir_out_bits {
6215         u8         status[0x8];
6216         u8         reserved_at_8[0x18];
6217
6218         u8         syndrome[0x20];
6219
6220         u8         reserved_at_40[0x8];
6221         u8         tirn[0x18];
6222
6223         u8         reserved_at_60[0x20];
6224 };
6225
6226 struct mlx5_ifc_create_tir_in_bits {
6227         u8         opcode[0x10];
6228         u8         reserved_at_10[0x10];
6229
6230         u8         reserved_at_20[0x10];
6231         u8         op_mod[0x10];
6232
6233         u8         reserved_at_40[0xc0];
6234
6235         struct mlx5_ifc_tirc_bits ctx;
6236 };
6237
6238 struct mlx5_ifc_create_srq_out_bits {
6239         u8         status[0x8];
6240         u8         reserved_at_8[0x18];
6241
6242         u8         syndrome[0x20];
6243
6244         u8         reserved_at_40[0x8];
6245         u8         srqn[0x18];
6246
6247         u8         reserved_at_60[0x20];
6248 };
6249
6250 struct mlx5_ifc_create_srq_in_bits {
6251         u8         opcode[0x10];
6252         u8         reserved_at_10[0x10];
6253
6254         u8         reserved_at_20[0x10];
6255         u8         op_mod[0x10];
6256
6257         u8         reserved_at_40[0x40];
6258
6259         struct mlx5_ifc_srqc_bits srq_context_entry;
6260
6261         u8         reserved_at_280[0x600];
6262
6263         u8         pas[0][0x40];
6264 };
6265
6266 struct mlx5_ifc_create_sq_out_bits {
6267         u8         status[0x8];
6268         u8         reserved_at_8[0x18];
6269
6270         u8         syndrome[0x20];
6271
6272         u8         reserved_at_40[0x8];
6273         u8         sqn[0x18];
6274
6275         u8         reserved_at_60[0x20];
6276 };
6277
6278 struct mlx5_ifc_create_sq_in_bits {
6279         u8         opcode[0x10];
6280         u8         reserved_at_10[0x10];
6281
6282         u8         reserved_at_20[0x10];
6283         u8         op_mod[0x10];
6284
6285         u8         reserved_at_40[0xc0];
6286
6287         struct mlx5_ifc_sqc_bits ctx;
6288 };
6289
6290 struct mlx5_ifc_create_scheduling_element_out_bits {
6291         u8         status[0x8];
6292         u8         reserved_at_8[0x18];
6293
6294         u8         syndrome[0x20];
6295
6296         u8         reserved_at_40[0x40];
6297
6298         u8         scheduling_element_id[0x20];
6299
6300         u8         reserved_at_a0[0x160];
6301 };
6302
6303 struct mlx5_ifc_create_scheduling_element_in_bits {
6304         u8         opcode[0x10];
6305         u8         reserved_at_10[0x10];
6306
6307         u8         reserved_at_20[0x10];
6308         u8         op_mod[0x10];
6309
6310         u8         scheduling_hierarchy[0x8];
6311         u8         reserved_at_48[0x18];
6312
6313         u8         reserved_at_60[0xa0];
6314
6315         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6316
6317         u8         reserved_at_300[0x100];
6318 };
6319
6320 struct mlx5_ifc_create_rqt_out_bits {
6321         u8         status[0x8];
6322         u8         reserved_at_8[0x18];
6323
6324         u8         syndrome[0x20];
6325
6326         u8         reserved_at_40[0x8];
6327         u8         rqtn[0x18];
6328
6329         u8         reserved_at_60[0x20];
6330 };
6331
6332 struct mlx5_ifc_create_rqt_in_bits {
6333         u8         opcode[0x10];
6334         u8         reserved_at_10[0x10];
6335
6336         u8         reserved_at_20[0x10];
6337         u8         op_mod[0x10];
6338
6339         u8         reserved_at_40[0xc0];
6340
6341         struct mlx5_ifc_rqtc_bits rqt_context;
6342 };
6343
6344 struct mlx5_ifc_create_rq_out_bits {
6345         u8         status[0x8];
6346         u8         reserved_at_8[0x18];
6347
6348         u8         syndrome[0x20];
6349
6350         u8         reserved_at_40[0x8];
6351         u8         rqn[0x18];
6352
6353         u8         reserved_at_60[0x20];
6354 };
6355
6356 struct mlx5_ifc_create_rq_in_bits {
6357         u8         opcode[0x10];
6358         u8         reserved_at_10[0x10];
6359
6360         u8         reserved_at_20[0x10];
6361         u8         op_mod[0x10];
6362
6363         u8         reserved_at_40[0xc0];
6364
6365         struct mlx5_ifc_rqc_bits ctx;
6366 };
6367
6368 struct mlx5_ifc_create_rmp_out_bits {
6369         u8         status[0x8];
6370         u8         reserved_at_8[0x18];
6371
6372         u8         syndrome[0x20];
6373
6374         u8         reserved_at_40[0x8];
6375         u8         rmpn[0x18];
6376
6377         u8         reserved_at_60[0x20];
6378 };
6379
6380 struct mlx5_ifc_create_rmp_in_bits {
6381         u8         opcode[0x10];
6382         u8         reserved_at_10[0x10];
6383
6384         u8         reserved_at_20[0x10];
6385         u8         op_mod[0x10];
6386
6387         u8         reserved_at_40[0xc0];
6388
6389         struct mlx5_ifc_rmpc_bits ctx;
6390 };
6391
6392 struct mlx5_ifc_create_qp_out_bits {
6393         u8         status[0x8];
6394         u8         reserved_at_8[0x18];
6395
6396         u8         syndrome[0x20];
6397
6398         u8         reserved_at_40[0x8];
6399         u8         qpn[0x18];
6400
6401         u8         reserved_at_60[0x20];
6402 };
6403
6404 struct mlx5_ifc_create_qp_in_bits {
6405         u8         opcode[0x10];
6406         u8         reserved_at_10[0x10];
6407
6408         u8         reserved_at_20[0x10];
6409         u8         op_mod[0x10];
6410
6411         u8         reserved_at_40[0x40];
6412
6413         u8         opt_param_mask[0x20];
6414
6415         u8         reserved_at_a0[0x20];
6416
6417         struct mlx5_ifc_qpc_bits qpc;
6418
6419         u8         reserved_at_800[0x80];
6420
6421         u8         pas[0][0x40];
6422 };
6423
6424 struct mlx5_ifc_create_psv_out_bits {
6425         u8         status[0x8];
6426         u8         reserved_at_8[0x18];
6427
6428         u8         syndrome[0x20];
6429
6430         u8         reserved_at_40[0x40];
6431
6432         u8         reserved_at_80[0x8];
6433         u8         psv0_index[0x18];
6434
6435         u8         reserved_at_a0[0x8];
6436         u8         psv1_index[0x18];
6437
6438         u8         reserved_at_c0[0x8];
6439         u8         psv2_index[0x18];
6440
6441         u8         reserved_at_e0[0x8];
6442         u8         psv3_index[0x18];
6443 };
6444
6445 struct mlx5_ifc_create_psv_in_bits {
6446         u8         opcode[0x10];
6447         u8         reserved_at_10[0x10];
6448
6449         u8         reserved_at_20[0x10];
6450         u8         op_mod[0x10];
6451
6452         u8         num_psv[0x4];
6453         u8         reserved_at_44[0x4];
6454         u8         pd[0x18];
6455
6456         u8         reserved_at_60[0x20];
6457 };
6458
6459 struct mlx5_ifc_create_mkey_out_bits {
6460         u8         status[0x8];
6461         u8         reserved_at_8[0x18];
6462
6463         u8         syndrome[0x20];
6464
6465         u8         reserved_at_40[0x8];
6466         u8         mkey_index[0x18];
6467
6468         u8         reserved_at_60[0x20];
6469 };
6470
6471 struct mlx5_ifc_create_mkey_in_bits {
6472         u8         opcode[0x10];
6473         u8         reserved_at_10[0x10];
6474
6475         u8         reserved_at_20[0x10];
6476         u8         op_mod[0x10];
6477
6478         u8         reserved_at_40[0x20];
6479
6480         u8         pg_access[0x1];
6481         u8         reserved_at_61[0x1f];
6482
6483         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6484
6485         u8         reserved_at_280[0x80];
6486
6487         u8         translations_octword_actual_size[0x20];
6488
6489         u8         reserved_at_320[0x560];
6490
6491         u8         klm_pas_mtt[0][0x20];
6492 };
6493
6494 struct mlx5_ifc_create_flow_table_out_bits {
6495         u8         status[0x8];
6496         u8         reserved_at_8[0x18];
6497
6498         u8         syndrome[0x20];
6499
6500         u8         reserved_at_40[0x8];
6501         u8         table_id[0x18];
6502
6503         u8         reserved_at_60[0x20];
6504 };
6505
6506 struct mlx5_ifc_create_flow_table_in_bits {
6507         u8         opcode[0x10];
6508         u8         reserved_at_10[0x10];
6509
6510         u8         reserved_at_20[0x10];
6511         u8         op_mod[0x10];
6512
6513         u8         other_vport[0x1];
6514         u8         reserved_at_41[0xf];
6515         u8         vport_number[0x10];
6516
6517         u8         reserved_at_60[0x20];
6518
6519         u8         table_type[0x8];
6520         u8         reserved_at_88[0x18];
6521
6522         u8         reserved_at_a0[0x20];
6523
6524         u8         encap_en[0x1];
6525         u8         decap_en[0x1];
6526         u8         reserved_at_c2[0x2];
6527         u8         table_miss_mode[0x4];
6528         u8         level[0x8];
6529         u8         reserved_at_d0[0x8];
6530         u8         log_size[0x8];
6531
6532         u8         reserved_at_e0[0x8];
6533         u8         table_miss_id[0x18];
6534
6535         u8         reserved_at_100[0x8];
6536         u8         lag_master_next_table_id[0x18];
6537
6538         u8         reserved_at_120[0x80];
6539 };
6540
6541 struct mlx5_ifc_create_flow_group_out_bits {
6542         u8         status[0x8];
6543         u8         reserved_at_8[0x18];
6544
6545         u8         syndrome[0x20];
6546
6547         u8         reserved_at_40[0x8];
6548         u8         group_id[0x18];
6549
6550         u8         reserved_at_60[0x20];
6551 };
6552
6553 enum {
6554         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6555         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6556         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6557 };
6558
6559 struct mlx5_ifc_create_flow_group_in_bits {
6560         u8         opcode[0x10];
6561         u8         reserved_at_10[0x10];
6562
6563         u8         reserved_at_20[0x10];
6564         u8         op_mod[0x10];
6565
6566         u8         other_vport[0x1];
6567         u8         reserved_at_41[0xf];
6568         u8         vport_number[0x10];
6569
6570         u8         reserved_at_60[0x20];
6571
6572         u8         table_type[0x8];
6573         u8         reserved_at_88[0x18];
6574
6575         u8         reserved_at_a0[0x8];
6576         u8         table_id[0x18];
6577
6578         u8         reserved_at_c0[0x20];
6579
6580         u8         start_flow_index[0x20];
6581
6582         u8         reserved_at_100[0x20];
6583
6584         u8         end_flow_index[0x20];
6585
6586         u8         reserved_at_140[0xa0];
6587
6588         u8         reserved_at_1e0[0x18];
6589         u8         match_criteria_enable[0x8];
6590
6591         struct mlx5_ifc_fte_match_param_bits match_criteria;
6592
6593         u8         reserved_at_1200[0xe00];
6594 };
6595
6596 struct mlx5_ifc_create_eq_out_bits {
6597         u8         status[0x8];
6598         u8         reserved_at_8[0x18];
6599
6600         u8         syndrome[0x20];
6601
6602         u8         reserved_at_40[0x18];
6603         u8         eq_number[0x8];
6604
6605         u8         reserved_at_60[0x20];
6606 };
6607
6608 struct mlx5_ifc_create_eq_in_bits {
6609         u8         opcode[0x10];
6610         u8         reserved_at_10[0x10];
6611
6612         u8         reserved_at_20[0x10];
6613         u8         op_mod[0x10];
6614
6615         u8         reserved_at_40[0x40];
6616
6617         struct mlx5_ifc_eqc_bits eq_context_entry;
6618
6619         u8         reserved_at_280[0x40];
6620
6621         u8         event_bitmask[0x40];
6622
6623         u8         reserved_at_300[0x580];
6624
6625         u8         pas[0][0x40];
6626 };
6627
6628 struct mlx5_ifc_create_dct_out_bits {
6629         u8         status[0x8];
6630         u8         reserved_at_8[0x18];
6631
6632         u8         syndrome[0x20];
6633
6634         u8         reserved_at_40[0x8];
6635         u8         dctn[0x18];
6636
6637         u8         reserved_at_60[0x20];
6638 };
6639
6640 struct mlx5_ifc_create_dct_in_bits {
6641         u8         opcode[0x10];
6642         u8         reserved_at_10[0x10];
6643
6644         u8         reserved_at_20[0x10];
6645         u8         op_mod[0x10];
6646
6647         u8         reserved_at_40[0x40];
6648
6649         struct mlx5_ifc_dctc_bits dct_context_entry;
6650
6651         u8         reserved_at_280[0x180];
6652 };
6653
6654 struct mlx5_ifc_create_cq_out_bits {
6655         u8         status[0x8];
6656         u8         reserved_at_8[0x18];
6657
6658         u8         syndrome[0x20];
6659
6660         u8         reserved_at_40[0x8];
6661         u8         cqn[0x18];
6662
6663         u8         reserved_at_60[0x20];
6664 };
6665
6666 struct mlx5_ifc_create_cq_in_bits {
6667         u8         opcode[0x10];
6668         u8         reserved_at_10[0x10];
6669
6670         u8         reserved_at_20[0x10];
6671         u8         op_mod[0x10];
6672
6673         u8         reserved_at_40[0x40];
6674
6675         struct mlx5_ifc_cqc_bits cq_context;
6676
6677         u8         reserved_at_280[0x600];
6678
6679         u8         pas[0][0x40];
6680 };
6681
6682 struct mlx5_ifc_config_int_moderation_out_bits {
6683         u8         status[0x8];
6684         u8         reserved_at_8[0x18];
6685
6686         u8         syndrome[0x20];
6687
6688         u8         reserved_at_40[0x4];
6689         u8         min_delay[0xc];
6690         u8         int_vector[0x10];
6691
6692         u8         reserved_at_60[0x20];
6693 };
6694
6695 enum {
6696         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
6697         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
6698 };
6699
6700 struct mlx5_ifc_config_int_moderation_in_bits {
6701         u8         opcode[0x10];
6702         u8         reserved_at_10[0x10];
6703
6704         u8         reserved_at_20[0x10];
6705         u8         op_mod[0x10];
6706
6707         u8         reserved_at_40[0x4];
6708         u8         min_delay[0xc];
6709         u8         int_vector[0x10];
6710
6711         u8         reserved_at_60[0x20];
6712 };
6713
6714 struct mlx5_ifc_attach_to_mcg_out_bits {
6715         u8         status[0x8];
6716         u8         reserved_at_8[0x18];
6717
6718         u8         syndrome[0x20];
6719
6720         u8         reserved_at_40[0x40];
6721 };
6722
6723 struct mlx5_ifc_attach_to_mcg_in_bits {
6724         u8         opcode[0x10];
6725         u8         reserved_at_10[0x10];
6726
6727         u8         reserved_at_20[0x10];
6728         u8         op_mod[0x10];
6729
6730         u8         reserved_at_40[0x8];
6731         u8         qpn[0x18];
6732
6733         u8         reserved_at_60[0x20];
6734
6735         u8         multicast_gid[16][0x8];
6736 };
6737
6738 struct mlx5_ifc_arm_xrq_out_bits {
6739         u8         status[0x8];
6740         u8         reserved_at_8[0x18];
6741
6742         u8         syndrome[0x20];
6743
6744         u8         reserved_at_40[0x40];
6745 };
6746
6747 struct mlx5_ifc_arm_xrq_in_bits {
6748         u8         opcode[0x10];
6749         u8         reserved_at_10[0x10];
6750
6751         u8         reserved_at_20[0x10];
6752         u8         op_mod[0x10];
6753
6754         u8         reserved_at_40[0x8];
6755         u8         xrqn[0x18];
6756
6757         u8         reserved_at_60[0x10];
6758         u8         lwm[0x10];
6759 };
6760
6761 struct mlx5_ifc_arm_xrc_srq_out_bits {
6762         u8         status[0x8];
6763         u8         reserved_at_8[0x18];
6764
6765         u8         syndrome[0x20];
6766
6767         u8         reserved_at_40[0x40];
6768 };
6769
6770 enum {
6771         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
6772 };
6773
6774 struct mlx5_ifc_arm_xrc_srq_in_bits {
6775         u8         opcode[0x10];
6776         u8         reserved_at_10[0x10];
6777
6778         u8         reserved_at_20[0x10];
6779         u8         op_mod[0x10];
6780
6781         u8         reserved_at_40[0x8];
6782         u8         xrc_srqn[0x18];
6783
6784         u8         reserved_at_60[0x10];
6785         u8         lwm[0x10];
6786 };
6787
6788 struct mlx5_ifc_arm_rq_out_bits {
6789         u8         status[0x8];
6790         u8         reserved_at_8[0x18];
6791
6792         u8         syndrome[0x20];
6793
6794         u8         reserved_at_40[0x40];
6795 };
6796
6797 enum {
6798         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6799         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6800 };
6801
6802 struct mlx5_ifc_arm_rq_in_bits {
6803         u8         opcode[0x10];
6804         u8         reserved_at_10[0x10];
6805
6806         u8         reserved_at_20[0x10];
6807         u8         op_mod[0x10];
6808
6809         u8         reserved_at_40[0x8];
6810         u8         srq_number[0x18];
6811
6812         u8         reserved_at_60[0x10];
6813         u8         lwm[0x10];
6814 };
6815
6816 struct mlx5_ifc_arm_dct_out_bits {
6817         u8         status[0x8];
6818         u8         reserved_at_8[0x18];
6819
6820         u8         syndrome[0x20];
6821
6822         u8         reserved_at_40[0x40];
6823 };
6824
6825 struct mlx5_ifc_arm_dct_in_bits {
6826         u8         opcode[0x10];
6827         u8         reserved_at_10[0x10];
6828
6829         u8         reserved_at_20[0x10];
6830         u8         op_mod[0x10];
6831
6832         u8         reserved_at_40[0x8];
6833         u8         dct_number[0x18];
6834
6835         u8         reserved_at_60[0x20];
6836 };
6837
6838 struct mlx5_ifc_alloc_xrcd_out_bits {
6839         u8         status[0x8];
6840         u8         reserved_at_8[0x18];
6841
6842         u8         syndrome[0x20];
6843
6844         u8         reserved_at_40[0x8];
6845         u8         xrcd[0x18];
6846
6847         u8         reserved_at_60[0x20];
6848 };
6849
6850 struct mlx5_ifc_alloc_xrcd_in_bits {
6851         u8         opcode[0x10];
6852         u8         reserved_at_10[0x10];
6853
6854         u8         reserved_at_20[0x10];
6855         u8         op_mod[0x10];
6856
6857         u8         reserved_at_40[0x40];
6858 };
6859
6860 struct mlx5_ifc_alloc_uar_out_bits {
6861         u8         status[0x8];
6862         u8         reserved_at_8[0x18];
6863
6864         u8         syndrome[0x20];
6865
6866         u8         reserved_at_40[0x8];
6867         u8         uar[0x18];
6868
6869         u8         reserved_at_60[0x20];
6870 };
6871
6872 struct mlx5_ifc_alloc_uar_in_bits {
6873         u8         opcode[0x10];
6874         u8         reserved_at_10[0x10];
6875
6876         u8         reserved_at_20[0x10];
6877         u8         op_mod[0x10];
6878
6879         u8         reserved_at_40[0x40];
6880 };
6881
6882 struct mlx5_ifc_alloc_transport_domain_out_bits {
6883         u8         status[0x8];
6884         u8         reserved_at_8[0x18];
6885
6886         u8         syndrome[0x20];
6887
6888         u8         reserved_at_40[0x8];
6889         u8         transport_domain[0x18];
6890
6891         u8         reserved_at_60[0x20];
6892 };
6893
6894 struct mlx5_ifc_alloc_transport_domain_in_bits {
6895         u8         opcode[0x10];
6896         u8         reserved_at_10[0x10];
6897
6898         u8         reserved_at_20[0x10];
6899         u8         op_mod[0x10];
6900
6901         u8         reserved_at_40[0x40];
6902 };
6903
6904 struct mlx5_ifc_alloc_q_counter_out_bits {
6905         u8         status[0x8];
6906         u8         reserved_at_8[0x18];
6907
6908         u8         syndrome[0x20];
6909
6910         u8         reserved_at_40[0x18];
6911         u8         counter_set_id[0x8];
6912
6913         u8         reserved_at_60[0x20];
6914 };
6915
6916 struct mlx5_ifc_alloc_q_counter_in_bits {
6917         u8         opcode[0x10];
6918         u8         reserved_at_10[0x10];
6919
6920         u8         reserved_at_20[0x10];
6921         u8         op_mod[0x10];
6922
6923         u8         reserved_at_40[0x40];
6924 };
6925
6926 struct mlx5_ifc_alloc_pd_out_bits {
6927         u8         status[0x8];
6928         u8         reserved_at_8[0x18];
6929
6930         u8         syndrome[0x20];
6931
6932         u8         reserved_at_40[0x8];
6933         u8         pd[0x18];
6934
6935         u8         reserved_at_60[0x20];
6936 };
6937
6938 struct mlx5_ifc_alloc_pd_in_bits {
6939         u8         opcode[0x10];
6940         u8         reserved_at_10[0x10];
6941
6942         u8         reserved_at_20[0x10];
6943         u8         op_mod[0x10];
6944
6945         u8         reserved_at_40[0x40];
6946 };
6947
6948 struct mlx5_ifc_alloc_flow_counter_out_bits {
6949         u8         status[0x8];
6950         u8         reserved_at_8[0x18];
6951
6952         u8         syndrome[0x20];
6953
6954         u8         reserved_at_40[0x10];
6955         u8         flow_counter_id[0x10];
6956
6957         u8         reserved_at_60[0x20];
6958 };
6959
6960 struct mlx5_ifc_alloc_flow_counter_in_bits {
6961         u8         opcode[0x10];
6962         u8         reserved_at_10[0x10];
6963
6964         u8         reserved_at_20[0x10];
6965         u8         op_mod[0x10];
6966
6967         u8         reserved_at_40[0x40];
6968 };
6969
6970 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6971         u8         status[0x8];
6972         u8         reserved_at_8[0x18];
6973
6974         u8         syndrome[0x20];
6975
6976         u8         reserved_at_40[0x40];
6977 };
6978
6979 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6980         u8         opcode[0x10];
6981         u8         reserved_at_10[0x10];
6982
6983         u8         reserved_at_20[0x10];
6984         u8         op_mod[0x10];
6985
6986         u8         reserved_at_40[0x20];
6987
6988         u8         reserved_at_60[0x10];
6989         u8         vxlan_udp_port[0x10];
6990 };
6991
6992 struct mlx5_ifc_set_rate_limit_out_bits {
6993         u8         status[0x8];
6994         u8         reserved_at_8[0x18];
6995
6996         u8         syndrome[0x20];
6997
6998         u8         reserved_at_40[0x40];
6999 };
7000
7001 struct mlx5_ifc_set_rate_limit_in_bits {
7002         u8         opcode[0x10];
7003         u8         reserved_at_10[0x10];
7004
7005         u8         reserved_at_20[0x10];
7006         u8         op_mod[0x10];
7007
7008         u8         reserved_at_40[0x10];
7009         u8         rate_limit_index[0x10];
7010
7011         u8         reserved_at_60[0x20];
7012
7013         u8         rate_limit[0x20];
7014 };
7015
7016 struct mlx5_ifc_access_register_out_bits {
7017         u8         status[0x8];
7018         u8         reserved_at_8[0x18];
7019
7020         u8         syndrome[0x20];
7021
7022         u8         reserved_at_40[0x40];
7023
7024         u8         register_data[0][0x20];
7025 };
7026
7027 enum {
7028         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7029         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7030 };
7031
7032 struct mlx5_ifc_access_register_in_bits {
7033         u8         opcode[0x10];
7034         u8         reserved_at_10[0x10];
7035
7036         u8         reserved_at_20[0x10];
7037         u8         op_mod[0x10];
7038
7039         u8         reserved_at_40[0x10];
7040         u8         register_id[0x10];
7041
7042         u8         argument[0x20];
7043
7044         u8         register_data[0][0x20];
7045 };
7046
7047 struct mlx5_ifc_sltp_reg_bits {
7048         u8         status[0x4];
7049         u8         version[0x4];
7050         u8         local_port[0x8];
7051         u8         pnat[0x2];
7052         u8         reserved_at_12[0x2];
7053         u8         lane[0x4];
7054         u8         reserved_at_18[0x8];
7055
7056         u8         reserved_at_20[0x20];
7057
7058         u8         reserved_at_40[0x7];
7059         u8         polarity[0x1];
7060         u8         ob_tap0[0x8];
7061         u8         ob_tap1[0x8];
7062         u8         ob_tap2[0x8];
7063
7064         u8         reserved_at_60[0xc];
7065         u8         ob_preemp_mode[0x4];
7066         u8         ob_reg[0x8];
7067         u8         ob_bias[0x8];
7068
7069         u8         reserved_at_80[0x20];
7070 };
7071
7072 struct mlx5_ifc_slrg_reg_bits {
7073         u8         status[0x4];
7074         u8         version[0x4];
7075         u8         local_port[0x8];
7076         u8         pnat[0x2];
7077         u8         reserved_at_12[0x2];
7078         u8         lane[0x4];
7079         u8         reserved_at_18[0x8];
7080
7081         u8         time_to_link_up[0x10];
7082         u8         reserved_at_30[0xc];
7083         u8         grade_lane_speed[0x4];
7084
7085         u8         grade_version[0x8];
7086         u8         grade[0x18];
7087
7088         u8         reserved_at_60[0x4];
7089         u8         height_grade_type[0x4];
7090         u8         height_grade[0x18];
7091
7092         u8         height_dz[0x10];
7093         u8         height_dv[0x10];
7094
7095         u8         reserved_at_a0[0x10];
7096         u8         height_sigma[0x10];
7097
7098         u8         reserved_at_c0[0x20];
7099
7100         u8         reserved_at_e0[0x4];
7101         u8         phase_grade_type[0x4];
7102         u8         phase_grade[0x18];
7103
7104         u8         reserved_at_100[0x8];
7105         u8         phase_eo_pos[0x8];
7106         u8         reserved_at_110[0x8];
7107         u8         phase_eo_neg[0x8];
7108
7109         u8         ffe_set_tested[0x10];
7110         u8         test_errors_per_lane[0x10];
7111 };
7112
7113 struct mlx5_ifc_pvlc_reg_bits {
7114         u8         reserved_at_0[0x8];
7115         u8         local_port[0x8];
7116         u8         reserved_at_10[0x10];
7117
7118         u8         reserved_at_20[0x1c];
7119         u8         vl_hw_cap[0x4];
7120
7121         u8         reserved_at_40[0x1c];
7122         u8         vl_admin[0x4];
7123
7124         u8         reserved_at_60[0x1c];
7125         u8         vl_operational[0x4];
7126 };
7127
7128 struct mlx5_ifc_pude_reg_bits {
7129         u8         swid[0x8];
7130         u8         local_port[0x8];
7131         u8         reserved_at_10[0x4];
7132         u8         admin_status[0x4];
7133         u8         reserved_at_18[0x4];
7134         u8         oper_status[0x4];
7135
7136         u8         reserved_at_20[0x60];
7137 };
7138
7139 struct mlx5_ifc_ptys_reg_bits {
7140         u8         reserved_at_0[0x1];
7141         u8         an_disable_admin[0x1];
7142         u8         an_disable_cap[0x1];
7143         u8         reserved_at_3[0x5];
7144         u8         local_port[0x8];
7145         u8         reserved_at_10[0xd];
7146         u8         proto_mask[0x3];
7147
7148         u8         an_status[0x4];
7149         u8         reserved_at_24[0x3c];
7150
7151         u8         eth_proto_capability[0x20];
7152
7153         u8         ib_link_width_capability[0x10];
7154         u8         ib_proto_capability[0x10];
7155
7156         u8         reserved_at_a0[0x20];
7157
7158         u8         eth_proto_admin[0x20];
7159
7160         u8         ib_link_width_admin[0x10];
7161         u8         ib_proto_admin[0x10];
7162
7163         u8         reserved_at_100[0x20];
7164
7165         u8         eth_proto_oper[0x20];
7166
7167         u8         ib_link_width_oper[0x10];
7168         u8         ib_proto_oper[0x10];
7169
7170         u8         reserved_at_160[0x20];
7171
7172         u8         eth_proto_lp_advertise[0x20];
7173
7174         u8         reserved_at_1a0[0x60];
7175 };
7176
7177 struct mlx5_ifc_mlcr_reg_bits {
7178         u8         reserved_at_0[0x8];
7179         u8         local_port[0x8];
7180         u8         reserved_at_10[0x20];
7181
7182         u8         beacon_duration[0x10];
7183         u8         reserved_at_40[0x10];
7184
7185         u8         beacon_remain[0x10];
7186 };
7187
7188 struct mlx5_ifc_ptas_reg_bits {
7189         u8         reserved_at_0[0x20];
7190
7191         u8         algorithm_options[0x10];
7192         u8         reserved_at_30[0x4];
7193         u8         repetitions_mode[0x4];
7194         u8         num_of_repetitions[0x8];
7195
7196         u8         grade_version[0x8];
7197         u8         height_grade_type[0x4];
7198         u8         phase_grade_type[0x4];
7199         u8         height_grade_weight[0x8];
7200         u8         phase_grade_weight[0x8];
7201
7202         u8         gisim_measure_bits[0x10];
7203         u8         adaptive_tap_measure_bits[0x10];
7204
7205         u8         ber_bath_high_error_threshold[0x10];
7206         u8         ber_bath_mid_error_threshold[0x10];
7207
7208         u8         ber_bath_low_error_threshold[0x10];
7209         u8         one_ratio_high_threshold[0x10];
7210
7211         u8         one_ratio_high_mid_threshold[0x10];
7212         u8         one_ratio_low_mid_threshold[0x10];
7213
7214         u8         one_ratio_low_threshold[0x10];
7215         u8         ndeo_error_threshold[0x10];
7216
7217         u8         mixer_offset_step_size[0x10];
7218         u8         reserved_at_110[0x8];
7219         u8         mix90_phase_for_voltage_bath[0x8];
7220
7221         u8         mixer_offset_start[0x10];
7222         u8         mixer_offset_end[0x10];
7223
7224         u8         reserved_at_140[0x15];
7225         u8         ber_test_time[0xb];
7226 };
7227
7228 struct mlx5_ifc_pspa_reg_bits {
7229         u8         swid[0x8];
7230         u8         local_port[0x8];
7231         u8         sub_port[0x8];
7232         u8         reserved_at_18[0x8];
7233
7234         u8         reserved_at_20[0x20];
7235 };
7236
7237 struct mlx5_ifc_pqdr_reg_bits {
7238         u8         reserved_at_0[0x8];
7239         u8         local_port[0x8];
7240         u8         reserved_at_10[0x5];
7241         u8         prio[0x3];
7242         u8         reserved_at_18[0x6];
7243         u8         mode[0x2];
7244
7245         u8         reserved_at_20[0x20];
7246
7247         u8         reserved_at_40[0x10];
7248         u8         min_threshold[0x10];
7249
7250         u8         reserved_at_60[0x10];
7251         u8         max_threshold[0x10];
7252
7253         u8         reserved_at_80[0x10];
7254         u8         mark_probability_denominator[0x10];
7255
7256         u8         reserved_at_a0[0x60];
7257 };
7258
7259 struct mlx5_ifc_ppsc_reg_bits {
7260         u8         reserved_at_0[0x8];
7261         u8         local_port[0x8];
7262         u8         reserved_at_10[0x10];
7263
7264         u8         reserved_at_20[0x60];
7265
7266         u8         reserved_at_80[0x1c];
7267         u8         wrps_admin[0x4];
7268
7269         u8         reserved_at_a0[0x1c];
7270         u8         wrps_status[0x4];
7271
7272         u8         reserved_at_c0[0x8];
7273         u8         up_threshold[0x8];
7274         u8         reserved_at_d0[0x8];
7275         u8         down_threshold[0x8];
7276
7277         u8         reserved_at_e0[0x20];
7278
7279         u8         reserved_at_100[0x1c];
7280         u8         srps_admin[0x4];
7281
7282         u8         reserved_at_120[0x1c];
7283         u8         srps_status[0x4];
7284
7285         u8         reserved_at_140[0x40];
7286 };
7287
7288 struct mlx5_ifc_pplr_reg_bits {
7289         u8         reserved_at_0[0x8];
7290         u8         local_port[0x8];
7291         u8         reserved_at_10[0x10];
7292
7293         u8         reserved_at_20[0x8];
7294         u8         lb_cap[0x8];
7295         u8         reserved_at_30[0x8];
7296         u8         lb_en[0x8];
7297 };
7298
7299 struct mlx5_ifc_pplm_reg_bits {
7300         u8         reserved_at_0[0x8];
7301         u8         local_port[0x8];
7302         u8         reserved_at_10[0x10];
7303
7304         u8         reserved_at_20[0x20];
7305
7306         u8         port_profile_mode[0x8];
7307         u8         static_port_profile[0x8];
7308         u8         active_port_profile[0x8];
7309         u8         reserved_at_58[0x8];
7310
7311         u8         retransmission_active[0x8];
7312         u8         fec_mode_active[0x18];
7313
7314         u8         reserved_at_80[0x20];
7315 };
7316
7317 struct mlx5_ifc_ppcnt_reg_bits {
7318         u8         swid[0x8];
7319         u8         local_port[0x8];
7320         u8         pnat[0x2];
7321         u8         reserved_at_12[0x8];
7322         u8         grp[0x6];
7323
7324         u8         clr[0x1];
7325         u8         reserved_at_21[0x1c];
7326         u8         prio_tc[0x3];
7327
7328         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7329 };
7330
7331 struct mlx5_ifc_mpcnt_reg_bits {
7332         u8         reserved_at_0[0x8];
7333         u8         pcie_index[0x8];
7334         u8         reserved_at_10[0xa];
7335         u8         grp[0x6];
7336
7337         u8         clr[0x1];
7338         u8         reserved_at_21[0x1f];
7339
7340         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7341 };
7342
7343 struct mlx5_ifc_ppad_reg_bits {
7344         u8         reserved_at_0[0x3];
7345         u8         single_mac[0x1];
7346         u8         reserved_at_4[0x4];
7347         u8         local_port[0x8];
7348         u8         mac_47_32[0x10];
7349
7350         u8         mac_31_0[0x20];
7351
7352         u8         reserved_at_40[0x40];
7353 };
7354
7355 struct mlx5_ifc_pmtu_reg_bits {
7356         u8         reserved_at_0[0x8];
7357         u8         local_port[0x8];
7358         u8         reserved_at_10[0x10];
7359
7360         u8         max_mtu[0x10];
7361         u8         reserved_at_30[0x10];
7362
7363         u8         admin_mtu[0x10];
7364         u8         reserved_at_50[0x10];
7365
7366         u8         oper_mtu[0x10];
7367         u8         reserved_at_70[0x10];
7368 };
7369
7370 struct mlx5_ifc_pmpr_reg_bits {
7371         u8         reserved_at_0[0x8];
7372         u8         module[0x8];
7373         u8         reserved_at_10[0x10];
7374
7375         u8         reserved_at_20[0x18];
7376         u8         attenuation_5g[0x8];
7377
7378         u8         reserved_at_40[0x18];
7379         u8         attenuation_7g[0x8];
7380
7381         u8         reserved_at_60[0x18];
7382         u8         attenuation_12g[0x8];
7383 };
7384
7385 struct mlx5_ifc_pmpe_reg_bits {
7386         u8         reserved_at_0[0x8];
7387         u8         module[0x8];
7388         u8         reserved_at_10[0xc];
7389         u8         module_status[0x4];
7390
7391         u8         reserved_at_20[0x60];
7392 };
7393
7394 struct mlx5_ifc_pmpc_reg_bits {
7395         u8         module_state_updated[32][0x8];
7396 };
7397
7398 struct mlx5_ifc_pmlpn_reg_bits {
7399         u8         reserved_at_0[0x4];
7400         u8         mlpn_status[0x4];
7401         u8         local_port[0x8];
7402         u8         reserved_at_10[0x10];
7403
7404         u8         e[0x1];
7405         u8         reserved_at_21[0x1f];
7406 };
7407
7408 struct mlx5_ifc_pmlp_reg_bits {
7409         u8         rxtx[0x1];
7410         u8         reserved_at_1[0x7];
7411         u8         local_port[0x8];
7412         u8         reserved_at_10[0x8];
7413         u8         width[0x8];
7414
7415         u8         lane0_module_mapping[0x20];
7416
7417         u8         lane1_module_mapping[0x20];
7418
7419         u8         lane2_module_mapping[0x20];
7420
7421         u8         lane3_module_mapping[0x20];
7422
7423         u8         reserved_at_a0[0x160];
7424 };
7425
7426 struct mlx5_ifc_pmaos_reg_bits {
7427         u8         reserved_at_0[0x8];
7428         u8         module[0x8];
7429         u8         reserved_at_10[0x4];
7430         u8         admin_status[0x4];
7431         u8         reserved_at_18[0x4];
7432         u8         oper_status[0x4];
7433
7434         u8         ase[0x1];
7435         u8         ee[0x1];
7436         u8         reserved_at_22[0x1c];
7437         u8         e[0x2];
7438
7439         u8         reserved_at_40[0x40];
7440 };
7441
7442 struct mlx5_ifc_plpc_reg_bits {
7443         u8         reserved_at_0[0x4];
7444         u8         profile_id[0xc];
7445         u8         reserved_at_10[0x4];
7446         u8         proto_mask[0x4];
7447         u8         reserved_at_18[0x8];
7448
7449         u8         reserved_at_20[0x10];
7450         u8         lane_speed[0x10];
7451
7452         u8         reserved_at_40[0x17];
7453         u8         lpbf[0x1];
7454         u8         fec_mode_policy[0x8];
7455
7456         u8         retransmission_capability[0x8];
7457         u8         fec_mode_capability[0x18];
7458
7459         u8         retransmission_support_admin[0x8];
7460         u8         fec_mode_support_admin[0x18];
7461
7462         u8         retransmission_request_admin[0x8];
7463         u8         fec_mode_request_admin[0x18];
7464
7465         u8         reserved_at_c0[0x80];
7466 };
7467
7468 struct mlx5_ifc_plib_reg_bits {
7469         u8         reserved_at_0[0x8];
7470         u8         local_port[0x8];
7471         u8         reserved_at_10[0x8];
7472         u8         ib_port[0x8];
7473
7474         u8         reserved_at_20[0x60];
7475 };
7476
7477 struct mlx5_ifc_plbf_reg_bits {
7478         u8         reserved_at_0[0x8];
7479         u8         local_port[0x8];
7480         u8         reserved_at_10[0xd];
7481         u8         lbf_mode[0x3];
7482
7483         u8         reserved_at_20[0x20];
7484 };
7485
7486 struct mlx5_ifc_pipg_reg_bits {
7487         u8         reserved_at_0[0x8];
7488         u8         local_port[0x8];
7489         u8         reserved_at_10[0x10];
7490
7491         u8         dic[0x1];
7492         u8         reserved_at_21[0x19];
7493         u8         ipg[0x4];
7494         u8         reserved_at_3e[0x2];
7495 };
7496
7497 struct mlx5_ifc_pifr_reg_bits {
7498         u8         reserved_at_0[0x8];
7499         u8         local_port[0x8];
7500         u8         reserved_at_10[0x10];
7501
7502         u8         reserved_at_20[0xe0];
7503
7504         u8         port_filter[8][0x20];
7505
7506         u8         port_filter_update_en[8][0x20];
7507 };
7508
7509 struct mlx5_ifc_pfcc_reg_bits {
7510         u8         reserved_at_0[0x8];
7511         u8         local_port[0x8];
7512         u8         reserved_at_10[0x10];
7513
7514         u8         ppan[0x4];
7515         u8         reserved_at_24[0x4];
7516         u8         prio_mask_tx[0x8];
7517         u8         reserved_at_30[0x8];
7518         u8         prio_mask_rx[0x8];
7519
7520         u8         pptx[0x1];
7521         u8         aptx[0x1];
7522         u8         reserved_at_42[0x6];
7523         u8         pfctx[0x8];
7524         u8         reserved_at_50[0x10];
7525
7526         u8         pprx[0x1];
7527         u8         aprx[0x1];
7528         u8         reserved_at_62[0x6];
7529         u8         pfcrx[0x8];
7530         u8         reserved_at_70[0x10];
7531
7532         u8         reserved_at_80[0x80];
7533 };
7534
7535 struct mlx5_ifc_pelc_reg_bits {
7536         u8         op[0x4];
7537         u8         reserved_at_4[0x4];
7538         u8         local_port[0x8];
7539         u8         reserved_at_10[0x10];
7540
7541         u8         op_admin[0x8];
7542         u8         op_capability[0x8];
7543         u8         op_request[0x8];
7544         u8         op_active[0x8];
7545
7546         u8         admin[0x40];
7547
7548         u8         capability[0x40];
7549
7550         u8         request[0x40];
7551
7552         u8         active[0x40];
7553
7554         u8         reserved_at_140[0x80];
7555 };
7556
7557 struct mlx5_ifc_peir_reg_bits {
7558         u8         reserved_at_0[0x8];
7559         u8         local_port[0x8];
7560         u8         reserved_at_10[0x10];
7561
7562         u8         reserved_at_20[0xc];
7563         u8         error_count[0x4];
7564         u8         reserved_at_30[0x10];
7565
7566         u8         reserved_at_40[0xc];
7567         u8         lane[0x4];
7568         u8         reserved_at_50[0x8];
7569         u8         error_type[0x8];
7570 };
7571
7572 struct mlx5_ifc_pcap_reg_bits {
7573         u8         reserved_at_0[0x8];
7574         u8         local_port[0x8];
7575         u8         reserved_at_10[0x10];
7576
7577         u8         port_capability_mask[4][0x20];
7578 };
7579
7580 struct mlx5_ifc_paos_reg_bits {
7581         u8         swid[0x8];
7582         u8         local_port[0x8];
7583         u8         reserved_at_10[0x4];
7584         u8         admin_status[0x4];
7585         u8         reserved_at_18[0x4];
7586         u8         oper_status[0x4];
7587
7588         u8         ase[0x1];
7589         u8         ee[0x1];
7590         u8         reserved_at_22[0x1c];
7591         u8         e[0x2];
7592
7593         u8         reserved_at_40[0x40];
7594 };
7595
7596 struct mlx5_ifc_pamp_reg_bits {
7597         u8         reserved_at_0[0x8];
7598         u8         opamp_group[0x8];
7599         u8         reserved_at_10[0xc];
7600         u8         opamp_group_type[0x4];
7601
7602         u8         start_index[0x10];
7603         u8         reserved_at_30[0x4];
7604         u8         num_of_indices[0xc];
7605
7606         u8         index_data[18][0x10];
7607 };
7608
7609 struct mlx5_ifc_pcmr_reg_bits {
7610         u8         reserved_at_0[0x8];
7611         u8         local_port[0x8];
7612         u8         reserved_at_10[0x2e];
7613         u8         fcs_cap[0x1];
7614         u8         reserved_at_3f[0x1f];
7615         u8         fcs_chk[0x1];
7616         u8         reserved_at_5f[0x1];
7617 };
7618
7619 struct mlx5_ifc_lane_2_module_mapping_bits {
7620         u8         reserved_at_0[0x6];
7621         u8         rx_lane[0x2];
7622         u8         reserved_at_8[0x6];
7623         u8         tx_lane[0x2];
7624         u8         reserved_at_10[0x8];
7625         u8         module[0x8];
7626 };
7627
7628 struct mlx5_ifc_bufferx_reg_bits {
7629         u8         reserved_at_0[0x6];
7630         u8         lossy[0x1];
7631         u8         epsb[0x1];
7632         u8         reserved_at_8[0xc];
7633         u8         size[0xc];
7634
7635         u8         xoff_threshold[0x10];
7636         u8         xon_threshold[0x10];
7637 };
7638
7639 struct mlx5_ifc_set_node_in_bits {
7640         u8         node_description[64][0x8];
7641 };
7642
7643 struct mlx5_ifc_register_power_settings_bits {
7644         u8         reserved_at_0[0x18];
7645         u8         power_settings_level[0x8];
7646
7647         u8         reserved_at_20[0x60];
7648 };
7649
7650 struct mlx5_ifc_register_host_endianness_bits {
7651         u8         he[0x1];
7652         u8         reserved_at_1[0x1f];
7653
7654         u8         reserved_at_20[0x60];
7655 };
7656
7657 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7658         u8         reserved_at_0[0x20];
7659
7660         u8         mkey[0x20];
7661
7662         u8         addressh_63_32[0x20];
7663
7664         u8         addressl_31_0[0x20];
7665 };
7666
7667 struct mlx5_ifc_ud_adrs_vector_bits {
7668         u8         dc_key[0x40];
7669
7670         u8         ext[0x1];
7671         u8         reserved_at_41[0x7];
7672         u8         destination_qp_dct[0x18];
7673
7674         u8         static_rate[0x4];
7675         u8         sl_eth_prio[0x4];
7676         u8         fl[0x1];
7677         u8         mlid[0x7];
7678         u8         rlid_udp_sport[0x10];
7679
7680         u8         reserved_at_80[0x20];
7681
7682         u8         rmac_47_16[0x20];
7683
7684         u8         rmac_15_0[0x10];
7685         u8         tclass[0x8];
7686         u8         hop_limit[0x8];
7687
7688         u8         reserved_at_e0[0x1];
7689         u8         grh[0x1];
7690         u8         reserved_at_e2[0x2];
7691         u8         src_addr_index[0x8];
7692         u8         flow_label[0x14];
7693
7694         u8         rgid_rip[16][0x8];
7695 };
7696
7697 struct mlx5_ifc_pages_req_event_bits {
7698         u8         reserved_at_0[0x10];
7699         u8         function_id[0x10];
7700
7701         u8         num_pages[0x20];
7702
7703         u8         reserved_at_40[0xa0];
7704 };
7705
7706 struct mlx5_ifc_eqe_bits {
7707         u8         reserved_at_0[0x8];
7708         u8         event_type[0x8];
7709         u8         reserved_at_10[0x8];
7710         u8         event_sub_type[0x8];
7711
7712         u8         reserved_at_20[0xe0];
7713
7714         union mlx5_ifc_event_auto_bits event_data;
7715
7716         u8         reserved_at_1e0[0x10];
7717         u8         signature[0x8];
7718         u8         reserved_at_1f8[0x7];
7719         u8         owner[0x1];
7720 };
7721
7722 enum {
7723         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
7724 };
7725
7726 struct mlx5_ifc_cmd_queue_entry_bits {
7727         u8         type[0x8];
7728         u8         reserved_at_8[0x18];
7729
7730         u8         input_length[0x20];
7731
7732         u8         input_mailbox_pointer_63_32[0x20];
7733
7734         u8         input_mailbox_pointer_31_9[0x17];
7735         u8         reserved_at_77[0x9];
7736
7737         u8         command_input_inline_data[16][0x8];
7738
7739         u8         command_output_inline_data[16][0x8];
7740
7741         u8         output_mailbox_pointer_63_32[0x20];
7742
7743         u8         output_mailbox_pointer_31_9[0x17];
7744         u8         reserved_at_1b7[0x9];
7745
7746         u8         output_length[0x20];
7747
7748         u8         token[0x8];
7749         u8         signature[0x8];
7750         u8         reserved_at_1f0[0x8];
7751         u8         status[0x7];
7752         u8         ownership[0x1];
7753 };
7754
7755 struct mlx5_ifc_cmd_out_bits {
7756         u8         status[0x8];
7757         u8         reserved_at_8[0x18];
7758
7759         u8         syndrome[0x20];
7760
7761         u8         command_output[0x20];
7762 };
7763
7764 struct mlx5_ifc_cmd_in_bits {
7765         u8         opcode[0x10];
7766         u8         reserved_at_10[0x10];
7767
7768         u8         reserved_at_20[0x10];
7769         u8         op_mod[0x10];
7770
7771         u8         command[0][0x20];
7772 };
7773
7774 struct mlx5_ifc_cmd_if_box_bits {
7775         u8         mailbox_data[512][0x8];
7776
7777         u8         reserved_at_1000[0x180];
7778
7779         u8         next_pointer_63_32[0x20];
7780
7781         u8         next_pointer_31_10[0x16];
7782         u8         reserved_at_11b6[0xa];
7783
7784         u8         block_number[0x20];
7785
7786         u8         reserved_at_11e0[0x8];
7787         u8         token[0x8];
7788         u8         ctrl_signature[0x8];
7789         u8         signature[0x8];
7790 };
7791
7792 struct mlx5_ifc_mtt_bits {
7793         u8         ptag_63_32[0x20];
7794
7795         u8         ptag_31_8[0x18];
7796         u8         reserved_at_38[0x6];
7797         u8         wr_en[0x1];
7798         u8         rd_en[0x1];
7799 };
7800
7801 struct mlx5_ifc_query_wol_rol_out_bits {
7802         u8         status[0x8];
7803         u8         reserved_at_8[0x18];
7804
7805         u8         syndrome[0x20];
7806
7807         u8         reserved_at_40[0x10];
7808         u8         rol_mode[0x8];
7809         u8         wol_mode[0x8];
7810
7811         u8         reserved_at_60[0x20];
7812 };
7813
7814 struct mlx5_ifc_query_wol_rol_in_bits {
7815         u8         opcode[0x10];
7816         u8         reserved_at_10[0x10];
7817
7818         u8         reserved_at_20[0x10];
7819         u8         op_mod[0x10];
7820
7821         u8         reserved_at_40[0x40];
7822 };
7823
7824 struct mlx5_ifc_set_wol_rol_out_bits {
7825         u8         status[0x8];
7826         u8         reserved_at_8[0x18];
7827
7828         u8         syndrome[0x20];
7829
7830         u8         reserved_at_40[0x40];
7831 };
7832
7833 struct mlx5_ifc_set_wol_rol_in_bits {
7834         u8         opcode[0x10];
7835         u8         reserved_at_10[0x10];
7836
7837         u8         reserved_at_20[0x10];
7838         u8         op_mod[0x10];
7839
7840         u8         rol_mode_valid[0x1];
7841         u8         wol_mode_valid[0x1];
7842         u8         reserved_at_42[0xe];
7843         u8         rol_mode[0x8];
7844         u8         wol_mode[0x8];
7845
7846         u8         reserved_at_60[0x20];
7847 };
7848
7849 enum {
7850         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
7851         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
7852         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
7853 };
7854
7855 enum {
7856         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
7857         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
7858         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
7859 };
7860
7861 enum {
7862         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
7863         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
7864         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
7865         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
7866         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
7867         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
7868         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
7869         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
7870         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
7871         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
7872         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
7873 };
7874
7875 struct mlx5_ifc_initial_seg_bits {
7876         u8         fw_rev_minor[0x10];
7877         u8         fw_rev_major[0x10];
7878
7879         u8         cmd_interface_rev[0x10];
7880         u8         fw_rev_subminor[0x10];
7881
7882         u8         reserved_at_40[0x40];
7883
7884         u8         cmdq_phy_addr_63_32[0x20];
7885
7886         u8         cmdq_phy_addr_31_12[0x14];
7887         u8         reserved_at_b4[0x2];
7888         u8         nic_interface[0x2];
7889         u8         log_cmdq_size[0x4];
7890         u8         log_cmdq_stride[0x4];
7891
7892         u8         command_doorbell_vector[0x20];
7893
7894         u8         reserved_at_e0[0xf00];
7895
7896         u8         initializing[0x1];
7897         u8         reserved_at_fe1[0x4];
7898         u8         nic_interface_supported[0x3];
7899         u8         reserved_at_fe8[0x18];
7900
7901         struct mlx5_ifc_health_buffer_bits health_buffer;
7902
7903         u8         no_dram_nic_offset[0x20];
7904
7905         u8         reserved_at_1220[0x6e40];
7906
7907         u8         reserved_at_8060[0x1f];
7908         u8         clear_int[0x1];
7909
7910         u8         health_syndrome[0x8];
7911         u8         health_counter[0x18];
7912
7913         u8         reserved_at_80a0[0x17fc0];
7914 };
7915
7916 union mlx5_ifc_ports_control_registers_document_bits {
7917         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7918         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7919         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7920         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7921         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7922         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7923         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7924         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7925         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7926         struct mlx5_ifc_pamp_reg_bits pamp_reg;
7927         struct mlx5_ifc_paos_reg_bits paos_reg;
7928         struct mlx5_ifc_pcap_reg_bits pcap_reg;
7929         struct mlx5_ifc_peir_reg_bits peir_reg;
7930         struct mlx5_ifc_pelc_reg_bits pelc_reg;
7931         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
7932         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
7933         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7934         struct mlx5_ifc_pifr_reg_bits pifr_reg;
7935         struct mlx5_ifc_pipg_reg_bits pipg_reg;
7936         struct mlx5_ifc_plbf_reg_bits plbf_reg;
7937         struct mlx5_ifc_plib_reg_bits plib_reg;
7938         struct mlx5_ifc_plpc_reg_bits plpc_reg;
7939         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7940         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7941         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7942         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7943         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7944         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7945         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7946         struct mlx5_ifc_ppad_reg_bits ppad_reg;
7947         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7948         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
7949         struct mlx5_ifc_pplm_reg_bits pplm_reg;
7950         struct mlx5_ifc_pplr_reg_bits pplr_reg;
7951         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7952         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7953         struct mlx5_ifc_pspa_reg_bits pspa_reg;
7954         struct mlx5_ifc_ptas_reg_bits ptas_reg;
7955         struct mlx5_ifc_ptys_reg_bits ptys_reg;
7956         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
7957         struct mlx5_ifc_pude_reg_bits pude_reg;
7958         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7959         struct mlx5_ifc_slrg_reg_bits slrg_reg;
7960         struct mlx5_ifc_sltp_reg_bits sltp_reg;
7961         u8         reserved_at_0[0x60e0];
7962 };
7963
7964 union mlx5_ifc_debug_enhancements_document_bits {
7965         struct mlx5_ifc_health_buffer_bits health_buffer;
7966         u8         reserved_at_0[0x200];
7967 };
7968
7969 union mlx5_ifc_uplink_pci_interface_document_bits {
7970         struct mlx5_ifc_initial_seg_bits initial_seg;
7971         u8         reserved_at_0[0x20060];
7972 };
7973
7974 struct mlx5_ifc_set_flow_table_root_out_bits {
7975         u8         status[0x8];
7976         u8         reserved_at_8[0x18];
7977
7978         u8         syndrome[0x20];
7979
7980         u8         reserved_at_40[0x40];
7981 };
7982
7983 struct mlx5_ifc_set_flow_table_root_in_bits {
7984         u8         opcode[0x10];
7985         u8         reserved_at_10[0x10];
7986
7987         u8         reserved_at_20[0x10];
7988         u8         op_mod[0x10];
7989
7990         u8         other_vport[0x1];
7991         u8         reserved_at_41[0xf];
7992         u8         vport_number[0x10];
7993
7994         u8         reserved_at_60[0x20];
7995
7996         u8         table_type[0x8];
7997         u8         reserved_at_88[0x18];
7998
7999         u8         reserved_at_a0[0x8];
8000         u8         table_id[0x18];
8001
8002         u8         reserved_at_c0[0x140];
8003 };
8004
8005 enum {
8006         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
8007         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8008 };
8009
8010 struct mlx5_ifc_modify_flow_table_out_bits {
8011         u8         status[0x8];
8012         u8         reserved_at_8[0x18];
8013
8014         u8         syndrome[0x20];
8015
8016         u8         reserved_at_40[0x40];
8017 };
8018
8019 struct mlx5_ifc_modify_flow_table_in_bits {
8020         u8         opcode[0x10];
8021         u8         reserved_at_10[0x10];
8022
8023         u8         reserved_at_20[0x10];
8024         u8         op_mod[0x10];
8025
8026         u8         other_vport[0x1];
8027         u8         reserved_at_41[0xf];
8028         u8         vport_number[0x10];
8029
8030         u8         reserved_at_60[0x10];
8031         u8         modify_field_select[0x10];
8032
8033         u8         table_type[0x8];
8034         u8         reserved_at_88[0x18];
8035
8036         u8         reserved_at_a0[0x8];
8037         u8         table_id[0x18];
8038
8039         u8         reserved_at_c0[0x4];
8040         u8         table_miss_mode[0x4];
8041         u8         reserved_at_c8[0x18];
8042
8043         u8         reserved_at_e0[0x8];
8044         u8         table_miss_id[0x18];
8045
8046         u8         reserved_at_100[0x8];
8047         u8         lag_master_next_table_id[0x18];
8048
8049         u8         reserved_at_120[0x80];
8050 };
8051
8052 struct mlx5_ifc_ets_tcn_config_reg_bits {
8053         u8         g[0x1];
8054         u8         b[0x1];
8055         u8         r[0x1];
8056         u8         reserved_at_3[0x9];
8057         u8         group[0x4];
8058         u8         reserved_at_10[0x9];
8059         u8         bw_allocation[0x7];
8060
8061         u8         reserved_at_20[0xc];
8062         u8         max_bw_units[0x4];
8063         u8         reserved_at_30[0x8];
8064         u8         max_bw_value[0x8];
8065 };
8066
8067 struct mlx5_ifc_ets_global_config_reg_bits {
8068         u8         reserved_at_0[0x2];
8069         u8         r[0x1];
8070         u8         reserved_at_3[0x1d];
8071
8072         u8         reserved_at_20[0xc];
8073         u8         max_bw_units[0x4];
8074         u8         reserved_at_30[0x8];
8075         u8         max_bw_value[0x8];
8076 };
8077
8078 struct mlx5_ifc_qetc_reg_bits {
8079         u8                                         reserved_at_0[0x8];
8080         u8                                         port_number[0x8];
8081         u8                                         reserved_at_10[0x30];
8082
8083         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
8084         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8085 };
8086
8087 struct mlx5_ifc_qtct_reg_bits {
8088         u8         reserved_at_0[0x8];
8089         u8         port_number[0x8];
8090         u8         reserved_at_10[0xd];
8091         u8         prio[0x3];
8092
8093         u8         reserved_at_20[0x1d];
8094         u8         tclass[0x3];
8095 };
8096
8097 struct mlx5_ifc_mcia_reg_bits {
8098         u8         l[0x1];
8099         u8         reserved_at_1[0x7];
8100         u8         module[0x8];
8101         u8         reserved_at_10[0x8];
8102         u8         status[0x8];
8103
8104         u8         i2c_device_address[0x8];
8105         u8         page_number[0x8];
8106         u8         device_address[0x10];
8107
8108         u8         reserved_at_40[0x10];
8109         u8         size[0x10];
8110
8111         u8         reserved_at_60[0x20];
8112
8113         u8         dword_0[0x20];
8114         u8         dword_1[0x20];
8115         u8         dword_2[0x20];
8116         u8         dword_3[0x20];
8117         u8         dword_4[0x20];
8118         u8         dword_5[0x20];
8119         u8         dword_6[0x20];
8120         u8         dword_7[0x20];
8121         u8         dword_8[0x20];
8122         u8         dword_9[0x20];
8123         u8         dword_10[0x20];
8124         u8         dword_11[0x20];
8125 };
8126
8127 struct mlx5_ifc_dcbx_param_bits {
8128         u8         dcbx_cee_cap[0x1];
8129         u8         dcbx_ieee_cap[0x1];
8130         u8         dcbx_standby_cap[0x1];
8131         u8         reserved_at_0[0x5];
8132         u8         port_number[0x8];
8133         u8         reserved_at_10[0xa];
8134         u8         max_application_table_size[6];
8135         u8         reserved_at_20[0x15];
8136         u8         version_oper[0x3];
8137         u8         reserved_at_38[5];
8138         u8         version_admin[0x3];
8139         u8         willing_admin[0x1];
8140         u8         reserved_at_41[0x3];
8141         u8         pfc_cap_oper[0x4];
8142         u8         reserved_at_48[0x4];
8143         u8         pfc_cap_admin[0x4];
8144         u8         reserved_at_50[0x4];
8145         u8         num_of_tc_oper[0x4];
8146         u8         reserved_at_58[0x4];
8147         u8         num_of_tc_admin[0x4];
8148         u8         remote_willing[0x1];
8149         u8         reserved_at_61[3];
8150         u8         remote_pfc_cap[4];
8151         u8         reserved_at_68[0x14];
8152         u8         remote_num_of_tc[0x4];
8153         u8         reserved_at_80[0x18];
8154         u8         error[0x8];
8155         u8         reserved_at_a0[0x160];
8156 };
8157
8158 struct mlx5_ifc_lagc_bits {
8159         u8         reserved_at_0[0x1d];
8160         u8         lag_state[0x3];
8161
8162         u8         reserved_at_20[0x14];
8163         u8         tx_remap_affinity_2[0x4];
8164         u8         reserved_at_38[0x4];
8165         u8         tx_remap_affinity_1[0x4];
8166 };
8167
8168 struct mlx5_ifc_create_lag_out_bits {
8169         u8         status[0x8];
8170         u8         reserved_at_8[0x18];
8171
8172         u8         syndrome[0x20];
8173
8174         u8         reserved_at_40[0x40];
8175 };
8176
8177 struct mlx5_ifc_create_lag_in_bits {
8178         u8         opcode[0x10];
8179         u8         reserved_at_10[0x10];
8180
8181         u8         reserved_at_20[0x10];
8182         u8         op_mod[0x10];
8183
8184         struct mlx5_ifc_lagc_bits ctx;
8185 };
8186
8187 struct mlx5_ifc_modify_lag_out_bits {
8188         u8         status[0x8];
8189         u8         reserved_at_8[0x18];
8190
8191         u8         syndrome[0x20];
8192
8193         u8         reserved_at_40[0x40];
8194 };
8195
8196 struct mlx5_ifc_modify_lag_in_bits {
8197         u8         opcode[0x10];
8198         u8         reserved_at_10[0x10];
8199
8200         u8         reserved_at_20[0x10];
8201         u8         op_mod[0x10];
8202
8203         u8         reserved_at_40[0x20];
8204         u8         field_select[0x20];
8205
8206         struct mlx5_ifc_lagc_bits ctx;
8207 };
8208
8209 struct mlx5_ifc_query_lag_out_bits {
8210         u8         status[0x8];
8211         u8         reserved_at_8[0x18];
8212
8213         u8         syndrome[0x20];
8214
8215         u8         reserved_at_40[0x40];
8216
8217         struct mlx5_ifc_lagc_bits ctx;
8218 };
8219
8220 struct mlx5_ifc_query_lag_in_bits {
8221         u8         opcode[0x10];
8222         u8         reserved_at_10[0x10];
8223
8224         u8         reserved_at_20[0x10];
8225         u8         op_mod[0x10];
8226
8227         u8         reserved_at_40[0x40];
8228 };
8229
8230 struct mlx5_ifc_destroy_lag_out_bits {
8231         u8         status[0x8];
8232         u8         reserved_at_8[0x18];
8233
8234         u8         syndrome[0x20];
8235
8236         u8         reserved_at_40[0x40];
8237 };
8238
8239 struct mlx5_ifc_destroy_lag_in_bits {
8240         u8         opcode[0x10];
8241         u8         reserved_at_10[0x10];
8242
8243         u8         reserved_at_20[0x10];
8244         u8         op_mod[0x10];
8245
8246         u8         reserved_at_40[0x40];
8247 };
8248
8249 struct mlx5_ifc_create_vport_lag_out_bits {
8250         u8         status[0x8];
8251         u8         reserved_at_8[0x18];
8252
8253         u8         syndrome[0x20];
8254
8255         u8         reserved_at_40[0x40];
8256 };
8257
8258 struct mlx5_ifc_create_vport_lag_in_bits {
8259         u8         opcode[0x10];
8260         u8         reserved_at_10[0x10];
8261
8262         u8         reserved_at_20[0x10];
8263         u8         op_mod[0x10];
8264
8265         u8         reserved_at_40[0x40];
8266 };
8267
8268 struct mlx5_ifc_destroy_vport_lag_out_bits {
8269         u8         status[0x8];
8270         u8         reserved_at_8[0x18];
8271
8272         u8         syndrome[0x20];
8273
8274         u8         reserved_at_40[0x40];
8275 };
8276
8277 struct mlx5_ifc_destroy_vport_lag_in_bits {
8278         u8         opcode[0x10];
8279         u8         reserved_at_10[0x10];
8280
8281         u8         reserved_at_20[0x10];
8282         u8         op_mod[0x10];
8283
8284         u8         reserved_at_40[0x40];
8285 };
8286
8287 #endif /* MLX5_IFC_H */