include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  71 };
  72
  73 enum {
  74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  75         MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
  76         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  77 };
  78
  79 enum {
  80         MLX5_SHARED_RESOURCE_UID = 0xffff,
  81 };
  82
  83 enum {
  84         MLX5_OBJ_TYPE_SW_ICM = 0x0008,
  85 };
  86
  87 enum {
  88         MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
  89         MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
  90         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
  91 };
  92
  93 enum {
  94         MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
  95         MLX5_OBJ_TYPE_MKEY = 0xff01,
  96         MLX5_OBJ_TYPE_QP = 0xff02,
  97         MLX5_OBJ_TYPE_PSV = 0xff03,
  98         MLX5_OBJ_TYPE_RMP = 0xff04,
  99         MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
 100         MLX5_OBJ_TYPE_RQ = 0xff06,
 101         MLX5_OBJ_TYPE_SQ = 0xff07,
 102         MLX5_OBJ_TYPE_TIR = 0xff08,
 103         MLX5_OBJ_TYPE_TIS = 0xff09,
 104         MLX5_OBJ_TYPE_DCT = 0xff0a,
 105         MLX5_OBJ_TYPE_XRQ = 0xff0b,
 106         MLX5_OBJ_TYPE_RQT = 0xff0e,
 107         MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
 108         MLX5_OBJ_TYPE_CQ = 0xff10,
 109 };
 110
 111 enum {
 112         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
 113         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
 114         MLX5_CMD_OP_INIT_HCA                      = 0x102,
 115         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
 116         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
 117         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
 118         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
 119         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 120         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 121         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 122         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 123         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 124         MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
 125         MLX5_CMD_OP_ALLOC_SF                      = 0x113,
 126         MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
 127         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 128         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 129         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 130         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 131         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 132         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 133         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 134         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 135         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 136         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 137         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 138         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 139         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 140         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 141         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 142         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 143         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 144         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 145         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 146         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 147         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 148         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 149         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 150         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 151         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 152         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 153         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 154         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 155         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 156         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 157         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 158         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 159         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 160         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 161         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 162         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 163         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 164         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 165         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 166         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 167         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 168         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 169         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 170         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 171         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 172         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 173         MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
 174         MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
 175         MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
 176         MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
 177         MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
 178         MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
 179         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 180         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 181         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 182         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 183         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 184         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 185         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 186         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 187         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 188         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 189         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 190         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 191         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 192         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 193         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 194         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 195         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 196         MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
 197         MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
 198         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 199         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 200         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 201         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 202         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 203         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 204         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 205         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 206         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 207         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 208         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 209         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 210         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 211         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 212         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 213         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 214         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 215         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 216         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 217         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 218         MLX5_CMD_OP_NOP                           = 0x80d,
 219         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 220         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 221         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 222         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 223         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 224         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 225         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 226         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 227         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 228         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 229         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 230         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 231         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 232         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 233         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 234         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 235         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 236         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 237         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 238         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 239         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 240         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 241         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 242         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 243         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 244         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 245         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 246         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 247         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 248         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 249         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 250         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 251         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 252         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 253         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 254         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 255         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 256         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 257         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 258         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 259         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 260         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 261         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 262         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 263         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 264         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 265         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 266         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 267         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 268         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 269         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 270         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 271         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 272         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 273         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 274         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 275         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 276         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 277         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 278         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 279         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 280         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 281         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 282         MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
 283         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 284         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 285         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 286         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 287         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 288         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 289         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 290         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 291         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 292         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 293         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 294         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 295         MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
 296         MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
 297         MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
 298         MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
 299         MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
 300         MLX5_CMD_OP_MAX
 301 };
 302
 303 /* Valid range for general commands that don't work over an object */
 304 enum {
 305         MLX5_CMD_OP_GENERAL_START = 0xb00,
 306         MLX5_CMD_OP_GENERAL_END = 0xd00,
 307 };
 308
 309 struct mlx5_ifc_flow_table_fields_supported_bits {
 310         u8         outer_dmac[0x1];
 311         u8         outer_smac[0x1];
 312         u8         outer_ether_type[0x1];
 313         u8         outer_ip_version[0x1];
 314         u8         outer_first_prio[0x1];
 315         u8         outer_first_cfi[0x1];
 316         u8         outer_first_vid[0x1];
 317         u8         outer_ipv4_ttl[0x1];
 318         u8         outer_second_prio[0x1];
 319         u8         outer_second_cfi[0x1];
 320         u8         outer_second_vid[0x1];
 321         u8         reserved_at_b[0x1];
 322         u8         outer_sip[0x1];
 323         u8         outer_dip[0x1];
 324         u8         outer_frag[0x1];
 325         u8         outer_ip_protocol[0x1];
 326         u8         outer_ip_ecn[0x1];
 327         u8         outer_ip_dscp[0x1];
 328         u8         outer_udp_sport[0x1];
 329         u8         outer_udp_dport[0x1];
 330         u8         outer_tcp_sport[0x1];
 331         u8         outer_tcp_dport[0x1];
 332         u8         outer_tcp_flags[0x1];
 333         u8         outer_gre_protocol[0x1];
 334         u8         outer_gre_key[0x1];
 335         u8         outer_vxlan_vni[0x1];
 336         u8         outer_geneve_vni[0x1];
 337         u8         outer_geneve_oam[0x1];
 338         u8         outer_geneve_protocol_type[0x1];
 339         u8         outer_geneve_opt_len[0x1];
 340         u8         reserved_at_1e[0x1];
 341         u8         source_eswitch_port[0x1];
 342
 343         u8         inner_dmac[0x1];
 344         u8         inner_smac[0x1];
 345         u8         inner_ether_type[0x1];
 346         u8         inner_ip_version[0x1];
 347         u8         inner_first_prio[0x1];
 348         u8         inner_first_cfi[0x1];
 349         u8         inner_first_vid[0x1];
 350         u8         reserved_at_27[0x1];
 351         u8         inner_second_prio[0x1];
 352         u8         inner_second_cfi[0x1];
 353         u8         inner_second_vid[0x1];
 354         u8         reserved_at_2b[0x1];
 355         u8         inner_sip[0x1];
 356         u8         inner_dip[0x1];
 357         u8         inner_frag[0x1];
 358         u8         inner_ip_protocol[0x1];
 359         u8         inner_ip_ecn[0x1];
 360         u8         inner_ip_dscp[0x1];
 361         u8         inner_udp_sport[0x1];
 362         u8         inner_udp_dport[0x1];
 363         u8         inner_tcp_sport[0x1];
 364         u8         inner_tcp_dport[0x1];
 365         u8         inner_tcp_flags[0x1];
 366         u8         reserved_at_37[0x9];
 367
 368         u8         geneve_tlv_option_0_data[0x1];
 369         u8         reserved_at_41[0x4];
 370         u8         outer_first_mpls_over_udp[0x4];
 371         u8         outer_first_mpls_over_gre[0x4];
 372         u8         inner_first_mpls[0x4];
 373         u8         outer_first_mpls[0x4];
 374         u8         reserved_at_55[0x2];
 375         u8         outer_esp_spi[0x1];
 376         u8         reserved_at_58[0x2];
 377         u8         bth_dst_qp[0x1];
 378         u8         reserved_at_5b[0x5];
 379
 380         u8         reserved_at_60[0x18];
 381         u8         metadata_reg_c_7[0x1];
 382         u8         metadata_reg_c_6[0x1];
 383         u8         metadata_reg_c_5[0x1];
 384         u8         metadata_reg_c_4[0x1];
 385         u8         metadata_reg_c_3[0x1];
 386         u8         metadata_reg_c_2[0x1];
 387         u8         metadata_reg_c_1[0x1];
 388         u8         metadata_reg_c_0[0x1];
 389 };
 390
 391 struct mlx5_ifc_flow_table_prop_layout_bits {
 392         u8         ft_support[0x1];
 393         u8         reserved_at_1[0x1];
 394         u8         flow_counter[0x1];
 395         u8         flow_modify_en[0x1];
 396         u8         modify_root[0x1];
 397         u8         identified_miss_table_mode[0x1];
 398         u8         flow_table_modify[0x1];
 399         u8         reformat[0x1];
 400         u8         decap[0x1];
 401         u8         reserved_at_9[0x1];
 402         u8         pop_vlan[0x1];
 403         u8         push_vlan[0x1];
 404         u8         reserved_at_c[0x1];
 405         u8         pop_vlan_2[0x1];
 406         u8         push_vlan_2[0x1];
 407         u8         reformat_and_vlan_action[0x1];
 408         u8         reserved_at_10[0x1];
 409         u8         sw_owner[0x1];
 410         u8         reformat_l3_tunnel_to_l2[0x1];
 411         u8         reformat_l2_to_l3_tunnel[0x1];
 412         u8         reformat_and_modify_action[0x1];
 413         u8         ignore_flow_level[0x1];
 414         u8         reserved_at_16[0x1];
 415         u8         table_miss_action_domain[0x1];
 416         u8         termination_table[0x1];
 417         u8         reserved_at_19[0x7];
 418         u8         reserved_at_20[0x2];
 419         u8         log_max_ft_size[0x6];
 420         u8         log_max_modify_header_context[0x8];
 421         u8         max_modify_header_actions[0x8];
 422         u8         max_ft_level[0x8];
 423
 424         u8         reserved_at_40[0x20];
 425
 426         u8         reserved_at_60[0x18];
 427         u8         log_max_ft_num[0x8];
 428
 429         u8         reserved_at_80[0x18];
 430         u8         log_max_destination[0x8];
 431
 432         u8         log_max_flow_counter[0x8];
 433         u8         reserved_at_a8[0x10];
 434         u8         log_max_flow[0x8];
 435
 436         u8         reserved_at_c0[0x40];
 437
 438         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 439
 440         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 441 };
 442
 443 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 444         u8         send[0x1];
 445         u8         receive[0x1];
 446         u8         write[0x1];
 447         u8         read[0x1];
 448         u8         atomic[0x1];
 449         u8         srq_receive[0x1];
 450         u8         reserved_at_6[0x1a];
 451 };
 452
 453 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 454         u8         smac_47_16[0x20];
 455
 456         u8         smac_15_0[0x10];
 457         u8         ethertype[0x10];
 458
 459         u8         dmac_47_16[0x20];
 460
 461         u8         dmac_15_0[0x10];
 462         u8         first_prio[0x3];
 463         u8         first_cfi[0x1];
 464         u8         first_vid[0xc];
 465
 466         u8         ip_protocol[0x8];
 467         u8         ip_dscp[0x6];
 468         u8         ip_ecn[0x2];
 469         u8         cvlan_tag[0x1];
 470         u8         svlan_tag[0x1];
 471         u8         frag[0x1];
 472         u8         ip_version[0x4];
 473         u8         tcp_flags[0x9];
 474
 475         u8         tcp_sport[0x10];
 476         u8         tcp_dport[0x10];
 477
 478         u8         reserved_at_c0[0x18];
 479         u8         ttl_hoplimit[0x8];
 480
 481         u8         udp_sport[0x10];
 482         u8         udp_dport[0x10];
 483
 484         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 485
 486         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 487 };
 488
 489 struct mlx5_ifc_nvgre_key_bits {
 490         u8 hi[0x18];
 491         u8 lo[0x8];
 492 };
 493
 494 union mlx5_ifc_gre_key_bits {
 495         struct mlx5_ifc_nvgre_key_bits nvgre;
 496         u8 key[0x20];
 497 };
 498
 499 struct mlx5_ifc_fte_match_set_misc_bits {
 500         u8         gre_c_present[0x1];
 501         u8         reserved_at_1[0x1];
 502         u8         gre_k_present[0x1];
 503         u8         gre_s_present[0x1];
 504         u8         source_vhca_port[0x4];
 505         u8         source_sqn[0x18];
 506
 507         u8         source_eswitch_owner_vhca_id[0x10];
 508         u8         source_port[0x10];
 509
 510         u8         outer_second_prio[0x3];
 511         u8         outer_second_cfi[0x1];
 512         u8         outer_second_vid[0xc];
 513         u8         inner_second_prio[0x3];
 514         u8         inner_second_cfi[0x1];
 515         u8         inner_second_vid[0xc];
 516
 517         u8         outer_second_cvlan_tag[0x1];
 518         u8         inner_second_cvlan_tag[0x1];
 519         u8         outer_second_svlan_tag[0x1];
 520         u8         inner_second_svlan_tag[0x1];
 521         u8         reserved_at_64[0xc];
 522         u8         gre_protocol[0x10];
 523
 524         union mlx5_ifc_gre_key_bits gre_key;
 525
 526         u8         vxlan_vni[0x18];
 527         u8         reserved_at_b8[0x8];
 528
 529         u8         geneve_vni[0x18];
 530         u8         reserved_at_d8[0x7];
 531         u8         geneve_oam[0x1];
 532
 533         u8         reserved_at_e0[0xc];
 534         u8         outer_ipv6_flow_label[0x14];
 535
 536         u8         reserved_at_100[0xc];
 537         u8         inner_ipv6_flow_label[0x14];
 538
 539         u8         reserved_at_120[0xa];
 540         u8         geneve_opt_len[0x6];
 541         u8         geneve_protocol_type[0x10];
 542
 543         u8         reserved_at_140[0x8];
 544         u8         bth_dst_qp[0x18];
 545         u8         reserved_at_160[0x20];
 546         u8         outer_esp_spi[0x20];
 547         u8         reserved_at_1a0[0x60];
 548 };
 549
 550 struct mlx5_ifc_fte_match_mpls_bits {
 551         u8         mpls_label[0x14];
 552         u8         mpls_exp[0x3];
 553         u8         mpls_s_bos[0x1];
 554         u8         mpls_ttl[0x8];
 555 };
 556
 557 struct mlx5_ifc_fte_match_set_misc2_bits {
 558         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 559
 560         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 561
 562         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 563
 564         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 565
 566         u8         metadata_reg_c_7[0x20];
 567
 568         u8         metadata_reg_c_6[0x20];
 569
 570         u8         metadata_reg_c_5[0x20];
 571
 572         u8         metadata_reg_c_4[0x20];
 573
 574         u8         metadata_reg_c_3[0x20];
 575
 576         u8         metadata_reg_c_2[0x20];
 577
 578         u8         metadata_reg_c_1[0x20];
 579
 580         u8         metadata_reg_c_0[0x20];
 581
 582         u8         metadata_reg_a[0x20];
 583
 584         u8         metadata_reg_b[0x20];
 585
 586         u8         reserved_at_1c0[0x40];
 587 };
 588
 589 struct mlx5_ifc_fte_match_set_misc3_bits {
 590         u8         inner_tcp_seq_num[0x20];
 591
 592         u8         outer_tcp_seq_num[0x20];
 593
 594         u8         inner_tcp_ack_num[0x20];
 595
 596         u8         outer_tcp_ack_num[0x20];
 597
 598         u8         reserved_at_80[0x8];
 599         u8         outer_vxlan_gpe_vni[0x18];
 600
 601         u8         outer_vxlan_gpe_next_protocol[0x8];
 602         u8         outer_vxlan_gpe_flags[0x8];
 603         u8         reserved_at_b0[0x10];
 604
 605         u8         icmp_header_data[0x20];
 606
 607         u8         icmpv6_header_data[0x20];
 608
 609         u8         icmp_type[0x8];
 610         u8         icmp_code[0x8];
 611         u8         icmpv6_type[0x8];
 612         u8         icmpv6_code[0x8];
 613
 614         u8         geneve_tlv_option_0_data[0x20];
 615
 616         u8         reserved_at_140[0xc0];
 617 };
 618
 619 struct mlx5_ifc_cmd_pas_bits {
 620         u8         pa_h[0x20];
 621
 622         u8         pa_l[0x14];
 623         u8         reserved_at_34[0xc];
 624 };
 625
 626 struct mlx5_ifc_uint64_bits {
 627         u8         hi[0x20];
 628
 629         u8         lo[0x20];
 630 };
 631
 632 enum {
 633         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 634         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 635         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 636         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 637         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 638         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 639         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 640         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 641         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 642         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 643 };
 644
 645 struct mlx5_ifc_ads_bits {
 646         u8         fl[0x1];
 647         u8         free_ar[0x1];
 648         u8         reserved_at_2[0xe];
 649         u8         pkey_index[0x10];
 650
 651         u8         reserved_at_20[0x8];
 652         u8         grh[0x1];
 653         u8         mlid[0x7];
 654         u8         rlid[0x10];
 655
 656         u8         ack_timeout[0x5];
 657         u8         reserved_at_45[0x3];
 658         u8         src_addr_index[0x8];
 659         u8         reserved_at_50[0x4];
 660         u8         stat_rate[0x4];
 661         u8         hop_limit[0x8];
 662
 663         u8         reserved_at_60[0x4];
 664         u8         tclass[0x8];
 665         u8         flow_label[0x14];
 666
 667         u8         rgid_rip[16][0x8];
 668
 669         u8         reserved_at_100[0x4];
 670         u8         f_dscp[0x1];
 671         u8         f_ecn[0x1];
 672         u8         reserved_at_106[0x1];
 673         u8         f_eth_prio[0x1];
 674         u8         ecn[0x2];
 675         u8         dscp[0x6];
 676         u8         udp_sport[0x10];
 677
 678         u8         dei_cfi[0x1];
 679         u8         eth_prio[0x3];
 680         u8         sl[0x4];
 681         u8         vhca_port_num[0x8];
 682         u8         rmac_47_32[0x10];
 683
 684         u8         rmac_31_0[0x20];
 685 };
 686
 687 struct mlx5_ifc_flow_table_nic_cap_bits {
 688         u8         nic_rx_multi_path_tirs[0x1];
 689         u8         nic_rx_multi_path_tirs_fts[0x1];
 690         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 691         u8         reserved_at_3[0x1d];
 692         u8         encap_general_header[0x1];
 693         u8         reserved_at_21[0xa];
 694         u8         log_max_packet_reformat_context[0x5];
 695         u8         reserved_at_30[0x6];
 696         u8         max_encap_header_size[0xa];
 697         u8         reserved_at_40[0x1c0];
 698
 699         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 700
 701         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 702
 703         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 704
 705         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 706
 707         u8         reserved_at_a00[0x200];
 708
 709         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 710
 711         u8         reserved_at_e00[0x1200];
 712
 713         u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
 714
 715         u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
 716
 717         u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
 718
 719         u8         reserved_at_20c0[0x5f40];
 720 };
 721
 722 enum {
 723         MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
 724         MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
 725         MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
 726         MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
 727         MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
 728         MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
 729         MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
 730         MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
 731 };
 732
 733 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 734         u8      fdb_to_vport_reg_c_id[0x8];
 735         u8      reserved_at_8[0xd];
 736         u8      fdb_modify_header_fwd_to_table[0x1];
 737         u8      reserved_at_16[0x1];
 738         u8      flow_source[0x1];
 739         u8      reserved_at_18[0x2];
 740         u8      multi_fdb_encap[0x1];
 741         u8      reserved_at_1b[0x1];
 742         u8      fdb_multi_path_to_table[0x1];
 743         u8      reserved_at_1d[0x3];
 744
 745         u8      reserved_at_20[0x1e0];
 746
 747         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 748
 749         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 750
 751         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 752
 753         u8      reserved_at_800[0x1000];
 754
 755         u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
 756
 757         u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
 758
 759         u8      sw_steering_uplink_icm_address_rx[0x40];
 760
 761         u8      sw_steering_uplink_icm_address_tx[0x40];
 762
 763         u8      reserved_at_1900[0x6700];
 764 };
 765
 766 enum {
 767         MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
 768         MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
 769 };
 770
 771 struct mlx5_ifc_e_switch_cap_bits {
 772         u8         vport_svlan_strip[0x1];
 773         u8         vport_cvlan_strip[0x1];
 774         u8         vport_svlan_insert[0x1];
 775         u8         vport_cvlan_insert_if_not_exist[0x1];
 776         u8         vport_cvlan_insert_overwrite[0x1];
 777         u8         reserved_at_5[0x3];
 778         u8         esw_uplink_ingress_acl[0x1];
 779         u8         reserved_at_9[0x10];
 780         u8         esw_functions_changed[0x1];
 781         u8         reserved_at_1a[0x1];
 782         u8         ecpf_vport_exists[0x1];
 783         u8         counter_eswitch_affinity[0x1];
 784         u8         merged_eswitch[0x1];
 785         u8         nic_vport_node_guid_modify[0x1];
 786         u8         nic_vport_port_guid_modify[0x1];
 787
 788         u8         vxlan_encap_decap[0x1];
 789         u8         nvgre_encap_decap[0x1];
 790         u8         reserved_at_22[0x1];
 791         u8         log_max_fdb_encap_uplink[0x5];
 792         u8         reserved_at_21[0x3];
 793         u8         log_max_packet_reformat_context[0x5];
 794         u8         reserved_2b[0x6];
 795         u8         max_encap_header_size[0xa];
 796
 797         u8         reserved_at_40[0xb];
 798         u8         log_max_esw_sf[0x5];
 799         u8         esw_sf_base_id[0x10];
 800
 801         u8         reserved_at_60[0x7a0];
 802
 803 };
 804
 805 struct mlx5_ifc_qos_cap_bits {
 806         u8         packet_pacing[0x1];
 807         u8         esw_scheduling[0x1];
 808         u8         esw_bw_share[0x1];
 809         u8         esw_rate_limit[0x1];
 810         u8         reserved_at_4[0x1];
 811         u8         packet_pacing_burst_bound[0x1];
 812         u8         packet_pacing_typical_size[0x1];
 813         u8         reserved_at_7[0x19];
 814
 815         u8         reserved_at_20[0x20];
 816
 817         u8         packet_pacing_max_rate[0x20];
 818
 819         u8         packet_pacing_min_rate[0x20];
 820
 821         u8         reserved_at_80[0x10];
 822         u8         packet_pacing_rate_table_size[0x10];
 823
 824         u8         esw_element_type[0x10];
 825         u8         esw_tsar_type[0x10];
 826
 827         u8         reserved_at_c0[0x10];
 828         u8         max_qos_para_vport[0x10];
 829
 830         u8         max_tsar_bw_share[0x20];
 831
 832         u8         reserved_at_100[0x700];
 833 };
 834
 835 struct mlx5_ifc_debug_cap_bits {
 836         u8         core_dump_general[0x1];
 837         u8         core_dump_qp[0x1];
 838         u8         reserved_at_2[0x7];
 839         u8         resource_dump[0x1];
 840         u8         reserved_at_a[0x16];
 841
 842         u8         reserved_at_20[0x2];
 843         u8         stall_detect[0x1];
 844         u8         reserved_at_23[0x1d];
 845
 846         u8         reserved_at_40[0x7c0];
 847 };
 848
 849 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 850         u8         csum_cap[0x1];
 851         u8         vlan_cap[0x1];
 852         u8         lro_cap[0x1];
 853         u8         lro_psh_flag[0x1];
 854         u8         lro_time_stamp[0x1];
 855         u8         reserved_at_5[0x2];
 856         u8         wqe_vlan_insert[0x1];
 857         u8         self_lb_en_modifiable[0x1];
 858         u8         reserved_at_9[0x2];
 859         u8         max_lso_cap[0x5];
 860         u8         multi_pkt_send_wqe[0x2];
 861         u8         wqe_inline_mode[0x2];
 862         u8         rss_ind_tbl_cap[0x4];
 863         u8         reg_umr_sq[0x1];
 864         u8         scatter_fcs[0x1];
 865         u8         enhanced_multi_pkt_send_wqe[0x1];
 866         u8         tunnel_lso_const_out_ip_id[0x1];
 867         u8         reserved_at_1c[0x2];
 868         u8         tunnel_stateless_gre[0x1];
 869         u8         tunnel_stateless_vxlan[0x1];
 870
 871         u8         swp[0x1];
 872         u8         swp_csum[0x1];
 873         u8         swp_lso[0x1];
 874         u8         cqe_checksum_full[0x1];
 875         u8         reserved_at_24[0x5];
 876         u8         tunnel_stateless_ip_over_ip[0x1];
 877         u8         reserved_at_2a[0x6];
 878         u8         max_vxlan_udp_ports[0x8];
 879         u8         reserved_at_38[0x6];
 880         u8         max_geneve_opt_len[0x1];
 881         u8         tunnel_stateless_geneve_rx[0x1];
 882
 883         u8         reserved_at_40[0x10];
 884         u8         lro_min_mss_size[0x10];
 885
 886         u8         reserved_at_60[0x120];
 887
 888         u8         lro_timer_supported_periods[4][0x20];
 889
 890         u8         reserved_at_200[0x600];
 891 };
 892
 893 struct mlx5_ifc_roce_cap_bits {
 894         u8         roce_apm[0x1];
 895         u8         reserved_at_1[0x1f];
 896
 897         u8         reserved_at_20[0x60];
 898
 899         u8         reserved_at_80[0xc];
 900         u8         l3_type[0x4];
 901         u8         reserved_at_90[0x8];
 902         u8         roce_version[0x8];
 903
 904         u8         reserved_at_a0[0x10];
 905         u8         r_roce_dest_udp_port[0x10];
 906
 907         u8         r_roce_max_src_udp_port[0x10];
 908         u8         r_roce_min_src_udp_port[0x10];
 909
 910         u8         reserved_at_e0[0x10];
 911         u8         roce_address_table_size[0x10];
 912
 913         u8         reserved_at_100[0x700];
 914 };
 915
 916 struct mlx5_ifc_sync_steering_in_bits {
 917         u8         opcode[0x10];
 918         u8         uid[0x10];
 919
 920         u8         reserved_at_20[0x10];
 921         u8         op_mod[0x10];
 922
 923         u8         reserved_at_40[0xc0];
 924 };
 925
 926 struct mlx5_ifc_sync_steering_out_bits {
 927         u8         status[0x8];
 928         u8         reserved_at_8[0x18];
 929
 930         u8         syndrome[0x20];
 931
 932         u8         reserved_at_40[0x40];
 933 };
 934
 935 struct mlx5_ifc_device_mem_cap_bits {
 936         u8         memic[0x1];
 937         u8         reserved_at_1[0x1f];
 938
 939         u8         reserved_at_20[0xb];
 940         u8         log_min_memic_alloc_size[0x5];
 941         u8         reserved_at_30[0x8];
 942         u8         log_max_memic_addr_alignment[0x8];
 943
 944         u8         memic_bar_start_addr[0x40];
 945
 946         u8         memic_bar_size[0x20];
 947
 948         u8         max_memic_size[0x20];
 949
 950         u8         steering_sw_icm_start_address[0x40];
 951
 952         u8         reserved_at_100[0x8];
 953         u8         log_header_modify_sw_icm_size[0x8];
 954         u8         reserved_at_110[0x2];
 955         u8         log_sw_icm_alloc_granularity[0x6];
 956         u8         log_steering_sw_icm_size[0x8];
 957
 958         u8         reserved_at_120[0x20];
 959
 960         u8         header_modify_sw_icm_start_address[0x40];
 961
 962         u8         reserved_at_180[0x680];
 963 };
 964
 965 struct mlx5_ifc_device_event_cap_bits {
 966         u8         user_affiliated_events[4][0x40];
 967
 968         u8         user_unaffiliated_events[4][0x40];
 969 };
 970
 971 struct mlx5_ifc_device_virtio_emulation_cap_bits {
 972         u8         reserved_at_0[0x20];
 973
 974         u8         reserved_at_20[0x13];
 975         u8         log_doorbell_stride[0x5];
 976         u8         reserved_at_38[0x3];
 977         u8         log_doorbell_bar_size[0x5];
 978
 979         u8         doorbell_bar_offset[0x40];
 980
 981         u8         reserved_at_80[0x780];
 982 };
 983
 984 enum {
 985         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 986         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 987         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 988         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 989         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 990         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 991         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 992         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 993         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 994 };
 995
 996 enum {
 997         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 998         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 999         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1000         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1001         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1002         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1003         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1004         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1005         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1006 };
1007
1008 struct mlx5_ifc_atomic_caps_bits {
1009         u8         reserved_at_0[0x40];
1010
1011         u8         atomic_req_8B_endianness_mode[0x2];
1012         u8         reserved_at_42[0x4];
1013         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1014
1015         u8         reserved_at_47[0x19];
1016
1017         u8         reserved_at_60[0x20];
1018
1019         u8         reserved_at_80[0x10];
1020         u8         atomic_operations[0x10];
1021
1022         u8         reserved_at_a0[0x10];
1023         u8         atomic_size_qp[0x10];
1024
1025         u8         reserved_at_c0[0x10];
1026         u8         atomic_size_dc[0x10];
1027
1028         u8         reserved_at_e0[0x720];
1029 };
1030
1031 struct mlx5_ifc_odp_cap_bits {
1032         u8         reserved_at_0[0x40];
1033
1034         u8         sig[0x1];
1035         u8         reserved_at_41[0x1f];
1036
1037         u8         reserved_at_60[0x20];
1038
1039         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1040
1041         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1042
1043         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1044
1045         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1046
1047         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1048
1049         u8         reserved_at_120[0x6E0];
1050 };
1051
1052 struct mlx5_ifc_calc_op {
1053         u8        reserved_at_0[0x10];
1054         u8        reserved_at_10[0x9];
1055         u8        op_swap_endianness[0x1];
1056         u8        op_min[0x1];
1057         u8        op_xor[0x1];
1058         u8        op_or[0x1];
1059         u8        op_and[0x1];
1060         u8        op_max[0x1];
1061         u8        op_add[0x1];
1062 };
1063
1064 struct mlx5_ifc_vector_calc_cap_bits {
1065         u8         calc_matrix[0x1];
1066         u8         reserved_at_1[0x1f];
1067         u8         reserved_at_20[0x8];
1068         u8         max_vec_count[0x8];
1069         u8         reserved_at_30[0xd];
1070         u8         max_chunk_size[0x3];
1071         struct mlx5_ifc_calc_op calc0;
1072         struct mlx5_ifc_calc_op calc1;
1073         struct mlx5_ifc_calc_op calc2;
1074         struct mlx5_ifc_calc_op calc3;
1075
1076         u8         reserved_at_c0[0x720];
1077 };
1078
1079 struct mlx5_ifc_tls_cap_bits {
1080         u8         tls_1_2_aes_gcm_128[0x1];
1081         u8         tls_1_3_aes_gcm_128[0x1];
1082         u8         tls_1_2_aes_gcm_256[0x1];
1083         u8         tls_1_3_aes_gcm_256[0x1];
1084         u8         reserved_at_4[0x1c];
1085
1086         u8         reserved_at_20[0x7e0];
1087 };
1088
1089 enum {
1090         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1091         MLX5_WQ_TYPE_CYCLIC       = 0x1,
1092         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1093         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1094 };
1095
1096 enum {
1097         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1098         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1099 };
1100
1101 enum {
1102         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1103         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1104         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1105         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1106         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1107 };
1108
1109 enum {
1110         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1111         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1112         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1113         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1114         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1115         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1116 };
1117
1118 enum {
1119         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1120         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1121 };
1122
1123 enum {
1124         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1125         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1126         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1127 };
1128
1129 enum {
1130         MLX5_CAP_PORT_TYPE_IB  = 0x0,
1131         MLX5_CAP_PORT_TYPE_ETH = 0x1,
1132 };
1133
1134 enum {
1135         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
1136         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
1137         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
1138 };
1139
1140 enum {
1141         MLX5_FLEX_PARSER_GENEVE_ENABLED         = 1 << 3,
1142         MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED      = 1 << 7,
1143         MLX5_FLEX_PARSER_ICMP_V4_ENABLED        = 1 << 8,
1144         MLX5_FLEX_PARSER_ICMP_V6_ENABLED        = 1 << 9,
1145 };
1146
1147 enum {
1148         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1149         MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1150 };
1151
1152 #define MLX5_FC_BULK_SIZE_FACTOR 128
1153
1154 enum mlx5_fc_bulk_alloc_bitmask {
1155         MLX5_FC_BULK_128   = (1 << 0),
1156         MLX5_FC_BULK_256   = (1 << 1),
1157         MLX5_FC_BULK_512   = (1 << 2),
1158         MLX5_FC_BULK_1024  = (1 << 3),
1159         MLX5_FC_BULK_2048  = (1 << 4),
1160         MLX5_FC_BULK_4096  = (1 << 5),
1161         MLX5_FC_BULK_8192  = (1 << 6),
1162         MLX5_FC_BULK_16384 = (1 << 7),
1163 };
1164
1165 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1166
1167 struct mlx5_ifc_cmd_hca_cap_bits {
1168         u8         reserved_at_0[0x30];
1169         u8         vhca_id[0x10];
1170
1171         u8         reserved_at_40[0x40];
1172
1173         u8         log_max_srq_sz[0x8];
1174         u8         log_max_qp_sz[0x8];
1175         u8         event_cap[0x1];
1176         u8         reserved_at_91[0x7];
1177         u8         prio_tag_required[0x1];
1178         u8         reserved_at_99[0x2];
1179         u8         log_max_qp[0x5];
1180
1181         u8         reserved_at_a0[0xb];
1182         u8         log_max_srq[0x5];
1183         u8         reserved_at_b0[0x10];
1184
1185         u8         max_sgl_for_optimized_performance[0x8];
1186         u8         log_max_cq_sz[0x8];
1187         u8         reserved_at_d0[0xb];
1188         u8         log_max_cq[0x5];
1189
1190         u8         log_max_eq_sz[0x8];
1191         u8         relaxed_ordering_write[0x1];
1192         u8         relaxed_ordering_read[0x1];
1193         u8         log_max_mkey[0x6];
1194         u8         reserved_at_f0[0x8];
1195         u8         dump_fill_mkey[0x1];
1196         u8         reserved_at_f9[0x2];
1197         u8         fast_teardown[0x1];
1198         u8         log_max_eq[0x4];
1199
1200         u8         max_indirection[0x8];
1201         u8         fixed_buffer_size[0x1];
1202         u8         log_max_mrw_sz[0x7];
1203         u8         force_teardown[0x1];
1204         u8         reserved_at_111[0x1];
1205         u8         log_max_bsf_list_size[0x6];
1206         u8         umr_extended_translation_offset[0x1];
1207         u8         null_mkey[0x1];
1208         u8         log_max_klm_list_size[0x6];
1209
1210         u8         reserved_at_120[0xa];
1211         u8         log_max_ra_req_dc[0x6];
1212         u8         reserved_at_130[0xa];
1213         u8         log_max_ra_res_dc[0x6];
1214
1215         u8         reserved_at_140[0x9];
1216         u8         roce_accl[0x1];
1217         u8         log_max_ra_req_qp[0x6];
1218         u8         reserved_at_150[0xa];
1219         u8         log_max_ra_res_qp[0x6];
1220
1221         u8         end_pad[0x1];
1222         u8         cc_query_allowed[0x1];
1223         u8         cc_modify_allowed[0x1];
1224         u8         start_pad[0x1];
1225         u8         cache_line_128byte[0x1];
1226         u8         reserved_at_165[0x4];
1227         u8         rts2rts_qp_counters_set_id[0x1];
1228         u8         reserved_at_16a[0x2];
1229         u8         vnic_env_int_rq_oob[0x1];
1230         u8         sbcam_reg[0x1];
1231         u8         reserved_at_16e[0x1];
1232         u8         qcam_reg[0x1];
1233         u8         gid_table_size[0x10];
1234
1235         u8         out_of_seq_cnt[0x1];
1236         u8         vport_counters[0x1];
1237         u8         retransmission_q_counters[0x1];
1238         u8         debug[0x1];
1239         u8         modify_rq_counter_set_id[0x1];
1240         u8         rq_delay_drop[0x1];
1241         u8         max_qp_cnt[0xa];
1242         u8         pkey_table_size[0x10];
1243
1244         u8         vport_group_manager[0x1];
1245         u8         vhca_group_manager[0x1];
1246         u8         ib_virt[0x1];
1247         u8         eth_virt[0x1];
1248         u8         vnic_env_queue_counters[0x1];
1249         u8         ets[0x1];
1250         u8         nic_flow_table[0x1];
1251         u8         eswitch_manager[0x1];
1252         u8         device_memory[0x1];
1253         u8         mcam_reg[0x1];
1254         u8         pcam_reg[0x1];
1255         u8         local_ca_ack_delay[0x5];
1256         u8         port_module_event[0x1];
1257         u8         enhanced_error_q_counters[0x1];
1258         u8         ports_check[0x1];
1259         u8         reserved_at_1b3[0x1];
1260         u8         disable_link_up[0x1];
1261         u8         beacon_led[0x1];
1262         u8         port_type[0x2];
1263         u8         num_ports[0x8];
1264
1265         u8         reserved_at_1c0[0x1];
1266         u8         pps[0x1];
1267         u8         pps_modify[0x1];
1268         u8         log_max_msg[0x5];
1269         u8         reserved_at_1c8[0x4];
1270         u8         max_tc[0x4];
1271         u8         temp_warn_event[0x1];
1272         u8         dcbx[0x1];
1273         u8         general_notification_event[0x1];
1274         u8         reserved_at_1d3[0x2];
1275         u8         fpga[0x1];
1276         u8         rol_s[0x1];
1277         u8         rol_g[0x1];
1278         u8         reserved_at_1d8[0x1];
1279         u8         wol_s[0x1];
1280         u8         wol_g[0x1];
1281         u8         wol_a[0x1];
1282         u8         wol_b[0x1];
1283         u8         wol_m[0x1];
1284         u8         wol_u[0x1];
1285         u8         wol_p[0x1];
1286
1287         u8         stat_rate_support[0x10];
1288         u8         reserved_at_1f0[0xc];
1289         u8         cqe_version[0x4];
1290
1291         u8         compact_address_vector[0x1];
1292         u8         striding_rq[0x1];
1293         u8         reserved_at_202[0x1];
1294         u8         ipoib_enhanced_offloads[0x1];
1295         u8         ipoib_basic_offloads[0x1];
1296         u8         reserved_at_205[0x1];
1297         u8         repeated_block_disabled[0x1];
1298         u8         umr_modify_entity_size_disabled[0x1];
1299         u8         umr_modify_atomic_disabled[0x1];
1300         u8         umr_indirect_mkey_disabled[0x1];
1301         u8         umr_fence[0x2];
1302         u8         dc_req_scat_data_cqe[0x1];
1303         u8         reserved_at_20d[0x2];
1304         u8         drain_sigerr[0x1];
1305         u8         cmdif_checksum[0x2];
1306         u8         sigerr_cqe[0x1];
1307         u8         reserved_at_213[0x1];
1308         u8         wq_signature[0x1];
1309         u8         sctr_data_cqe[0x1];
1310         u8         reserved_at_216[0x1];
1311         u8         sho[0x1];
1312         u8         tph[0x1];
1313         u8         rf[0x1];
1314         u8         dct[0x1];
1315         u8         qos[0x1];
1316         u8         eth_net_offloads[0x1];
1317         u8         roce[0x1];
1318         u8         atomic[0x1];
1319         u8         reserved_at_21f[0x1];
1320
1321         u8         cq_oi[0x1];
1322         u8         cq_resize[0x1];
1323         u8         cq_moderation[0x1];
1324         u8         reserved_at_223[0x3];
1325         u8         cq_eq_remap[0x1];
1326         u8         pg[0x1];
1327         u8         block_lb_mc[0x1];
1328         u8         reserved_at_229[0x1];
1329         u8         scqe_break_moderation[0x1];
1330         u8         cq_period_start_from_cqe[0x1];
1331         u8         cd[0x1];
1332         u8         reserved_at_22d[0x1];
1333         u8         apm[0x1];
1334         u8         vector_calc[0x1];
1335         u8         umr_ptr_rlky[0x1];
1336         u8         imaicl[0x1];
1337         u8         qp_packet_based[0x1];
1338         u8         reserved_at_233[0x3];
1339         u8         qkv[0x1];
1340         u8         pkv[0x1];
1341         u8         set_deth_sqpn[0x1];
1342         u8         reserved_at_239[0x3];
1343         u8         xrc[0x1];
1344         u8         ud[0x1];
1345         u8         uc[0x1];
1346         u8         rc[0x1];
1347
1348         u8         uar_4k[0x1];
1349         u8         reserved_at_241[0x9];
1350         u8         uar_sz[0x6];
1351         u8         reserved_at_250[0x8];
1352         u8         log_pg_sz[0x8];
1353
1354         u8         bf[0x1];
1355         u8         driver_version[0x1];
1356         u8         pad_tx_eth_packet[0x1];
1357         u8         reserved_at_263[0x8];
1358         u8         log_bf_reg_size[0x5];
1359
1360         u8         reserved_at_270[0x8];
1361         u8         lag_tx_port_affinity[0x1];
1362         u8         reserved_at_279[0x2];
1363         u8         lag_master[0x1];
1364         u8         num_lag_ports[0x4];
1365
1366         u8         reserved_at_280[0x10];
1367         u8         max_wqe_sz_sq[0x10];
1368
1369         u8         reserved_at_2a0[0x10];
1370         u8         max_wqe_sz_rq[0x10];
1371
1372         u8         max_flow_counter_31_16[0x10];
1373         u8         max_wqe_sz_sq_dc[0x10];
1374
1375         u8         reserved_at_2e0[0x7];
1376         u8         max_qp_mcg[0x19];
1377
1378         u8         reserved_at_300[0x10];
1379         u8         flow_counter_bulk_alloc[0x8];
1380         u8         log_max_mcg[0x8];
1381
1382         u8         reserved_at_320[0x3];
1383         u8         log_max_transport_domain[0x5];
1384         u8         reserved_at_328[0x3];
1385         u8         log_max_pd[0x5];
1386         u8         reserved_at_330[0xb];
1387         u8         log_max_xrcd[0x5];
1388
1389         u8         nic_receive_steering_discard[0x1];
1390         u8         receive_discard_vport_down[0x1];
1391         u8         transmit_discard_vport_down[0x1];
1392         u8         reserved_at_343[0x5];
1393         u8         log_max_flow_counter_bulk[0x8];
1394         u8         max_flow_counter_15_0[0x10];
1395
1396
1397         u8         reserved_at_360[0x3];
1398         u8         log_max_rq[0x5];
1399         u8         reserved_at_368[0x3];
1400         u8         log_max_sq[0x5];
1401         u8         reserved_at_370[0x3];
1402         u8         log_max_tir[0x5];
1403         u8         reserved_at_378[0x3];
1404         u8         log_max_tis[0x5];
1405
1406         u8         basic_cyclic_rcv_wqe[0x1];
1407         u8         reserved_at_381[0x2];
1408         u8         log_max_rmp[0x5];
1409         u8         reserved_at_388[0x3];
1410         u8         log_max_rqt[0x5];
1411         u8         reserved_at_390[0x3];
1412         u8         log_max_rqt_size[0x5];
1413         u8         reserved_at_398[0x3];
1414         u8         log_max_tis_per_sq[0x5];
1415
1416         u8         ext_stride_num_range[0x1];
1417         u8         reserved_at_3a1[0x2];
1418         u8         log_max_stride_sz_rq[0x5];
1419         u8         reserved_at_3a8[0x3];
1420         u8         log_min_stride_sz_rq[0x5];
1421         u8         reserved_at_3b0[0x3];
1422         u8         log_max_stride_sz_sq[0x5];
1423         u8         reserved_at_3b8[0x3];
1424         u8         log_min_stride_sz_sq[0x5];
1425
1426         u8         hairpin[0x1];
1427         u8         reserved_at_3c1[0x2];
1428         u8         log_max_hairpin_queues[0x5];
1429         u8         reserved_at_3c8[0x3];
1430         u8         log_max_hairpin_wq_data_sz[0x5];
1431         u8         reserved_at_3d0[0x3];
1432         u8         log_max_hairpin_num_packets[0x5];
1433         u8         reserved_at_3d8[0x3];
1434         u8         log_max_wq_sz[0x5];
1435
1436         u8         nic_vport_change_event[0x1];
1437         u8         disable_local_lb_uc[0x1];
1438         u8         disable_local_lb_mc[0x1];
1439         u8         log_min_hairpin_wq_data_sz[0x5];
1440         u8         reserved_at_3e8[0x3];
1441         u8         log_max_vlan_list[0x5];
1442         u8         reserved_at_3f0[0x3];
1443         u8         log_max_current_mc_list[0x5];
1444         u8         reserved_at_3f8[0x3];
1445         u8         log_max_current_uc_list[0x5];
1446
1447         u8         general_obj_types[0x40];
1448
1449         u8         reserved_at_440[0x20];
1450
1451         u8         tls[0x1];
1452         u8         reserved_at_461[0x2];
1453         u8         log_max_uctx[0x5];
1454         u8         reserved_at_468[0x3];
1455         u8         log_max_umem[0x5];
1456         u8         max_num_eqs[0x10];
1457
1458         u8         reserved_at_480[0x3];
1459         u8         log_max_l2_table[0x5];
1460         u8         reserved_at_488[0x8];
1461         u8         log_uar_page_sz[0x10];
1462
1463         u8         reserved_at_4a0[0x20];
1464         u8         device_frequency_mhz[0x20];
1465         u8         device_frequency_khz[0x20];
1466
1467         u8         reserved_at_500[0x20];
1468         u8         num_of_uars_per_page[0x20];
1469
1470         u8         flex_parser_protocols[0x20];
1471
1472         u8         max_geneve_tlv_options[0x8];
1473         u8         reserved_at_568[0x3];
1474         u8         max_geneve_tlv_option_data_len[0x5];
1475         u8         reserved_at_570[0x10];
1476
1477         u8         reserved_at_580[0x33];
1478         u8         log_max_dek[0x5];
1479         u8         reserved_at_5b8[0x4];
1480         u8         mini_cqe_resp_stride_index[0x1];
1481         u8         cqe_128_always[0x1];
1482         u8         cqe_compression_128[0x1];
1483         u8         cqe_compression[0x1];
1484
1485         u8         cqe_compression_timeout[0x10];
1486         u8         cqe_compression_max_num[0x10];
1487
1488         u8         reserved_at_5e0[0x10];
1489         u8         tag_matching[0x1];
1490         u8         rndv_offload_rc[0x1];
1491         u8         rndv_offload_dc[0x1];
1492         u8         log_tag_matching_list_sz[0x5];
1493         u8         reserved_at_5f8[0x3];
1494         u8         log_max_xrq[0x5];
1495
1496         u8         affiliate_nic_vport_criteria[0x8];
1497         u8         native_port_num[0x8];
1498         u8         num_vhca_ports[0x8];
1499         u8         reserved_at_618[0x6];
1500         u8         sw_owner_id[0x1];
1501         u8         reserved_at_61f[0x1];
1502
1503         u8         max_num_of_monitor_counters[0x10];
1504         u8         num_ppcnt_monitor_counters[0x10];
1505
1506         u8         reserved_at_640[0x10];
1507         u8         num_q_monitor_counters[0x10];
1508
1509         u8         reserved_at_660[0x20];
1510
1511         u8         sf[0x1];
1512         u8         sf_set_partition[0x1];
1513         u8         reserved_at_682[0x1];
1514         u8         log_max_sf[0x5];
1515         u8         reserved_at_688[0x8];
1516         u8         log_min_sf_size[0x8];
1517         u8         max_num_sf_partitions[0x8];
1518
1519         u8         uctx_cap[0x20];
1520
1521         u8         reserved_at_6c0[0x4];
1522         u8         flex_parser_id_geneve_tlv_option_0[0x4];
1523         u8         flex_parser_id_icmp_dw1[0x4];
1524         u8         flex_parser_id_icmp_dw0[0x4];
1525         u8         flex_parser_id_icmpv6_dw1[0x4];
1526         u8         flex_parser_id_icmpv6_dw0[0x4];
1527         u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1528         u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1529
1530         u8         reserved_at_6e0[0x10];
1531         u8         sf_base_id[0x10];
1532
1533         u8         reserved_at_700[0x80];
1534         u8         vhca_tunnel_commands[0x40];
1535         u8         reserved_at_7c0[0x40];
1536 };
1537
1538 enum mlx5_flow_destination_type {
1539         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1540         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1541         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1542
1543         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1544         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1545         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1546 };
1547
1548 enum mlx5_flow_table_miss_action {
1549         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1550         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1551         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1552 };
1553
1554 struct mlx5_ifc_dest_format_struct_bits {
1555         u8         destination_type[0x8];
1556         u8         destination_id[0x18];
1557
1558         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1559         u8         packet_reformat[0x1];
1560         u8         reserved_at_22[0xe];
1561         u8         destination_eswitch_owner_vhca_id[0x10];
1562 };
1563
1564 struct mlx5_ifc_flow_counter_list_bits {
1565         u8         flow_counter_id[0x20];
1566
1567         u8         reserved_at_20[0x20];
1568 };
1569
1570 struct mlx5_ifc_extended_dest_format_bits {
1571         struct mlx5_ifc_dest_format_struct_bits destination_entry;
1572
1573         u8         packet_reformat_id[0x20];
1574
1575         u8         reserved_at_60[0x20];
1576 };
1577
1578 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1579         struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1580         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1581 };
1582
1583 struct mlx5_ifc_fte_match_param_bits {
1584         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1585
1586         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1587
1588         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1589
1590         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1591
1592         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1593
1594         u8         reserved_at_a00[0x600];
1595 };
1596
1597 enum {
1598         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1599         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1600         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1601         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1602         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1603 };
1604
1605 struct mlx5_ifc_rx_hash_field_select_bits {
1606         u8         l3_prot_type[0x1];
1607         u8         l4_prot_type[0x1];
1608         u8         selected_fields[0x1e];
1609 };
1610
1611 enum {
1612         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1613         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1614 };
1615
1616 enum {
1617         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1618         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1619 };
1620
1621 struct mlx5_ifc_wq_bits {
1622         u8         wq_type[0x4];
1623         u8         wq_signature[0x1];
1624         u8         end_padding_mode[0x2];
1625         u8         cd_slave[0x1];
1626         u8         reserved_at_8[0x18];
1627
1628         u8         hds_skip_first_sge[0x1];
1629         u8         log2_hds_buf_size[0x3];
1630         u8         reserved_at_24[0x7];
1631         u8         page_offset[0x5];
1632         u8         lwm[0x10];
1633
1634         u8         reserved_at_40[0x8];
1635         u8         pd[0x18];
1636
1637         u8         reserved_at_60[0x8];
1638         u8         uar_page[0x18];
1639
1640         u8         dbr_addr[0x40];
1641
1642         u8         hw_counter[0x20];
1643
1644         u8         sw_counter[0x20];
1645
1646         u8         reserved_at_100[0xc];
1647         u8         log_wq_stride[0x4];
1648         u8         reserved_at_110[0x3];
1649         u8         log_wq_pg_sz[0x5];
1650         u8         reserved_at_118[0x3];
1651         u8         log_wq_sz[0x5];
1652
1653         u8         dbr_umem_valid[0x1];
1654         u8         wq_umem_valid[0x1];
1655         u8         reserved_at_122[0x1];
1656         u8         log_hairpin_num_packets[0x5];
1657         u8         reserved_at_128[0x3];
1658         u8         log_hairpin_data_sz[0x5];
1659
1660         u8         reserved_at_130[0x4];
1661         u8         log_wqe_num_of_strides[0x4];
1662         u8         two_byte_shift_en[0x1];
1663         u8         reserved_at_139[0x4];
1664         u8         log_wqe_stride_size[0x3];
1665
1666         u8         reserved_at_140[0x4c0];
1667
1668         struct mlx5_ifc_cmd_pas_bits pas[0];
1669 };
1670
1671 struct mlx5_ifc_rq_num_bits {
1672         u8         reserved_at_0[0x8];
1673         u8         rq_num[0x18];
1674 };
1675
1676 struct mlx5_ifc_mac_address_layout_bits {
1677         u8         reserved_at_0[0x10];
1678         u8         mac_addr_47_32[0x10];
1679
1680         u8         mac_addr_31_0[0x20];
1681 };
1682
1683 struct mlx5_ifc_vlan_layout_bits {
1684         u8         reserved_at_0[0x14];
1685         u8         vlan[0x0c];
1686
1687         u8         reserved_at_20[0x20];
1688 };
1689
1690 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1691         u8         reserved_at_0[0xa0];
1692
1693         u8         min_time_between_cnps[0x20];
1694
1695         u8         reserved_at_c0[0x12];
1696         u8         cnp_dscp[0x6];
1697         u8         reserved_at_d8[0x4];
1698         u8         cnp_prio_mode[0x1];
1699         u8         cnp_802p_prio[0x3];
1700
1701         u8         reserved_at_e0[0x720];
1702 };
1703
1704 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1705         u8         reserved_at_0[0x60];
1706
1707         u8         reserved_at_60[0x4];
1708         u8         clamp_tgt_rate[0x1];
1709         u8         reserved_at_65[0x3];
1710         u8         clamp_tgt_rate_after_time_inc[0x1];
1711         u8         reserved_at_69[0x17];
1712
1713         u8         reserved_at_80[0x20];
1714
1715         u8         rpg_time_reset[0x20];
1716
1717         u8         rpg_byte_reset[0x20];
1718
1719         u8         rpg_threshold[0x20];
1720
1721         u8         rpg_max_rate[0x20];
1722
1723         u8         rpg_ai_rate[0x20];
1724
1725         u8         rpg_hai_rate[0x20];
1726
1727         u8         rpg_gd[0x20];
1728
1729         u8         rpg_min_dec_fac[0x20];
1730
1731         u8         rpg_min_rate[0x20];
1732
1733         u8         reserved_at_1c0[0xe0];
1734
1735         u8         rate_to_set_on_first_cnp[0x20];
1736
1737         u8         dce_tcp_g[0x20];
1738
1739         u8         dce_tcp_rtt[0x20];
1740
1741         u8         rate_reduce_monitor_period[0x20];
1742
1743         u8         reserved_at_320[0x20];
1744
1745         u8         initial_alpha_value[0x20];
1746
1747         u8         reserved_at_360[0x4a0];
1748 };
1749
1750 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1751         u8         reserved_at_0[0x80];
1752
1753         u8         rppp_max_rps[0x20];
1754
1755         u8         rpg_time_reset[0x20];
1756
1757         u8         rpg_byte_reset[0x20];
1758
1759         u8         rpg_threshold[0x20];
1760
1761         u8         rpg_max_rate[0x20];
1762
1763         u8         rpg_ai_rate[0x20];
1764
1765         u8         rpg_hai_rate[0x20];
1766
1767         u8         rpg_gd[0x20];
1768
1769         u8         rpg_min_dec_fac[0x20];
1770
1771         u8         rpg_min_rate[0x20];
1772
1773         u8         reserved_at_1c0[0x640];
1774 };
1775
1776 enum {
1777         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1778         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1779         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1780 };
1781
1782 struct mlx5_ifc_resize_field_select_bits {
1783         u8         resize_field_select[0x20];
1784 };
1785
1786 struct mlx5_ifc_resource_dump_bits {
1787         u8         more_dump[0x1];
1788         u8         inline_dump[0x1];
1789         u8         reserved_at_2[0xa];
1790         u8         seq_num[0x4];
1791         u8         segment_type[0x10];
1792
1793         u8         reserved_at_20[0x10];
1794         u8         vhca_id[0x10];
1795
1796         u8         index1[0x20];
1797
1798         u8         index2[0x20];
1799
1800         u8         num_of_obj1[0x10];
1801         u8         num_of_obj2[0x10];
1802
1803         u8         reserved_at_a0[0x20];
1804
1805         u8         device_opaque[0x40];
1806
1807         u8         mkey[0x20];
1808
1809         u8         size[0x20];
1810
1811         u8         address[0x40];
1812
1813         u8         inline_data[52][0x20];
1814 };
1815
1816 struct mlx5_ifc_resource_dump_menu_record_bits {
1817         u8         reserved_at_0[0x4];
1818         u8         num_of_obj2_supports_active[0x1];
1819         u8         num_of_obj2_supports_all[0x1];
1820         u8         must_have_num_of_obj2[0x1];
1821         u8         support_num_of_obj2[0x1];
1822         u8         num_of_obj1_supports_active[0x1];
1823         u8         num_of_obj1_supports_all[0x1];
1824         u8         must_have_num_of_obj1[0x1];
1825         u8         support_num_of_obj1[0x1];
1826         u8         must_have_index2[0x1];
1827         u8         support_index2[0x1];
1828         u8         must_have_index1[0x1];
1829         u8         support_index1[0x1];
1830         u8         segment_type[0x10];
1831
1832         u8         segment_name[4][0x20];
1833
1834         u8         index1_name[4][0x20];
1835
1836         u8         index2_name[4][0x20];
1837 };
1838
1839 struct mlx5_ifc_resource_dump_segment_header_bits {
1840         u8         length_dw[0x10];
1841         u8         segment_type[0x10];
1842 };
1843
1844 struct mlx5_ifc_resource_dump_command_segment_bits {
1845         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1846
1847         u8         segment_called[0x10];
1848         u8         vhca_id[0x10];
1849
1850         u8         index1[0x20];
1851
1852         u8         index2[0x20];
1853
1854         u8         num_of_obj1[0x10];
1855         u8         num_of_obj2[0x10];
1856 };
1857
1858 struct mlx5_ifc_resource_dump_error_segment_bits {
1859         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1860
1861         u8         reserved_at_20[0x10];
1862         u8         syndrome_id[0x10];
1863
1864         u8         reserved_at_40[0x40];
1865
1866         u8         error[8][0x20];
1867 };
1868
1869 struct mlx5_ifc_resource_dump_info_segment_bits {
1870         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1871
1872         u8         reserved_at_20[0x18];
1873         u8         dump_version[0x8];
1874
1875         u8         hw_version[0x20];
1876
1877         u8         fw_version[0x20];
1878 };
1879
1880 struct mlx5_ifc_resource_dump_menu_segment_bits {
1881         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1882
1883         u8         reserved_at_20[0x10];
1884         u8         num_of_records[0x10];
1885
1886         struct mlx5_ifc_resource_dump_menu_record_bits record[0];
1887 };
1888
1889 struct mlx5_ifc_resource_dump_resource_segment_bits {
1890         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1891
1892         u8         reserved_at_20[0x20];
1893
1894         u8         index1[0x20];
1895
1896         u8         index2[0x20];
1897
1898         u8         payload[0][0x20];
1899 };
1900
1901 struct mlx5_ifc_resource_dump_terminate_segment_bits {
1902         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1903 };
1904
1905 struct mlx5_ifc_menu_resource_dump_response_bits {
1906         struct mlx5_ifc_resource_dump_info_segment_bits info;
1907         struct mlx5_ifc_resource_dump_command_segment_bits cmd;
1908         struct mlx5_ifc_resource_dump_menu_segment_bits menu;
1909         struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
1910 };
1911
1912 enum {
1913         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1914         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1915         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1916         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1917 };
1918
1919 struct mlx5_ifc_modify_field_select_bits {
1920         u8         modify_field_select[0x20];
1921 };
1922
1923 struct mlx5_ifc_field_select_r_roce_np_bits {
1924         u8         field_select_r_roce_np[0x20];
1925 };
1926
1927 struct mlx5_ifc_field_select_r_roce_rp_bits {
1928         u8         field_select_r_roce_rp[0x20];
1929 };
1930
1931 enum {
1932         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1933         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1934         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1935         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1936         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1937         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1938         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1939         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1940         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1941         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1942 };
1943
1944 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1945         u8         field_select_8021qaurp[0x20];
1946 };
1947
1948 struct mlx5_ifc_phys_layer_cntrs_bits {
1949         u8         time_since_last_clear_high[0x20];
1950
1951         u8         time_since_last_clear_low[0x20];
1952
1953         u8         symbol_errors_high[0x20];
1954
1955         u8         symbol_errors_low[0x20];
1956
1957         u8         sync_headers_errors_high[0x20];
1958
1959         u8         sync_headers_errors_low[0x20];
1960
1961         u8         edpl_bip_errors_lane0_high[0x20];
1962
1963         u8         edpl_bip_errors_lane0_low[0x20];
1964
1965         u8         edpl_bip_errors_lane1_high[0x20];
1966
1967         u8         edpl_bip_errors_lane1_low[0x20];
1968
1969         u8         edpl_bip_errors_lane2_high[0x20];
1970
1971         u8         edpl_bip_errors_lane2_low[0x20];
1972
1973         u8         edpl_bip_errors_lane3_high[0x20];
1974
1975         u8         edpl_bip_errors_lane3_low[0x20];
1976
1977         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1978
1979         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1980
1981         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1982
1983         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1984
1985         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1986
1987         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1988
1989         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1990
1991         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1992
1993         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1994
1995         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1996
1997         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1998
1999         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2000
2001         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2002
2003         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2004
2005         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2006
2007         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2008
2009         u8         rs_fec_corrected_blocks_high[0x20];
2010
2011         u8         rs_fec_corrected_blocks_low[0x20];
2012
2013         u8         rs_fec_uncorrectable_blocks_high[0x20];
2014
2015         u8         rs_fec_uncorrectable_blocks_low[0x20];
2016
2017         u8         rs_fec_no_errors_blocks_high[0x20];
2018
2019         u8         rs_fec_no_errors_blocks_low[0x20];
2020
2021         u8         rs_fec_single_error_blocks_high[0x20];
2022
2023         u8         rs_fec_single_error_blocks_low[0x20];
2024
2025         u8         rs_fec_corrected_symbols_total_high[0x20];
2026
2027         u8         rs_fec_corrected_symbols_total_low[0x20];
2028
2029         u8         rs_fec_corrected_symbols_lane0_high[0x20];
2030
2031         u8         rs_fec_corrected_symbols_lane0_low[0x20];
2032
2033         u8         rs_fec_corrected_symbols_lane1_high[0x20];
2034
2035         u8         rs_fec_corrected_symbols_lane1_low[0x20];
2036
2037         u8         rs_fec_corrected_symbols_lane2_high[0x20];
2038
2039         u8         rs_fec_corrected_symbols_lane2_low[0x20];
2040
2041         u8         rs_fec_corrected_symbols_lane3_high[0x20];
2042
2043         u8         rs_fec_corrected_symbols_lane3_low[0x20];
2044
2045         u8         link_down_events[0x20];
2046
2047         u8         successful_recovery_events[0x20];
2048
2049         u8         reserved_at_640[0x180];
2050 };
2051
2052 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2053         u8         time_since_last_clear_high[0x20];
2054
2055         u8         time_since_last_clear_low[0x20];
2056
2057         u8         phy_received_bits_high[0x20];
2058
2059         u8         phy_received_bits_low[0x20];
2060
2061         u8         phy_symbol_errors_high[0x20];
2062
2063         u8         phy_symbol_errors_low[0x20];
2064
2065         u8         phy_corrected_bits_high[0x20];
2066
2067         u8         phy_corrected_bits_low[0x20];
2068
2069         u8         phy_corrected_bits_lane0_high[0x20];
2070
2071         u8         phy_corrected_bits_lane0_low[0x20];
2072
2073         u8         phy_corrected_bits_lane1_high[0x20];
2074
2075         u8         phy_corrected_bits_lane1_low[0x20];
2076
2077         u8         phy_corrected_bits_lane2_high[0x20];
2078
2079         u8         phy_corrected_bits_lane2_low[0x20];
2080
2081         u8         phy_corrected_bits_lane3_high[0x20];
2082
2083         u8         phy_corrected_bits_lane3_low[0x20];
2084
2085         u8         reserved_at_200[0x5c0];
2086 };
2087
2088 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2089         u8         symbol_error_counter[0x10];
2090
2091         u8         link_error_recovery_counter[0x8];
2092
2093         u8         link_downed_counter[0x8];
2094
2095         u8         port_rcv_errors[0x10];
2096
2097         u8         port_rcv_remote_physical_errors[0x10];
2098
2099         u8         port_rcv_switch_relay_errors[0x10];
2100
2101         u8         port_xmit_discards[0x10];
2102
2103         u8         port_xmit_constraint_errors[0x8];
2104
2105         u8         port_rcv_constraint_errors[0x8];
2106
2107         u8         reserved_at_70[0x8];
2108
2109         u8         link_overrun_errors[0x8];
2110
2111         u8         reserved_at_80[0x10];
2112
2113         u8         vl_15_dropped[0x10];
2114
2115         u8         reserved_at_a0[0x80];
2116
2117         u8         port_xmit_wait[0x20];
2118 };
2119
2120 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2121         u8         transmit_queue_high[0x20];
2122
2123         u8         transmit_queue_low[0x20];
2124
2125         u8         no_buffer_discard_uc_high[0x20];
2126
2127         u8         no_buffer_discard_uc_low[0x20];
2128
2129         u8         reserved_at_80[0x740];
2130 };
2131
2132 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2133         u8         wred_discard_high[0x20];
2134
2135         u8         wred_discard_low[0x20];
2136
2137         u8         ecn_marked_tc_high[0x20];
2138
2139         u8         ecn_marked_tc_low[0x20];
2140
2141         u8         reserved_at_80[0x740];
2142 };
2143
2144 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2145         u8         rx_octets_high[0x20];
2146
2147         u8         rx_octets_low[0x20];
2148
2149         u8         reserved_at_40[0xc0];
2150
2151         u8         rx_frames_high[0x20];
2152
2153         u8         rx_frames_low[0x20];
2154
2155         u8         tx_octets_high[0x20];
2156
2157         u8         tx_octets_low[0x20];
2158
2159         u8         reserved_at_180[0xc0];
2160
2161         u8         tx_frames_high[0x20];
2162
2163         u8         tx_frames_low[0x20];
2164
2165         u8         rx_pause_high[0x20];
2166
2167         u8         rx_pause_low[0x20];
2168
2169         u8         rx_pause_duration_high[0x20];
2170
2171         u8         rx_pause_duration_low[0x20];
2172
2173         u8         tx_pause_high[0x20];
2174
2175         u8         tx_pause_low[0x20];
2176
2177         u8         tx_pause_duration_high[0x20];
2178
2179         u8         tx_pause_duration_low[0x20];
2180
2181         u8         rx_pause_transition_high[0x20];
2182
2183         u8         rx_pause_transition_low[0x20];
2184
2185         u8         rx_discards_high[0x20];
2186
2187         u8         rx_discards_low[0x20];
2188
2189         u8         device_stall_minor_watermark_cnt_high[0x20];
2190
2191         u8         device_stall_minor_watermark_cnt_low[0x20];
2192
2193         u8         device_stall_critical_watermark_cnt_high[0x20];
2194
2195         u8         device_stall_critical_watermark_cnt_low[0x20];
2196
2197         u8         reserved_at_480[0x340];
2198 };
2199
2200 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2201         u8         port_transmit_wait_high[0x20];
2202
2203         u8         port_transmit_wait_low[0x20];
2204
2205         u8         reserved_at_40[0x100];
2206
2207         u8         rx_buffer_almost_full_high[0x20];
2208
2209         u8         rx_buffer_almost_full_low[0x20];
2210
2211         u8         rx_buffer_full_high[0x20];
2212
2213         u8         rx_buffer_full_low[0x20];
2214
2215         u8         rx_icrc_encapsulated_high[0x20];
2216
2217         u8         rx_icrc_encapsulated_low[0x20];
2218
2219         u8         reserved_at_200[0x5c0];
2220 };
2221
2222 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2223         u8         dot3stats_alignment_errors_high[0x20];
2224
2225         u8         dot3stats_alignment_errors_low[0x20];
2226
2227         u8         dot3stats_fcs_errors_high[0x20];
2228
2229         u8         dot3stats_fcs_errors_low[0x20];
2230
2231         u8         dot3stats_single_collision_frames_high[0x20];
2232
2233         u8         dot3stats_single_collision_frames_low[0x20];
2234
2235         u8         dot3stats_multiple_collision_frames_high[0x20];
2236
2237         u8         dot3stats_multiple_collision_frames_low[0x20];
2238
2239         u8         dot3stats_sqe_test_errors_high[0x20];
2240
2241         u8         dot3stats_sqe_test_errors_low[0x20];
2242
2243         u8         dot3stats_deferred_transmissions_high[0x20];
2244
2245         u8         dot3stats_deferred_transmissions_low[0x20];
2246
2247         u8         dot3stats_late_collisions_high[0x20];
2248
2249         u8         dot3stats_late_collisions_low[0x20];
2250
2251         u8         dot3stats_excessive_collisions_high[0x20];
2252
2253         u8         dot3stats_excessive_collisions_low[0x20];
2254
2255         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2256
2257         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2258
2259         u8         dot3stats_carrier_sense_errors_high[0x20];
2260
2261         u8         dot3stats_carrier_sense_errors_low[0x20];
2262
2263         u8         dot3stats_frame_too_longs_high[0x20];
2264
2265         u8         dot3stats_frame_too_longs_low[0x20];
2266
2267         u8         dot3stats_internal_mac_receive_errors_high[0x20];
2268
2269         u8         dot3stats_internal_mac_receive_errors_low[0x20];
2270
2271         u8         dot3stats_symbol_errors_high[0x20];
2272
2273         u8         dot3stats_symbol_errors_low[0x20];
2274
2275         u8         dot3control_in_unknown_opcodes_high[0x20];
2276
2277         u8         dot3control_in_unknown_opcodes_low[0x20];
2278
2279         u8         dot3in_pause_frames_high[0x20];
2280
2281         u8         dot3in_pause_frames_low[0x20];
2282
2283         u8         dot3out_pause_frames_high[0x20];
2284
2285         u8         dot3out_pause_frames_low[0x20];
2286
2287         u8         reserved_at_400[0x3c0];
2288 };
2289
2290 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2291         u8         ether_stats_drop_events_high[0x20];
2292
2293         u8         ether_stats_drop_events_low[0x20];
2294
2295         u8         ether_stats_octets_high[0x20];
2296
2297         u8         ether_stats_octets_low[0x20];
2298
2299         u8         ether_stats_pkts_high[0x20];
2300
2301         u8         ether_stats_pkts_low[0x20];
2302
2303         u8         ether_stats_broadcast_pkts_high[0x20];
2304
2305         u8         ether_stats_broadcast_pkts_low[0x20];
2306
2307         u8         ether_stats_multicast_pkts_high[0x20];
2308
2309         u8         ether_stats_multicast_pkts_low[0x20];
2310
2311         u8         ether_stats_crc_align_errors_high[0x20];
2312
2313         u8         ether_stats_crc_align_errors_low[0x20];
2314
2315         u8         ether_stats_undersize_pkts_high[0x20];
2316
2317         u8         ether_stats_undersize_pkts_low[0x20];
2318
2319         u8         ether_stats_oversize_pkts_high[0x20];
2320
2321         u8         ether_stats_oversize_pkts_low[0x20];
2322
2323         u8         ether_stats_fragments_high[0x20];
2324
2325         u8         ether_stats_fragments_low[0x20];
2326
2327         u8         ether_stats_jabbers_high[0x20];
2328
2329         u8         ether_stats_jabbers_low[0x20];
2330
2331         u8         ether_stats_collisions_high[0x20];
2332
2333         u8         ether_stats_collisions_low[0x20];
2334
2335         u8         ether_stats_pkts64octets_high[0x20];
2336
2337         u8         ether_stats_pkts64octets_low[0x20];
2338
2339         u8         ether_stats_pkts65to127octets_high[0x20];
2340
2341         u8         ether_stats_pkts65to127octets_low[0x20];
2342
2343         u8         ether_stats_pkts128to255octets_high[0x20];
2344
2345         u8         ether_stats_pkts128to255octets_low[0x20];
2346
2347         u8         ether_stats_pkts256to511octets_high[0x20];
2348
2349         u8         ether_stats_pkts256to511octets_low[0x20];
2350
2351         u8         ether_stats_pkts512to1023octets_high[0x20];
2352
2353         u8         ether_stats_pkts512to1023octets_low[0x20];
2354
2355         u8         ether_stats_pkts1024to1518octets_high[0x20];
2356
2357         u8         ether_stats_pkts1024to1518octets_low[0x20];
2358
2359         u8         ether_stats_pkts1519to2047octets_high[0x20];
2360
2361         u8         ether_stats_pkts1519to2047octets_low[0x20];
2362
2363         u8         ether_stats_pkts2048to4095octets_high[0x20];
2364
2365         u8         ether_stats_pkts2048to4095octets_low[0x20];
2366
2367         u8         ether_stats_pkts4096to8191octets_high[0x20];
2368
2369         u8         ether_stats_pkts4096to8191octets_low[0x20];
2370
2371         u8         ether_stats_pkts8192to10239octets_high[0x20];
2372
2373         u8         ether_stats_pkts8192to10239octets_low[0x20];
2374
2375         u8         reserved_at_540[0x280];
2376 };
2377
2378 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2379         u8         if_in_octets_high[0x20];
2380
2381         u8         if_in_octets_low[0x20];
2382
2383         u8         if_in_ucast_pkts_high[0x20];
2384
2385         u8         if_in_ucast_pkts_low[0x20];
2386
2387         u8         if_in_discards_high[0x20];
2388
2389         u8         if_in_discards_low[0x20];
2390
2391         u8         if_in_errors_high[0x20];
2392
2393         u8         if_in_errors_low[0x20];
2394
2395         u8         if_in_unknown_protos_high[0x20];
2396
2397         u8         if_in_unknown_protos_low[0x20];
2398
2399         u8         if_out_octets_high[0x20];
2400
2401         u8         if_out_octets_low[0x20];
2402
2403         u8         if_out_ucast_pkts_high[0x20];
2404
2405         u8         if_out_ucast_pkts_low[0x20];
2406
2407         u8         if_out_discards_high[0x20];
2408
2409         u8         if_out_discards_low[0x20];
2410
2411         u8         if_out_errors_high[0x20];
2412
2413         u8         if_out_errors_low[0x20];
2414
2415         u8         if_in_multicast_pkts_high[0x20];
2416
2417         u8         if_in_multicast_pkts_low[0x20];
2418
2419         u8         if_in_broadcast_pkts_high[0x20];
2420
2421         u8         if_in_broadcast_pkts_low[0x20];
2422
2423         u8         if_out_multicast_pkts_high[0x20];
2424
2425         u8         if_out_multicast_pkts_low[0x20];
2426
2427         u8         if_out_broadcast_pkts_high[0x20];
2428
2429         u8         if_out_broadcast_pkts_low[0x20];
2430
2431         u8         reserved_at_340[0x480];
2432 };
2433
2434 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2435         u8         a_frames_transmitted_ok_high[0x20];
2436
2437         u8         a_frames_transmitted_ok_low[0x20];
2438
2439         u8         a_frames_received_ok_high[0x20];
2440
2441         u8         a_frames_received_ok_low[0x20];
2442
2443         u8         a_frame_check_sequence_errors_high[0x20];
2444
2445         u8         a_frame_check_sequence_errors_low[0x20];
2446
2447         u8         a_alignment_errors_high[0x20];
2448
2449         u8         a_alignment_errors_low[0x20];
2450
2451         u8         a_octets_transmitted_ok_high[0x20];
2452
2453         u8         a_octets_transmitted_ok_low[0x20];
2454
2455         u8         a_octets_received_ok_high[0x20];
2456
2457         u8         a_octets_received_ok_low[0x20];
2458
2459         u8         a_multicast_frames_xmitted_ok_high[0x20];
2460
2461         u8         a_multicast_frames_xmitted_ok_low[0x20];
2462
2463         u8         a_broadcast_frames_xmitted_ok_high[0x20];
2464
2465         u8         a_broadcast_frames_xmitted_ok_low[0x20];
2466
2467         u8         a_multicast_frames_received_ok_high[0x20];
2468
2469         u8         a_multicast_frames_received_ok_low[0x20];
2470
2471         u8         a_broadcast_frames_received_ok_high[0x20];
2472
2473         u8         a_broadcast_frames_received_ok_low[0x20];
2474
2475         u8         a_in_range_length_errors_high[0x20];
2476
2477         u8         a_in_range_length_errors_low[0x20];
2478
2479         u8         a_out_of_range_length_field_high[0x20];
2480
2481         u8         a_out_of_range_length_field_low[0x20];
2482
2483         u8         a_frame_too_long_errors_high[0x20];
2484
2485         u8         a_frame_too_long_errors_low[0x20];
2486
2487         u8         a_symbol_error_during_carrier_high[0x20];
2488
2489         u8         a_symbol_error_during_carrier_low[0x20];
2490
2491         u8         a_mac_control_frames_transmitted_high[0x20];
2492
2493         u8         a_mac_control_frames_transmitted_low[0x20];
2494
2495         u8         a_mac_control_frames_received_high[0x20];
2496
2497         u8         a_mac_control_frames_received_low[0x20];
2498
2499         u8         a_unsupported_opcodes_received_high[0x20];
2500
2501         u8         a_unsupported_opcodes_received_low[0x20];
2502
2503         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2504
2505         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2506
2507         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2508
2509         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2510
2511         u8         reserved_at_4c0[0x300];
2512 };
2513
2514 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2515         u8         life_time_counter_high[0x20];
2516
2517         u8         life_time_counter_low[0x20];
2518
2519         u8         rx_errors[0x20];
2520
2521         u8         tx_errors[0x20];
2522
2523         u8         l0_to_recovery_eieos[0x20];
2524
2525         u8         l0_to_recovery_ts[0x20];
2526
2527         u8         l0_to_recovery_framing[0x20];
2528
2529         u8         l0_to_recovery_retrain[0x20];
2530
2531         u8         crc_error_dllp[0x20];
2532
2533         u8         crc_error_tlp[0x20];
2534
2535         u8         tx_overflow_buffer_pkt_high[0x20];
2536
2537         u8         tx_overflow_buffer_pkt_low[0x20];
2538
2539         u8         outbound_stalled_reads[0x20];
2540
2541         u8         outbound_stalled_writes[0x20];
2542
2543         u8         outbound_stalled_reads_events[0x20];
2544
2545         u8         outbound_stalled_writes_events[0x20];
2546
2547         u8         reserved_at_200[0x5c0];
2548 };
2549
2550 struct mlx5_ifc_cmd_inter_comp_event_bits {
2551         u8         command_completion_vector[0x20];
2552
2553         u8         reserved_at_20[0xc0];
2554 };
2555
2556 struct mlx5_ifc_stall_vl_event_bits {
2557         u8         reserved_at_0[0x18];
2558         u8         port_num[0x1];
2559         u8         reserved_at_19[0x3];
2560         u8         vl[0x4];
2561
2562         u8         reserved_at_20[0xa0];
2563 };
2564
2565 struct mlx5_ifc_db_bf_congestion_event_bits {
2566         u8         event_subtype[0x8];
2567         u8         reserved_at_8[0x8];
2568         u8         congestion_level[0x8];
2569         u8         reserved_at_18[0x8];
2570
2571         u8         reserved_at_20[0xa0];
2572 };
2573
2574 struct mlx5_ifc_gpio_event_bits {
2575         u8         reserved_at_0[0x60];
2576
2577         u8         gpio_event_hi[0x20];
2578
2579         u8         gpio_event_lo[0x20];
2580
2581         u8         reserved_at_a0[0x40];
2582 };
2583
2584 struct mlx5_ifc_port_state_change_event_bits {
2585         u8         reserved_at_0[0x40];
2586
2587         u8         port_num[0x4];
2588         u8         reserved_at_44[0x1c];
2589
2590         u8         reserved_at_60[0x80];
2591 };
2592
2593 struct mlx5_ifc_dropped_packet_logged_bits {
2594         u8         reserved_at_0[0xe0];
2595 };
2596
2597 enum {
2598         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2599         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2600 };
2601
2602 struct mlx5_ifc_cq_error_bits {
2603         u8         reserved_at_0[0x8];
2604         u8         cqn[0x18];
2605
2606         u8         reserved_at_20[0x20];
2607
2608         u8         reserved_at_40[0x18];
2609         u8         syndrome[0x8];
2610
2611         u8         reserved_at_60[0x80];
2612 };
2613
2614 struct mlx5_ifc_rdma_page_fault_event_bits {
2615         u8         bytes_committed[0x20];
2616
2617         u8         r_key[0x20];
2618
2619         u8         reserved_at_40[0x10];
2620         u8         packet_len[0x10];
2621
2622         u8         rdma_op_len[0x20];
2623
2624         u8         rdma_va[0x40];
2625
2626         u8         reserved_at_c0[0x5];
2627         u8         rdma[0x1];
2628         u8         write[0x1];
2629         u8         requestor[0x1];
2630         u8         qp_number[0x18];
2631 };
2632
2633 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2634         u8         bytes_committed[0x20];
2635
2636         u8         reserved_at_20[0x10];
2637         u8         wqe_index[0x10];
2638
2639         u8         reserved_at_40[0x10];
2640         u8         len[0x10];
2641
2642         u8         reserved_at_60[0x60];
2643
2644         u8         reserved_at_c0[0x5];
2645         u8         rdma[0x1];
2646         u8         write_read[0x1];
2647         u8         requestor[0x1];
2648         u8         qpn[0x18];
2649 };
2650
2651 struct mlx5_ifc_qp_events_bits {
2652         u8         reserved_at_0[0xa0];
2653
2654         u8         type[0x8];
2655         u8         reserved_at_a8[0x18];
2656
2657         u8         reserved_at_c0[0x8];
2658         u8         qpn_rqn_sqn[0x18];
2659 };
2660
2661 struct mlx5_ifc_dct_events_bits {
2662         u8         reserved_at_0[0xc0];
2663
2664         u8         reserved_at_c0[0x8];
2665         u8         dct_number[0x18];
2666 };
2667
2668 struct mlx5_ifc_comp_event_bits {
2669         u8         reserved_at_0[0xc0];
2670
2671         u8         reserved_at_c0[0x8];
2672         u8         cq_number[0x18];
2673 };
2674
2675 enum {
2676         MLX5_QPC_STATE_RST        = 0x0,
2677         MLX5_QPC_STATE_INIT       = 0x1,
2678         MLX5_QPC_STATE_RTR        = 0x2,
2679         MLX5_QPC_STATE_RTS        = 0x3,
2680         MLX5_QPC_STATE_SQER       = 0x4,
2681         MLX5_QPC_STATE_ERR        = 0x6,
2682         MLX5_QPC_STATE_SQD        = 0x7,
2683         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2684 };
2685
2686 enum {
2687         MLX5_QPC_ST_RC            = 0x0,
2688         MLX5_QPC_ST_UC            = 0x1,
2689         MLX5_QPC_ST_UD            = 0x2,
2690         MLX5_QPC_ST_XRC           = 0x3,
2691         MLX5_QPC_ST_DCI           = 0x5,
2692         MLX5_QPC_ST_QP0           = 0x7,
2693         MLX5_QPC_ST_QP1           = 0x8,
2694         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2695         MLX5_QPC_ST_REG_UMR       = 0xc,
2696 };
2697
2698 enum {
2699         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2700         MLX5_QPC_PM_STATE_REARM     = 0x1,
2701         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2702         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2703 };
2704
2705 enum {
2706         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2707 };
2708
2709 enum {
2710         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2711         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2712 };
2713
2714 enum {
2715         MLX5_QPC_MTU_256_BYTES        = 0x1,
2716         MLX5_QPC_MTU_512_BYTES        = 0x2,
2717         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2718         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2719         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2720         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2721 };
2722
2723 enum {
2724         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2725         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2726         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2727         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2728         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2729         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2730         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2731         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2732 };
2733
2734 enum {
2735         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2736         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2737         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2738 };
2739
2740 enum {
2741         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2742         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2743         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2744 };
2745
2746 struct mlx5_ifc_qpc_bits {
2747         u8         state[0x4];
2748         u8         lag_tx_port_affinity[0x4];
2749         u8         st[0x8];
2750         u8         reserved_at_10[0x3];
2751         u8         pm_state[0x2];
2752         u8         reserved_at_15[0x1];
2753         u8         req_e2e_credit_mode[0x2];
2754         u8         offload_type[0x4];
2755         u8         end_padding_mode[0x2];
2756         u8         reserved_at_1e[0x2];
2757
2758         u8         wq_signature[0x1];
2759         u8         block_lb_mc[0x1];
2760         u8         atomic_like_write_en[0x1];
2761         u8         latency_sensitive[0x1];
2762         u8         reserved_at_24[0x1];
2763         u8         drain_sigerr[0x1];
2764         u8         reserved_at_26[0x2];
2765         u8         pd[0x18];
2766
2767         u8         mtu[0x3];
2768         u8         log_msg_max[0x5];
2769         u8         reserved_at_48[0x1];
2770         u8         log_rq_size[0x4];
2771         u8         log_rq_stride[0x3];
2772         u8         no_sq[0x1];
2773         u8         log_sq_size[0x4];
2774         u8         reserved_at_55[0x6];
2775         u8         rlky[0x1];
2776         u8         ulp_stateless_offload_mode[0x4];
2777
2778         u8         counter_set_id[0x8];
2779         u8         uar_page[0x18];
2780
2781         u8         reserved_at_80[0x8];
2782         u8         user_index[0x18];
2783
2784         u8         reserved_at_a0[0x3];
2785         u8         log_page_size[0x5];
2786         u8         remote_qpn[0x18];
2787
2788         struct mlx5_ifc_ads_bits primary_address_path;
2789
2790         struct mlx5_ifc_ads_bits secondary_address_path;
2791
2792         u8         log_ack_req_freq[0x4];
2793         u8         reserved_at_384[0x4];
2794         u8         log_sra_max[0x3];
2795         u8         reserved_at_38b[0x2];
2796         u8         retry_count[0x3];
2797         u8         rnr_retry[0x3];
2798         u8         reserved_at_393[0x1];
2799         u8         fre[0x1];
2800         u8         cur_rnr_retry[0x3];
2801         u8         cur_retry_count[0x3];
2802         u8         reserved_at_39b[0x5];
2803
2804         u8         reserved_at_3a0[0x20];
2805
2806         u8         reserved_at_3c0[0x8];
2807         u8         next_send_psn[0x18];
2808
2809         u8         reserved_at_3e0[0x8];
2810         u8         cqn_snd[0x18];
2811
2812         u8         reserved_at_400[0x8];
2813         u8         deth_sqpn[0x18];
2814
2815         u8         reserved_at_420[0x20];
2816
2817         u8         reserved_at_440[0x8];
2818         u8         last_acked_psn[0x18];
2819
2820         u8         reserved_at_460[0x8];
2821         u8         ssn[0x18];
2822
2823         u8         reserved_at_480[0x8];
2824         u8         log_rra_max[0x3];
2825         u8         reserved_at_48b[0x1];
2826         u8         atomic_mode[0x4];
2827         u8         rre[0x1];
2828         u8         rwe[0x1];
2829         u8         rae[0x1];
2830         u8         reserved_at_493[0x1];
2831         u8         page_offset[0x6];
2832         u8         reserved_at_49a[0x3];
2833         u8         cd_slave_receive[0x1];
2834         u8         cd_slave_send[0x1];
2835         u8         cd_master[0x1];
2836
2837         u8         reserved_at_4a0[0x3];
2838         u8         min_rnr_nak[0x5];
2839         u8         next_rcv_psn[0x18];
2840
2841         u8         reserved_at_4c0[0x8];
2842         u8         xrcd[0x18];
2843
2844         u8         reserved_at_4e0[0x8];
2845         u8         cqn_rcv[0x18];
2846
2847         u8         dbr_addr[0x40];
2848
2849         u8         q_key[0x20];
2850
2851         u8         reserved_at_560[0x5];
2852         u8         rq_type[0x3];
2853         u8         srqn_rmpn_xrqn[0x18];
2854
2855         u8         reserved_at_580[0x8];
2856         u8         rmsn[0x18];
2857
2858         u8         hw_sq_wqebb_counter[0x10];
2859         u8         sw_sq_wqebb_counter[0x10];
2860
2861         u8         hw_rq_counter[0x20];
2862
2863         u8         sw_rq_counter[0x20];
2864
2865         u8         reserved_at_600[0x20];
2866
2867         u8         reserved_at_620[0xf];
2868         u8         cgs[0x1];
2869         u8         cs_req[0x8];
2870         u8         cs_res[0x8];
2871
2872         u8         dc_access_key[0x40];
2873
2874         u8         reserved_at_680[0x3];
2875         u8         dbr_umem_valid[0x1];
2876
2877         u8         reserved_at_684[0xbc];
2878 };
2879
2880 struct mlx5_ifc_roce_addr_layout_bits {
2881         u8         source_l3_address[16][0x8];
2882
2883         u8         reserved_at_80[0x3];
2884         u8         vlan_valid[0x1];
2885         u8         vlan_id[0xc];
2886         u8         source_mac_47_32[0x10];
2887
2888         u8         source_mac_31_0[0x20];
2889
2890         u8         reserved_at_c0[0x14];
2891         u8         roce_l3_type[0x4];
2892         u8         roce_version[0x8];
2893
2894         u8         reserved_at_e0[0x20];
2895 };
2896
2897 union mlx5_ifc_hca_cap_union_bits {
2898         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2899         struct mlx5_ifc_odp_cap_bits odp_cap;
2900         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2901         struct mlx5_ifc_roce_cap_bits roce_cap;
2902         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2903         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2904         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2905         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2906         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2907         struct mlx5_ifc_qos_cap_bits qos_cap;
2908         struct mlx5_ifc_debug_cap_bits debug_cap;
2909         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2910         struct mlx5_ifc_tls_cap_bits tls_cap;
2911         struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
2912         struct mlx5_ifc_device_virtio_emulation_cap_bits virtio_emulation_cap;
2913         u8         reserved_at_0[0x8000];
2914 };
2915
2916 enum {
2917         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2918         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2919         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2920         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2921         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2922         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2923         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2924         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2925         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2926         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
2927         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2928 };
2929
2930 enum {
2931         MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
2932         MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
2933         MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
2934 };
2935
2936 struct mlx5_ifc_vlan_bits {
2937         u8         ethtype[0x10];
2938         u8         prio[0x3];
2939         u8         cfi[0x1];
2940         u8         vid[0xc];
2941 };
2942
2943 struct mlx5_ifc_flow_context_bits {
2944         struct mlx5_ifc_vlan_bits push_vlan;
2945
2946         u8         group_id[0x20];
2947
2948         u8         reserved_at_40[0x8];
2949         u8         flow_tag[0x18];
2950
2951         u8         reserved_at_60[0x10];
2952         u8         action[0x10];
2953
2954         u8         extended_destination[0x1];
2955         u8         reserved_at_81[0x1];
2956         u8         flow_source[0x2];
2957         u8         reserved_at_84[0x4];
2958         u8         destination_list_size[0x18];
2959
2960         u8         reserved_at_a0[0x8];
2961         u8         flow_counter_list_size[0x18];
2962
2963         u8         packet_reformat_id[0x20];
2964
2965         u8         modify_header_id[0x20];
2966
2967         struct mlx5_ifc_vlan_bits push_vlan_2;
2968
2969         u8         reserved_at_120[0xe0];
2970
2971         struct mlx5_ifc_fte_match_param_bits match_value;
2972
2973         u8         reserved_at_1200[0x600];
2974
2975         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2976 };
2977
2978 enum {
2979         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2980         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2981 };
2982
2983 struct mlx5_ifc_xrc_srqc_bits {
2984         u8         state[0x4];
2985         u8         log_xrc_srq_size[0x4];
2986         u8         reserved_at_8[0x18];
2987
2988         u8         wq_signature[0x1];
2989         u8         cont_srq[0x1];
2990         u8         reserved_at_22[0x1];
2991         u8         rlky[0x1];
2992         u8         basic_cyclic_rcv_wqe[0x1];
2993         u8         log_rq_stride[0x3];
2994         u8         xrcd[0x18];
2995
2996         u8         page_offset[0x6];
2997         u8         reserved_at_46[0x1];
2998         u8         dbr_umem_valid[0x1];
2999         u8         cqn[0x18];
3000
3001         u8         reserved_at_60[0x20];
3002
3003         u8         user_index_equal_xrc_srqn[0x1];
3004         u8         reserved_at_81[0x1];
3005         u8         log_page_size[0x6];
3006         u8         user_index[0x18];
3007
3008         u8         reserved_at_a0[0x20];
3009
3010         u8         reserved_at_c0[0x8];
3011         u8         pd[0x18];
3012
3013         u8         lwm[0x10];
3014         u8         wqe_cnt[0x10];
3015
3016         u8         reserved_at_100[0x40];
3017
3018         u8         db_record_addr_h[0x20];
3019
3020         u8         db_record_addr_l[0x1e];
3021         u8         reserved_at_17e[0x2];
3022
3023         u8         reserved_at_180[0x80];
3024 };
3025
3026 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3027         u8         counter_error_queues[0x20];
3028
3029         u8         total_error_queues[0x20];
3030
3031         u8         send_queue_priority_update_flow[0x20];
3032
3033         u8         reserved_at_60[0x20];
3034
3035         u8         nic_receive_steering_discard[0x40];
3036
3037         u8         receive_discard_vport_down[0x40];
3038
3039         u8         transmit_discard_vport_down[0x40];
3040
3041         u8         reserved_at_140[0xa0];
3042
3043         u8         internal_rq_out_of_buffer[0x20];
3044
3045         u8         reserved_at_200[0xe00];
3046 };
3047
3048 struct mlx5_ifc_traffic_counter_bits {
3049         u8         packets[0x40];
3050
3051         u8         octets[0x40];
3052 };
3053
3054 struct mlx5_ifc_tisc_bits {
3055         u8         strict_lag_tx_port_affinity[0x1];
3056         u8         tls_en[0x1];
3057         u8         reserved_at_2[0x2];
3058         u8         lag_tx_port_affinity[0x04];
3059
3060         u8         reserved_at_8[0x4];
3061         u8         prio[0x4];
3062         u8         reserved_at_10[0x10];
3063
3064         u8         reserved_at_20[0x100];
3065
3066         u8         reserved_at_120[0x8];
3067         u8         transport_domain[0x18];
3068
3069         u8         reserved_at_140[0x8];
3070         u8         underlay_qpn[0x18];
3071
3072         u8         reserved_at_160[0x8];
3073         u8         pd[0x18];
3074
3075         u8         reserved_at_180[0x380];
3076 };
3077
3078 enum {
3079         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3080         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3081 };
3082
3083 enum {
3084         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
3085         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
3086 };
3087
3088 enum {
3089         MLX5_RX_HASH_FN_NONE           = 0x0,
3090         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3091         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3092 };
3093
3094 enum {
3095         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3096         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3097 };
3098
3099 struct mlx5_ifc_tirc_bits {
3100         u8         reserved_at_0[0x20];
3101
3102         u8         disp_type[0x4];
3103         u8         reserved_at_24[0x1c];
3104
3105         u8         reserved_at_40[0x40];
3106
3107         u8         reserved_at_80[0x4];
3108         u8         lro_timeout_period_usecs[0x10];
3109         u8         lro_enable_mask[0x4];
3110         u8         lro_max_ip_payload_size[0x8];
3111
3112         u8         reserved_at_a0[0x40];
3113
3114         u8         reserved_at_e0[0x8];
3115         u8         inline_rqn[0x18];
3116
3117         u8         rx_hash_symmetric[0x1];
3118         u8         reserved_at_101[0x1];
3119         u8         tunneled_offload_en[0x1];
3120         u8         reserved_at_103[0x5];
3121         u8         indirect_table[0x18];
3122
3123         u8         rx_hash_fn[0x4];
3124         u8         reserved_at_124[0x2];
3125         u8         self_lb_block[0x2];
3126         u8         transport_domain[0x18];
3127
3128         u8         rx_hash_toeplitz_key[10][0x20];
3129
3130         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3131
3132         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3133
3134         u8         reserved_at_2c0[0x4c0];
3135 };
3136
3137 enum {
3138         MLX5_SRQC_STATE_GOOD   = 0x0,
3139         MLX5_SRQC_STATE_ERROR  = 0x1,
3140 };
3141
3142 struct mlx5_ifc_srqc_bits {
3143         u8         state[0x4];
3144         u8         log_srq_size[0x4];
3145         u8         reserved_at_8[0x18];
3146
3147         u8         wq_signature[0x1];
3148         u8         cont_srq[0x1];
3149         u8         reserved_at_22[0x1];
3150         u8         rlky[0x1];
3151         u8         reserved_at_24[0x1];
3152         u8         log_rq_stride[0x3];
3153         u8         xrcd[0x18];
3154
3155         u8         page_offset[0x6];
3156         u8         reserved_at_46[0x2];
3157         u8         cqn[0x18];
3158
3159         u8         reserved_at_60[0x20];
3160
3161         u8         reserved_at_80[0x2];
3162         u8         log_page_size[0x6];
3163         u8         reserved_at_88[0x18];
3164
3165         u8         reserved_at_a0[0x20];
3166
3167         u8         reserved_at_c0[0x8];
3168         u8         pd[0x18];
3169
3170         u8         lwm[0x10];
3171         u8         wqe_cnt[0x10];
3172
3173         u8         reserved_at_100[0x40];
3174
3175         u8         dbr_addr[0x40];
3176
3177         u8         reserved_at_180[0x80];
3178 };
3179
3180 enum {
3181         MLX5_SQC_STATE_RST  = 0x0,
3182         MLX5_SQC_STATE_RDY  = 0x1,
3183         MLX5_SQC_STATE_ERR  = 0x3,
3184 };
3185
3186 struct mlx5_ifc_sqc_bits {
3187         u8         rlky[0x1];
3188         u8         cd_master[0x1];
3189         u8         fre[0x1];
3190         u8         flush_in_error_en[0x1];
3191         u8         allow_multi_pkt_send_wqe[0x1];
3192         u8         min_wqe_inline_mode[0x3];
3193         u8         state[0x4];
3194         u8         reg_umr[0x1];
3195         u8         allow_swp[0x1];
3196         u8         hairpin[0x1];
3197         u8         reserved_at_f[0x11];
3198
3199         u8         reserved_at_20[0x8];
3200         u8         user_index[0x18];
3201
3202         u8         reserved_at_40[0x8];
3203         u8         cqn[0x18];
3204
3205         u8         reserved_at_60[0x8];
3206         u8         hairpin_peer_rq[0x18];
3207
3208         u8         reserved_at_80[0x10];
3209         u8         hairpin_peer_vhca[0x10];
3210
3211         u8         reserved_at_a0[0x50];
3212
3213         u8         packet_pacing_rate_limit_index[0x10];
3214         u8         tis_lst_sz[0x10];
3215         u8         reserved_at_110[0x10];
3216
3217         u8         reserved_at_120[0x40];
3218
3219         u8         reserved_at_160[0x8];
3220         u8         tis_num_0[0x18];
3221
3222         struct mlx5_ifc_wq_bits wq;
3223 };
3224
3225 enum {
3226         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3227         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3228         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3229         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3230 };
3231
3232 enum {
3233         ELEMENT_TYPE_CAP_MASK_TASR              = 1 << 0,
3234         ELEMENT_TYPE_CAP_MASK_VPORT             = 1 << 1,
3235         ELEMENT_TYPE_CAP_MASK_VPORT_TC          = 1 << 2,
3236         ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC     = 1 << 3,
3237 };
3238
3239 struct mlx5_ifc_scheduling_context_bits {
3240         u8         element_type[0x8];
3241         u8         reserved_at_8[0x18];
3242
3243         u8         element_attributes[0x20];
3244
3245         u8         parent_element_id[0x20];
3246
3247         u8         reserved_at_60[0x40];
3248
3249         u8         bw_share[0x20];
3250
3251         u8         max_average_bw[0x20];
3252
3253         u8         reserved_at_e0[0x120];
3254 };
3255
3256 struct mlx5_ifc_rqtc_bits {
3257         u8         reserved_at_0[0xa0];
3258
3259         u8         reserved_at_a0[0x10];
3260         u8         rqt_max_size[0x10];
3261
3262         u8         reserved_at_c0[0x10];
3263         u8         rqt_actual_size[0x10];
3264
3265         u8         reserved_at_e0[0x6a0];
3266
3267         struct mlx5_ifc_rq_num_bits rq_num[0];
3268 };
3269
3270 enum {
3271         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3272         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3273 };
3274
3275 enum {
3276         MLX5_RQC_STATE_RST  = 0x0,
3277         MLX5_RQC_STATE_RDY  = 0x1,
3278         MLX5_RQC_STATE_ERR  = 0x3,
3279 };
3280
3281 struct mlx5_ifc_rqc_bits {
3282         u8         rlky[0x1];
3283         u8         delay_drop_en[0x1];
3284         u8         scatter_fcs[0x1];
3285         u8         vsd[0x1];
3286         u8         mem_rq_type[0x4];
3287         u8         state[0x4];
3288         u8         reserved_at_c[0x1];
3289         u8         flush_in_error_en[0x1];
3290         u8         hairpin[0x1];
3291         u8         reserved_at_f[0x11];
3292
3293         u8         reserved_at_20[0x8];
3294         u8         user_index[0x18];
3295
3296         u8         reserved_at_40[0x8];
3297         u8         cqn[0x18];
3298
3299         u8         counter_set_id[0x8];
3300         u8         reserved_at_68[0x18];
3301
3302         u8         reserved_at_80[0x8];
3303         u8         rmpn[0x18];
3304
3305         u8         reserved_at_a0[0x8];
3306         u8         hairpin_peer_sq[0x18];
3307
3308         u8         reserved_at_c0[0x10];
3309         u8         hairpin_peer_vhca[0x10];
3310
3311         u8         reserved_at_e0[0xa0];
3312
3313         struct mlx5_ifc_wq_bits wq;
3314 };
3315
3316 enum {
3317         MLX5_RMPC_STATE_RDY  = 0x1,
3318         MLX5_RMPC_STATE_ERR  = 0x3,
3319 };
3320
3321 struct mlx5_ifc_rmpc_bits {
3322         u8         reserved_at_0[0x8];
3323         u8         state[0x4];
3324         u8         reserved_at_c[0x14];
3325
3326         u8         basic_cyclic_rcv_wqe[0x1];
3327         u8         reserved_at_21[0x1f];
3328
3329         u8         reserved_at_40[0x140];
3330
3331         struct mlx5_ifc_wq_bits wq;
3332 };
3333
3334 struct mlx5_ifc_nic_vport_context_bits {
3335         u8         reserved_at_0[0x5];
3336         u8         min_wqe_inline_mode[0x3];
3337         u8         reserved_at_8[0x15];
3338         u8         disable_mc_local_lb[0x1];
3339         u8         disable_uc_local_lb[0x1];
3340         u8         roce_en[0x1];
3341
3342         u8         arm_change_event[0x1];
3343         u8         reserved_at_21[0x1a];
3344         u8         event_on_mtu[0x1];
3345         u8         event_on_promisc_change[0x1];
3346         u8         event_on_vlan_change[0x1];
3347         u8         event_on_mc_address_change[0x1];
3348         u8         event_on_uc_address_change[0x1];
3349
3350         u8         reserved_at_40[0xc];
3351
3352         u8         affiliation_criteria[0x4];
3353         u8         affiliated_vhca_id[0x10];
3354
3355         u8         reserved_at_60[0xd0];
3356
3357         u8         mtu[0x10];
3358
3359         u8         system_image_guid[0x40];
3360         u8         port_guid[0x40];
3361         u8         node_guid[0x40];
3362
3363         u8         reserved_at_200[0x140];
3364         u8         qkey_violation_counter[0x10];
3365         u8         reserved_at_350[0x430];
3366
3367         u8         promisc_uc[0x1];
3368         u8         promisc_mc[0x1];
3369         u8         promisc_all[0x1];
3370         u8         reserved_at_783[0x2];
3371         u8         allowed_list_type[0x3];
3372         u8         reserved_at_788[0xc];
3373         u8         allowed_list_size[0xc];
3374
3375         struct mlx5_ifc_mac_address_layout_bits permanent_address;
3376
3377         u8         reserved_at_7e0[0x20];
3378
3379         u8         current_uc_mac_address[0][0x40];
3380 };
3381
3382 enum {
3383         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
3384         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
3385         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
3386         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
3387         MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3388         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3389 };
3390
3391 struct mlx5_ifc_mkc_bits {
3392         u8         reserved_at_0[0x1];
3393         u8         free[0x1];
3394         u8         reserved_at_2[0x1];
3395         u8         access_mode_4_2[0x3];
3396         u8         reserved_at_6[0x7];
3397         u8         relaxed_ordering_write[0x1];
3398         u8         reserved_at_e[0x1];
3399         u8         small_fence_on_rdma_read_response[0x1];
3400         u8         umr_en[0x1];
3401         u8         a[0x1];
3402         u8         rw[0x1];
3403         u8         rr[0x1];
3404         u8         lw[0x1];
3405         u8         lr[0x1];
3406         u8         access_mode_1_0[0x2];
3407         u8         reserved_at_18[0x8];
3408
3409         u8         qpn[0x18];
3410         u8         mkey_7_0[0x8];
3411
3412         u8         reserved_at_40[0x20];
3413
3414         u8         length64[0x1];
3415         u8         bsf_en[0x1];
3416         u8         sync_umr[0x1];
3417         u8         reserved_at_63[0x2];
3418         u8         expected_sigerr_count[0x1];
3419         u8         reserved_at_66[0x1];
3420         u8         en_rinval[0x1];
3421         u8         pd[0x18];
3422
3423         u8         start_addr[0x40];
3424
3425         u8         len[0x40];
3426
3427         u8         bsf_octword_size[0x20];
3428
3429         u8         reserved_at_120[0x80];
3430
3431         u8         translations_octword_size[0x20];
3432
3433         u8         reserved_at_1c0[0x19];
3434         u8         relaxed_ordering_read[0x1];
3435         u8         reserved_at_1d9[0x1];
3436         u8         log_page_size[0x5];
3437
3438         u8         reserved_at_1e0[0x20];
3439 };
3440
3441 struct mlx5_ifc_pkey_bits {
3442         u8         reserved_at_0[0x10];
3443         u8         pkey[0x10];
3444 };
3445
3446 struct mlx5_ifc_array128_auto_bits {
3447         u8         array128_auto[16][0x8];
3448 };
3449
3450 struct mlx5_ifc_hca_vport_context_bits {
3451         u8         field_select[0x20];
3452
3453         u8         reserved_at_20[0xe0];
3454
3455         u8         sm_virt_aware[0x1];
3456         u8         has_smi[0x1];
3457         u8         has_raw[0x1];
3458         u8         grh_required[0x1];
3459         u8         reserved_at_104[0xc];
3460         u8         port_physical_state[0x4];
3461         u8         vport_state_policy[0x4];
3462         u8         port_state[0x4];
3463         u8         vport_state[0x4];
3464
3465         u8         reserved_at_120[0x20];
3466
3467         u8         system_image_guid[0x40];
3468
3469         u8         port_guid[0x40];
3470
3471         u8         node_guid[0x40];
3472
3473         u8         cap_mask1[0x20];
3474
3475         u8         cap_mask1_field_select[0x20];
3476
3477         u8         cap_mask2[0x20];
3478
3479         u8         cap_mask2_field_select[0x20];
3480
3481         u8         reserved_at_280[0x80];
3482
3483         u8         lid[0x10];
3484         u8         reserved_at_310[0x4];
3485         u8         init_type_reply[0x4];
3486         u8         lmc[0x3];
3487         u8         subnet_timeout[0x5];
3488
3489         u8         sm_lid[0x10];
3490         u8         sm_sl[0x4];
3491         u8         reserved_at_334[0xc];
3492
3493         u8         qkey_violation_counter[0x10];
3494         u8         pkey_violation_counter[0x10];
3495
3496         u8         reserved_at_360[0xca0];
3497 };
3498
3499 struct mlx5_ifc_esw_vport_context_bits {
3500         u8         fdb_to_vport_reg_c[0x1];
3501         u8         reserved_at_1[0x2];
3502         u8         vport_svlan_strip[0x1];
3503         u8         vport_cvlan_strip[0x1];
3504         u8         vport_svlan_insert[0x1];
3505         u8         vport_cvlan_insert[0x2];
3506         u8         fdb_to_vport_reg_c_id[0x8];
3507         u8         reserved_at_10[0x10];
3508
3509         u8         reserved_at_20[0x20];
3510
3511         u8         svlan_cfi[0x1];
3512         u8         svlan_pcp[0x3];
3513         u8         svlan_id[0xc];
3514         u8         cvlan_cfi[0x1];
3515         u8         cvlan_pcp[0x3];
3516         u8         cvlan_id[0xc];
3517
3518         u8         reserved_at_60[0x720];
3519
3520         u8         sw_steering_vport_icm_address_rx[0x40];
3521
3522         u8         sw_steering_vport_icm_address_tx[0x40];
3523 };
3524
3525 enum {
3526         MLX5_EQC_STATUS_OK                = 0x0,
3527         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
3528 };
3529
3530 enum {
3531         MLX5_EQC_ST_ARMED  = 0x9,
3532         MLX5_EQC_ST_FIRED  = 0xa,
3533 };
3534
3535 struct mlx5_ifc_eqc_bits {
3536         u8         status[0x4];
3537         u8         reserved_at_4[0x9];
3538         u8         ec[0x1];
3539         u8         oi[0x1];
3540         u8         reserved_at_f[0x5];
3541         u8         st[0x4];
3542         u8         reserved_at_18[0x8];
3543
3544         u8         reserved_at_20[0x20];
3545
3546         u8         reserved_at_40[0x14];
3547         u8         page_offset[0x6];
3548         u8         reserved_at_5a[0x6];
3549
3550         u8         reserved_at_60[0x3];
3551         u8         log_eq_size[0x5];
3552         u8         uar_page[0x18];
3553
3554         u8         reserved_at_80[0x20];
3555
3556         u8         reserved_at_a0[0x18];
3557         u8         intr[0x8];
3558
3559         u8         reserved_at_c0[0x3];
3560         u8         log_page_size[0x5];
3561         u8         reserved_at_c8[0x18];
3562
3563         u8         reserved_at_e0[0x60];
3564
3565         u8         reserved_at_140[0x8];
3566         u8         consumer_counter[0x18];
3567
3568         u8         reserved_at_160[0x8];
3569         u8         producer_counter[0x18];
3570
3571         u8         reserved_at_180[0x80];
3572 };
3573
3574 enum {
3575         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3576         MLX5_DCTC_STATE_DRAINING  = 0x1,
3577         MLX5_DCTC_STATE_DRAINED   = 0x2,
3578 };
3579
3580 enum {
3581         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3582         MLX5_DCTC_CS_RES_NA         = 0x1,
3583         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3584 };
3585
3586 enum {
3587         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3588         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3589         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3590         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3591         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3592 };
3593
3594 struct mlx5_ifc_dctc_bits {
3595         u8         reserved_at_0[0x4];
3596         u8         state[0x4];
3597         u8         reserved_at_8[0x18];
3598
3599         u8         reserved_at_20[0x8];
3600         u8         user_index[0x18];
3601
3602         u8         reserved_at_40[0x8];
3603         u8         cqn[0x18];
3604
3605         u8         counter_set_id[0x8];
3606         u8         atomic_mode[0x4];
3607         u8         rre[0x1];
3608         u8         rwe[0x1];
3609         u8         rae[0x1];
3610         u8         atomic_like_write_en[0x1];
3611         u8         latency_sensitive[0x1];
3612         u8         rlky[0x1];
3613         u8         free_ar[0x1];
3614         u8         reserved_at_73[0xd];
3615
3616         u8         reserved_at_80[0x8];
3617         u8         cs_res[0x8];
3618         u8         reserved_at_90[0x3];
3619         u8         min_rnr_nak[0x5];
3620         u8         reserved_at_98[0x8];
3621
3622         u8         reserved_at_a0[0x8];
3623         u8         srqn_xrqn[0x18];
3624
3625         u8         reserved_at_c0[0x8];
3626         u8         pd[0x18];
3627
3628         u8         tclass[0x8];
3629         u8         reserved_at_e8[0x4];
3630         u8         flow_label[0x14];
3631
3632         u8         dc_access_key[0x40];
3633
3634         u8         reserved_at_140[0x5];
3635         u8         mtu[0x3];
3636         u8         port[0x8];
3637         u8         pkey_index[0x10];
3638
3639         u8         reserved_at_160[0x8];
3640         u8         my_addr_index[0x8];
3641         u8         reserved_at_170[0x8];
3642         u8         hop_limit[0x8];
3643
3644         u8         dc_access_key_violation_count[0x20];
3645
3646         u8         reserved_at_1a0[0x14];
3647         u8         dei_cfi[0x1];
3648         u8         eth_prio[0x3];
3649         u8         ecn[0x2];
3650         u8         dscp[0x6];
3651
3652         u8         reserved_at_1c0[0x40];
3653 };
3654
3655 enum {
3656         MLX5_CQC_STATUS_OK             = 0x0,
3657         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3658         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3659 };
3660
3661 enum {
3662         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3663         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3664 };
3665
3666 enum {
3667         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3668         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3669         MLX5_CQC_ST_FIRED                                 = 0xa,
3670 };
3671
3672 enum {
3673         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3674         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3675         MLX5_CQ_PERIOD_NUM_MODES
3676 };
3677
3678 struct mlx5_ifc_cqc_bits {
3679         u8         status[0x4];
3680         u8         reserved_at_4[0x2];
3681         u8         dbr_umem_valid[0x1];
3682         u8         reserved_at_7[0x1];
3683         u8         cqe_sz[0x3];
3684         u8         cc[0x1];
3685         u8         reserved_at_c[0x1];
3686         u8         scqe_break_moderation_en[0x1];
3687         u8         oi[0x1];
3688         u8         cq_period_mode[0x2];
3689         u8         cqe_comp_en[0x1];
3690         u8         mini_cqe_res_format[0x2];
3691         u8         st[0x4];
3692         u8         reserved_at_18[0x8];
3693
3694         u8         reserved_at_20[0x20];
3695
3696         u8         reserved_at_40[0x14];
3697         u8         page_offset[0x6];
3698         u8         reserved_at_5a[0x6];
3699
3700         u8         reserved_at_60[0x3];
3701         u8         log_cq_size[0x5];
3702         u8         uar_page[0x18];
3703
3704         u8         reserved_at_80[0x4];
3705         u8         cq_period[0xc];
3706         u8         cq_max_count[0x10];
3707
3708         u8         reserved_at_a0[0x18];
3709         u8         c_eqn[0x8];
3710
3711         u8         reserved_at_c0[0x3];
3712         u8         log_page_size[0x5];
3713         u8         reserved_at_c8[0x18];
3714
3715         u8         reserved_at_e0[0x20];
3716
3717         u8         reserved_at_100[0x8];
3718         u8         last_notified_index[0x18];
3719
3720         u8         reserved_at_120[0x8];
3721         u8         last_solicit_index[0x18];
3722
3723         u8         reserved_at_140[0x8];
3724         u8         consumer_counter[0x18];
3725
3726         u8         reserved_at_160[0x8];
3727         u8         producer_counter[0x18];
3728
3729         u8         reserved_at_180[0x40];
3730
3731         u8         dbr_addr[0x40];
3732 };
3733
3734 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3735         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3736         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3737         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3738         u8         reserved_at_0[0x800];
3739 };
3740
3741 struct mlx5_ifc_query_adapter_param_block_bits {
3742         u8         reserved_at_0[0xc0];
3743
3744         u8         reserved_at_c0[0x8];
3745         u8         ieee_vendor_id[0x18];
3746
3747         u8         reserved_at_e0[0x10];
3748         u8         vsd_vendor_id[0x10];
3749
3750         u8         vsd[208][0x8];
3751
3752         u8         vsd_contd_psid[16][0x8];
3753 };
3754
3755 enum {
3756         MLX5_XRQC_STATE_GOOD   = 0x0,
3757         MLX5_XRQC_STATE_ERROR  = 0x1,
3758 };
3759
3760 enum {
3761         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3762         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3763 };
3764
3765 enum {
3766         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3767 };
3768
3769 struct mlx5_ifc_tag_matching_topology_context_bits {
3770         u8         log_matching_list_sz[0x4];
3771         u8         reserved_at_4[0xc];
3772         u8         append_next_index[0x10];
3773
3774         u8         sw_phase_cnt[0x10];
3775         u8         hw_phase_cnt[0x10];
3776
3777         u8         reserved_at_40[0x40];
3778 };
3779
3780 struct mlx5_ifc_xrqc_bits {
3781         u8         state[0x4];
3782         u8         rlkey[0x1];
3783         u8         reserved_at_5[0xf];
3784         u8         topology[0x4];
3785         u8         reserved_at_18[0x4];
3786         u8         offload[0x4];
3787
3788         u8         reserved_at_20[0x8];
3789         u8         user_index[0x18];
3790
3791         u8         reserved_at_40[0x8];
3792         u8         cqn[0x18];
3793
3794         u8         reserved_at_60[0xa0];
3795
3796         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3797
3798         u8         reserved_at_180[0x280];
3799
3800         struct mlx5_ifc_wq_bits wq;
3801 };
3802
3803 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3804         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3805         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3806         u8         reserved_at_0[0x20];
3807 };
3808
3809 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3810         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3811         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3812         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3813         u8         reserved_at_0[0x20];
3814 };
3815
3816 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3817         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3818         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3819         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3820         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3821         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3822         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3823         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
3824         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
3825         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3826         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3827         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3828         u8         reserved_at_0[0x7c0];
3829 };
3830
3831 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3832         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3833         u8         reserved_at_0[0x7c0];
3834 };
3835
3836 union mlx5_ifc_event_auto_bits {
3837         struct mlx5_ifc_comp_event_bits comp_event;
3838         struct mlx5_ifc_dct_events_bits dct_events;
3839         struct mlx5_ifc_qp_events_bits qp_events;
3840         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3841         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3842         struct mlx5_ifc_cq_error_bits cq_error;
3843         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3844         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3845         struct mlx5_ifc_gpio_event_bits gpio_event;
3846         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3847         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3848         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3849         u8         reserved_at_0[0xe0];
3850 };
3851
3852 struct mlx5_ifc_health_buffer_bits {
3853         u8         reserved_at_0[0x100];
3854
3855         u8         assert_existptr[0x20];
3856
3857         u8         assert_callra[0x20];
3858
3859         u8         reserved_at_140[0x40];
3860
3861         u8         fw_version[0x20];
3862
3863         u8         hw_id[0x20];
3864
3865         u8         reserved_at_1c0[0x20];
3866
3867         u8         irisc_index[0x8];
3868         u8         synd[0x8];
3869         u8         ext_synd[0x10];
3870 };
3871
3872 struct mlx5_ifc_register_loopback_control_bits {
3873         u8         no_lb[0x1];
3874         u8         reserved_at_1[0x7];
3875         u8         port[0x8];
3876         u8         reserved_at_10[0x10];
3877
3878         u8         reserved_at_20[0x60];
3879 };
3880
3881 struct mlx5_ifc_vport_tc_element_bits {
3882         u8         traffic_class[0x4];
3883         u8         reserved_at_4[0xc];
3884         u8         vport_number[0x10];
3885 };
3886
3887 struct mlx5_ifc_vport_element_bits {
3888         u8         reserved_at_0[0x10];
3889         u8         vport_number[0x10];
3890 };
3891
3892 enum {
3893         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3894         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3895         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3896 };
3897
3898 struct mlx5_ifc_tsar_element_bits {
3899         u8         reserved_at_0[0x8];
3900         u8         tsar_type[0x8];
3901         u8         reserved_at_10[0x10];
3902 };
3903
3904 enum {
3905         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3906         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3907 };
3908
3909 struct mlx5_ifc_teardown_hca_out_bits {
3910         u8         status[0x8];
3911         u8         reserved_at_8[0x18];
3912
3913         u8         syndrome[0x20];
3914
3915         u8         reserved_at_40[0x3f];
3916
3917         u8         state[0x1];
3918 };
3919
3920 enum {
3921         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3922         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3923         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3924 };
3925
3926 struct mlx5_ifc_teardown_hca_in_bits {
3927         u8         opcode[0x10];
3928         u8         reserved_at_10[0x10];
3929
3930         u8         reserved_at_20[0x10];
3931         u8         op_mod[0x10];
3932
3933         u8         reserved_at_40[0x10];
3934         u8         profile[0x10];
3935
3936         u8         reserved_at_60[0x20];
3937 };
3938
3939 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3940         u8         status[0x8];
3941         u8         reserved_at_8[0x18];
3942
3943         u8         syndrome[0x20];
3944
3945         u8         reserved_at_40[0x40];
3946 };
3947
3948 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3949         u8         opcode[0x10];
3950         u8         uid[0x10];
3951
3952         u8         reserved_at_20[0x10];
3953         u8         op_mod[0x10];
3954
3955         u8         reserved_at_40[0x8];
3956         u8         qpn[0x18];
3957
3958         u8         reserved_at_60[0x20];
3959
3960         u8         opt_param_mask[0x20];
3961
3962         u8         reserved_at_a0[0x20];
3963
3964         struct mlx5_ifc_qpc_bits qpc;
3965
3966         u8         reserved_at_800[0x80];
3967 };
3968
3969 struct mlx5_ifc_sqd2rts_qp_out_bits {
3970         u8         status[0x8];
3971         u8         reserved_at_8[0x18];
3972
3973         u8         syndrome[0x20];
3974
3975         u8         reserved_at_40[0x40];
3976 };
3977
3978 struct mlx5_ifc_sqd2rts_qp_in_bits {
3979         u8         opcode[0x10];
3980         u8         uid[0x10];
3981
3982         u8         reserved_at_20[0x10];
3983         u8         op_mod[0x10];
3984
3985         u8         reserved_at_40[0x8];
3986         u8         qpn[0x18];
3987
3988         u8         reserved_at_60[0x20];
3989
3990         u8         opt_param_mask[0x20];
3991
3992         u8         reserved_at_a0[0x20];
3993
3994         struct mlx5_ifc_qpc_bits qpc;
3995
3996         u8         reserved_at_800[0x80];
3997 };
3998
3999 struct mlx5_ifc_set_roce_address_out_bits {
4000         u8         status[0x8];
4001         u8         reserved_at_8[0x18];
4002
4003         u8         syndrome[0x20];
4004
4005         u8         reserved_at_40[0x40];
4006 };
4007
4008 struct mlx5_ifc_set_roce_address_in_bits {
4009         u8         opcode[0x10];
4010         u8         reserved_at_10[0x10];
4011
4012         u8         reserved_at_20[0x10];
4013         u8         op_mod[0x10];
4014
4015         u8         roce_address_index[0x10];
4016         u8         reserved_at_50[0xc];
4017         u8         vhca_port_num[0x4];
4018
4019         u8         reserved_at_60[0x20];
4020
4021         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4022 };
4023
4024 struct mlx5_ifc_set_mad_demux_out_bits {
4025         u8         status[0x8];
4026         u8         reserved_at_8[0x18];
4027
4028         u8         syndrome[0x20];
4029
4030         u8         reserved_at_40[0x40];
4031 };
4032
4033 enum {
4034         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4035         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4036 };
4037
4038 struct mlx5_ifc_set_mad_demux_in_bits {
4039         u8         opcode[0x10];
4040         u8         reserved_at_10[0x10];
4041
4042         u8         reserved_at_20[0x10];
4043         u8         op_mod[0x10];
4044
4045         u8         reserved_at_40[0x20];
4046
4047         u8         reserved_at_60[0x6];
4048         u8         demux_mode[0x2];
4049         u8         reserved_at_68[0x18];
4050 };
4051
4052 struct mlx5_ifc_set_l2_table_entry_out_bits {
4053         u8         status[0x8];
4054         u8         reserved_at_8[0x18];
4055
4056         u8         syndrome[0x20];
4057
4058         u8         reserved_at_40[0x40];
4059 };
4060
4061 struct mlx5_ifc_set_l2_table_entry_in_bits {
4062         u8         opcode[0x10];
4063         u8         reserved_at_10[0x10];
4064
4065         u8         reserved_at_20[0x10];
4066         u8         op_mod[0x10];
4067
4068         u8         reserved_at_40[0x60];
4069
4070         u8         reserved_at_a0[0x8];
4071         u8         table_index[0x18];
4072
4073         u8         reserved_at_c0[0x20];
4074
4075         u8         reserved_at_e0[0x13];
4076         u8         vlan_valid[0x1];
4077         u8         vlan[0xc];
4078
4079         struct mlx5_ifc_mac_address_layout_bits mac_address;
4080
4081         u8         reserved_at_140[0xc0];
4082 };
4083
4084 struct mlx5_ifc_set_issi_out_bits {
4085         u8         status[0x8];
4086         u8         reserved_at_8[0x18];
4087
4088         u8         syndrome[0x20];
4089
4090         u8         reserved_at_40[0x40];
4091 };
4092
4093 struct mlx5_ifc_set_issi_in_bits {
4094         u8         opcode[0x10];
4095         u8         reserved_at_10[0x10];
4096
4097         u8         reserved_at_20[0x10];
4098         u8         op_mod[0x10];
4099
4100         u8         reserved_at_40[0x10];
4101         u8         current_issi[0x10];
4102
4103         u8         reserved_at_60[0x20];
4104 };
4105
4106 struct mlx5_ifc_set_hca_cap_out_bits {
4107         u8         status[0x8];
4108         u8         reserved_at_8[0x18];
4109
4110         u8         syndrome[0x20];
4111
4112         u8         reserved_at_40[0x40];
4113 };
4114
4115 struct mlx5_ifc_set_hca_cap_in_bits {
4116         u8         opcode[0x10];
4117         u8         reserved_at_10[0x10];
4118
4119         u8         reserved_at_20[0x10];
4120         u8         op_mod[0x10];
4121
4122         u8         reserved_at_40[0x40];
4123
4124         union mlx5_ifc_hca_cap_union_bits capability;
4125 };
4126
4127 enum {
4128         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
4129         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
4130         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
4131         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
4132 };
4133
4134 struct mlx5_ifc_set_fte_out_bits {
4135         u8         status[0x8];
4136         u8         reserved_at_8[0x18];
4137
4138         u8         syndrome[0x20];
4139
4140         u8         reserved_at_40[0x40];
4141 };
4142
4143 struct mlx5_ifc_set_fte_in_bits {
4144         u8         opcode[0x10];
4145         u8         reserved_at_10[0x10];
4146
4147         u8         reserved_at_20[0x10];
4148         u8         op_mod[0x10];
4149
4150         u8         other_vport[0x1];
4151         u8         reserved_at_41[0xf];
4152         u8         vport_number[0x10];
4153
4154         u8         reserved_at_60[0x20];
4155
4156         u8         table_type[0x8];
4157         u8         reserved_at_88[0x18];
4158
4159         u8         reserved_at_a0[0x8];
4160         u8         table_id[0x18];
4161
4162         u8         ignore_flow_level[0x1];
4163         u8         reserved_at_c1[0x17];
4164         u8         modify_enable_mask[0x8];
4165
4166         u8         reserved_at_e0[0x20];
4167
4168         u8         flow_index[0x20];
4169
4170         u8         reserved_at_120[0xe0];
4171
4172         struct mlx5_ifc_flow_context_bits flow_context;
4173 };
4174
4175 struct mlx5_ifc_rts2rts_qp_out_bits {
4176         u8         status[0x8];
4177         u8         reserved_at_8[0x18];
4178
4179         u8         syndrome[0x20];
4180
4181         u8         reserved_at_40[0x40];
4182 };
4183
4184 struct mlx5_ifc_rts2rts_qp_in_bits {
4185         u8         opcode[0x10];
4186         u8         uid[0x10];
4187
4188         u8         reserved_at_20[0x10];
4189         u8         op_mod[0x10];
4190
4191         u8         reserved_at_40[0x8];
4192         u8         qpn[0x18];
4193
4194         u8         reserved_at_60[0x20];
4195
4196         u8         opt_param_mask[0x20];
4197
4198         u8         reserved_at_a0[0x20];
4199
4200         struct mlx5_ifc_qpc_bits qpc;
4201
4202         u8         reserved_at_800[0x80];
4203 };
4204
4205 struct mlx5_ifc_rtr2rts_qp_out_bits {
4206         u8         status[0x8];
4207         u8         reserved_at_8[0x18];
4208
4209         u8         syndrome[0x20];
4210
4211         u8         reserved_at_40[0x40];
4212 };
4213
4214 struct mlx5_ifc_rtr2rts_qp_in_bits {
4215         u8         opcode[0x10];
4216         u8         uid[0x10];
4217
4218         u8         reserved_at_20[0x10];
4219         u8         op_mod[0x10];
4220
4221         u8         reserved_at_40[0x8];
4222         u8         qpn[0x18];
4223
4224         u8         reserved_at_60[0x20];
4225
4226         u8         opt_param_mask[0x20];
4227
4228         u8         reserved_at_a0[0x20];
4229
4230         struct mlx5_ifc_qpc_bits qpc;
4231
4232         u8         reserved_at_800[0x80];
4233 };
4234
4235 struct mlx5_ifc_rst2init_qp_out_bits {
4236         u8         status[0x8];
4237         u8         reserved_at_8[0x18];
4238
4239         u8         syndrome[0x20];
4240
4241         u8         reserved_at_40[0x40];
4242 };
4243
4244 struct mlx5_ifc_rst2init_qp_in_bits {
4245         u8         opcode[0x10];
4246         u8         uid[0x10];
4247
4248         u8         reserved_at_20[0x10];
4249         u8         op_mod[0x10];
4250
4251         u8         reserved_at_40[0x8];
4252         u8         qpn[0x18];
4253
4254         u8         reserved_at_60[0x20];
4255
4256         u8         opt_param_mask[0x20];
4257
4258         u8         reserved_at_a0[0x20];
4259
4260         struct mlx5_ifc_qpc_bits qpc;
4261
4262         u8         reserved_at_800[0x80];
4263 };
4264
4265 struct mlx5_ifc_query_xrq_out_bits {
4266         u8         status[0x8];
4267         u8         reserved_at_8[0x18];
4268
4269         u8         syndrome[0x20];
4270
4271         u8         reserved_at_40[0x40];
4272
4273         struct mlx5_ifc_xrqc_bits xrq_context;
4274 };
4275
4276 struct mlx5_ifc_query_xrq_in_bits {
4277         u8         opcode[0x10];
4278         u8         reserved_at_10[0x10];
4279
4280         u8         reserved_at_20[0x10];
4281         u8         op_mod[0x10];
4282
4283         u8         reserved_at_40[0x8];
4284         u8         xrqn[0x18];
4285
4286         u8         reserved_at_60[0x20];
4287 };
4288
4289 struct mlx5_ifc_query_xrc_srq_out_bits {
4290         u8         status[0x8];
4291         u8         reserved_at_8[0x18];
4292
4293         u8         syndrome[0x20];
4294
4295         u8         reserved_at_40[0x40];
4296
4297         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4298
4299         u8         reserved_at_280[0x600];
4300
4301         u8         pas[0][0x40];
4302 };
4303
4304 struct mlx5_ifc_query_xrc_srq_in_bits {
4305         u8         opcode[0x10];
4306         u8         reserved_at_10[0x10];
4307
4308         u8         reserved_at_20[0x10];
4309         u8         op_mod[0x10];
4310
4311         u8         reserved_at_40[0x8];
4312         u8         xrc_srqn[0x18];
4313
4314         u8         reserved_at_60[0x20];
4315 };
4316
4317 enum {
4318         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4319         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4320 };
4321
4322 struct mlx5_ifc_query_vport_state_out_bits {
4323         u8         status[0x8];
4324         u8         reserved_at_8[0x18];
4325
4326         u8         syndrome[0x20];
4327
4328         u8         reserved_at_40[0x20];
4329
4330         u8         reserved_at_60[0x18];
4331         u8         admin_state[0x4];
4332         u8         state[0x4];
4333 };
4334
4335 enum {
4336         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
4337         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
4338 };
4339
4340 struct mlx5_ifc_arm_monitor_counter_in_bits {
4341         u8         opcode[0x10];
4342         u8         uid[0x10];
4343
4344         u8         reserved_at_20[0x10];
4345         u8         op_mod[0x10];
4346
4347         u8         reserved_at_40[0x20];
4348
4349         u8         reserved_at_60[0x20];
4350 };
4351
4352 struct mlx5_ifc_arm_monitor_counter_out_bits {
4353         u8         status[0x8];
4354         u8         reserved_at_8[0x18];
4355
4356         u8         syndrome[0x20];
4357
4358         u8         reserved_at_40[0x40];
4359 };
4360
4361 enum {
4362         MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
4363         MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4364 };
4365
4366 enum mlx5_monitor_counter_ppcnt {
4367         MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
4368         MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
4369         MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
4370         MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4371         MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
4372         MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
4373 };
4374
4375 enum {
4376         MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
4377 };
4378
4379 struct mlx5_ifc_monitor_counter_output_bits {
4380         u8         reserved_at_0[0x4];
4381         u8         type[0x4];
4382         u8         reserved_at_8[0x8];
4383         u8         counter[0x10];
4384
4385         u8         counter_group_id[0x20];
4386 };
4387
4388 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4389 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
4390 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4391                                           MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4392
4393 struct mlx5_ifc_set_monitor_counter_in_bits {
4394         u8         opcode[0x10];
4395         u8         uid[0x10];
4396
4397         u8         reserved_at_20[0x10];
4398         u8         op_mod[0x10];
4399
4400         u8         reserved_at_40[0x10];
4401         u8         num_of_counters[0x10];
4402
4403         u8         reserved_at_60[0x20];
4404
4405         struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4406 };
4407
4408 struct mlx5_ifc_set_monitor_counter_out_bits {
4409         u8         status[0x8];
4410         u8         reserved_at_8[0x18];
4411
4412         u8         syndrome[0x20];
4413
4414         u8         reserved_at_40[0x40];
4415 };
4416
4417 struct mlx5_ifc_query_vport_state_in_bits {
4418         u8         opcode[0x10];
4419         u8         reserved_at_10[0x10];
4420
4421         u8         reserved_at_20[0x10];
4422         u8         op_mod[0x10];
4423
4424         u8         other_vport[0x1];
4425         u8         reserved_at_41[0xf];
4426         u8         vport_number[0x10];
4427
4428         u8         reserved_at_60[0x20];
4429 };
4430
4431 struct mlx5_ifc_query_vnic_env_out_bits {
4432         u8         status[0x8];
4433         u8         reserved_at_8[0x18];
4434
4435         u8         syndrome[0x20];
4436
4437         u8         reserved_at_40[0x40];
4438
4439         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4440 };
4441
4442 enum {
4443         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4444 };
4445
4446 struct mlx5_ifc_query_vnic_env_in_bits {
4447         u8         opcode[0x10];
4448         u8         reserved_at_10[0x10];
4449
4450         u8         reserved_at_20[0x10];
4451         u8         op_mod[0x10];
4452
4453         u8         other_vport[0x1];
4454         u8         reserved_at_41[0xf];
4455         u8         vport_number[0x10];
4456
4457         u8         reserved_at_60[0x20];
4458 };
4459
4460 struct mlx5_ifc_query_vport_counter_out_bits {
4461         u8         status[0x8];
4462         u8         reserved_at_8[0x18];
4463
4464         u8         syndrome[0x20];
4465
4466         u8         reserved_at_40[0x40];
4467
4468         struct mlx5_ifc_traffic_counter_bits received_errors;
4469
4470         struct mlx5_ifc_traffic_counter_bits transmit_errors;
4471
4472         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4473
4474         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4475
4476         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4477
4478         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4479
4480         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4481
4482         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4483
4484         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4485
4486         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4487
4488         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4489
4490         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4491
4492         u8         reserved_at_680[0xa00];
4493 };
4494
4495 enum {
4496         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4497 };
4498
4499 struct mlx5_ifc_query_vport_counter_in_bits {
4500         u8         opcode[0x10];
4501         u8         reserved_at_10[0x10];
4502
4503         u8         reserved_at_20[0x10];
4504         u8         op_mod[0x10];
4505
4506         u8         other_vport[0x1];
4507         u8         reserved_at_41[0xb];
4508         u8         port_num[0x4];
4509         u8         vport_number[0x10];
4510
4511         u8         reserved_at_60[0x60];
4512
4513         u8         clear[0x1];
4514         u8         reserved_at_c1[0x1f];
4515
4516         u8         reserved_at_e0[0x20];
4517 };
4518
4519 struct mlx5_ifc_query_tis_out_bits {
4520         u8         status[0x8];
4521         u8         reserved_at_8[0x18];
4522
4523         u8         syndrome[0x20];
4524
4525         u8         reserved_at_40[0x40];
4526
4527         struct mlx5_ifc_tisc_bits tis_context;
4528 };
4529
4530 struct mlx5_ifc_query_tis_in_bits {
4531         u8         opcode[0x10];
4532         u8         reserved_at_10[0x10];
4533
4534         u8         reserved_at_20[0x10];
4535         u8         op_mod[0x10];
4536
4537         u8         reserved_at_40[0x8];
4538         u8         tisn[0x18];
4539
4540         u8         reserved_at_60[0x20];
4541 };
4542
4543 struct mlx5_ifc_query_tir_out_bits {
4544         u8         status[0x8];
4545         u8         reserved_at_8[0x18];
4546
4547         u8         syndrome[0x20];
4548
4549         u8         reserved_at_40[0xc0];
4550
4551         struct mlx5_ifc_tirc_bits tir_context;
4552 };
4553
4554 struct mlx5_ifc_query_tir_in_bits {
4555         u8         opcode[0x10];
4556         u8         reserved_at_10[0x10];
4557
4558         u8         reserved_at_20[0x10];
4559         u8         op_mod[0x10];
4560
4561         u8         reserved_at_40[0x8];
4562         u8         tirn[0x18];
4563
4564         u8         reserved_at_60[0x20];
4565 };
4566
4567 struct mlx5_ifc_query_srq_out_bits {
4568         u8         status[0x8];
4569         u8         reserved_at_8[0x18];
4570
4571         u8         syndrome[0x20];
4572
4573         u8         reserved_at_40[0x40];
4574
4575         struct mlx5_ifc_srqc_bits srq_context_entry;
4576
4577         u8         reserved_at_280[0x600];
4578
4579         u8         pas[0][0x40];
4580 };
4581
4582 struct mlx5_ifc_query_srq_in_bits {
4583         u8         opcode[0x10];
4584         u8         reserved_at_10[0x10];
4585
4586         u8         reserved_at_20[0x10];
4587         u8         op_mod[0x10];
4588
4589         u8         reserved_at_40[0x8];
4590         u8         srqn[0x18];
4591
4592         u8         reserved_at_60[0x20];
4593 };
4594
4595 struct mlx5_ifc_query_sq_out_bits {
4596         u8         status[0x8];
4597         u8         reserved_at_8[0x18];
4598
4599         u8         syndrome[0x20];
4600
4601         u8         reserved_at_40[0xc0];
4602
4603         struct mlx5_ifc_sqc_bits sq_context;
4604 };
4605
4606 struct mlx5_ifc_query_sq_in_bits {
4607         u8         opcode[0x10];
4608         u8         reserved_at_10[0x10];
4609
4610         u8         reserved_at_20[0x10];
4611         u8         op_mod[0x10];
4612
4613         u8         reserved_at_40[0x8];
4614         u8         sqn[0x18];
4615
4616         u8         reserved_at_60[0x20];
4617 };
4618
4619 struct mlx5_ifc_query_special_contexts_out_bits {
4620         u8         status[0x8];
4621         u8         reserved_at_8[0x18];
4622
4623         u8         syndrome[0x20];
4624
4625         u8         dump_fill_mkey[0x20];
4626
4627         u8         resd_lkey[0x20];
4628
4629         u8         null_mkey[0x20];
4630
4631         u8         reserved_at_a0[0x60];
4632 };
4633
4634 struct mlx5_ifc_query_special_contexts_in_bits {
4635         u8         opcode[0x10];
4636         u8         reserved_at_10[0x10];
4637
4638         u8         reserved_at_20[0x10];
4639         u8         op_mod[0x10];
4640
4641         u8         reserved_at_40[0x40];
4642 };
4643
4644 struct mlx5_ifc_query_scheduling_element_out_bits {
4645         u8         opcode[0x10];
4646         u8         reserved_at_10[0x10];
4647
4648         u8         reserved_at_20[0x10];
4649         u8         op_mod[0x10];
4650
4651         u8         reserved_at_40[0xc0];
4652
4653         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4654
4655         u8         reserved_at_300[0x100];
4656 };
4657
4658 enum {
4659         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4660 };
4661
4662 struct mlx5_ifc_query_scheduling_element_in_bits {
4663         u8         opcode[0x10];
4664         u8         reserved_at_10[0x10];
4665
4666         u8         reserved_at_20[0x10];
4667         u8         op_mod[0x10];
4668
4669         u8         scheduling_hierarchy[0x8];
4670         u8         reserved_at_48[0x18];
4671
4672         u8         scheduling_element_id[0x20];
4673
4674         u8         reserved_at_80[0x180];
4675 };
4676
4677 struct mlx5_ifc_query_rqt_out_bits {
4678         u8         status[0x8];
4679         u8         reserved_at_8[0x18];
4680
4681         u8         syndrome[0x20];
4682
4683         u8         reserved_at_40[0xc0];
4684
4685         struct mlx5_ifc_rqtc_bits rqt_context;
4686 };
4687
4688 struct mlx5_ifc_query_rqt_in_bits {
4689         u8         opcode[0x10];
4690         u8         reserved_at_10[0x10];
4691
4692         u8         reserved_at_20[0x10];
4693         u8         op_mod[0x10];
4694
4695         u8         reserved_at_40[0x8];
4696         u8         rqtn[0x18];
4697
4698         u8         reserved_at_60[0x20];
4699 };
4700
4701 struct mlx5_ifc_query_rq_out_bits {
4702         u8         status[0x8];
4703         u8         reserved_at_8[0x18];
4704
4705         u8         syndrome[0x20];
4706
4707         u8         reserved_at_40[0xc0];
4708
4709         struct mlx5_ifc_rqc_bits rq_context;
4710 };
4711
4712 struct mlx5_ifc_query_rq_in_bits {
4713         u8         opcode[0x10];
4714         u8         reserved_at_10[0x10];
4715
4716         u8         reserved_at_20[0x10];
4717         u8         op_mod[0x10];
4718
4719         u8         reserved_at_40[0x8];
4720         u8         rqn[0x18];
4721
4722         u8         reserved_at_60[0x20];
4723 };
4724
4725 struct mlx5_ifc_query_roce_address_out_bits {
4726         u8         status[0x8];
4727         u8         reserved_at_8[0x18];
4728
4729         u8         syndrome[0x20];
4730
4731         u8         reserved_at_40[0x40];
4732
4733         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4734 };
4735
4736 struct mlx5_ifc_query_roce_address_in_bits {
4737         u8         opcode[0x10];
4738         u8         reserved_at_10[0x10];
4739
4740         u8         reserved_at_20[0x10];
4741         u8         op_mod[0x10];
4742
4743         u8         roce_address_index[0x10];
4744         u8         reserved_at_50[0xc];
4745         u8         vhca_port_num[0x4];
4746
4747         u8         reserved_at_60[0x20];
4748 };
4749
4750 struct mlx5_ifc_query_rmp_out_bits {
4751         u8         status[0x8];
4752         u8         reserved_at_8[0x18];
4753
4754         u8         syndrome[0x20];
4755
4756         u8         reserved_at_40[0xc0];
4757
4758         struct mlx5_ifc_rmpc_bits rmp_context;
4759 };
4760
4761 struct mlx5_ifc_query_rmp_in_bits {
4762         u8         opcode[0x10];
4763         u8         reserved_at_10[0x10];
4764
4765         u8         reserved_at_20[0x10];
4766         u8         op_mod[0x10];
4767
4768         u8         reserved_at_40[0x8];
4769         u8         rmpn[0x18];
4770
4771         u8         reserved_at_60[0x20];
4772 };
4773
4774 struct mlx5_ifc_query_qp_out_bits {
4775         u8         status[0x8];
4776         u8         reserved_at_8[0x18];
4777
4778         u8         syndrome[0x20];
4779
4780         u8         reserved_at_40[0x40];
4781
4782         u8         opt_param_mask[0x20];
4783
4784         u8         reserved_at_a0[0x20];
4785
4786         struct mlx5_ifc_qpc_bits qpc;
4787
4788         u8         reserved_at_800[0x80];
4789
4790         u8         pas[0][0x40];
4791 };
4792
4793 struct mlx5_ifc_query_qp_in_bits {
4794         u8         opcode[0x10];
4795         u8         reserved_at_10[0x10];
4796
4797         u8         reserved_at_20[0x10];
4798         u8         op_mod[0x10];
4799
4800         u8         reserved_at_40[0x8];
4801         u8         qpn[0x18];
4802
4803         u8         reserved_at_60[0x20];
4804 };
4805
4806 struct mlx5_ifc_query_q_counter_out_bits {
4807         u8         status[0x8];
4808         u8         reserved_at_8[0x18];
4809
4810         u8         syndrome[0x20];
4811
4812         u8         reserved_at_40[0x40];
4813
4814         u8         rx_write_requests[0x20];
4815
4816         u8         reserved_at_a0[0x20];
4817
4818         u8         rx_read_requests[0x20];
4819
4820         u8         reserved_at_e0[0x20];
4821
4822         u8         rx_atomic_requests[0x20];
4823
4824         u8         reserved_at_120[0x20];
4825
4826         u8         rx_dct_connect[0x20];
4827
4828         u8         reserved_at_160[0x20];
4829
4830         u8         out_of_buffer[0x20];
4831
4832         u8         reserved_at_1a0[0x20];
4833
4834         u8         out_of_sequence[0x20];
4835
4836         u8         reserved_at_1e0[0x20];
4837
4838         u8         duplicate_request[0x20];
4839
4840         u8         reserved_at_220[0x20];
4841
4842         u8         rnr_nak_retry_err[0x20];
4843
4844         u8         reserved_at_260[0x20];
4845
4846         u8         packet_seq_err[0x20];
4847
4848         u8         reserved_at_2a0[0x20];
4849
4850         u8         implied_nak_seq_err[0x20];
4851
4852         u8         reserved_at_2e0[0x20];
4853
4854         u8         local_ack_timeout_err[0x20];
4855
4856         u8         reserved_at_320[0xa0];
4857
4858         u8         resp_local_length_error[0x20];
4859
4860         u8         req_local_length_error[0x20];
4861
4862         u8         resp_local_qp_error[0x20];
4863
4864         u8         local_operation_error[0x20];
4865
4866         u8         resp_local_protection[0x20];
4867
4868         u8         req_local_protection[0x20];
4869
4870         u8         resp_cqe_error[0x20];
4871
4872         u8         req_cqe_error[0x20];
4873
4874         u8         req_mw_binding[0x20];
4875
4876         u8         req_bad_response[0x20];
4877
4878         u8         req_remote_invalid_request[0x20];
4879
4880         u8         resp_remote_invalid_request[0x20];
4881
4882         u8         req_remote_access_errors[0x20];
4883
4884         u8         resp_remote_access_errors[0x20];
4885
4886         u8         req_remote_operation_errors[0x20];
4887
4888         u8         req_transport_retries_exceeded[0x20];
4889
4890         u8         cq_overflow[0x20];
4891
4892         u8         resp_cqe_flush_error[0x20];
4893
4894         u8         req_cqe_flush_error[0x20];
4895
4896         u8         reserved_at_620[0x20];
4897
4898         u8         roce_adp_retrans[0x20];
4899
4900         u8         roce_adp_retrans_to[0x20];
4901
4902         u8         roce_slow_restart[0x20];
4903
4904         u8         roce_slow_restart_cnps[0x20];
4905
4906         u8         roce_slow_restart_trans[0x20];
4907
4908         u8         reserved_at_6e0[0x120];
4909 };
4910
4911 struct mlx5_ifc_query_q_counter_in_bits {
4912         u8         opcode[0x10];
4913         u8         reserved_at_10[0x10];
4914
4915         u8         reserved_at_20[0x10];
4916         u8         op_mod[0x10];
4917
4918         u8         reserved_at_40[0x80];
4919
4920         u8         clear[0x1];
4921         u8         reserved_at_c1[0x1f];
4922
4923         u8         reserved_at_e0[0x18];
4924         u8         counter_set_id[0x8];
4925 };
4926
4927 struct mlx5_ifc_query_pages_out_bits {
4928         u8         status[0x8];
4929         u8         reserved_at_8[0x18];
4930
4931         u8         syndrome[0x20];
4932
4933         u8         embedded_cpu_function[0x1];
4934         u8         reserved_at_41[0xf];
4935         u8         function_id[0x10];
4936
4937         u8         num_pages[0x20];
4938 };
4939
4940 enum {
4941         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4942         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4943         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4944 };
4945
4946 struct mlx5_ifc_query_pages_in_bits {
4947         u8         opcode[0x10];
4948         u8         reserved_at_10[0x10];
4949
4950         u8         reserved_at_20[0x10];
4951         u8         op_mod[0x10];
4952
4953         u8         embedded_cpu_function[0x1];
4954         u8         reserved_at_41[0xf];
4955         u8         function_id[0x10];
4956
4957         u8         reserved_at_60[0x20];
4958 };
4959
4960 struct mlx5_ifc_query_nic_vport_context_out_bits {
4961         u8         status[0x8];
4962         u8         reserved_at_8[0x18];
4963
4964         u8         syndrome[0x20];
4965
4966         u8         reserved_at_40[0x40];
4967
4968         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4969 };
4970
4971 struct mlx5_ifc_query_nic_vport_context_in_bits {
4972         u8         opcode[0x10];
4973         u8         reserved_at_10[0x10];
4974
4975         u8         reserved_at_20[0x10];
4976         u8         op_mod[0x10];
4977
4978         u8         other_vport[0x1];
4979         u8         reserved_at_41[0xf];
4980         u8         vport_number[0x10];
4981
4982         u8         reserved_at_60[0x5];
4983         u8         allowed_list_type[0x3];
4984         u8         reserved_at_68[0x18];
4985 };
4986
4987 struct mlx5_ifc_query_mkey_out_bits {
4988         u8         status[0x8];
4989         u8         reserved_at_8[0x18];
4990
4991         u8         syndrome[0x20];
4992
4993         u8         reserved_at_40[0x40];
4994
4995         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4996
4997         u8         reserved_at_280[0x600];
4998
4999         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5000
5001         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5002 };
5003
5004 struct mlx5_ifc_query_mkey_in_bits {
5005         u8         opcode[0x10];
5006         u8         reserved_at_10[0x10];
5007
5008         u8         reserved_at_20[0x10];
5009         u8         op_mod[0x10];
5010
5011         u8         reserved_at_40[0x8];
5012         u8         mkey_index[0x18];
5013
5014         u8         pg_access[0x1];
5015         u8         reserved_at_61[0x1f];
5016 };
5017
5018 struct mlx5_ifc_query_mad_demux_out_bits {
5019         u8         status[0x8];
5020         u8         reserved_at_8[0x18];
5021
5022         u8         syndrome[0x20];
5023
5024         u8         reserved_at_40[0x40];
5025
5026         u8         mad_dumux_parameters_block[0x20];
5027 };
5028
5029 struct mlx5_ifc_query_mad_demux_in_bits {
5030         u8         opcode[0x10];
5031         u8         reserved_at_10[0x10];
5032
5033         u8         reserved_at_20[0x10];
5034         u8         op_mod[0x10];
5035
5036         u8         reserved_at_40[0x40];
5037 };
5038
5039 struct mlx5_ifc_query_l2_table_entry_out_bits {
5040         u8         status[0x8];
5041         u8         reserved_at_8[0x18];
5042
5043         u8         syndrome[0x20];
5044
5045         u8         reserved_at_40[0xa0];
5046
5047         u8         reserved_at_e0[0x13];
5048         u8         vlan_valid[0x1];
5049         u8         vlan[0xc];
5050
5051         struct mlx5_ifc_mac_address_layout_bits mac_address;
5052
5053         u8         reserved_at_140[0xc0];
5054 };
5055
5056 struct mlx5_ifc_query_l2_table_entry_in_bits {
5057         u8         opcode[0x10];
5058         u8         reserved_at_10[0x10];
5059
5060         u8         reserved_at_20[0x10];
5061         u8         op_mod[0x10];
5062
5063         u8         reserved_at_40[0x60];
5064
5065         u8         reserved_at_a0[0x8];
5066         u8         table_index[0x18];
5067
5068         u8         reserved_at_c0[0x140];
5069 };
5070
5071 struct mlx5_ifc_query_issi_out_bits {
5072         u8         status[0x8];
5073         u8         reserved_at_8[0x18];
5074
5075         u8         syndrome[0x20];
5076
5077         u8         reserved_at_40[0x10];
5078         u8         current_issi[0x10];
5079
5080         u8         reserved_at_60[0xa0];
5081
5082         u8         reserved_at_100[76][0x8];
5083         u8         supported_issi_dw0[0x20];
5084 };
5085
5086 struct mlx5_ifc_query_issi_in_bits {
5087         u8         opcode[0x10];
5088         u8         reserved_at_10[0x10];
5089
5090         u8         reserved_at_20[0x10];
5091         u8         op_mod[0x10];
5092
5093         u8         reserved_at_40[0x40];
5094 };
5095
5096 struct mlx5_ifc_set_driver_version_out_bits {
5097         u8         status[0x8];
5098         u8         reserved_0[0x18];
5099
5100         u8         syndrome[0x20];
5101         u8         reserved_1[0x40];
5102 };
5103
5104 struct mlx5_ifc_set_driver_version_in_bits {
5105         u8         opcode[0x10];
5106         u8         reserved_0[0x10];
5107
5108         u8         reserved_1[0x10];
5109         u8         op_mod[0x10];
5110
5111         u8         reserved_2[0x40];
5112         u8         driver_version[64][0x8];
5113 };
5114
5115 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5116         u8         status[0x8];
5117         u8         reserved_at_8[0x18];
5118
5119         u8         syndrome[0x20];
5120
5121         u8         reserved_at_40[0x40];
5122
5123         struct mlx5_ifc_pkey_bits pkey[0];
5124 };
5125
5126 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5127         u8         opcode[0x10];
5128         u8         reserved_at_10[0x10];
5129
5130         u8         reserved_at_20[0x10];
5131         u8         op_mod[0x10];
5132
5133         u8         other_vport[0x1];
5134         u8         reserved_at_41[0xb];
5135         u8         port_num[0x4];
5136         u8         vport_number[0x10];
5137
5138         u8         reserved_at_60[0x10];
5139         u8         pkey_index[0x10];
5140 };
5141
5142 enum {
5143         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
5144         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
5145         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5146 };
5147
5148 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5149         u8         status[0x8];
5150         u8         reserved_at_8[0x18];
5151
5152         u8         syndrome[0x20];
5153
5154         u8         reserved_at_40[0x20];
5155
5156         u8         gids_num[0x10];
5157         u8         reserved_at_70[0x10];
5158
5159         struct mlx5_ifc_array128_auto_bits gid[0];
5160 };
5161
5162 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5163         u8         opcode[0x10];
5164         u8         reserved_at_10[0x10];
5165
5166         u8         reserved_at_20[0x10];
5167         u8         op_mod[0x10];
5168
5169         u8         other_vport[0x1];
5170         u8         reserved_at_41[0xb];
5171         u8         port_num[0x4];
5172         u8         vport_number[0x10];
5173
5174         u8         reserved_at_60[0x10];
5175         u8         gid_index[0x10];
5176 };
5177
5178 struct mlx5_ifc_query_hca_vport_context_out_bits {
5179         u8         status[0x8];
5180         u8         reserved_at_8[0x18];
5181
5182         u8         syndrome[0x20];
5183
5184         u8         reserved_at_40[0x40];
5185
5186         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5187 };
5188
5189 struct mlx5_ifc_query_hca_vport_context_in_bits {
5190         u8         opcode[0x10];
5191         u8         reserved_at_10[0x10];
5192
5193         u8         reserved_at_20[0x10];
5194         u8         op_mod[0x10];
5195
5196         u8         other_vport[0x1];
5197         u8         reserved_at_41[0xb];
5198         u8         port_num[0x4];
5199         u8         vport_number[0x10];
5200
5201         u8         reserved_at_60[0x20];
5202 };
5203
5204 struct mlx5_ifc_query_hca_cap_out_bits {
5205         u8         status[0x8];
5206         u8         reserved_at_8[0x18];
5207
5208         u8         syndrome[0x20];
5209
5210         u8         reserved_at_40[0x40];
5211
5212         union mlx5_ifc_hca_cap_union_bits capability;
5213 };
5214
5215 struct mlx5_ifc_query_hca_cap_in_bits {
5216         u8         opcode[0x10];
5217         u8         reserved_at_10[0x10];
5218
5219         u8         reserved_at_20[0x10];
5220         u8         op_mod[0x10];
5221
5222         u8         other_function[0x1];
5223         u8         reserved_at_41[0xf];
5224         u8         function_id[0x10];
5225
5226         u8         reserved_at_60[0x20];
5227 };
5228
5229 struct mlx5_ifc_other_hca_cap_bits {
5230         u8         roce[0x1];
5231         u8         reserved_at_1[0x27f];
5232 };
5233
5234 struct mlx5_ifc_query_other_hca_cap_out_bits {
5235         u8         status[0x8];
5236         u8         reserved_at_8[0x18];
5237
5238         u8         syndrome[0x20];
5239
5240         u8         reserved_at_40[0x40];
5241
5242         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5243 };
5244
5245 struct mlx5_ifc_query_other_hca_cap_in_bits {
5246         u8         opcode[0x10];
5247         u8         reserved_at_10[0x10];
5248
5249         u8         reserved_at_20[0x10];
5250         u8         op_mod[0x10];
5251
5252         u8         reserved_at_40[0x10];
5253         u8         function_id[0x10];
5254
5255         u8         reserved_at_60[0x20];
5256 };
5257
5258 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5259         u8         status[0x8];
5260         u8         reserved_at_8[0x18];
5261
5262         u8         syndrome[0x20];
5263
5264         u8         reserved_at_40[0x40];
5265 };
5266
5267 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5268         u8         opcode[0x10];
5269         u8         reserved_at_10[0x10];
5270
5271         u8         reserved_at_20[0x10];
5272         u8         op_mod[0x10];
5273
5274         u8         reserved_at_40[0x10];
5275         u8         function_id[0x10];
5276         u8         field_select[0x20];
5277
5278         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5279 };
5280
5281 struct mlx5_ifc_flow_table_context_bits {
5282         u8         reformat_en[0x1];
5283         u8         decap_en[0x1];
5284         u8         sw_owner[0x1];
5285         u8         termination_table[0x1];
5286         u8         table_miss_action[0x4];
5287         u8         level[0x8];
5288         u8         reserved_at_10[0x8];
5289         u8         log_size[0x8];
5290
5291         u8         reserved_at_20[0x8];
5292         u8         table_miss_id[0x18];
5293
5294         u8         reserved_at_40[0x8];
5295         u8         lag_master_next_table_id[0x18];
5296
5297         u8         reserved_at_60[0x60];
5298
5299         u8         sw_owner_icm_root_1[0x40];
5300
5301         u8         sw_owner_icm_root_0[0x40];
5302
5303 };
5304
5305 struct mlx5_ifc_query_flow_table_out_bits {
5306         u8         status[0x8];
5307         u8         reserved_at_8[0x18];
5308
5309         u8         syndrome[0x20];
5310
5311         u8         reserved_at_40[0x80];
5312
5313         struct mlx5_ifc_flow_table_context_bits flow_table_context;
5314 };
5315
5316 struct mlx5_ifc_query_flow_table_in_bits {
5317         u8         opcode[0x10];
5318         u8         reserved_at_10[0x10];
5319
5320         u8         reserved_at_20[0x10];
5321         u8         op_mod[0x10];
5322
5323         u8         reserved_at_40[0x40];
5324
5325         u8         table_type[0x8];
5326         u8         reserved_at_88[0x18];
5327
5328         u8         reserved_at_a0[0x8];
5329         u8         table_id[0x18];
5330
5331         u8         reserved_at_c0[0x140];
5332 };
5333
5334 struct mlx5_ifc_query_fte_out_bits {
5335         u8         status[0x8];
5336         u8         reserved_at_8[0x18];
5337
5338         u8         syndrome[0x20];
5339
5340         u8         reserved_at_40[0x1c0];
5341
5342         struct mlx5_ifc_flow_context_bits flow_context;
5343 };
5344
5345 struct mlx5_ifc_query_fte_in_bits {
5346         u8         opcode[0x10];
5347         u8         reserved_at_10[0x10];
5348
5349         u8         reserved_at_20[0x10];
5350         u8         op_mod[0x10];
5351
5352         u8         reserved_at_40[0x40];
5353
5354         u8         table_type[0x8];
5355         u8         reserved_at_88[0x18];
5356
5357         u8         reserved_at_a0[0x8];
5358         u8         table_id[0x18];
5359
5360         u8         reserved_at_c0[0x40];
5361
5362         u8         flow_index[0x20];
5363
5364         u8         reserved_at_120[0xe0];
5365 };
5366
5367 enum {
5368         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5369         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5370         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5371         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5372         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5373 };
5374
5375 struct mlx5_ifc_query_flow_group_out_bits {
5376         u8         status[0x8];
5377         u8         reserved_at_8[0x18];
5378
5379         u8         syndrome[0x20];
5380
5381         u8         reserved_at_40[0xa0];
5382
5383         u8         start_flow_index[0x20];
5384
5385         u8         reserved_at_100[0x20];
5386
5387         u8         end_flow_index[0x20];
5388
5389         u8         reserved_at_140[0xa0];
5390
5391         u8         reserved_at_1e0[0x18];
5392         u8         match_criteria_enable[0x8];
5393
5394         struct mlx5_ifc_fte_match_param_bits match_criteria;
5395
5396         u8         reserved_at_1200[0xe00];
5397 };
5398
5399 struct mlx5_ifc_query_flow_group_in_bits {
5400         u8         opcode[0x10];
5401         u8         reserved_at_10[0x10];
5402
5403         u8         reserved_at_20[0x10];
5404         u8         op_mod[0x10];
5405
5406         u8         reserved_at_40[0x40];
5407
5408         u8         table_type[0x8];
5409         u8         reserved_at_88[0x18];
5410
5411         u8         reserved_at_a0[0x8];
5412         u8         table_id[0x18];
5413
5414         u8         group_id[0x20];
5415
5416         u8         reserved_at_e0[0x120];
5417 };
5418
5419 struct mlx5_ifc_query_flow_counter_out_bits {
5420         u8         status[0x8];
5421         u8         reserved_at_8[0x18];
5422
5423         u8         syndrome[0x20];
5424
5425         u8         reserved_at_40[0x40];
5426
5427         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
5428 };
5429
5430 struct mlx5_ifc_query_flow_counter_in_bits {
5431         u8         opcode[0x10];
5432         u8         reserved_at_10[0x10];
5433
5434         u8         reserved_at_20[0x10];
5435         u8         op_mod[0x10];
5436
5437         u8         reserved_at_40[0x80];
5438
5439         u8         clear[0x1];
5440         u8         reserved_at_c1[0xf];
5441         u8         num_of_counters[0x10];
5442
5443         u8         flow_counter_id[0x20];
5444 };
5445
5446 struct mlx5_ifc_query_esw_vport_context_out_bits {
5447         u8         status[0x8];
5448         u8         reserved_at_8[0x18];
5449
5450         u8         syndrome[0x20];
5451
5452         u8         reserved_at_40[0x40];
5453
5454         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5455 };
5456
5457 struct mlx5_ifc_query_esw_vport_context_in_bits {
5458         u8         opcode[0x10];
5459         u8         reserved_at_10[0x10];
5460
5461         u8         reserved_at_20[0x10];
5462         u8         op_mod[0x10];
5463
5464         u8         other_vport[0x1];
5465         u8         reserved_at_41[0xf];
5466         u8         vport_number[0x10];
5467
5468         u8         reserved_at_60[0x20];
5469 };
5470
5471 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5472         u8         status[0x8];
5473         u8         reserved_at_8[0x18];
5474
5475         u8         syndrome[0x20];
5476
5477         u8         reserved_at_40[0x40];
5478 };
5479
5480 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5481         u8         reserved_at_0[0x1b];
5482         u8         fdb_to_vport_reg_c_id[0x1];
5483         u8         vport_cvlan_insert[0x1];
5484         u8         vport_svlan_insert[0x1];
5485         u8         vport_cvlan_strip[0x1];
5486         u8         vport_svlan_strip[0x1];
5487 };
5488
5489 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5490         u8         opcode[0x10];
5491         u8         reserved_at_10[0x10];
5492
5493         u8         reserved_at_20[0x10];
5494         u8         op_mod[0x10];
5495
5496         u8         other_vport[0x1];
5497         u8         reserved_at_41[0xf];
5498         u8         vport_number[0x10];
5499
5500         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5501
5502         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5503 };
5504
5505 struct mlx5_ifc_query_eq_out_bits {
5506         u8         status[0x8];
5507         u8         reserved_at_8[0x18];
5508
5509         u8         syndrome[0x20];
5510
5511         u8         reserved_at_40[0x40];
5512
5513         struct mlx5_ifc_eqc_bits eq_context_entry;
5514
5515         u8         reserved_at_280[0x40];
5516
5517         u8         event_bitmask[0x40];
5518
5519         u8         reserved_at_300[0x580];
5520
5521         u8         pas[0][0x40];
5522 };
5523
5524 struct mlx5_ifc_query_eq_in_bits {
5525         u8         opcode[0x10];
5526         u8         reserved_at_10[0x10];
5527
5528         u8         reserved_at_20[0x10];
5529         u8         op_mod[0x10];
5530
5531         u8         reserved_at_40[0x18];
5532         u8         eq_number[0x8];
5533
5534         u8         reserved_at_60[0x20];
5535 };
5536
5537 struct mlx5_ifc_packet_reformat_context_in_bits {
5538         u8         reserved_at_0[0x5];
5539         u8         reformat_type[0x3];
5540         u8         reserved_at_8[0xe];
5541         u8         reformat_data_size[0xa];
5542
5543         u8         reserved_at_20[0x10];
5544         u8         reformat_data[2][0x8];
5545
5546         u8         more_reformat_data[0][0x8];
5547 };
5548
5549 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5550         u8         status[0x8];
5551         u8         reserved_at_8[0x18];
5552
5553         u8         syndrome[0x20];
5554
5555         u8         reserved_at_40[0xa0];
5556
5557         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
5558 };
5559
5560 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5561         u8         opcode[0x10];
5562         u8         reserved_at_10[0x10];
5563
5564         u8         reserved_at_20[0x10];
5565         u8         op_mod[0x10];
5566
5567         u8         packet_reformat_id[0x20];
5568
5569         u8         reserved_at_60[0xa0];
5570 };
5571
5572 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5573         u8         status[0x8];
5574         u8         reserved_at_8[0x18];
5575
5576         u8         syndrome[0x20];
5577
5578         u8         packet_reformat_id[0x20];
5579
5580         u8         reserved_at_60[0x20];
5581 };
5582
5583 enum mlx5_reformat_ctx_type {
5584         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5585         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5586         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5587         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5588         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5589 };
5590
5591 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5592         u8         opcode[0x10];
5593         u8         reserved_at_10[0x10];
5594
5595         u8         reserved_at_20[0x10];
5596         u8         op_mod[0x10];
5597
5598         u8         reserved_at_40[0xa0];
5599
5600         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5601 };
5602
5603 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5604         u8         status[0x8];
5605         u8         reserved_at_8[0x18];
5606
5607         u8         syndrome[0x20];
5608
5609         u8         reserved_at_40[0x40];
5610 };
5611
5612 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5613         u8         opcode[0x10];
5614         u8         reserved_at_10[0x10];
5615
5616         u8         reserved_20[0x10];
5617         u8         op_mod[0x10];
5618
5619         u8         packet_reformat_id[0x20];
5620
5621         u8         reserved_60[0x20];
5622 };
5623
5624 struct mlx5_ifc_set_action_in_bits {
5625         u8         action_type[0x4];
5626         u8         field[0xc];
5627         u8         reserved_at_10[0x3];
5628         u8         offset[0x5];
5629         u8         reserved_at_18[0x3];
5630         u8         length[0x5];
5631
5632         u8         data[0x20];
5633 };
5634
5635 struct mlx5_ifc_add_action_in_bits {
5636         u8         action_type[0x4];
5637         u8         field[0xc];
5638         u8         reserved_at_10[0x10];
5639
5640         u8         data[0x20];
5641 };
5642
5643 struct mlx5_ifc_copy_action_in_bits {
5644         u8         action_type[0x4];
5645         u8         src_field[0xc];
5646         u8         reserved_at_10[0x3];
5647         u8         src_offset[0x5];
5648         u8         reserved_at_18[0x3];
5649         u8         length[0x5];
5650
5651         u8         reserved_at_20[0x4];
5652         u8         dst_field[0xc];
5653         u8         reserved_at_30[0x3];
5654         u8         dst_offset[0x5];
5655         u8         reserved_at_38[0x8];
5656 };
5657
5658 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
5659         struct mlx5_ifc_set_action_in_bits set_action_in;
5660         struct mlx5_ifc_add_action_in_bits add_action_in;
5661         struct mlx5_ifc_copy_action_in_bits copy_action_in;
5662         u8         reserved_at_0[0x40];
5663 };
5664
5665 enum {
5666         MLX5_ACTION_TYPE_SET   = 0x1,
5667         MLX5_ACTION_TYPE_ADD   = 0x2,
5668         MLX5_ACTION_TYPE_COPY  = 0x3,
5669 };
5670
5671 enum {
5672         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
5673         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
5674         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
5675         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
5676         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
5677         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
5678         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
5679         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
5680         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
5681         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
5682         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
5683         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
5684         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
5685         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
5686         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
5687         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
5688         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
5689         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
5690         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
5691         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
5692         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
5693         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
5694         MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
5695         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5696         MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
5697         MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
5698         MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
5699         MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
5700         MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
5701         MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
5702         MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
5703         MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
5704         MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
5705         MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
5706         MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
5707         MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
5708 };
5709
5710 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5711         u8         status[0x8];
5712         u8         reserved_at_8[0x18];
5713
5714         u8         syndrome[0x20];
5715
5716         u8         modify_header_id[0x20];
5717
5718         u8         reserved_at_60[0x20];
5719 };
5720
5721 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5722         u8         opcode[0x10];
5723         u8         reserved_at_10[0x10];
5724
5725         u8         reserved_at_20[0x10];
5726         u8         op_mod[0x10];
5727
5728         u8         reserved_at_40[0x20];
5729
5730         u8         table_type[0x8];
5731         u8         reserved_at_68[0x10];
5732         u8         num_of_actions[0x8];
5733
5734         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
5735 };
5736
5737 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5738         u8         status[0x8];
5739         u8         reserved_at_8[0x18];
5740
5741         u8         syndrome[0x20];
5742
5743         u8         reserved_at_40[0x40];
5744 };
5745
5746 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5747         u8         opcode[0x10];
5748         u8         reserved_at_10[0x10];
5749
5750         u8         reserved_at_20[0x10];
5751         u8         op_mod[0x10];
5752
5753         u8         modify_header_id[0x20];
5754
5755         u8         reserved_at_60[0x20];
5756 };
5757
5758 struct mlx5_ifc_query_dct_out_bits {
5759         u8         status[0x8];
5760         u8         reserved_at_8[0x18];
5761
5762         u8         syndrome[0x20];
5763
5764         u8         reserved_at_40[0x40];
5765
5766         struct mlx5_ifc_dctc_bits dct_context_entry;
5767
5768         u8         reserved_at_280[0x180];
5769 };
5770
5771 struct mlx5_ifc_query_dct_in_bits {
5772         u8         opcode[0x10];
5773         u8         reserved_at_10[0x10];
5774
5775         u8         reserved_at_20[0x10];
5776         u8         op_mod[0x10];
5777
5778         u8         reserved_at_40[0x8];
5779         u8         dctn[0x18];
5780
5781         u8         reserved_at_60[0x20];
5782 };
5783
5784 struct mlx5_ifc_query_cq_out_bits {
5785         u8         status[0x8];
5786         u8         reserved_at_8[0x18];
5787
5788         u8         syndrome[0x20];
5789
5790         u8         reserved_at_40[0x40];
5791
5792         struct mlx5_ifc_cqc_bits cq_context;
5793
5794         u8         reserved_at_280[0x600];
5795
5796         u8         pas[0][0x40];
5797 };
5798
5799 struct mlx5_ifc_query_cq_in_bits {
5800         u8         opcode[0x10];
5801         u8         reserved_at_10[0x10];
5802
5803         u8         reserved_at_20[0x10];
5804         u8         op_mod[0x10];
5805
5806         u8         reserved_at_40[0x8];
5807         u8         cqn[0x18];
5808
5809         u8         reserved_at_60[0x20];
5810 };
5811
5812 struct mlx5_ifc_query_cong_status_out_bits {
5813         u8         status[0x8];
5814         u8         reserved_at_8[0x18];
5815
5816         u8         syndrome[0x20];
5817
5818         u8         reserved_at_40[0x20];
5819
5820         u8         enable[0x1];
5821         u8         tag_enable[0x1];
5822         u8         reserved_at_62[0x1e];
5823 };
5824
5825 struct mlx5_ifc_query_cong_status_in_bits {
5826         u8         opcode[0x10];
5827         u8         reserved_at_10[0x10];
5828
5829         u8         reserved_at_20[0x10];
5830         u8         op_mod[0x10];
5831
5832         u8         reserved_at_40[0x18];
5833         u8         priority[0x4];
5834         u8         cong_protocol[0x4];
5835
5836         u8         reserved_at_60[0x20];
5837 };
5838
5839 struct mlx5_ifc_query_cong_statistics_out_bits {
5840         u8         status[0x8];
5841         u8         reserved_at_8[0x18];
5842
5843         u8         syndrome[0x20];
5844
5845         u8         reserved_at_40[0x40];
5846
5847         u8         rp_cur_flows[0x20];
5848
5849         u8         sum_flows[0x20];
5850
5851         u8         rp_cnp_ignored_high[0x20];
5852
5853         u8         rp_cnp_ignored_low[0x20];
5854
5855         u8         rp_cnp_handled_high[0x20];
5856
5857         u8         rp_cnp_handled_low[0x20];
5858
5859         u8         reserved_at_140[0x100];
5860
5861         u8         time_stamp_high[0x20];
5862
5863         u8         time_stamp_low[0x20];
5864
5865         u8         accumulators_period[0x20];
5866
5867         u8         np_ecn_marked_roce_packets_high[0x20];
5868
5869         u8         np_ecn_marked_roce_packets_low[0x20];
5870
5871         u8         np_cnp_sent_high[0x20];
5872
5873         u8         np_cnp_sent_low[0x20];
5874
5875         u8         reserved_at_320[0x560];
5876 };
5877
5878 struct mlx5_ifc_query_cong_statistics_in_bits {
5879         u8         opcode[0x10];
5880         u8         reserved_at_10[0x10];
5881
5882         u8         reserved_at_20[0x10];
5883         u8         op_mod[0x10];
5884
5885         u8         clear[0x1];
5886         u8         reserved_at_41[0x1f];
5887
5888         u8         reserved_at_60[0x20];
5889 };
5890
5891 struct mlx5_ifc_query_cong_params_out_bits {
5892         u8         status[0x8];
5893         u8         reserved_at_8[0x18];
5894
5895         u8         syndrome[0x20];
5896
5897         u8         reserved_at_40[0x40];
5898
5899         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5900 };
5901
5902 struct mlx5_ifc_query_cong_params_in_bits {
5903         u8         opcode[0x10];
5904         u8         reserved_at_10[0x10];
5905
5906         u8         reserved_at_20[0x10];
5907         u8         op_mod[0x10];
5908
5909         u8         reserved_at_40[0x1c];
5910         u8         cong_protocol[0x4];
5911
5912         u8         reserved_at_60[0x20];
5913 };
5914
5915 struct mlx5_ifc_query_adapter_out_bits {
5916         u8         status[0x8];
5917         u8         reserved_at_8[0x18];
5918
5919         u8         syndrome[0x20];
5920
5921         u8         reserved_at_40[0x40];
5922
5923         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5924 };
5925
5926 struct mlx5_ifc_query_adapter_in_bits {
5927         u8         opcode[0x10];
5928         u8         reserved_at_10[0x10];
5929
5930         u8         reserved_at_20[0x10];
5931         u8         op_mod[0x10];
5932
5933         u8         reserved_at_40[0x40];
5934 };
5935
5936 struct mlx5_ifc_qp_2rst_out_bits {
5937         u8         status[0x8];
5938         u8         reserved_at_8[0x18];
5939
5940         u8         syndrome[0x20];
5941
5942         u8         reserved_at_40[0x40];
5943 };
5944
5945 struct mlx5_ifc_qp_2rst_in_bits {
5946         u8         opcode[0x10];
5947         u8         uid[0x10];
5948
5949         u8         reserved_at_20[0x10];
5950         u8         op_mod[0x10];
5951
5952         u8         reserved_at_40[0x8];
5953         u8         qpn[0x18];
5954
5955         u8         reserved_at_60[0x20];
5956 };
5957
5958 struct mlx5_ifc_qp_2err_out_bits {
5959         u8         status[0x8];
5960         u8         reserved_at_8[0x18];
5961
5962         u8         syndrome[0x20];
5963
5964         u8         reserved_at_40[0x40];
5965 };
5966
5967 struct mlx5_ifc_qp_2err_in_bits {
5968         u8         opcode[0x10];
5969         u8         uid[0x10];
5970
5971         u8         reserved_at_20[0x10];
5972         u8         op_mod[0x10];
5973
5974         u8         reserved_at_40[0x8];
5975         u8         qpn[0x18];
5976
5977         u8         reserved_at_60[0x20];
5978 };
5979
5980 struct mlx5_ifc_page_fault_resume_out_bits {
5981         u8         status[0x8];
5982         u8         reserved_at_8[0x18];
5983
5984         u8         syndrome[0x20];
5985
5986         u8         reserved_at_40[0x40];
5987 };
5988
5989 struct mlx5_ifc_page_fault_resume_in_bits {
5990         u8         opcode[0x10];
5991         u8         reserved_at_10[0x10];
5992
5993         u8         reserved_at_20[0x10];
5994         u8         op_mod[0x10];
5995
5996         u8         error[0x1];
5997         u8         reserved_at_41[0x4];
5998         u8         page_fault_type[0x3];
5999         u8         wq_number[0x18];
6000
6001         u8         reserved_at_60[0x8];
6002         u8         token[0x18];
6003 };
6004
6005 struct mlx5_ifc_nop_out_bits {
6006         u8         status[0x8];
6007         u8         reserved_at_8[0x18];
6008
6009         u8         syndrome[0x20];
6010
6011         u8         reserved_at_40[0x40];
6012 };
6013
6014 struct mlx5_ifc_nop_in_bits {
6015         u8         opcode[0x10];
6016         u8         reserved_at_10[0x10];
6017
6018         u8         reserved_at_20[0x10];
6019         u8         op_mod[0x10];
6020
6021         u8         reserved_at_40[0x40];
6022 };
6023
6024 struct mlx5_ifc_modify_vport_state_out_bits {
6025         u8         status[0x8];
6026         u8         reserved_at_8[0x18];
6027
6028         u8         syndrome[0x20];
6029
6030         u8         reserved_at_40[0x40];
6031 };
6032
6033 struct mlx5_ifc_modify_vport_state_in_bits {
6034         u8         opcode[0x10];
6035         u8         reserved_at_10[0x10];
6036
6037         u8         reserved_at_20[0x10];
6038         u8         op_mod[0x10];
6039
6040         u8         other_vport[0x1];
6041         u8         reserved_at_41[0xf];
6042         u8         vport_number[0x10];
6043
6044         u8         reserved_at_60[0x18];
6045         u8         admin_state[0x4];
6046         u8         reserved_at_7c[0x4];
6047 };
6048
6049 struct mlx5_ifc_modify_tis_out_bits {
6050         u8         status[0x8];
6051         u8         reserved_at_8[0x18];
6052
6053         u8         syndrome[0x20];
6054
6055         u8         reserved_at_40[0x40];
6056 };
6057
6058 struct mlx5_ifc_modify_tis_bitmask_bits {
6059         u8         reserved_at_0[0x20];
6060
6061         u8         reserved_at_20[0x1d];
6062         u8         lag_tx_port_affinity[0x1];
6063         u8         strict_lag_tx_port_affinity[0x1];
6064         u8         prio[0x1];
6065 };
6066
6067 struct mlx5_ifc_modify_tis_in_bits {
6068         u8         opcode[0x10];
6069         u8         uid[0x10];
6070
6071         u8         reserved_at_20[0x10];
6072         u8         op_mod[0x10];
6073
6074         u8         reserved_at_40[0x8];
6075         u8         tisn[0x18];
6076
6077         u8         reserved_at_60[0x20];
6078
6079         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6080
6081         u8         reserved_at_c0[0x40];
6082
6083         struct mlx5_ifc_tisc_bits ctx;
6084 };
6085
6086 struct mlx5_ifc_modify_tir_bitmask_bits {
6087         u8         reserved_at_0[0x20];
6088
6089         u8         reserved_at_20[0x1b];
6090         u8         self_lb_en[0x1];
6091         u8         reserved_at_3c[0x1];
6092         u8         hash[0x1];
6093         u8         reserved_at_3e[0x1];
6094         u8         lro[0x1];
6095 };
6096
6097 struct mlx5_ifc_modify_tir_out_bits {
6098         u8         status[0x8];
6099         u8         reserved_at_8[0x18];
6100
6101         u8         syndrome[0x20];
6102
6103         u8         reserved_at_40[0x40];
6104 };
6105
6106 struct mlx5_ifc_modify_tir_in_bits {
6107         u8         opcode[0x10];
6108         u8         uid[0x10];
6109
6110         u8         reserved_at_20[0x10];
6111         u8         op_mod[0x10];
6112
6113         u8         reserved_at_40[0x8];
6114         u8         tirn[0x18];
6115
6116         u8         reserved_at_60[0x20];
6117
6118         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
6119
6120         u8         reserved_at_c0[0x40];
6121
6122         struct mlx5_ifc_tirc_bits ctx;
6123 };
6124
6125 struct mlx5_ifc_modify_sq_out_bits {
6126         u8         status[0x8];
6127         u8         reserved_at_8[0x18];
6128
6129         u8         syndrome[0x20];
6130
6131         u8         reserved_at_40[0x40];
6132 };
6133
6134 struct mlx5_ifc_modify_sq_in_bits {
6135         u8         opcode[0x10];
6136         u8         uid[0x10];
6137
6138         u8         reserved_at_20[0x10];
6139         u8         op_mod[0x10];
6140
6141         u8         sq_state[0x4];
6142         u8         reserved_at_44[0x4];
6143         u8         sqn[0x18];
6144
6145         u8         reserved_at_60[0x20];
6146
6147         u8         modify_bitmask[0x40];
6148
6149         u8         reserved_at_c0[0x40];
6150
6151         struct mlx5_ifc_sqc_bits ctx;
6152 };
6153
6154 struct mlx5_ifc_modify_scheduling_element_out_bits {
6155         u8         status[0x8];
6156         u8         reserved_at_8[0x18];
6157
6158         u8         syndrome[0x20];
6159
6160         u8         reserved_at_40[0x1c0];
6161 };
6162
6163 enum {
6164         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6165         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6166 };
6167
6168 struct mlx5_ifc_modify_scheduling_element_in_bits {
6169         u8         opcode[0x10];
6170         u8         reserved_at_10[0x10];
6171
6172         u8         reserved_at_20[0x10];
6173         u8         op_mod[0x10];
6174
6175         u8         scheduling_hierarchy[0x8];
6176         u8         reserved_at_48[0x18];
6177
6178         u8         scheduling_element_id[0x20];
6179
6180         u8         reserved_at_80[0x20];
6181
6182         u8         modify_bitmask[0x20];
6183
6184         u8         reserved_at_c0[0x40];
6185
6186         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6187
6188         u8         reserved_at_300[0x100];
6189 };
6190
6191 struct mlx5_ifc_modify_rqt_out_bits {
6192         u8         status[0x8];
6193         u8         reserved_at_8[0x18];
6194
6195         u8         syndrome[0x20];
6196
6197         u8         reserved_at_40[0x40];
6198 };
6199
6200 struct mlx5_ifc_rqt_bitmask_bits {
6201         u8         reserved_at_0[0x20];
6202
6203         u8         reserved_at_20[0x1f];
6204         u8         rqn_list[0x1];
6205 };
6206
6207 struct mlx5_ifc_modify_rqt_in_bits {
6208         u8         opcode[0x10];
6209         u8         uid[0x10];
6210
6211         u8         reserved_at_20[0x10];
6212         u8         op_mod[0x10];
6213
6214         u8         reserved_at_40[0x8];
6215         u8         rqtn[0x18];
6216
6217         u8         reserved_at_60[0x20];
6218
6219         struct mlx5_ifc_rqt_bitmask_bits bitmask;
6220
6221         u8         reserved_at_c0[0x40];
6222
6223         struct mlx5_ifc_rqtc_bits ctx;
6224 };
6225
6226 struct mlx5_ifc_modify_rq_out_bits {
6227         u8         status[0x8];
6228         u8         reserved_at_8[0x18];
6229
6230         u8         syndrome[0x20];
6231
6232         u8         reserved_at_40[0x40];
6233 };
6234
6235 enum {
6236         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6237         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6238         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6239 };
6240
6241 struct mlx5_ifc_modify_rq_in_bits {
6242         u8         opcode[0x10];
6243         u8         uid[0x10];
6244
6245         u8         reserved_at_20[0x10];
6246         u8         op_mod[0x10];
6247
6248         u8         rq_state[0x4];
6249         u8         reserved_at_44[0x4];
6250         u8         rqn[0x18];
6251
6252         u8         reserved_at_60[0x20];
6253
6254         u8         modify_bitmask[0x40];
6255
6256         u8         reserved_at_c0[0x40];
6257
6258         struct mlx5_ifc_rqc_bits ctx;
6259 };
6260
6261 struct mlx5_ifc_modify_rmp_out_bits {
6262         u8         status[0x8];
6263         u8         reserved_at_8[0x18];
6264
6265         u8         syndrome[0x20];
6266
6267         u8         reserved_at_40[0x40];
6268 };
6269
6270 struct mlx5_ifc_rmp_bitmask_bits {
6271         u8         reserved_at_0[0x20];
6272
6273         u8         reserved_at_20[0x1f];
6274         u8         lwm[0x1];
6275 };
6276
6277 struct mlx5_ifc_modify_rmp_in_bits {
6278         u8         opcode[0x10];
6279         u8         uid[0x10];
6280
6281         u8         reserved_at_20[0x10];
6282         u8         op_mod[0x10];
6283
6284         u8         rmp_state[0x4];
6285         u8         reserved_at_44[0x4];
6286         u8         rmpn[0x18];
6287
6288         u8         reserved_at_60[0x20];
6289
6290         struct mlx5_ifc_rmp_bitmask_bits bitmask;
6291
6292         u8         reserved_at_c0[0x40];
6293
6294         struct mlx5_ifc_rmpc_bits ctx;
6295 };
6296
6297 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6298         u8         status[0x8];
6299         u8         reserved_at_8[0x18];
6300
6301         u8         syndrome[0x20];
6302
6303         u8         reserved_at_40[0x40];
6304 };
6305
6306 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6307         u8         reserved_at_0[0x12];
6308         u8         affiliation[0x1];
6309         u8         reserved_at_13[0x1];
6310         u8         disable_uc_local_lb[0x1];
6311         u8         disable_mc_local_lb[0x1];
6312         u8         node_guid[0x1];
6313         u8         port_guid[0x1];
6314         u8         min_inline[0x1];
6315         u8         mtu[0x1];
6316         u8         change_event[0x1];
6317         u8         promisc[0x1];
6318         u8         permanent_address[0x1];
6319         u8         addresses_list[0x1];
6320         u8         roce_en[0x1];
6321         u8         reserved_at_1f[0x1];
6322 };
6323
6324 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6325         u8         opcode[0x10];
6326         u8         reserved_at_10[0x10];
6327
6328         u8         reserved_at_20[0x10];
6329         u8         op_mod[0x10];
6330
6331         u8         other_vport[0x1];
6332         u8         reserved_at_41[0xf];
6333         u8         vport_number[0x10];
6334
6335         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6336
6337         u8         reserved_at_80[0x780];
6338
6339         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6340 };
6341
6342 struct mlx5_ifc_modify_hca_vport_context_out_bits {
6343         u8         status[0x8];
6344         u8         reserved_at_8[0x18];
6345
6346         u8         syndrome[0x20];
6347
6348         u8         reserved_at_40[0x40];
6349 };
6350
6351 struct mlx5_ifc_modify_hca_vport_context_in_bits {
6352         u8         opcode[0x10];
6353         u8         reserved_at_10[0x10];
6354
6355         u8         reserved_at_20[0x10];
6356         u8         op_mod[0x10];
6357
6358         u8         other_vport[0x1];
6359         u8         reserved_at_41[0xb];
6360         u8         port_num[0x4];
6361         u8         vport_number[0x10];
6362
6363         u8         reserved_at_60[0x20];
6364
6365         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6366 };
6367
6368 struct mlx5_ifc_modify_cq_out_bits {
6369         u8         status[0x8];
6370         u8         reserved_at_8[0x18];
6371
6372         u8         syndrome[0x20];
6373
6374         u8         reserved_at_40[0x40];
6375 };
6376
6377 enum {
6378         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
6379         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
6380 };
6381
6382 struct mlx5_ifc_modify_cq_in_bits {
6383         u8         opcode[0x10];
6384         u8         uid[0x10];
6385
6386         u8         reserved_at_20[0x10];
6387         u8         op_mod[0x10];
6388
6389         u8         reserved_at_40[0x8];
6390         u8         cqn[0x18];
6391
6392         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6393
6394         struct mlx5_ifc_cqc_bits cq_context;
6395
6396         u8         reserved_at_280[0x60];
6397
6398         u8         cq_umem_valid[0x1];
6399         u8         reserved_at_2e1[0x1f];
6400
6401         u8         reserved_at_300[0x580];
6402
6403         u8         pas[0][0x40];
6404 };
6405
6406 struct mlx5_ifc_modify_cong_status_out_bits {
6407         u8         status[0x8];
6408         u8         reserved_at_8[0x18];
6409
6410         u8         syndrome[0x20];
6411
6412         u8         reserved_at_40[0x40];
6413 };
6414
6415 struct mlx5_ifc_modify_cong_status_in_bits {
6416         u8         opcode[0x10];
6417         u8         reserved_at_10[0x10];
6418
6419         u8         reserved_at_20[0x10];
6420         u8         op_mod[0x10];
6421
6422         u8         reserved_at_40[0x18];
6423         u8         priority[0x4];
6424         u8         cong_protocol[0x4];
6425
6426         u8         enable[0x1];
6427         u8         tag_enable[0x1];
6428         u8         reserved_at_62[0x1e];
6429 };
6430
6431 struct mlx5_ifc_modify_cong_params_out_bits {
6432         u8         status[0x8];
6433         u8         reserved_at_8[0x18];
6434
6435         u8         syndrome[0x20];
6436
6437         u8         reserved_at_40[0x40];
6438 };
6439
6440 struct mlx5_ifc_modify_cong_params_in_bits {
6441         u8         opcode[0x10];
6442         u8         reserved_at_10[0x10];
6443
6444         u8         reserved_at_20[0x10];
6445         u8         op_mod[0x10];
6446
6447         u8         reserved_at_40[0x1c];
6448         u8         cong_protocol[0x4];
6449
6450         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6451
6452         u8         reserved_at_80[0x80];
6453
6454         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6455 };
6456
6457 struct mlx5_ifc_manage_pages_out_bits {
6458         u8         status[0x8];
6459         u8         reserved_at_8[0x18];
6460
6461         u8         syndrome[0x20];
6462
6463         u8         output_num_entries[0x20];
6464
6465         u8         reserved_at_60[0x20];
6466
6467         u8         pas[0][0x40];
6468 };
6469
6470 enum {
6471         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
6472         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
6473         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
6474 };
6475
6476 struct mlx5_ifc_manage_pages_in_bits {
6477         u8         opcode[0x10];
6478         u8         reserved_at_10[0x10];
6479
6480         u8         reserved_at_20[0x10];
6481         u8         op_mod[0x10];
6482
6483         u8         embedded_cpu_function[0x1];
6484         u8         reserved_at_41[0xf];
6485         u8         function_id[0x10];
6486
6487         u8         input_num_entries[0x20];
6488
6489         u8         pas[0][0x40];
6490 };
6491
6492 struct mlx5_ifc_mad_ifc_out_bits {
6493         u8         status[0x8];
6494         u8         reserved_at_8[0x18];
6495
6496         u8         syndrome[0x20];
6497
6498         u8         reserved_at_40[0x40];
6499
6500         u8         response_mad_packet[256][0x8];
6501 };
6502
6503 struct mlx5_ifc_mad_ifc_in_bits {
6504         u8         opcode[0x10];
6505         u8         reserved_at_10[0x10];
6506
6507         u8         reserved_at_20[0x10];
6508         u8         op_mod[0x10];
6509
6510         u8         remote_lid[0x10];
6511         u8         reserved_at_50[0x8];
6512         u8         port[0x8];
6513
6514         u8         reserved_at_60[0x20];
6515
6516         u8         mad[256][0x8];
6517 };
6518
6519 struct mlx5_ifc_init_hca_out_bits {
6520         u8         status[0x8];
6521         u8         reserved_at_8[0x18];
6522
6523         u8         syndrome[0x20];
6524
6525         u8         reserved_at_40[0x40];
6526 };
6527
6528 struct mlx5_ifc_init_hca_in_bits {
6529         u8         opcode[0x10];
6530         u8         reserved_at_10[0x10];
6531
6532         u8         reserved_at_20[0x10];
6533         u8         op_mod[0x10];
6534
6535         u8         reserved_at_40[0x40];
6536         u8         sw_owner_id[4][0x20];
6537 };
6538
6539 struct mlx5_ifc_init2rtr_qp_out_bits {
6540         u8         status[0x8];
6541         u8         reserved_at_8[0x18];
6542
6543         u8         syndrome[0x20];
6544
6545         u8         reserved_at_40[0x40];
6546 };
6547
6548 struct mlx5_ifc_init2rtr_qp_in_bits {
6549         u8         opcode[0x10];
6550         u8         uid[0x10];
6551
6552         u8         reserved_at_20[0x10];
6553         u8         op_mod[0x10];
6554
6555         u8         reserved_at_40[0x8];
6556         u8         qpn[0x18];
6557
6558         u8         reserved_at_60[0x20];
6559
6560         u8         opt_param_mask[0x20];
6561
6562         u8         reserved_at_a0[0x20];
6563
6564         struct mlx5_ifc_qpc_bits qpc;
6565
6566         u8         reserved_at_800[0x80];
6567 };
6568
6569 struct mlx5_ifc_init2init_qp_out_bits {
6570         u8         status[0x8];
6571         u8         reserved_at_8[0x18];
6572
6573         u8         syndrome[0x20];
6574
6575         u8         reserved_at_40[0x40];
6576 };
6577
6578 struct mlx5_ifc_init2init_qp_in_bits {
6579         u8         opcode[0x10];
6580         u8         uid[0x10];
6581
6582         u8         reserved_at_20[0x10];
6583         u8         op_mod[0x10];
6584
6585         u8         reserved_at_40[0x8];
6586         u8         qpn[0x18];
6587
6588         u8         reserved_at_60[0x20];
6589
6590         u8         opt_param_mask[0x20];
6591
6592         u8         reserved_at_a0[0x20];
6593
6594         struct mlx5_ifc_qpc_bits qpc;
6595
6596         u8         reserved_at_800[0x80];
6597 };
6598
6599 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6600         u8         status[0x8];
6601         u8         reserved_at_8[0x18];
6602
6603         u8         syndrome[0x20];
6604
6605         u8         reserved_at_40[0x40];
6606
6607         u8         packet_headers_log[128][0x8];
6608
6609         u8         packet_syndrome[64][0x8];
6610 };
6611
6612 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6613         u8         opcode[0x10];
6614         u8         reserved_at_10[0x10];
6615
6616         u8         reserved_at_20[0x10];
6617         u8         op_mod[0x10];
6618
6619         u8         reserved_at_40[0x40];
6620 };
6621
6622 struct mlx5_ifc_gen_eqe_in_bits {
6623         u8         opcode[0x10];
6624         u8         reserved_at_10[0x10];
6625
6626         u8         reserved_at_20[0x10];
6627         u8         op_mod[0x10];
6628
6629         u8         reserved_at_40[0x18];
6630         u8         eq_number[0x8];
6631
6632         u8         reserved_at_60[0x20];
6633
6634         u8         eqe[64][0x8];
6635 };
6636
6637 struct mlx5_ifc_gen_eq_out_bits {
6638         u8         status[0x8];
6639         u8         reserved_at_8[0x18];
6640
6641         u8         syndrome[0x20];
6642
6643         u8         reserved_at_40[0x40];
6644 };
6645
6646 struct mlx5_ifc_enable_hca_out_bits {
6647         u8         status[0x8];
6648         u8         reserved_at_8[0x18];
6649
6650         u8         syndrome[0x20];
6651
6652         u8         reserved_at_40[0x20];
6653 };
6654
6655 struct mlx5_ifc_enable_hca_in_bits {
6656         u8         opcode[0x10];
6657         u8         reserved_at_10[0x10];
6658
6659         u8         reserved_at_20[0x10];
6660         u8         op_mod[0x10];
6661
6662         u8         embedded_cpu_function[0x1];
6663         u8         reserved_at_41[0xf];
6664         u8         function_id[0x10];
6665
6666         u8         reserved_at_60[0x20];
6667 };
6668
6669 struct mlx5_ifc_drain_dct_out_bits {
6670         u8         status[0x8];
6671         u8         reserved_at_8[0x18];
6672
6673         u8         syndrome[0x20];
6674
6675         u8         reserved_at_40[0x40];
6676 };
6677
6678 struct mlx5_ifc_drain_dct_in_bits {
6679         u8         opcode[0x10];
6680         u8         uid[0x10];
6681
6682         u8         reserved_at_20[0x10];
6683         u8         op_mod[0x10];
6684
6685         u8         reserved_at_40[0x8];
6686         u8         dctn[0x18];
6687
6688         u8         reserved_at_60[0x20];
6689 };
6690
6691 struct mlx5_ifc_disable_hca_out_bits {
6692         u8         status[0x8];
6693         u8         reserved_at_8[0x18];
6694
6695         u8         syndrome[0x20];
6696
6697         u8         reserved_at_40[0x20];
6698 };
6699
6700 struct mlx5_ifc_disable_hca_in_bits {
6701         u8         opcode[0x10];
6702         u8         reserved_at_10[0x10];
6703
6704         u8         reserved_at_20[0x10];
6705         u8         op_mod[0x10];
6706
6707         u8         embedded_cpu_function[0x1];
6708         u8         reserved_at_41[0xf];
6709         u8         function_id[0x10];
6710
6711         u8         reserved_at_60[0x20];
6712 };
6713
6714 struct mlx5_ifc_detach_from_mcg_out_bits {
6715         u8         status[0x8];
6716         u8         reserved_at_8[0x18];
6717
6718         u8         syndrome[0x20];
6719
6720         u8         reserved_at_40[0x40];
6721 };
6722
6723 struct mlx5_ifc_detach_from_mcg_in_bits {
6724         u8         opcode[0x10];
6725         u8         uid[0x10];
6726
6727         u8         reserved_at_20[0x10];
6728         u8         op_mod[0x10];
6729
6730         u8         reserved_at_40[0x8];
6731         u8         qpn[0x18];
6732
6733         u8         reserved_at_60[0x20];
6734
6735         u8         multicast_gid[16][0x8];
6736 };
6737
6738 struct mlx5_ifc_destroy_xrq_out_bits {
6739         u8         status[0x8];
6740         u8         reserved_at_8[0x18];
6741
6742         u8         syndrome[0x20];
6743
6744         u8         reserved_at_40[0x40];
6745 };
6746
6747 struct mlx5_ifc_destroy_xrq_in_bits {
6748         u8         opcode[0x10];
6749         u8         uid[0x10];
6750
6751         u8         reserved_at_20[0x10];
6752         u8         op_mod[0x10];
6753
6754         u8         reserved_at_40[0x8];
6755         u8         xrqn[0x18];
6756
6757         u8         reserved_at_60[0x20];
6758 };
6759
6760 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6761         u8         status[0x8];
6762         u8         reserved_at_8[0x18];
6763
6764         u8         syndrome[0x20];
6765
6766         u8         reserved_at_40[0x40];
6767 };
6768
6769 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6770         u8         opcode[0x10];
6771         u8         uid[0x10];
6772
6773         u8         reserved_at_20[0x10];
6774         u8         op_mod[0x10];
6775
6776         u8         reserved_at_40[0x8];
6777         u8         xrc_srqn[0x18];
6778
6779         u8         reserved_at_60[0x20];
6780 };
6781
6782 struct mlx5_ifc_destroy_tis_out_bits {
6783         u8         status[0x8];
6784         u8         reserved_at_8[0x18];
6785
6786         u8         syndrome[0x20];
6787
6788         u8         reserved_at_40[0x40];
6789 };
6790
6791 struct mlx5_ifc_destroy_tis_in_bits {
6792         u8         opcode[0x10];
6793         u8         uid[0x10];
6794
6795         u8         reserved_at_20[0x10];
6796         u8         op_mod[0x10];
6797
6798         u8         reserved_at_40[0x8];
6799         u8         tisn[0x18];
6800
6801         u8         reserved_at_60[0x20];
6802 };
6803
6804 struct mlx5_ifc_destroy_tir_out_bits {
6805         u8         status[0x8];
6806         u8         reserved_at_8[0x18];
6807
6808         u8         syndrome[0x20];
6809
6810         u8         reserved_at_40[0x40];
6811 };
6812
6813 struct mlx5_ifc_destroy_tir_in_bits {
6814         u8         opcode[0x10];
6815         u8         uid[0x10];
6816
6817         u8         reserved_at_20[0x10];
6818         u8         op_mod[0x10];
6819
6820         u8         reserved_at_40[0x8];
6821         u8         tirn[0x18];
6822
6823         u8         reserved_at_60[0x20];
6824 };
6825
6826 struct mlx5_ifc_destroy_srq_out_bits {
6827         u8         status[0x8];
6828         u8         reserved_at_8[0x18];
6829
6830         u8         syndrome[0x20];
6831
6832         u8         reserved_at_40[0x40];
6833 };
6834
6835 struct mlx5_ifc_destroy_srq_in_bits {
6836         u8         opcode[0x10];
6837         u8         uid[0x10];
6838
6839         u8         reserved_at_20[0x10];
6840         u8         op_mod[0x10];
6841
6842         u8         reserved_at_40[0x8];
6843         u8         srqn[0x18];
6844
6845         u8         reserved_at_60[0x20];
6846 };
6847
6848 struct mlx5_ifc_destroy_sq_out_bits {
6849         u8         status[0x8];
6850         u8         reserved_at_8[0x18];
6851
6852         u8         syndrome[0x20];
6853
6854         u8         reserved_at_40[0x40];
6855 };
6856
6857 struct mlx5_ifc_destroy_sq_in_bits {
6858         u8         opcode[0x10];
6859         u8         uid[0x10];
6860
6861         u8         reserved_at_20[0x10];
6862         u8         op_mod[0x10];
6863
6864         u8         reserved_at_40[0x8];
6865         u8         sqn[0x18];
6866
6867         u8         reserved_at_60[0x20];
6868 };
6869
6870 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6871         u8         status[0x8];
6872         u8         reserved_at_8[0x18];
6873
6874         u8         syndrome[0x20];
6875
6876         u8         reserved_at_40[0x1c0];
6877 };
6878
6879 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6880         u8         opcode[0x10];
6881         u8         reserved_at_10[0x10];
6882
6883         u8         reserved_at_20[0x10];
6884         u8         op_mod[0x10];
6885
6886         u8         scheduling_hierarchy[0x8];
6887         u8         reserved_at_48[0x18];
6888
6889         u8         scheduling_element_id[0x20];
6890
6891         u8         reserved_at_80[0x180];
6892 };
6893
6894 struct mlx5_ifc_destroy_rqt_out_bits {
6895         u8         status[0x8];
6896         u8         reserved_at_8[0x18];
6897
6898         u8         syndrome[0x20];
6899
6900         u8         reserved_at_40[0x40];
6901 };
6902
6903 struct mlx5_ifc_destroy_rqt_in_bits {
6904         u8         opcode[0x10];
6905         u8         uid[0x10];
6906
6907         u8         reserved_at_20[0x10];
6908         u8         op_mod[0x10];
6909
6910         u8         reserved_at_40[0x8];
6911         u8         rqtn[0x18];
6912
6913         u8         reserved_at_60[0x20];
6914 };
6915
6916 struct mlx5_ifc_destroy_rq_out_bits {
6917         u8         status[0x8];
6918         u8         reserved_at_8[0x18];
6919
6920         u8         syndrome[0x20];
6921
6922         u8         reserved_at_40[0x40];
6923 };
6924
6925 struct mlx5_ifc_destroy_rq_in_bits {
6926         u8         opcode[0x10];
6927         u8         uid[0x10];
6928
6929         u8         reserved_at_20[0x10];
6930         u8         op_mod[0x10];
6931
6932         u8         reserved_at_40[0x8];
6933         u8         rqn[0x18];
6934
6935         u8         reserved_at_60[0x20];
6936 };
6937
6938 struct mlx5_ifc_set_delay_drop_params_in_bits {
6939         u8         opcode[0x10];
6940         u8         reserved_at_10[0x10];
6941
6942         u8         reserved_at_20[0x10];
6943         u8         op_mod[0x10];
6944
6945         u8         reserved_at_40[0x20];
6946
6947         u8         reserved_at_60[0x10];
6948         u8         delay_drop_timeout[0x10];
6949 };
6950
6951 struct mlx5_ifc_set_delay_drop_params_out_bits {
6952         u8         status[0x8];
6953         u8         reserved_at_8[0x18];
6954
6955         u8         syndrome[0x20];
6956
6957         u8         reserved_at_40[0x40];
6958 };
6959
6960 struct mlx5_ifc_destroy_rmp_out_bits {
6961         u8         status[0x8];
6962         u8         reserved_at_8[0x18];
6963
6964         u8         syndrome[0x20];
6965
6966         u8         reserved_at_40[0x40];
6967 };
6968
6969 struct mlx5_ifc_destroy_rmp_in_bits {
6970         u8         opcode[0x10];
6971         u8         uid[0x10];
6972
6973         u8         reserved_at_20[0x10];
6974         u8         op_mod[0x10];
6975
6976         u8         reserved_at_40[0x8];
6977         u8         rmpn[0x18];
6978
6979         u8         reserved_at_60[0x20];
6980 };
6981
6982 struct mlx5_ifc_destroy_qp_out_bits {
6983         u8         status[0x8];
6984         u8         reserved_at_8[0x18];
6985
6986         u8         syndrome[0x20];
6987
6988         u8         reserved_at_40[0x40];
6989 };
6990
6991 struct mlx5_ifc_destroy_qp_in_bits {
6992         u8         opcode[0x10];
6993         u8         uid[0x10];
6994
6995         u8         reserved_at_20[0x10];
6996         u8         op_mod[0x10];
6997
6998         u8         reserved_at_40[0x8];
6999         u8         qpn[0x18];
7000
7001         u8         reserved_at_60[0x20];
7002 };
7003
7004 struct mlx5_ifc_destroy_psv_out_bits {
7005         u8         status[0x8];
7006         u8         reserved_at_8[0x18];
7007
7008         u8         syndrome[0x20];
7009
7010         u8         reserved_at_40[0x40];
7011 };
7012
7013 struct mlx5_ifc_destroy_psv_in_bits {
7014         u8         opcode[0x10];
7015         u8         reserved_at_10[0x10];
7016
7017         u8         reserved_at_20[0x10];
7018         u8         op_mod[0x10];
7019
7020         u8         reserved_at_40[0x8];
7021         u8         psvn[0x18];
7022
7023         u8         reserved_at_60[0x20];
7024 };
7025
7026 struct mlx5_ifc_destroy_mkey_out_bits {
7027         u8         status[0x8];
7028         u8         reserved_at_8[0x18];
7029
7030         u8         syndrome[0x20];
7031
7032         u8         reserved_at_40[0x40];
7033 };
7034
7035 struct mlx5_ifc_destroy_mkey_in_bits {
7036         u8         opcode[0x10];
7037         u8         reserved_at_10[0x10];
7038
7039         u8         reserved_at_20[0x10];
7040         u8         op_mod[0x10];
7041
7042         u8         reserved_at_40[0x8];
7043         u8         mkey_index[0x18];
7044
7045         u8         reserved_at_60[0x20];
7046 };
7047
7048 struct mlx5_ifc_destroy_flow_table_out_bits {
7049         u8         status[0x8];
7050         u8         reserved_at_8[0x18];
7051
7052         u8         syndrome[0x20];
7053
7054         u8         reserved_at_40[0x40];
7055 };
7056
7057 struct mlx5_ifc_destroy_flow_table_in_bits {
7058         u8         opcode[0x10];
7059         u8         reserved_at_10[0x10];
7060
7061         u8         reserved_at_20[0x10];
7062         u8         op_mod[0x10];
7063
7064         u8         other_vport[0x1];
7065         u8         reserved_at_41[0xf];
7066         u8         vport_number[0x10];
7067
7068         u8         reserved_at_60[0x20];
7069
7070         u8         table_type[0x8];
7071         u8         reserved_at_88[0x18];
7072
7073         u8         reserved_at_a0[0x8];
7074         u8         table_id[0x18];
7075
7076         u8         reserved_at_c0[0x140];
7077 };
7078
7079 struct mlx5_ifc_destroy_flow_group_out_bits {
7080         u8         status[0x8];
7081         u8         reserved_at_8[0x18];
7082
7083         u8         syndrome[0x20];
7084
7085         u8         reserved_at_40[0x40];
7086 };
7087
7088 struct mlx5_ifc_destroy_flow_group_in_bits {
7089         u8         opcode[0x10];
7090         u8         reserved_at_10[0x10];
7091
7092         u8         reserved_at_20[0x10];
7093         u8         op_mod[0x10];
7094
7095         u8         other_vport[0x1];
7096         u8         reserved_at_41[0xf];
7097         u8         vport_number[0x10];
7098
7099         u8         reserved_at_60[0x20];
7100
7101         u8         table_type[0x8];
7102         u8         reserved_at_88[0x18];
7103
7104         u8         reserved_at_a0[0x8];
7105         u8         table_id[0x18];
7106
7107         u8         group_id[0x20];
7108
7109         u8         reserved_at_e0[0x120];
7110 };
7111
7112 struct mlx5_ifc_destroy_eq_out_bits {
7113         u8         status[0x8];
7114         u8         reserved_at_8[0x18];
7115
7116         u8         syndrome[0x20];
7117
7118         u8         reserved_at_40[0x40];
7119 };
7120
7121 struct mlx5_ifc_destroy_eq_in_bits {
7122         u8         opcode[0x10];
7123         u8         reserved_at_10[0x10];
7124
7125         u8         reserved_at_20[0x10];
7126         u8         op_mod[0x10];
7127
7128         u8         reserved_at_40[0x18];
7129         u8         eq_number[0x8];
7130
7131         u8         reserved_at_60[0x20];
7132 };
7133
7134 struct mlx5_ifc_destroy_dct_out_bits {
7135         u8         status[0x8];
7136         u8         reserved_at_8[0x18];
7137
7138         u8         syndrome[0x20];
7139
7140         u8         reserved_at_40[0x40];
7141 };
7142
7143 struct mlx5_ifc_destroy_dct_in_bits {
7144         u8         opcode[0x10];
7145         u8         uid[0x10];
7146
7147         u8         reserved_at_20[0x10];
7148         u8         op_mod[0x10];
7149
7150         u8         reserved_at_40[0x8];
7151         u8         dctn[0x18];
7152
7153         u8         reserved_at_60[0x20];
7154 };
7155
7156 struct mlx5_ifc_destroy_cq_out_bits {
7157         u8         status[0x8];
7158         u8         reserved_at_8[0x18];
7159
7160         u8         syndrome[0x20];
7161
7162         u8         reserved_at_40[0x40];
7163 };
7164
7165 struct mlx5_ifc_destroy_cq_in_bits {
7166         u8         opcode[0x10];
7167         u8         uid[0x10];
7168
7169         u8         reserved_at_20[0x10];
7170         u8         op_mod[0x10];
7171
7172         u8         reserved_at_40[0x8];
7173         u8         cqn[0x18];
7174
7175         u8         reserved_at_60[0x20];
7176 };
7177
7178 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7179         u8         status[0x8];
7180         u8         reserved_at_8[0x18];
7181
7182         u8         syndrome[0x20];
7183
7184         u8         reserved_at_40[0x40];
7185 };
7186
7187 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7188         u8         opcode[0x10];
7189         u8         reserved_at_10[0x10];
7190
7191         u8         reserved_at_20[0x10];
7192         u8         op_mod[0x10];
7193
7194         u8         reserved_at_40[0x20];
7195
7196         u8         reserved_at_60[0x10];
7197         u8         vxlan_udp_port[0x10];
7198 };
7199
7200 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7201         u8         status[0x8];
7202         u8         reserved_at_8[0x18];
7203
7204         u8         syndrome[0x20];
7205
7206         u8         reserved_at_40[0x40];
7207 };
7208
7209 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7210         u8         opcode[0x10];
7211         u8         reserved_at_10[0x10];
7212
7213         u8         reserved_at_20[0x10];
7214         u8         op_mod[0x10];
7215
7216         u8         reserved_at_40[0x60];
7217
7218         u8         reserved_at_a0[0x8];
7219         u8         table_index[0x18];
7220
7221         u8         reserved_at_c0[0x140];
7222 };
7223
7224 struct mlx5_ifc_delete_fte_out_bits {
7225         u8         status[0x8];
7226         u8         reserved_at_8[0x18];
7227
7228         u8         syndrome[0x20];
7229
7230         u8         reserved_at_40[0x40];
7231 };
7232
7233 struct mlx5_ifc_delete_fte_in_bits {
7234         u8         opcode[0x10];
7235         u8         reserved_at_10[0x10];
7236
7237         u8         reserved_at_20[0x10];
7238         u8         op_mod[0x10];
7239
7240         u8         other_vport[0x1];
7241         u8         reserved_at_41[0xf];
7242         u8         vport_number[0x10];
7243
7244         u8         reserved_at_60[0x20];
7245
7246         u8         table_type[0x8];
7247         u8         reserved_at_88[0x18];
7248
7249         u8         reserved_at_a0[0x8];
7250         u8         table_id[0x18];
7251
7252         u8         reserved_at_c0[0x40];
7253
7254         u8         flow_index[0x20];
7255
7256         u8         reserved_at_120[0xe0];
7257 };
7258
7259 struct mlx5_ifc_dealloc_xrcd_out_bits {
7260         u8         status[0x8];
7261         u8         reserved_at_8[0x18];
7262
7263         u8         syndrome[0x20];
7264
7265         u8         reserved_at_40[0x40];
7266 };
7267
7268 struct mlx5_ifc_dealloc_xrcd_in_bits {
7269         u8         opcode[0x10];
7270         u8         uid[0x10];
7271
7272         u8         reserved_at_20[0x10];
7273         u8         op_mod[0x10];
7274
7275         u8         reserved_at_40[0x8];
7276         u8         xrcd[0x18];
7277
7278         u8         reserved_at_60[0x20];
7279 };
7280
7281 struct mlx5_ifc_dealloc_uar_out_bits {
7282         u8         status[0x8];
7283         u8         reserved_at_8[0x18];
7284
7285         u8         syndrome[0x20];
7286
7287         u8         reserved_at_40[0x40];
7288 };
7289
7290 struct mlx5_ifc_dealloc_uar_in_bits {
7291         u8         opcode[0x10];
7292         u8         reserved_at_10[0x10];
7293
7294         u8         reserved_at_20[0x10];
7295         u8         op_mod[0x10];
7296
7297         u8         reserved_at_40[0x8];
7298         u8         uar[0x18];
7299
7300         u8         reserved_at_60[0x20];
7301 };
7302
7303 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7304         u8         status[0x8];
7305         u8         reserved_at_8[0x18];
7306
7307         u8         syndrome[0x20];
7308
7309         u8         reserved_at_40[0x40];
7310 };
7311
7312 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7313         u8         opcode[0x10];
7314         u8         uid[0x10];
7315
7316         u8         reserved_at_20[0x10];
7317         u8         op_mod[0x10];
7318
7319         u8         reserved_at_40[0x8];
7320         u8         transport_domain[0x18];
7321
7322         u8         reserved_at_60[0x20];
7323 };
7324
7325 struct mlx5_ifc_dealloc_q_counter_out_bits {
7326         u8         status[0x8];
7327         u8         reserved_at_8[0x18];
7328
7329         u8         syndrome[0x20];
7330
7331         u8         reserved_at_40[0x40];
7332 };
7333
7334 struct mlx5_ifc_dealloc_q_counter_in_bits {
7335         u8         opcode[0x10];
7336         u8         reserved_at_10[0x10];
7337
7338         u8         reserved_at_20[0x10];
7339         u8         op_mod[0x10];
7340
7341         u8         reserved_at_40[0x18];
7342         u8         counter_set_id[0x8];
7343
7344         u8         reserved_at_60[0x20];
7345 };
7346
7347 struct mlx5_ifc_dealloc_pd_out_bits {
7348         u8         status[0x8];
7349         u8         reserved_at_8[0x18];
7350
7351         u8         syndrome[0x20];
7352
7353         u8         reserved_at_40[0x40];
7354 };
7355
7356 struct mlx5_ifc_dealloc_pd_in_bits {
7357         u8         opcode[0x10];
7358         u8         uid[0x10];
7359
7360         u8         reserved_at_20[0x10];
7361         u8         op_mod[0x10];
7362
7363         u8         reserved_at_40[0x8];
7364         u8         pd[0x18];
7365
7366         u8         reserved_at_60[0x20];
7367 };
7368
7369 struct mlx5_ifc_dealloc_flow_counter_out_bits {
7370         u8         status[0x8];
7371         u8         reserved_at_8[0x18];
7372
7373         u8         syndrome[0x20];
7374
7375         u8         reserved_at_40[0x40];
7376 };
7377
7378 struct mlx5_ifc_dealloc_flow_counter_in_bits {
7379         u8         opcode[0x10];
7380         u8         reserved_at_10[0x10];
7381
7382         u8         reserved_at_20[0x10];
7383         u8         op_mod[0x10];
7384
7385         u8         flow_counter_id[0x20];
7386
7387         u8         reserved_at_60[0x20];
7388 };
7389
7390 struct mlx5_ifc_create_xrq_out_bits {
7391         u8         status[0x8];
7392         u8         reserved_at_8[0x18];
7393
7394         u8         syndrome[0x20];
7395
7396         u8         reserved_at_40[0x8];
7397         u8         xrqn[0x18];
7398
7399         u8         reserved_at_60[0x20];
7400 };
7401
7402 struct mlx5_ifc_create_xrq_in_bits {
7403         u8         opcode[0x10];
7404         u8         uid[0x10];
7405
7406         u8         reserved_at_20[0x10];
7407         u8         op_mod[0x10];
7408
7409         u8         reserved_at_40[0x40];
7410
7411         struct mlx5_ifc_xrqc_bits xrq_context;
7412 };
7413
7414 struct mlx5_ifc_create_xrc_srq_out_bits {
7415         u8         status[0x8];
7416         u8         reserved_at_8[0x18];
7417
7418         u8         syndrome[0x20];
7419
7420         u8         reserved_at_40[0x8];
7421         u8         xrc_srqn[0x18];
7422
7423         u8         reserved_at_60[0x20];
7424 };
7425
7426 struct mlx5_ifc_create_xrc_srq_in_bits {
7427         u8         opcode[0x10];
7428         u8         uid[0x10];
7429
7430         u8         reserved_at_20[0x10];
7431         u8         op_mod[0x10];
7432
7433         u8         reserved_at_40[0x40];
7434
7435         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7436
7437         u8         reserved_at_280[0x60];
7438
7439         u8         xrc_srq_umem_valid[0x1];
7440         u8         reserved_at_2e1[0x1f];
7441
7442         u8         reserved_at_300[0x580];
7443
7444         u8         pas[0][0x40];
7445 };
7446
7447 struct mlx5_ifc_create_tis_out_bits {
7448         u8         status[0x8];
7449         u8         reserved_at_8[0x18];
7450
7451         u8         syndrome[0x20];
7452
7453         u8         reserved_at_40[0x8];
7454         u8         tisn[0x18];
7455
7456         u8         reserved_at_60[0x20];
7457 };
7458
7459 struct mlx5_ifc_create_tis_in_bits {
7460         u8         opcode[0x10];
7461         u8         uid[0x10];
7462
7463         u8         reserved_at_20[0x10];
7464         u8         op_mod[0x10];
7465
7466         u8         reserved_at_40[0xc0];
7467
7468         struct mlx5_ifc_tisc_bits ctx;
7469 };
7470
7471 struct mlx5_ifc_create_tir_out_bits {
7472         u8         status[0x8];
7473         u8         icm_address_63_40[0x18];
7474
7475         u8         syndrome[0x20];
7476
7477         u8         icm_address_39_32[0x8];
7478         u8         tirn[0x18];
7479
7480         u8         icm_address_31_0[0x20];
7481 };
7482
7483 struct mlx5_ifc_create_tir_in_bits {
7484         u8         opcode[0x10];
7485         u8         uid[0x10];
7486
7487         u8         reserved_at_20[0x10];
7488         u8         op_mod[0x10];
7489
7490         u8         reserved_at_40[0xc0];
7491
7492         struct mlx5_ifc_tirc_bits ctx;
7493 };
7494
7495 struct mlx5_ifc_create_srq_out_bits {
7496         u8         status[0x8];
7497         u8         reserved_at_8[0x18];
7498
7499         u8         syndrome[0x20];
7500
7501         u8         reserved_at_40[0x8];
7502         u8         srqn[0x18];
7503
7504         u8         reserved_at_60[0x20];
7505 };
7506
7507 struct mlx5_ifc_create_srq_in_bits {
7508         u8         opcode[0x10];
7509         u8         uid[0x10];
7510
7511         u8         reserved_at_20[0x10];
7512         u8         op_mod[0x10];
7513
7514         u8         reserved_at_40[0x40];
7515
7516         struct mlx5_ifc_srqc_bits srq_context_entry;
7517
7518         u8         reserved_at_280[0x600];
7519
7520         u8         pas[0][0x40];
7521 };
7522
7523 struct mlx5_ifc_create_sq_out_bits {
7524         u8         status[0x8];
7525         u8         reserved_at_8[0x18];
7526
7527         u8         syndrome[0x20];
7528
7529         u8         reserved_at_40[0x8];
7530         u8         sqn[0x18];
7531
7532         u8         reserved_at_60[0x20];
7533 };
7534
7535 struct mlx5_ifc_create_sq_in_bits {
7536         u8         opcode[0x10];
7537         u8         uid[0x10];
7538
7539         u8         reserved_at_20[0x10];
7540         u8         op_mod[0x10];
7541
7542         u8         reserved_at_40[0xc0];
7543
7544         struct mlx5_ifc_sqc_bits ctx;
7545 };
7546
7547 struct mlx5_ifc_create_scheduling_element_out_bits {
7548         u8         status[0x8];
7549         u8         reserved_at_8[0x18];
7550
7551         u8         syndrome[0x20];
7552
7553         u8         reserved_at_40[0x40];
7554
7555         u8         scheduling_element_id[0x20];
7556
7557         u8         reserved_at_a0[0x160];
7558 };
7559
7560 struct mlx5_ifc_create_scheduling_element_in_bits {
7561         u8         opcode[0x10];
7562         u8         reserved_at_10[0x10];
7563
7564         u8         reserved_at_20[0x10];
7565         u8         op_mod[0x10];
7566
7567         u8         scheduling_hierarchy[0x8];
7568         u8         reserved_at_48[0x18];
7569
7570         u8         reserved_at_60[0xa0];
7571
7572         struct mlx5_ifc_scheduling_context_bits scheduling_context;
7573
7574         u8         reserved_at_300[0x100];
7575 };
7576
7577 struct mlx5_ifc_create_rqt_out_bits {
7578         u8         status[0x8];
7579         u8         reserved_at_8[0x18];
7580
7581         u8         syndrome[0x20];
7582
7583         u8         reserved_at_40[0x8];
7584         u8         rqtn[0x18];
7585
7586         u8         reserved_at_60[0x20];
7587 };
7588
7589 struct mlx5_ifc_create_rqt_in_bits {
7590         u8         opcode[0x10];
7591         u8         uid[0x10];
7592
7593         u8         reserved_at_20[0x10];
7594         u8         op_mod[0x10];
7595
7596         u8         reserved_at_40[0xc0];
7597
7598         struct mlx5_ifc_rqtc_bits rqt_context;
7599 };
7600
7601 struct mlx5_ifc_create_rq_out_bits {
7602         u8         status[0x8];
7603         u8         reserved_at_8[0x18];
7604
7605         u8         syndrome[0x20];
7606
7607         u8         reserved_at_40[0x8];
7608         u8         rqn[0x18];
7609
7610         u8         reserved_at_60[0x20];
7611 };
7612
7613 struct mlx5_ifc_create_rq_in_bits {
7614         u8         opcode[0x10];
7615         u8         uid[0x10];
7616
7617         u8         reserved_at_20[0x10];
7618         u8         op_mod[0x10];
7619
7620         u8         reserved_at_40[0xc0];
7621
7622         struct mlx5_ifc_rqc_bits ctx;
7623 };
7624
7625 struct mlx5_ifc_create_rmp_out_bits {
7626         u8         status[0x8];
7627         u8         reserved_at_8[0x18];
7628
7629         u8         syndrome[0x20];
7630
7631         u8         reserved_at_40[0x8];
7632         u8         rmpn[0x18];
7633
7634         u8         reserved_at_60[0x20];
7635 };
7636
7637 struct mlx5_ifc_create_rmp_in_bits {
7638         u8         opcode[0x10];
7639         u8         uid[0x10];
7640
7641         u8         reserved_at_20[0x10];
7642         u8         op_mod[0x10];
7643
7644         u8         reserved_at_40[0xc0];
7645
7646         struct mlx5_ifc_rmpc_bits ctx;
7647 };
7648
7649 struct mlx5_ifc_create_qp_out_bits {
7650         u8         status[0x8];
7651         u8         reserved_at_8[0x18];
7652
7653         u8         syndrome[0x20];
7654
7655         u8         reserved_at_40[0x8];
7656         u8         qpn[0x18];
7657
7658         u8         reserved_at_60[0x20];
7659 };
7660
7661 struct mlx5_ifc_create_qp_in_bits {
7662         u8         opcode[0x10];
7663         u8         uid[0x10];
7664
7665         u8         reserved_at_20[0x10];
7666         u8         op_mod[0x10];
7667
7668         u8         reserved_at_40[0x40];
7669
7670         u8         opt_param_mask[0x20];
7671
7672         u8         reserved_at_a0[0x20];
7673
7674         struct mlx5_ifc_qpc_bits qpc;
7675
7676         u8         reserved_at_800[0x60];
7677
7678         u8         wq_umem_valid[0x1];
7679         u8         reserved_at_861[0x1f];
7680
7681         u8         pas[0][0x40];
7682 };
7683
7684 struct mlx5_ifc_create_psv_out_bits {
7685         u8         status[0x8];
7686         u8         reserved_at_8[0x18];
7687
7688         u8         syndrome[0x20];
7689
7690         u8         reserved_at_40[0x40];
7691
7692         u8         reserved_at_80[0x8];
7693         u8         psv0_index[0x18];
7694
7695         u8         reserved_at_a0[0x8];
7696         u8         psv1_index[0x18];
7697
7698         u8         reserved_at_c0[0x8];
7699         u8         psv2_index[0x18];
7700
7701         u8         reserved_at_e0[0x8];
7702         u8         psv3_index[0x18];
7703 };
7704
7705 struct mlx5_ifc_create_psv_in_bits {
7706         u8         opcode[0x10];
7707         u8         reserved_at_10[0x10];
7708
7709         u8         reserved_at_20[0x10];
7710         u8         op_mod[0x10];
7711
7712         u8         num_psv[0x4];
7713         u8         reserved_at_44[0x4];
7714         u8         pd[0x18];
7715
7716         u8         reserved_at_60[0x20];
7717 };
7718
7719 struct mlx5_ifc_create_mkey_out_bits {
7720         u8         status[0x8];
7721         u8         reserved_at_8[0x18];
7722
7723         u8         syndrome[0x20];
7724
7725         u8         reserved_at_40[0x8];
7726         u8         mkey_index[0x18];
7727
7728         u8         reserved_at_60[0x20];
7729 };
7730
7731 struct mlx5_ifc_create_mkey_in_bits {
7732         u8         opcode[0x10];
7733         u8         reserved_at_10[0x10];
7734
7735         u8         reserved_at_20[0x10];
7736         u8         op_mod[0x10];
7737
7738         u8         reserved_at_40[0x20];
7739
7740         u8         pg_access[0x1];
7741         u8         mkey_umem_valid[0x1];
7742         u8         reserved_at_62[0x1e];
7743
7744         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7745
7746         u8         reserved_at_280[0x80];
7747
7748         u8         translations_octword_actual_size[0x20];
7749
7750         u8         reserved_at_320[0x560];
7751
7752         u8         klm_pas_mtt[0][0x20];
7753 };
7754
7755 enum {
7756         MLX5_FLOW_TABLE_TYPE_NIC_RX             = 0x0,
7757         MLX5_FLOW_TABLE_TYPE_NIC_TX             = 0x1,
7758         MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL     = 0x2,
7759         MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL    = 0x3,
7760         MLX5_FLOW_TABLE_TYPE_FDB                = 0X4,
7761         MLX5_FLOW_TABLE_TYPE_SNIFFER_RX         = 0X5,
7762         MLX5_FLOW_TABLE_TYPE_SNIFFER_TX         = 0X6,
7763 };
7764
7765 struct mlx5_ifc_create_flow_table_out_bits {
7766         u8         status[0x8];
7767         u8         icm_address_63_40[0x18];
7768
7769         u8         syndrome[0x20];
7770
7771         u8         icm_address_39_32[0x8];
7772         u8         table_id[0x18];
7773
7774         u8         icm_address_31_0[0x20];
7775 };
7776
7777 struct mlx5_ifc_create_flow_table_in_bits {
7778         u8         opcode[0x10];
7779         u8         reserved_at_10[0x10];
7780
7781         u8         reserved_at_20[0x10];
7782         u8         op_mod[0x10];
7783
7784         u8         other_vport[0x1];
7785         u8         reserved_at_41[0xf];
7786         u8         vport_number[0x10];
7787
7788         u8         reserved_at_60[0x20];
7789
7790         u8         table_type[0x8];
7791         u8         reserved_at_88[0x18];
7792
7793         u8         reserved_at_a0[0x20];
7794
7795         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7796 };
7797
7798 struct mlx5_ifc_create_flow_group_out_bits {
7799         u8         status[0x8];
7800         u8         reserved_at_8[0x18];
7801
7802         u8         syndrome[0x20];
7803
7804         u8         reserved_at_40[0x8];
7805         u8         group_id[0x18];
7806
7807         u8         reserved_at_60[0x20];
7808 };
7809
7810 enum {
7811         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
7812         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
7813         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
7814         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7815 };
7816
7817 struct mlx5_ifc_create_flow_group_in_bits {
7818         u8         opcode[0x10];
7819         u8         reserved_at_10[0x10];
7820
7821         u8         reserved_at_20[0x10];
7822         u8         op_mod[0x10];
7823
7824         u8         other_vport[0x1];
7825         u8         reserved_at_41[0xf];
7826         u8         vport_number[0x10];
7827
7828         u8         reserved_at_60[0x20];
7829
7830         u8         table_type[0x8];
7831         u8         reserved_at_88[0x18];
7832
7833         u8         reserved_at_a0[0x8];
7834         u8         table_id[0x18];
7835
7836         u8         source_eswitch_owner_vhca_id_valid[0x1];
7837
7838         u8         reserved_at_c1[0x1f];
7839
7840         u8         start_flow_index[0x20];
7841
7842         u8         reserved_at_100[0x20];
7843
7844         u8         end_flow_index[0x20];
7845
7846         u8         reserved_at_140[0xa0];
7847
7848         u8         reserved_at_1e0[0x18];
7849         u8         match_criteria_enable[0x8];
7850
7851         struct mlx5_ifc_fte_match_param_bits match_criteria;
7852
7853         u8         reserved_at_1200[0xe00];
7854 };
7855
7856 struct mlx5_ifc_create_eq_out_bits {
7857         u8         status[0x8];
7858         u8         reserved_at_8[0x18];
7859
7860         u8         syndrome[0x20];
7861
7862         u8         reserved_at_40[0x18];
7863         u8         eq_number[0x8];
7864
7865         u8         reserved_at_60[0x20];
7866 };
7867
7868 struct mlx5_ifc_create_eq_in_bits {
7869         u8         opcode[0x10];
7870         u8         uid[0x10];
7871
7872         u8         reserved_at_20[0x10];
7873         u8         op_mod[0x10];
7874
7875         u8         reserved_at_40[0x40];
7876
7877         struct mlx5_ifc_eqc_bits eq_context_entry;
7878
7879         u8         reserved_at_280[0x40];
7880
7881         u8         event_bitmask[4][0x40];
7882
7883         u8         reserved_at_3c0[0x4c0];
7884
7885         u8         pas[0][0x40];
7886 };
7887
7888 struct mlx5_ifc_create_dct_out_bits {
7889         u8         status[0x8];
7890         u8         reserved_at_8[0x18];
7891
7892         u8         syndrome[0x20];
7893
7894         u8         reserved_at_40[0x8];
7895         u8         dctn[0x18];
7896
7897         u8         reserved_at_60[0x20];
7898 };
7899
7900 struct mlx5_ifc_create_dct_in_bits {
7901         u8         opcode[0x10];
7902         u8         uid[0x10];
7903
7904         u8         reserved_at_20[0x10];
7905         u8         op_mod[0x10];
7906
7907         u8         reserved_at_40[0x40];
7908
7909         struct mlx5_ifc_dctc_bits dct_context_entry;
7910
7911         u8         reserved_at_280[0x180];
7912 };
7913
7914 struct mlx5_ifc_create_cq_out_bits {
7915         u8         status[0x8];
7916         u8         reserved_at_8[0x18];
7917
7918         u8         syndrome[0x20];
7919
7920         u8         reserved_at_40[0x8];
7921         u8         cqn[0x18];
7922
7923         u8         reserved_at_60[0x20];
7924 };
7925
7926 struct mlx5_ifc_create_cq_in_bits {
7927         u8         opcode[0x10];
7928         u8         uid[0x10];
7929
7930         u8         reserved_at_20[0x10];
7931         u8         op_mod[0x10];
7932
7933         u8         reserved_at_40[0x40];
7934
7935         struct mlx5_ifc_cqc_bits cq_context;
7936
7937         u8         reserved_at_280[0x60];
7938
7939         u8         cq_umem_valid[0x1];
7940         u8         reserved_at_2e1[0x59f];
7941
7942         u8         pas[0][0x40];
7943 };
7944
7945 struct mlx5_ifc_config_int_moderation_out_bits {
7946         u8         status[0x8];
7947         u8         reserved_at_8[0x18];
7948
7949         u8         syndrome[0x20];
7950
7951         u8         reserved_at_40[0x4];
7952         u8         min_delay[0xc];
7953         u8         int_vector[0x10];
7954
7955         u8         reserved_at_60[0x20];
7956 };
7957
7958 enum {
7959         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7960         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7961 };
7962
7963 struct mlx5_ifc_config_int_moderation_in_bits {
7964         u8         opcode[0x10];
7965         u8         reserved_at_10[0x10];
7966
7967         u8         reserved_at_20[0x10];
7968         u8         op_mod[0x10];
7969
7970         u8         reserved_at_40[0x4];
7971         u8         min_delay[0xc];
7972         u8         int_vector[0x10];
7973
7974         u8         reserved_at_60[0x20];
7975 };
7976
7977 struct mlx5_ifc_attach_to_mcg_out_bits {
7978         u8         status[0x8];
7979         u8         reserved_at_8[0x18];
7980
7981         u8         syndrome[0x20];
7982
7983         u8         reserved_at_40[0x40];
7984 };
7985
7986 struct mlx5_ifc_attach_to_mcg_in_bits {
7987         u8         opcode[0x10];
7988         u8         uid[0x10];
7989
7990         u8         reserved_at_20[0x10];
7991         u8         op_mod[0x10];
7992
7993         u8         reserved_at_40[0x8];
7994         u8         qpn[0x18];
7995
7996         u8         reserved_at_60[0x20];
7997
7998         u8         multicast_gid[16][0x8];
7999 };
8000
8001 struct mlx5_ifc_arm_xrq_out_bits {
8002         u8         status[0x8];
8003         u8         reserved_at_8[0x18];
8004
8005         u8         syndrome[0x20];
8006
8007         u8         reserved_at_40[0x40];
8008 };
8009
8010 struct mlx5_ifc_arm_xrq_in_bits {
8011         u8         opcode[0x10];
8012         u8         reserved_at_10[0x10];
8013
8014         u8         reserved_at_20[0x10];
8015         u8         op_mod[0x10];
8016
8017         u8         reserved_at_40[0x8];
8018         u8         xrqn[0x18];
8019
8020         u8         reserved_at_60[0x10];
8021         u8         lwm[0x10];
8022 };
8023
8024 struct mlx5_ifc_arm_xrc_srq_out_bits {
8025         u8         status[0x8];
8026         u8         reserved_at_8[0x18];
8027
8028         u8         syndrome[0x20];
8029
8030         u8         reserved_at_40[0x40];
8031 };
8032
8033 enum {
8034         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
8035 };
8036
8037 struct mlx5_ifc_arm_xrc_srq_in_bits {
8038         u8         opcode[0x10];
8039         u8         uid[0x10];
8040
8041         u8         reserved_at_20[0x10];
8042         u8         op_mod[0x10];
8043
8044         u8         reserved_at_40[0x8];
8045         u8         xrc_srqn[0x18];
8046
8047         u8         reserved_at_60[0x10];
8048         u8         lwm[0x10];
8049 };
8050
8051 struct mlx5_ifc_arm_rq_out_bits {
8052         u8         status[0x8];
8053         u8         reserved_at_8[0x18];
8054
8055         u8         syndrome[0x20];
8056
8057         u8         reserved_at_40[0x40];
8058 };
8059
8060 enum {
8061         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8062         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8063 };
8064
8065 struct mlx5_ifc_arm_rq_in_bits {
8066         u8         opcode[0x10];
8067         u8         uid[0x10];
8068
8069         u8         reserved_at_20[0x10];
8070         u8         op_mod[0x10];
8071
8072         u8         reserved_at_40[0x8];
8073         u8         srq_number[0x18];
8074
8075         u8         reserved_at_60[0x10];
8076         u8         lwm[0x10];
8077 };
8078
8079 struct mlx5_ifc_arm_dct_out_bits {
8080         u8         status[0x8];
8081         u8         reserved_at_8[0x18];
8082
8083         u8         syndrome[0x20];
8084
8085         u8         reserved_at_40[0x40];
8086 };
8087
8088 struct mlx5_ifc_arm_dct_in_bits {
8089         u8         opcode[0x10];
8090         u8         reserved_at_10[0x10];
8091
8092         u8         reserved_at_20[0x10];
8093         u8         op_mod[0x10];
8094
8095         u8         reserved_at_40[0x8];
8096         u8         dct_number[0x18];
8097
8098         u8         reserved_at_60[0x20];
8099 };
8100
8101 struct mlx5_ifc_alloc_xrcd_out_bits {
8102         u8         status[0x8];
8103         u8         reserved_at_8[0x18];
8104
8105         u8         syndrome[0x20];
8106
8107         u8         reserved_at_40[0x8];
8108         u8         xrcd[0x18];
8109
8110         u8         reserved_at_60[0x20];
8111 };
8112
8113 struct mlx5_ifc_alloc_xrcd_in_bits {
8114         u8         opcode[0x10];
8115         u8         uid[0x10];
8116
8117         u8         reserved_at_20[0x10];
8118         u8         op_mod[0x10];
8119
8120         u8         reserved_at_40[0x40];
8121 };
8122
8123 struct mlx5_ifc_alloc_uar_out_bits {
8124         u8         status[0x8];
8125         u8         reserved_at_8[0x18];
8126
8127         u8         syndrome[0x20];
8128
8129         u8         reserved_at_40[0x8];
8130         u8         uar[0x18];
8131
8132         u8         reserved_at_60[0x20];
8133 };
8134
8135 struct mlx5_ifc_alloc_uar_in_bits {
8136         u8         opcode[0x10];
8137         u8         reserved_at_10[0x10];
8138
8139         u8         reserved_at_20[0x10];
8140         u8         op_mod[0x10];
8141
8142         u8         reserved_at_40[0x40];
8143 };
8144
8145 struct mlx5_ifc_alloc_transport_domain_out_bits {
8146         u8         status[0x8];
8147         u8         reserved_at_8[0x18];
8148
8149         u8         syndrome[0x20];
8150
8151         u8         reserved_at_40[0x8];
8152         u8         transport_domain[0x18];
8153
8154         u8         reserved_at_60[0x20];
8155 };
8156
8157 struct mlx5_ifc_alloc_transport_domain_in_bits {
8158         u8         opcode[0x10];
8159         u8         uid[0x10];
8160
8161         u8         reserved_at_20[0x10];
8162         u8         op_mod[0x10];
8163
8164         u8         reserved_at_40[0x40];
8165 };
8166
8167 struct mlx5_ifc_alloc_q_counter_out_bits {
8168         u8         status[0x8];
8169         u8         reserved_at_8[0x18];
8170
8171         u8         syndrome[0x20];
8172
8173         u8         reserved_at_40[0x18];
8174         u8         counter_set_id[0x8];
8175
8176         u8         reserved_at_60[0x20];
8177 };
8178
8179 struct mlx5_ifc_alloc_q_counter_in_bits {
8180         u8         opcode[0x10];
8181         u8         uid[0x10];
8182
8183         u8         reserved_at_20[0x10];
8184         u8         op_mod[0x10];
8185
8186         u8         reserved_at_40[0x40];
8187 };
8188
8189 struct mlx5_ifc_alloc_pd_out_bits {
8190         u8         status[0x8];
8191         u8         reserved_at_8[0x18];
8192
8193         u8         syndrome[0x20];
8194
8195         u8         reserved_at_40[0x8];
8196         u8         pd[0x18];
8197
8198         u8         reserved_at_60[0x20];
8199 };
8200
8201 struct mlx5_ifc_alloc_pd_in_bits {
8202         u8         opcode[0x10];
8203         u8         uid[0x10];
8204
8205         u8         reserved_at_20[0x10];
8206         u8         op_mod[0x10];
8207
8208         u8         reserved_at_40[0x40];
8209 };
8210
8211 struct mlx5_ifc_alloc_flow_counter_out_bits {
8212         u8         status[0x8];
8213         u8         reserved_at_8[0x18];
8214
8215         u8         syndrome[0x20];
8216
8217         u8         flow_counter_id[0x20];
8218
8219         u8         reserved_at_60[0x20];
8220 };
8221
8222 struct mlx5_ifc_alloc_flow_counter_in_bits {
8223         u8         opcode[0x10];
8224         u8         reserved_at_10[0x10];
8225
8226         u8         reserved_at_20[0x10];
8227         u8         op_mod[0x10];
8228
8229         u8         reserved_at_40[0x38];
8230         u8         flow_counter_bulk[0x8];
8231 };
8232
8233 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8234         u8         status[0x8];
8235         u8         reserved_at_8[0x18];
8236
8237         u8         syndrome[0x20];
8238
8239         u8         reserved_at_40[0x40];
8240 };
8241
8242 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8243         u8         opcode[0x10];
8244         u8         reserved_at_10[0x10];
8245
8246         u8         reserved_at_20[0x10];
8247         u8         op_mod[0x10];
8248
8249         u8         reserved_at_40[0x20];
8250
8251         u8         reserved_at_60[0x10];
8252         u8         vxlan_udp_port[0x10];
8253 };
8254
8255 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8256         u8         status[0x8];
8257         u8         reserved_at_8[0x18];
8258
8259         u8         syndrome[0x20];
8260
8261         u8         reserved_at_40[0x40];
8262 };
8263
8264 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8265         u8         opcode[0x10];
8266         u8         reserved_at_10[0x10];
8267
8268         u8         reserved_at_20[0x10];
8269         u8         op_mod[0x10];
8270
8271         u8         reserved_at_40[0x10];
8272         u8         rate_limit_index[0x10];
8273
8274         u8         reserved_at_60[0x20];
8275
8276         u8         rate_limit[0x20];
8277
8278         u8         burst_upper_bound[0x20];
8279
8280         u8         reserved_at_c0[0x10];
8281         u8         typical_packet_size[0x10];
8282
8283         u8         reserved_at_e0[0x120];
8284 };
8285
8286 struct mlx5_ifc_access_register_out_bits {
8287         u8         status[0x8];
8288         u8         reserved_at_8[0x18];
8289
8290         u8         syndrome[0x20];
8291
8292         u8         reserved_at_40[0x40];
8293
8294         u8         register_data[0][0x20];
8295 };
8296
8297 enum {
8298         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
8299         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
8300 };
8301
8302 struct mlx5_ifc_access_register_in_bits {
8303         u8         opcode[0x10];
8304         u8         reserved_at_10[0x10];
8305
8306         u8         reserved_at_20[0x10];
8307         u8         op_mod[0x10];
8308
8309         u8         reserved_at_40[0x10];
8310         u8         register_id[0x10];
8311
8312         u8         argument[0x20];
8313
8314         u8         register_data[0][0x20];
8315 };
8316
8317 struct mlx5_ifc_sltp_reg_bits {
8318         u8         status[0x4];
8319         u8         version[0x4];
8320         u8         local_port[0x8];
8321         u8         pnat[0x2];
8322         u8         reserved_at_12[0x2];
8323         u8         lane[0x4];
8324         u8         reserved_at_18[0x8];
8325
8326         u8         reserved_at_20[0x20];
8327
8328         u8         reserved_at_40[0x7];
8329         u8         polarity[0x1];
8330         u8         ob_tap0[0x8];
8331         u8         ob_tap1[0x8];
8332         u8         ob_tap2[0x8];
8333
8334         u8         reserved_at_60[0xc];
8335         u8         ob_preemp_mode[0x4];
8336         u8         ob_reg[0x8];
8337         u8         ob_bias[0x8];
8338
8339         u8         reserved_at_80[0x20];
8340 };
8341
8342 struct mlx5_ifc_slrg_reg_bits {
8343         u8         status[0x4];
8344         u8         version[0x4];
8345         u8         local_port[0x8];
8346         u8         pnat[0x2];
8347         u8         reserved_at_12[0x2];
8348         u8         lane[0x4];
8349         u8         reserved_at_18[0x8];
8350
8351         u8         time_to_link_up[0x10];
8352         u8         reserved_at_30[0xc];
8353         u8         grade_lane_speed[0x4];
8354
8355         u8         grade_version[0x8];
8356         u8         grade[0x18];
8357
8358         u8         reserved_at_60[0x4];
8359         u8         height_grade_type[0x4];
8360         u8         height_grade[0x18];
8361
8362         u8         height_dz[0x10];
8363         u8         height_dv[0x10];
8364
8365         u8         reserved_at_a0[0x10];
8366         u8         height_sigma[0x10];
8367
8368         u8         reserved_at_c0[0x20];
8369
8370         u8         reserved_at_e0[0x4];
8371         u8         phase_grade_type[0x4];
8372         u8         phase_grade[0x18];
8373
8374         u8         reserved_at_100[0x8];
8375         u8         phase_eo_pos[0x8];
8376         u8         reserved_at_110[0x8];
8377         u8         phase_eo_neg[0x8];
8378
8379         u8         ffe_set_tested[0x10];
8380         u8         test_errors_per_lane[0x10];
8381 };
8382
8383 struct mlx5_ifc_pvlc_reg_bits {
8384         u8         reserved_at_0[0x8];
8385         u8         local_port[0x8];
8386         u8         reserved_at_10[0x10];
8387
8388         u8         reserved_at_20[0x1c];
8389         u8         vl_hw_cap[0x4];
8390
8391         u8         reserved_at_40[0x1c];
8392         u8         vl_admin[0x4];
8393
8394         u8         reserved_at_60[0x1c];
8395         u8         vl_operational[0x4];
8396 };
8397
8398 struct mlx5_ifc_pude_reg_bits {
8399         u8         swid[0x8];
8400         u8         local_port[0x8];
8401         u8         reserved_at_10[0x4];
8402         u8         admin_status[0x4];
8403         u8         reserved_at_18[0x4];
8404         u8         oper_status[0x4];
8405
8406         u8         reserved_at_20[0x60];
8407 };
8408
8409 struct mlx5_ifc_ptys_reg_bits {
8410         u8         reserved_at_0[0x1];
8411         u8         an_disable_admin[0x1];
8412         u8         an_disable_cap[0x1];
8413         u8         reserved_at_3[0x5];
8414         u8         local_port[0x8];
8415         u8         reserved_at_10[0xd];
8416         u8         proto_mask[0x3];
8417
8418         u8         an_status[0x4];
8419         u8         reserved_at_24[0x1c];
8420
8421         u8         ext_eth_proto_capability[0x20];
8422
8423         u8         eth_proto_capability[0x20];
8424
8425         u8         ib_link_width_capability[0x10];
8426         u8         ib_proto_capability[0x10];
8427
8428         u8         ext_eth_proto_admin[0x20];
8429
8430         u8         eth_proto_admin[0x20];
8431
8432         u8         ib_link_width_admin[0x10];
8433         u8         ib_proto_admin[0x10];
8434
8435         u8         ext_eth_proto_oper[0x20];
8436
8437         u8         eth_proto_oper[0x20];
8438
8439         u8         ib_link_width_oper[0x10];
8440         u8         ib_proto_oper[0x10];
8441
8442         u8         reserved_at_160[0x1c];
8443         u8         connector_type[0x4];
8444
8445         u8         eth_proto_lp_advertise[0x20];
8446
8447         u8         reserved_at_1a0[0x60];
8448 };
8449
8450 struct mlx5_ifc_mlcr_reg_bits {
8451         u8         reserved_at_0[0x8];
8452         u8         local_port[0x8];
8453         u8         reserved_at_10[0x20];
8454
8455         u8         beacon_duration[0x10];
8456         u8         reserved_at_40[0x10];
8457
8458         u8         beacon_remain[0x10];
8459 };
8460
8461 struct mlx5_ifc_ptas_reg_bits {
8462         u8         reserved_at_0[0x20];
8463
8464         u8         algorithm_options[0x10];
8465         u8         reserved_at_30[0x4];
8466         u8         repetitions_mode[0x4];
8467         u8         num_of_repetitions[0x8];
8468
8469         u8         grade_version[0x8];
8470         u8         height_grade_type[0x4];
8471         u8         phase_grade_type[0x4];
8472         u8         height_grade_weight[0x8];
8473         u8         phase_grade_weight[0x8];
8474
8475         u8         gisim_measure_bits[0x10];
8476         u8         adaptive_tap_measure_bits[0x10];
8477
8478         u8         ber_bath_high_error_threshold[0x10];
8479         u8         ber_bath_mid_error_threshold[0x10];
8480
8481         u8         ber_bath_low_error_threshold[0x10];
8482         u8         one_ratio_high_threshold[0x10];
8483
8484         u8         one_ratio_high_mid_threshold[0x10];
8485         u8         one_ratio_low_mid_threshold[0x10];
8486
8487         u8         one_ratio_low_threshold[0x10];
8488         u8         ndeo_error_threshold[0x10];
8489
8490         u8         mixer_offset_step_size[0x10];
8491         u8         reserved_at_110[0x8];
8492         u8         mix90_phase_for_voltage_bath[0x8];
8493
8494         u8         mixer_offset_start[0x10];
8495         u8         mixer_offset_end[0x10];
8496
8497         u8         reserved_at_140[0x15];
8498         u8         ber_test_time[0xb];
8499 };
8500
8501 struct mlx5_ifc_pspa_reg_bits {
8502         u8         swid[0x8];
8503         u8         local_port[0x8];
8504         u8         sub_port[0x8];
8505         u8         reserved_at_18[0x8];
8506
8507         u8         reserved_at_20[0x20];
8508 };
8509
8510 struct mlx5_ifc_pqdr_reg_bits {
8511         u8         reserved_at_0[0x8];
8512         u8         local_port[0x8];
8513         u8         reserved_at_10[0x5];
8514         u8         prio[0x3];
8515         u8         reserved_at_18[0x6];
8516         u8         mode[0x2];
8517
8518         u8         reserved_at_20[0x20];
8519
8520         u8         reserved_at_40[0x10];
8521         u8         min_threshold[0x10];
8522
8523         u8         reserved_at_60[0x10];
8524         u8         max_threshold[0x10];
8525
8526         u8         reserved_at_80[0x10];
8527         u8         mark_probability_denominator[0x10];
8528
8529         u8         reserved_at_a0[0x60];
8530 };
8531
8532 struct mlx5_ifc_ppsc_reg_bits {
8533         u8         reserved_at_0[0x8];
8534         u8         local_port[0x8];
8535         u8         reserved_at_10[0x10];
8536
8537         u8         reserved_at_20[0x60];
8538
8539         u8         reserved_at_80[0x1c];
8540         u8         wrps_admin[0x4];
8541
8542         u8         reserved_at_a0[0x1c];
8543         u8         wrps_status[0x4];
8544
8545         u8         reserved_at_c0[0x8];
8546         u8         up_threshold[0x8];
8547         u8         reserved_at_d0[0x8];
8548         u8         down_threshold[0x8];
8549
8550         u8         reserved_at_e0[0x20];
8551
8552         u8         reserved_at_100[0x1c];
8553         u8         srps_admin[0x4];
8554
8555         u8         reserved_at_120[0x1c];
8556         u8         srps_status[0x4];
8557
8558         u8         reserved_at_140[0x40];
8559 };
8560
8561 struct mlx5_ifc_pplr_reg_bits {
8562         u8         reserved_at_0[0x8];
8563         u8         local_port[0x8];
8564         u8         reserved_at_10[0x10];
8565
8566         u8         reserved_at_20[0x8];
8567         u8         lb_cap[0x8];
8568         u8         reserved_at_30[0x8];
8569         u8         lb_en[0x8];
8570 };
8571
8572 struct mlx5_ifc_pplm_reg_bits {
8573         u8         reserved_at_0[0x8];
8574         u8         local_port[0x8];
8575         u8         reserved_at_10[0x10];
8576
8577         u8         reserved_at_20[0x20];
8578
8579         u8         port_profile_mode[0x8];
8580         u8         static_port_profile[0x8];
8581         u8         active_port_profile[0x8];
8582         u8         reserved_at_58[0x8];
8583
8584         u8         retransmission_active[0x8];
8585         u8         fec_mode_active[0x18];
8586
8587         u8         rs_fec_correction_bypass_cap[0x4];
8588         u8         reserved_at_84[0x8];
8589         u8         fec_override_cap_56g[0x4];
8590         u8         fec_override_cap_100g[0x4];
8591         u8         fec_override_cap_50g[0x4];
8592         u8         fec_override_cap_25g[0x4];
8593         u8         fec_override_cap_10g_40g[0x4];
8594
8595         u8         rs_fec_correction_bypass_admin[0x4];
8596         u8         reserved_at_a4[0x8];
8597         u8         fec_override_admin_56g[0x4];
8598         u8         fec_override_admin_100g[0x4];
8599         u8         fec_override_admin_50g[0x4];
8600         u8         fec_override_admin_25g[0x4];
8601         u8         fec_override_admin_10g_40g[0x4];
8602
8603         u8         fec_override_cap_400g_8x[0x10];
8604         u8         fec_override_cap_200g_4x[0x10];
8605
8606         u8         fec_override_cap_100g_2x[0x10];
8607         u8         fec_override_cap_50g_1x[0x10];
8608
8609         u8         fec_override_admin_400g_8x[0x10];
8610         u8         fec_override_admin_200g_4x[0x10];
8611
8612         u8         fec_override_admin_100g_2x[0x10];
8613         u8         fec_override_admin_50g_1x[0x10];
8614 };
8615
8616 struct mlx5_ifc_ppcnt_reg_bits {
8617         u8         swid[0x8];
8618         u8         local_port[0x8];
8619         u8         pnat[0x2];
8620         u8         reserved_at_12[0x8];
8621         u8         grp[0x6];
8622
8623         u8         clr[0x1];
8624         u8         reserved_at_21[0x1c];
8625         u8         prio_tc[0x3];
8626
8627         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8628 };
8629
8630 struct mlx5_ifc_mpein_reg_bits {
8631         u8         reserved_at_0[0x2];
8632         u8         depth[0x6];
8633         u8         pcie_index[0x8];
8634         u8         node[0x8];
8635         u8         reserved_at_18[0x8];
8636
8637         u8         capability_mask[0x20];
8638
8639         u8         reserved_at_40[0x8];
8640         u8         link_width_enabled[0x8];
8641         u8         link_speed_enabled[0x10];
8642
8643         u8         lane0_physical_position[0x8];
8644         u8         link_width_active[0x8];
8645         u8         link_speed_active[0x10];
8646
8647         u8         num_of_pfs[0x10];
8648         u8         num_of_vfs[0x10];
8649
8650         u8         bdf0[0x10];
8651         u8         reserved_at_b0[0x10];
8652
8653         u8         max_read_request_size[0x4];
8654         u8         max_payload_size[0x4];
8655         u8         reserved_at_c8[0x5];
8656         u8         pwr_status[0x3];
8657         u8         port_type[0x4];
8658         u8         reserved_at_d4[0xb];
8659         u8         lane_reversal[0x1];
8660
8661         u8         reserved_at_e0[0x14];
8662         u8         pci_power[0xc];
8663
8664         u8         reserved_at_100[0x20];
8665
8666         u8         device_status[0x10];
8667         u8         port_state[0x8];
8668         u8         reserved_at_138[0x8];
8669
8670         u8         reserved_at_140[0x10];
8671         u8         receiver_detect_result[0x10];
8672
8673         u8         reserved_at_160[0x20];
8674 };
8675
8676 struct mlx5_ifc_mpcnt_reg_bits {
8677         u8         reserved_at_0[0x8];
8678         u8         pcie_index[0x8];
8679         u8         reserved_at_10[0xa];
8680         u8         grp[0x6];
8681
8682         u8         clr[0x1];
8683         u8         reserved_at_21[0x1f];
8684
8685         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8686 };
8687
8688 struct mlx5_ifc_ppad_reg_bits {
8689         u8         reserved_at_0[0x3];
8690         u8         single_mac[0x1];
8691         u8         reserved_at_4[0x4];
8692         u8         local_port[0x8];
8693         u8         mac_47_32[0x10];
8694
8695         u8         mac_31_0[0x20];
8696
8697         u8         reserved_at_40[0x40];
8698 };
8699
8700 struct mlx5_ifc_pmtu_reg_bits {
8701         u8         reserved_at_0[0x8];
8702         u8         local_port[0x8];
8703         u8         reserved_at_10[0x10];
8704
8705         u8         max_mtu[0x10];
8706         u8         reserved_at_30[0x10];
8707
8708         u8         admin_mtu[0x10];
8709         u8         reserved_at_50[0x10];
8710
8711         u8         oper_mtu[0x10];
8712         u8         reserved_at_70[0x10];
8713 };
8714
8715 struct mlx5_ifc_pmpr_reg_bits {
8716         u8         reserved_at_0[0x8];
8717         u8         module[0x8];
8718         u8         reserved_at_10[0x10];
8719
8720         u8         reserved_at_20[0x18];
8721         u8         attenuation_5g[0x8];
8722
8723         u8         reserved_at_40[0x18];
8724         u8         attenuation_7g[0x8];
8725
8726         u8         reserved_at_60[0x18];
8727         u8         attenuation_12g[0x8];
8728 };
8729
8730 struct mlx5_ifc_pmpe_reg_bits {
8731         u8         reserved_at_0[0x8];
8732         u8         module[0x8];
8733         u8         reserved_at_10[0xc];
8734         u8         module_status[0x4];
8735
8736         u8         reserved_at_20[0x60];
8737 };
8738
8739 struct mlx5_ifc_pmpc_reg_bits {
8740         u8         module_state_updated[32][0x8];
8741 };
8742
8743 struct mlx5_ifc_pmlpn_reg_bits {
8744         u8         reserved_at_0[0x4];
8745         u8         mlpn_status[0x4];
8746         u8         local_port[0x8];
8747         u8         reserved_at_10[0x10];
8748
8749         u8         e[0x1];
8750         u8         reserved_at_21[0x1f];
8751 };
8752
8753 struct mlx5_ifc_pmlp_reg_bits {
8754         u8         rxtx[0x1];
8755         u8         reserved_at_1[0x7];
8756         u8         local_port[0x8];
8757         u8         reserved_at_10[0x8];
8758         u8         width[0x8];
8759
8760         u8         lane0_module_mapping[0x20];
8761
8762         u8         lane1_module_mapping[0x20];
8763
8764         u8         lane2_module_mapping[0x20];
8765
8766         u8         lane3_module_mapping[0x20];
8767
8768         u8         reserved_at_a0[0x160];
8769 };
8770
8771 struct mlx5_ifc_pmaos_reg_bits {
8772         u8         reserved_at_0[0x8];
8773         u8         module[0x8];
8774         u8         reserved_at_10[0x4];
8775         u8         admin_status[0x4];
8776         u8         reserved_at_18[0x4];
8777         u8         oper_status[0x4];
8778
8779         u8         ase[0x1];
8780         u8         ee[0x1];
8781         u8         reserved_at_22[0x1c];
8782         u8         e[0x2];
8783
8784         u8         reserved_at_40[0x40];
8785 };
8786
8787 struct mlx5_ifc_plpc_reg_bits {
8788         u8         reserved_at_0[0x4];
8789         u8         profile_id[0xc];
8790         u8         reserved_at_10[0x4];
8791         u8         proto_mask[0x4];
8792         u8         reserved_at_18[0x8];
8793
8794         u8         reserved_at_20[0x10];
8795         u8         lane_speed[0x10];
8796
8797         u8         reserved_at_40[0x17];
8798         u8         lpbf[0x1];
8799         u8         fec_mode_policy[0x8];
8800
8801         u8         retransmission_capability[0x8];
8802         u8         fec_mode_capability[0x18];
8803
8804         u8         retransmission_support_admin[0x8];
8805         u8         fec_mode_support_admin[0x18];
8806
8807         u8         retransmission_request_admin[0x8];
8808         u8         fec_mode_request_admin[0x18];
8809
8810         u8         reserved_at_c0[0x80];
8811 };
8812
8813 struct mlx5_ifc_plib_reg_bits {
8814         u8         reserved_at_0[0x8];
8815         u8         local_port[0x8];
8816         u8         reserved_at_10[0x8];
8817         u8         ib_port[0x8];
8818
8819         u8         reserved_at_20[0x60];
8820 };
8821
8822 struct mlx5_ifc_plbf_reg_bits {
8823         u8         reserved_at_0[0x8];
8824         u8         local_port[0x8];
8825         u8         reserved_at_10[0xd];
8826         u8         lbf_mode[0x3];
8827
8828         u8         reserved_at_20[0x20];
8829 };
8830
8831 struct mlx5_ifc_pipg_reg_bits {
8832         u8         reserved_at_0[0x8];
8833         u8         local_port[0x8];
8834         u8         reserved_at_10[0x10];
8835
8836         u8         dic[0x1];
8837         u8         reserved_at_21[0x19];
8838         u8         ipg[0x4];
8839         u8         reserved_at_3e[0x2];
8840 };
8841
8842 struct mlx5_ifc_pifr_reg_bits {
8843         u8         reserved_at_0[0x8];
8844         u8         local_port[0x8];
8845         u8         reserved_at_10[0x10];
8846
8847         u8         reserved_at_20[0xe0];
8848
8849         u8         port_filter[8][0x20];
8850
8851         u8         port_filter_update_en[8][0x20];
8852 };
8853
8854 struct mlx5_ifc_pfcc_reg_bits {
8855         u8         reserved_at_0[0x8];
8856         u8         local_port[0x8];
8857         u8         reserved_at_10[0xb];
8858         u8         ppan_mask_n[0x1];
8859         u8         minor_stall_mask[0x1];
8860         u8         critical_stall_mask[0x1];
8861         u8         reserved_at_1e[0x2];
8862
8863         u8         ppan[0x4];
8864         u8         reserved_at_24[0x4];
8865         u8         prio_mask_tx[0x8];
8866         u8         reserved_at_30[0x8];
8867         u8         prio_mask_rx[0x8];
8868
8869         u8         pptx[0x1];
8870         u8         aptx[0x1];
8871         u8         pptx_mask_n[0x1];
8872         u8         reserved_at_43[0x5];
8873         u8         pfctx[0x8];
8874         u8         reserved_at_50[0x10];
8875
8876         u8         pprx[0x1];
8877         u8         aprx[0x1];
8878         u8         pprx_mask_n[0x1];
8879         u8         reserved_at_63[0x5];
8880         u8         pfcrx[0x8];
8881         u8         reserved_at_70[0x10];
8882
8883         u8         device_stall_minor_watermark[0x10];
8884         u8         device_stall_critical_watermark[0x10];
8885
8886         u8         reserved_at_a0[0x60];
8887 };
8888
8889 struct mlx5_ifc_pelc_reg_bits {
8890         u8         op[0x4];
8891         u8         reserved_at_4[0x4];
8892         u8         local_port[0x8];
8893         u8         reserved_at_10[0x10];
8894
8895         u8         op_admin[0x8];
8896         u8         op_capability[0x8];
8897         u8         op_request[0x8];
8898         u8         op_active[0x8];
8899
8900         u8         admin[0x40];
8901
8902         u8         capability[0x40];
8903
8904         u8         request[0x40];
8905
8906         u8         active[0x40];
8907
8908         u8         reserved_at_140[0x80];
8909 };
8910
8911 struct mlx5_ifc_peir_reg_bits {
8912         u8         reserved_at_0[0x8];
8913         u8         local_port[0x8];
8914         u8         reserved_at_10[0x10];
8915
8916         u8         reserved_at_20[0xc];
8917         u8         error_count[0x4];
8918         u8         reserved_at_30[0x10];
8919
8920         u8         reserved_at_40[0xc];
8921         u8         lane[0x4];
8922         u8         reserved_at_50[0x8];
8923         u8         error_type[0x8];
8924 };
8925
8926 struct mlx5_ifc_mpegc_reg_bits {
8927         u8         reserved_at_0[0x30];
8928         u8         field_select[0x10];
8929
8930         u8         tx_overflow_sense[0x1];
8931         u8         mark_cqe[0x1];
8932         u8         mark_cnp[0x1];
8933         u8         reserved_at_43[0x1b];
8934         u8         tx_lossy_overflow_oper[0x2];
8935
8936         u8         reserved_at_60[0x100];
8937 };
8938
8939 struct mlx5_ifc_pcam_enhanced_features_bits {
8940         u8         reserved_at_0[0x68];
8941         u8         fec_50G_per_lane_in_pplm[0x1];
8942         u8         reserved_at_69[0x4];
8943         u8         rx_icrc_encapsulated_counter[0x1];
8944         u8         reserved_at_6e[0x4];
8945         u8         ptys_extended_ethernet[0x1];
8946         u8         reserved_at_73[0x3];
8947         u8         pfcc_mask[0x1];
8948         u8         reserved_at_77[0x3];
8949         u8         per_lane_error_counters[0x1];
8950         u8         rx_buffer_fullness_counters[0x1];
8951         u8         ptys_connector_type[0x1];
8952         u8         reserved_at_7d[0x1];
8953         u8         ppcnt_discard_group[0x1];
8954         u8         ppcnt_statistical_group[0x1];
8955 };
8956
8957 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8958         u8         port_access_reg_cap_mask_127_to_96[0x20];
8959         u8         port_access_reg_cap_mask_95_to_64[0x20];
8960
8961         u8         port_access_reg_cap_mask_63_to_36[0x1c];
8962         u8         pplm[0x1];
8963         u8         port_access_reg_cap_mask_34_to_32[0x3];
8964
8965         u8         port_access_reg_cap_mask_31_to_13[0x13];
8966         u8         pbmc[0x1];
8967         u8         pptb[0x1];
8968         u8         port_access_reg_cap_mask_10_to_09[0x2];
8969         u8         ppcnt[0x1];
8970         u8         port_access_reg_cap_mask_07_to_00[0x8];
8971 };
8972
8973 struct mlx5_ifc_pcam_reg_bits {
8974         u8         reserved_at_0[0x8];
8975         u8         feature_group[0x8];
8976         u8         reserved_at_10[0x8];
8977         u8         access_reg_group[0x8];
8978
8979         u8         reserved_at_20[0x20];
8980
8981         union {
8982                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8983                 u8         reserved_at_0[0x80];
8984         } port_access_reg_cap_mask;
8985
8986         u8         reserved_at_c0[0x80];
8987
8988         union {
8989                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8990                 u8         reserved_at_0[0x80];
8991         } feature_cap_mask;
8992
8993         u8         reserved_at_1c0[0xc0];
8994 };
8995
8996 struct mlx5_ifc_mcam_enhanced_features_bits {
8997         u8         reserved_at_0[0x6e];
8998         u8         pci_status_and_power[0x1];
8999         u8         reserved_at_6f[0x5];
9000         u8         mark_tx_action_cnp[0x1];
9001         u8         mark_tx_action_cqe[0x1];
9002         u8         dynamic_tx_overflow[0x1];
9003         u8         reserved_at_77[0x4];
9004         u8         pcie_outbound_stalled[0x1];
9005         u8         tx_overflow_buffer_pkt[0x1];
9006         u8         mtpps_enh_out_per_adj[0x1];
9007         u8         mtpps_fs[0x1];
9008         u8         pcie_performance_group[0x1];
9009 };
9010
9011 struct mlx5_ifc_mcam_access_reg_bits {
9012         u8         reserved_at_0[0x1c];
9013         u8         mcda[0x1];
9014         u8         mcc[0x1];
9015         u8         mcqi[0x1];
9016         u8         mcqs[0x1];
9017
9018         u8         regs_95_to_87[0x9];
9019         u8         mpegc[0x1];
9020         u8         regs_85_to_68[0x12];
9021         u8         tracer_registers[0x4];
9022
9023         u8         regs_63_to_32[0x20];
9024         u8         regs_31_to_0[0x20];
9025 };
9026
9027 struct mlx5_ifc_mcam_access_reg_bits1 {
9028         u8         regs_127_to_96[0x20];
9029
9030         u8         regs_95_to_64[0x20];
9031
9032         u8         regs_63_to_32[0x20];
9033
9034         u8         regs_31_to_0[0x20];
9035 };
9036
9037 struct mlx5_ifc_mcam_access_reg_bits2 {
9038         u8         regs_127_to_99[0x1d];
9039         u8         mirc[0x1];
9040         u8         regs_97_to_96[0x2];
9041
9042         u8         regs_95_to_64[0x20];
9043
9044         u8         regs_63_to_32[0x20];
9045
9046         u8         regs_31_to_0[0x20];
9047 };
9048
9049 struct mlx5_ifc_mcam_reg_bits {
9050         u8         reserved_at_0[0x8];
9051         u8         feature_group[0x8];
9052         u8         reserved_at_10[0x8];
9053         u8         access_reg_group[0x8];
9054
9055         u8         reserved_at_20[0x20];
9056
9057         union {
9058                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
9059                 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9060                 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
9061                 u8         reserved_at_0[0x80];
9062         } mng_access_reg_cap_mask;
9063
9064         u8         reserved_at_c0[0x80];
9065
9066         union {
9067                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9068                 u8         reserved_at_0[0x80];
9069         } mng_feature_cap_mask;
9070
9071         u8         reserved_at_1c0[0x80];
9072 };
9073
9074 struct mlx5_ifc_qcam_access_reg_cap_mask {
9075         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
9076         u8         qpdpm[0x1];
9077         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
9078         u8         qdpm[0x1];
9079         u8         qpts[0x1];
9080         u8         qcap[0x1];
9081         u8         qcam_access_reg_cap_mask_0[0x1];
9082 };
9083
9084 struct mlx5_ifc_qcam_qos_feature_cap_mask {
9085         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
9086         u8         qpts_trust_both[0x1];
9087 };
9088
9089 struct mlx5_ifc_qcam_reg_bits {
9090         u8         reserved_at_0[0x8];
9091         u8         feature_group[0x8];
9092         u8         reserved_at_10[0x8];
9093         u8         access_reg_group[0x8];
9094         u8         reserved_at_20[0x20];
9095
9096         union {
9097                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9098                 u8  reserved_at_0[0x80];
9099         } qos_access_reg_cap_mask;
9100
9101         u8         reserved_at_c0[0x80];
9102
9103         union {
9104                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9105                 u8  reserved_at_0[0x80];
9106         } qos_feature_cap_mask;
9107
9108         u8         reserved_at_1c0[0x80];
9109 };
9110
9111 struct mlx5_ifc_core_dump_reg_bits {
9112         u8         reserved_at_0[0x18];
9113         u8         core_dump_type[0x8];
9114
9115         u8         reserved_at_20[0x30];
9116         u8         vhca_id[0x10];
9117
9118         u8         reserved_at_60[0x8];
9119         u8         qpn[0x18];
9120         u8         reserved_at_80[0x180];
9121 };
9122
9123 struct mlx5_ifc_pcap_reg_bits {
9124         u8         reserved_at_0[0x8];
9125         u8         local_port[0x8];
9126         u8         reserved_at_10[0x10];
9127
9128         u8         port_capability_mask[4][0x20];
9129 };
9130
9131 struct mlx5_ifc_paos_reg_bits {
9132         u8         swid[0x8];
9133         u8         local_port[0x8];
9134         u8         reserved_at_10[0x4];
9135         u8         admin_status[0x4];
9136         u8         reserved_at_18[0x4];
9137         u8         oper_status[0x4];
9138
9139         u8         ase[0x1];
9140         u8         ee[0x1];
9141         u8         reserved_at_22[0x1c];
9142         u8         e[0x2];
9143
9144         u8         reserved_at_40[0x40];
9145 };
9146
9147 struct mlx5_ifc_pamp_reg_bits {
9148         u8         reserved_at_0[0x8];
9149         u8         opamp_group[0x8];
9150         u8         reserved_at_10[0xc];
9151         u8         opamp_group_type[0x4];
9152
9153         u8         start_index[0x10];
9154         u8         reserved_at_30[0x4];
9155         u8         num_of_indices[0xc];
9156
9157         u8         index_data[18][0x10];
9158 };
9159
9160 struct mlx5_ifc_pcmr_reg_bits {
9161         u8         reserved_at_0[0x8];
9162         u8         local_port[0x8];
9163         u8         reserved_at_10[0x10];
9164         u8         entropy_force_cap[0x1];
9165         u8         entropy_calc_cap[0x1];
9166         u8         entropy_gre_calc_cap[0x1];
9167         u8         reserved_at_23[0x1b];
9168         u8         fcs_cap[0x1];
9169         u8         reserved_at_3f[0x1];
9170         u8         entropy_force[0x1];
9171         u8         entropy_calc[0x1];
9172         u8         entropy_gre_calc[0x1];
9173         u8         reserved_at_43[0x1b];
9174         u8         fcs_chk[0x1];
9175         u8         reserved_at_5f[0x1];
9176 };
9177
9178 struct mlx5_ifc_lane_2_module_mapping_bits {
9179         u8         reserved_at_0[0x6];
9180         u8         rx_lane[0x2];
9181         u8         reserved_at_8[0x6];
9182         u8         tx_lane[0x2];
9183         u8         reserved_at_10[0x8];
9184         u8         module[0x8];
9185 };
9186
9187 struct mlx5_ifc_bufferx_reg_bits {
9188         u8         reserved_at_0[0x6];
9189         u8         lossy[0x1];
9190         u8         epsb[0x1];
9191         u8         reserved_at_8[0xc];
9192         u8         size[0xc];
9193
9194         u8         xoff_threshold[0x10];
9195         u8         xon_threshold[0x10];
9196 };
9197
9198 struct mlx5_ifc_set_node_in_bits {
9199         u8         node_description[64][0x8];
9200 };
9201
9202 struct mlx5_ifc_register_power_settings_bits {
9203         u8         reserved_at_0[0x18];
9204         u8         power_settings_level[0x8];
9205
9206         u8         reserved_at_20[0x60];
9207 };
9208
9209 struct mlx5_ifc_register_host_endianness_bits {
9210         u8         he[0x1];
9211         u8         reserved_at_1[0x1f];
9212
9213         u8         reserved_at_20[0x60];
9214 };
9215
9216 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9217         u8         reserved_at_0[0x20];
9218
9219         u8         mkey[0x20];
9220
9221         u8         addressh_63_32[0x20];
9222
9223         u8         addressl_31_0[0x20];
9224 };
9225
9226 struct mlx5_ifc_ud_adrs_vector_bits {
9227         u8         dc_key[0x40];
9228
9229         u8         ext[0x1];
9230         u8         reserved_at_41[0x7];
9231         u8         destination_qp_dct[0x18];
9232
9233         u8         static_rate[0x4];
9234         u8         sl_eth_prio[0x4];
9235         u8         fl[0x1];
9236         u8         mlid[0x7];
9237         u8         rlid_udp_sport[0x10];
9238
9239         u8         reserved_at_80[0x20];
9240
9241         u8         rmac_47_16[0x20];
9242
9243         u8         rmac_15_0[0x10];
9244         u8         tclass[0x8];
9245         u8         hop_limit[0x8];
9246
9247         u8         reserved_at_e0[0x1];
9248         u8         grh[0x1];
9249         u8         reserved_at_e2[0x2];
9250         u8         src_addr_index[0x8];
9251         u8         flow_label[0x14];
9252
9253         u8         rgid_rip[16][0x8];
9254 };
9255
9256 struct mlx5_ifc_pages_req_event_bits {
9257         u8         reserved_at_0[0x10];
9258         u8         function_id[0x10];
9259
9260         u8         num_pages[0x20];
9261
9262         u8         reserved_at_40[0xa0];
9263 };
9264
9265 struct mlx5_ifc_eqe_bits {
9266         u8         reserved_at_0[0x8];
9267         u8         event_type[0x8];
9268         u8         reserved_at_10[0x8];
9269         u8         event_sub_type[0x8];
9270
9271         u8         reserved_at_20[0xe0];
9272
9273         union mlx5_ifc_event_auto_bits event_data;
9274
9275         u8         reserved_at_1e0[0x10];
9276         u8         signature[0x8];
9277         u8         reserved_at_1f8[0x7];
9278         u8         owner[0x1];
9279 };
9280
9281 enum {
9282         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9283 };
9284
9285 struct mlx5_ifc_cmd_queue_entry_bits {
9286         u8         type[0x8];
9287         u8         reserved_at_8[0x18];
9288
9289         u8         input_length[0x20];
9290
9291         u8         input_mailbox_pointer_63_32[0x20];
9292
9293         u8         input_mailbox_pointer_31_9[0x17];
9294         u8         reserved_at_77[0x9];
9295
9296         u8         command_input_inline_data[16][0x8];
9297
9298         u8         command_output_inline_data[16][0x8];
9299
9300         u8         output_mailbox_pointer_63_32[0x20];
9301
9302         u8         output_mailbox_pointer_31_9[0x17];
9303         u8         reserved_at_1b7[0x9];
9304
9305         u8         output_length[0x20];
9306
9307         u8         token[0x8];
9308         u8         signature[0x8];
9309         u8         reserved_at_1f0[0x8];
9310         u8         status[0x7];
9311         u8         ownership[0x1];
9312 };
9313
9314 struct mlx5_ifc_cmd_out_bits {
9315         u8         status[0x8];
9316         u8         reserved_at_8[0x18];
9317
9318         u8         syndrome[0x20];
9319
9320         u8         command_output[0x20];
9321 };
9322
9323 struct mlx5_ifc_cmd_in_bits {
9324         u8         opcode[0x10];
9325         u8         reserved_at_10[0x10];
9326
9327         u8         reserved_at_20[0x10];
9328         u8         op_mod[0x10];
9329
9330         u8         command[0][0x20];
9331 };
9332
9333 struct mlx5_ifc_cmd_if_box_bits {
9334         u8         mailbox_data[512][0x8];
9335
9336         u8         reserved_at_1000[0x180];
9337
9338         u8         next_pointer_63_32[0x20];
9339
9340         u8         next_pointer_31_10[0x16];
9341         u8         reserved_at_11b6[0xa];
9342
9343         u8         block_number[0x20];
9344
9345         u8         reserved_at_11e0[0x8];
9346         u8         token[0x8];
9347         u8         ctrl_signature[0x8];
9348         u8         signature[0x8];
9349 };
9350
9351 struct mlx5_ifc_mtt_bits {
9352         u8         ptag_63_32[0x20];
9353
9354         u8         ptag_31_8[0x18];
9355         u8         reserved_at_38[0x6];
9356         u8         wr_en[0x1];
9357         u8         rd_en[0x1];
9358 };
9359
9360 struct mlx5_ifc_query_wol_rol_out_bits {
9361         u8         status[0x8];
9362         u8         reserved_at_8[0x18];
9363
9364         u8         syndrome[0x20];
9365
9366         u8         reserved_at_40[0x10];
9367         u8         rol_mode[0x8];
9368         u8         wol_mode[0x8];
9369
9370         u8         reserved_at_60[0x20];
9371 };
9372
9373 struct mlx5_ifc_query_wol_rol_in_bits {
9374         u8         opcode[0x10];
9375         u8         reserved_at_10[0x10];
9376
9377         u8         reserved_at_20[0x10];
9378         u8         op_mod[0x10];
9379
9380         u8         reserved_at_40[0x40];
9381 };
9382
9383 struct mlx5_ifc_set_wol_rol_out_bits {
9384         u8         status[0x8];
9385         u8         reserved_at_8[0x18];
9386
9387         u8         syndrome[0x20];
9388
9389         u8         reserved_at_40[0x40];
9390 };
9391
9392 struct mlx5_ifc_set_wol_rol_in_bits {
9393         u8         opcode[0x10];
9394         u8         reserved_at_10[0x10];
9395
9396         u8         reserved_at_20[0x10];
9397         u8         op_mod[0x10];
9398
9399         u8         rol_mode_valid[0x1];
9400         u8         wol_mode_valid[0x1];
9401         u8         reserved_at_42[0xe];
9402         u8         rol_mode[0x8];
9403         u8         wol_mode[0x8];
9404
9405         u8         reserved_at_60[0x20];
9406 };
9407
9408 enum {
9409         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
9410         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
9411         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
9412 };
9413
9414 enum {
9415         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
9416         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
9417         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
9418 };
9419
9420 enum {
9421         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
9422         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
9423         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
9424         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
9425         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
9426         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
9427         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
9428         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
9429         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
9430         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
9431         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
9432 };
9433
9434 struct mlx5_ifc_initial_seg_bits {
9435         u8         fw_rev_minor[0x10];
9436         u8         fw_rev_major[0x10];
9437
9438         u8         cmd_interface_rev[0x10];
9439         u8         fw_rev_subminor[0x10];
9440
9441         u8         reserved_at_40[0x40];
9442
9443         u8         cmdq_phy_addr_63_32[0x20];
9444
9445         u8         cmdq_phy_addr_31_12[0x14];
9446         u8         reserved_at_b4[0x2];
9447         u8         nic_interface[0x2];
9448         u8         log_cmdq_size[0x4];
9449         u8         log_cmdq_stride[0x4];
9450
9451         u8         command_doorbell_vector[0x20];
9452
9453         u8         reserved_at_e0[0xf00];
9454
9455         u8         initializing[0x1];
9456         u8         reserved_at_fe1[0x4];
9457         u8         nic_interface_supported[0x3];
9458         u8         embedded_cpu[0x1];
9459         u8         reserved_at_fe9[0x17];
9460
9461         struct mlx5_ifc_health_buffer_bits health_buffer;
9462
9463         u8         no_dram_nic_offset[0x20];
9464
9465         u8         reserved_at_1220[0x6e40];
9466
9467         u8         reserved_at_8060[0x1f];
9468         u8         clear_int[0x1];
9469
9470         u8         health_syndrome[0x8];
9471         u8         health_counter[0x18];
9472
9473         u8         reserved_at_80a0[0x17fc0];
9474 };
9475
9476 struct mlx5_ifc_mtpps_reg_bits {
9477         u8         reserved_at_0[0xc];
9478         u8         cap_number_of_pps_pins[0x4];
9479         u8         reserved_at_10[0x4];
9480         u8         cap_max_num_of_pps_in_pins[0x4];
9481         u8         reserved_at_18[0x4];
9482         u8         cap_max_num_of_pps_out_pins[0x4];
9483
9484         u8         reserved_at_20[0x24];
9485         u8         cap_pin_3_mode[0x4];
9486         u8         reserved_at_48[0x4];
9487         u8         cap_pin_2_mode[0x4];
9488         u8         reserved_at_50[0x4];
9489         u8         cap_pin_1_mode[0x4];
9490         u8         reserved_at_58[0x4];
9491         u8         cap_pin_0_mode[0x4];
9492
9493         u8         reserved_at_60[0x4];
9494         u8         cap_pin_7_mode[0x4];
9495         u8         reserved_at_68[0x4];
9496         u8         cap_pin_6_mode[0x4];
9497         u8         reserved_at_70[0x4];
9498         u8         cap_pin_5_mode[0x4];
9499         u8         reserved_at_78[0x4];
9500         u8         cap_pin_4_mode[0x4];
9501
9502         u8         field_select[0x20];
9503         u8         reserved_at_a0[0x60];
9504
9505         u8         enable[0x1];
9506         u8         reserved_at_101[0xb];
9507         u8         pattern[0x4];
9508         u8         reserved_at_110[0x4];
9509         u8         pin_mode[0x4];
9510         u8         pin[0x8];
9511
9512         u8         reserved_at_120[0x20];
9513
9514         u8         time_stamp[0x40];
9515
9516         u8         out_pulse_duration[0x10];
9517         u8         out_periodic_adjustment[0x10];
9518         u8         enhanced_out_periodic_adjustment[0x20];
9519
9520         u8         reserved_at_1c0[0x20];
9521 };
9522
9523 struct mlx5_ifc_mtppse_reg_bits {
9524         u8         reserved_at_0[0x18];
9525         u8         pin[0x8];
9526         u8         event_arm[0x1];
9527         u8         reserved_at_21[0x1b];
9528         u8         event_generation_mode[0x4];
9529         u8         reserved_at_40[0x40];
9530 };
9531
9532 struct mlx5_ifc_mcqs_reg_bits {
9533         u8         last_index_flag[0x1];
9534         u8         reserved_at_1[0x7];
9535         u8         fw_device[0x8];
9536         u8         component_index[0x10];
9537
9538         u8         reserved_at_20[0x10];
9539         u8         identifier[0x10];
9540
9541         u8         reserved_at_40[0x17];
9542         u8         component_status[0x5];
9543         u8         component_update_state[0x4];
9544
9545         u8         last_update_state_changer_type[0x4];
9546         u8         last_update_state_changer_host_id[0x4];
9547         u8         reserved_at_68[0x18];
9548 };
9549
9550 struct mlx5_ifc_mcqi_cap_bits {
9551         u8         supported_info_bitmask[0x20];
9552
9553         u8         component_size[0x20];
9554
9555         u8         max_component_size[0x20];
9556
9557         u8         log_mcda_word_size[0x4];
9558         u8         reserved_at_64[0xc];
9559         u8         mcda_max_write_size[0x10];
9560
9561         u8         rd_en[0x1];
9562         u8         reserved_at_81[0x1];
9563         u8         match_chip_id[0x1];
9564         u8         match_psid[0x1];
9565         u8         check_user_timestamp[0x1];
9566         u8         match_base_guid_mac[0x1];
9567         u8         reserved_at_86[0x1a];
9568 };
9569
9570 struct mlx5_ifc_mcqi_version_bits {
9571         u8         reserved_at_0[0x2];
9572         u8         build_time_valid[0x1];
9573         u8         user_defined_time_valid[0x1];
9574         u8         reserved_at_4[0x14];
9575         u8         version_string_length[0x8];
9576
9577         u8         version[0x20];
9578
9579         u8         build_time[0x40];
9580
9581         u8         user_defined_time[0x40];
9582
9583         u8         build_tool_version[0x20];
9584
9585         u8         reserved_at_e0[0x20];
9586
9587         u8         version_string[92][0x8];
9588 };
9589
9590 struct mlx5_ifc_mcqi_activation_method_bits {
9591         u8         pending_server_ac_power_cycle[0x1];
9592         u8         pending_server_dc_power_cycle[0x1];
9593         u8         pending_server_reboot[0x1];
9594         u8         pending_fw_reset[0x1];
9595         u8         auto_activate[0x1];
9596         u8         all_hosts_sync[0x1];
9597         u8         device_hw_reset[0x1];
9598         u8         reserved_at_7[0x19];
9599 };
9600
9601 union mlx5_ifc_mcqi_reg_data_bits {
9602         struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
9603         struct mlx5_ifc_mcqi_version_bits           mcqi_version;
9604         struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9605 };
9606
9607 struct mlx5_ifc_mcqi_reg_bits {
9608         u8         read_pending_component[0x1];
9609         u8         reserved_at_1[0xf];
9610         u8         component_index[0x10];
9611
9612         u8         reserved_at_20[0x20];
9613
9614         u8         reserved_at_40[0x1b];
9615         u8         info_type[0x5];
9616
9617         u8         info_size[0x20];
9618
9619         u8         offset[0x20];
9620
9621         u8         reserved_at_a0[0x10];
9622         u8         data_size[0x10];
9623
9624         union mlx5_ifc_mcqi_reg_data_bits data[0];
9625 };
9626
9627 struct mlx5_ifc_mcc_reg_bits {
9628         u8         reserved_at_0[0x4];
9629         u8         time_elapsed_since_last_cmd[0xc];
9630         u8         reserved_at_10[0x8];
9631         u8         instruction[0x8];
9632
9633         u8         reserved_at_20[0x10];
9634         u8         component_index[0x10];
9635
9636         u8         reserved_at_40[0x8];
9637         u8         update_handle[0x18];
9638
9639         u8         handle_owner_type[0x4];
9640         u8         handle_owner_host_id[0x4];
9641         u8         reserved_at_68[0x1];
9642         u8         control_progress[0x7];
9643         u8         error_code[0x8];
9644         u8         reserved_at_78[0x4];
9645         u8         control_state[0x4];
9646
9647         u8         component_size[0x20];
9648
9649         u8         reserved_at_a0[0x60];
9650 };
9651
9652 struct mlx5_ifc_mcda_reg_bits {
9653         u8         reserved_at_0[0x8];
9654         u8         update_handle[0x18];
9655
9656         u8         offset[0x20];
9657
9658         u8         reserved_at_40[0x10];
9659         u8         size[0x10];
9660
9661         u8         reserved_at_60[0x20];
9662
9663         u8         data[0][0x20];
9664 };
9665
9666 struct mlx5_ifc_mirc_reg_bits {
9667         u8         reserved_at_0[0x18];
9668         u8         status_code[0x8];
9669
9670         u8         reserved_at_20[0x20];
9671 };
9672
9673 union mlx5_ifc_ports_control_registers_document_bits {
9674         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9675         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9676         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9677         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9678         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9679         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9680         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9681         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
9682         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
9683         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9684         struct mlx5_ifc_pamp_reg_bits pamp_reg;
9685         struct mlx5_ifc_paos_reg_bits paos_reg;
9686         struct mlx5_ifc_pcap_reg_bits pcap_reg;
9687         struct mlx5_ifc_peir_reg_bits peir_reg;
9688         struct mlx5_ifc_pelc_reg_bits pelc_reg;
9689         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9690         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
9691         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9692         struct mlx5_ifc_pifr_reg_bits pifr_reg;
9693         struct mlx5_ifc_pipg_reg_bits pipg_reg;
9694         struct mlx5_ifc_plbf_reg_bits plbf_reg;
9695         struct mlx5_ifc_plib_reg_bits plib_reg;
9696         struct mlx5_ifc_plpc_reg_bits plpc_reg;
9697         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9698         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9699         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9700         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9701         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9702         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9703         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9704         struct mlx5_ifc_ppad_reg_bits ppad_reg;
9705         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9706         struct mlx5_ifc_mpein_reg_bits mpein_reg;
9707         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
9708         struct mlx5_ifc_pplm_reg_bits pplm_reg;
9709         struct mlx5_ifc_pplr_reg_bits pplr_reg;
9710         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9711         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9712         struct mlx5_ifc_pspa_reg_bits pspa_reg;
9713         struct mlx5_ifc_ptas_reg_bits ptas_reg;
9714         struct mlx5_ifc_ptys_reg_bits ptys_reg;
9715         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
9716         struct mlx5_ifc_pude_reg_bits pude_reg;
9717         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9718         struct mlx5_ifc_slrg_reg_bits slrg_reg;
9719         struct mlx5_ifc_sltp_reg_bits sltp_reg;
9720         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9721         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
9722         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
9723         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9724         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
9725         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9726         struct mlx5_ifc_mcc_reg_bits mcc_reg;
9727         struct mlx5_ifc_mcda_reg_bits mcda_reg;
9728         struct mlx5_ifc_mirc_reg_bits mirc_reg;
9729         u8         reserved_at_0[0x60e0];
9730 };
9731
9732 union mlx5_ifc_debug_enhancements_document_bits {
9733         struct mlx5_ifc_health_buffer_bits health_buffer;
9734         u8         reserved_at_0[0x200];
9735 };
9736
9737 union mlx5_ifc_uplink_pci_interface_document_bits {
9738         struct mlx5_ifc_initial_seg_bits initial_seg;
9739         u8         reserved_at_0[0x20060];
9740 };
9741
9742 struct mlx5_ifc_set_flow_table_root_out_bits {
9743         u8         status[0x8];
9744         u8         reserved_at_8[0x18];
9745
9746         u8         syndrome[0x20];
9747
9748         u8         reserved_at_40[0x40];
9749 };
9750
9751 struct mlx5_ifc_set_flow_table_root_in_bits {
9752         u8         opcode[0x10];
9753         u8         reserved_at_10[0x10];
9754
9755         u8         reserved_at_20[0x10];
9756         u8         op_mod[0x10];
9757
9758         u8         other_vport[0x1];
9759         u8         reserved_at_41[0xf];
9760         u8         vport_number[0x10];
9761
9762         u8         reserved_at_60[0x20];
9763
9764         u8         table_type[0x8];
9765         u8         reserved_at_88[0x18];
9766
9767         u8         reserved_at_a0[0x8];
9768         u8         table_id[0x18];
9769
9770         u8         reserved_at_c0[0x8];
9771         u8         underlay_qpn[0x18];
9772         u8         reserved_at_e0[0x120];
9773 };
9774
9775 enum {
9776         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
9777         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
9778 };
9779
9780 struct mlx5_ifc_modify_flow_table_out_bits {
9781         u8         status[0x8];
9782         u8         reserved_at_8[0x18];
9783
9784         u8         syndrome[0x20];
9785
9786         u8         reserved_at_40[0x40];
9787 };
9788
9789 struct mlx5_ifc_modify_flow_table_in_bits {
9790         u8         opcode[0x10];
9791         u8         reserved_at_10[0x10];
9792
9793         u8         reserved_at_20[0x10];
9794         u8         op_mod[0x10];
9795
9796         u8         other_vport[0x1];
9797         u8         reserved_at_41[0xf];
9798         u8         vport_number[0x10];
9799
9800         u8         reserved_at_60[0x10];
9801         u8         modify_field_select[0x10];
9802
9803         u8         table_type[0x8];
9804         u8         reserved_at_88[0x18];
9805
9806         u8         reserved_at_a0[0x8];
9807         u8         table_id[0x18];
9808
9809         struct mlx5_ifc_flow_table_context_bits flow_table_context;
9810 };
9811
9812 struct mlx5_ifc_ets_tcn_config_reg_bits {
9813         u8         g[0x1];
9814         u8         b[0x1];
9815         u8         r[0x1];
9816         u8         reserved_at_3[0x9];
9817         u8         group[0x4];
9818         u8         reserved_at_10[0x9];
9819         u8         bw_allocation[0x7];
9820
9821         u8         reserved_at_20[0xc];
9822         u8         max_bw_units[0x4];
9823         u8         reserved_at_30[0x8];
9824         u8         max_bw_value[0x8];
9825 };
9826
9827 struct mlx5_ifc_ets_global_config_reg_bits {
9828         u8         reserved_at_0[0x2];
9829         u8         r[0x1];
9830         u8         reserved_at_3[0x1d];
9831
9832         u8         reserved_at_20[0xc];
9833         u8         max_bw_units[0x4];
9834         u8         reserved_at_30[0x8];
9835         u8         max_bw_value[0x8];
9836 };
9837
9838 struct mlx5_ifc_qetc_reg_bits {
9839         u8                                         reserved_at_0[0x8];
9840         u8                                         port_number[0x8];
9841         u8                                         reserved_at_10[0x30];
9842
9843         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
9844         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9845 };
9846
9847 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9848         u8         e[0x1];
9849         u8         reserved_at_01[0x0b];
9850         u8         prio[0x04];
9851 };
9852
9853 struct mlx5_ifc_qpdpm_reg_bits {
9854         u8                                     reserved_at_0[0x8];
9855         u8                                     local_port[0x8];
9856         u8                                     reserved_at_10[0x10];
9857         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
9858 };
9859
9860 struct mlx5_ifc_qpts_reg_bits {
9861         u8         reserved_at_0[0x8];
9862         u8         local_port[0x8];
9863         u8         reserved_at_10[0x2d];
9864         u8         trust_state[0x3];
9865 };
9866
9867 struct mlx5_ifc_pptb_reg_bits {
9868         u8         reserved_at_0[0x2];
9869         u8         mm[0x2];
9870         u8         reserved_at_4[0x4];
9871         u8         local_port[0x8];
9872         u8         reserved_at_10[0x6];
9873         u8         cm[0x1];
9874         u8         um[0x1];
9875         u8         pm[0x8];
9876
9877         u8         prio_x_buff[0x20];
9878
9879         u8         pm_msb[0x8];
9880         u8         reserved_at_48[0x10];
9881         u8         ctrl_buff[0x4];
9882         u8         untagged_buff[0x4];
9883 };
9884
9885 struct mlx5_ifc_pbmc_reg_bits {
9886         u8         reserved_at_0[0x8];
9887         u8         local_port[0x8];
9888         u8         reserved_at_10[0x10];
9889
9890         u8         xoff_timer_value[0x10];
9891         u8         xoff_refresh[0x10];
9892
9893         u8         reserved_at_40[0x9];
9894         u8         fullness_threshold[0x7];
9895         u8         port_buffer_size[0x10];
9896
9897         struct mlx5_ifc_bufferx_reg_bits buffer[10];
9898
9899         u8         reserved_at_2e0[0x40];
9900 };
9901
9902 struct mlx5_ifc_qtct_reg_bits {
9903         u8         reserved_at_0[0x8];
9904         u8         port_number[0x8];
9905         u8         reserved_at_10[0xd];
9906         u8         prio[0x3];
9907
9908         u8         reserved_at_20[0x1d];
9909         u8         tclass[0x3];
9910 };
9911
9912 struct mlx5_ifc_mcia_reg_bits {
9913         u8         l[0x1];
9914         u8         reserved_at_1[0x7];
9915         u8         module[0x8];
9916         u8         reserved_at_10[0x8];
9917         u8         status[0x8];
9918
9919         u8         i2c_device_address[0x8];
9920         u8         page_number[0x8];
9921         u8         device_address[0x10];
9922
9923         u8         reserved_at_40[0x10];
9924         u8         size[0x10];
9925
9926         u8         reserved_at_60[0x20];
9927
9928         u8         dword_0[0x20];
9929         u8         dword_1[0x20];
9930         u8         dword_2[0x20];
9931         u8         dword_3[0x20];
9932         u8         dword_4[0x20];
9933         u8         dword_5[0x20];
9934         u8         dword_6[0x20];
9935         u8         dword_7[0x20];
9936         u8         dword_8[0x20];
9937         u8         dword_9[0x20];
9938         u8         dword_10[0x20];
9939         u8         dword_11[0x20];
9940 };
9941
9942 struct mlx5_ifc_dcbx_param_bits {
9943         u8         dcbx_cee_cap[0x1];
9944         u8         dcbx_ieee_cap[0x1];
9945         u8         dcbx_standby_cap[0x1];
9946         u8         reserved_at_3[0x5];
9947         u8         port_number[0x8];
9948         u8         reserved_at_10[0xa];
9949         u8         max_application_table_size[6];
9950         u8         reserved_at_20[0x15];
9951         u8         version_oper[0x3];
9952         u8         reserved_at_38[5];
9953         u8         version_admin[0x3];
9954         u8         willing_admin[0x1];
9955         u8         reserved_at_41[0x3];
9956         u8         pfc_cap_oper[0x4];
9957         u8         reserved_at_48[0x4];
9958         u8         pfc_cap_admin[0x4];
9959         u8         reserved_at_50[0x4];
9960         u8         num_of_tc_oper[0x4];
9961         u8         reserved_at_58[0x4];
9962         u8         num_of_tc_admin[0x4];
9963         u8         remote_willing[0x1];
9964         u8         reserved_at_61[3];
9965         u8         remote_pfc_cap[4];
9966         u8         reserved_at_68[0x14];
9967         u8         remote_num_of_tc[0x4];
9968         u8         reserved_at_80[0x18];
9969         u8         error[0x8];
9970         u8         reserved_at_a0[0x160];
9971 };
9972
9973 struct mlx5_ifc_lagc_bits {
9974         u8         reserved_at_0[0x1d];
9975         u8         lag_state[0x3];
9976
9977         u8         reserved_at_20[0x14];
9978         u8         tx_remap_affinity_2[0x4];
9979         u8         reserved_at_38[0x4];
9980         u8         tx_remap_affinity_1[0x4];
9981 };
9982
9983 struct mlx5_ifc_create_lag_out_bits {
9984         u8         status[0x8];
9985         u8         reserved_at_8[0x18];
9986
9987         u8         syndrome[0x20];
9988
9989         u8         reserved_at_40[0x40];
9990 };
9991
9992 struct mlx5_ifc_create_lag_in_bits {
9993         u8         opcode[0x10];
9994         u8         reserved_at_10[0x10];
9995
9996         u8         reserved_at_20[0x10];
9997         u8         op_mod[0x10];
9998
9999         struct mlx5_ifc_lagc_bits ctx;
10000 };
10001
10002 struct mlx5_ifc_modify_lag_out_bits {
10003         u8         status[0x8];
10004         u8         reserved_at_8[0x18];
10005
10006         u8         syndrome[0x20];
10007
10008         u8         reserved_at_40[0x40];
10009 };
10010
10011 struct mlx5_ifc_modify_lag_in_bits {
10012         u8         opcode[0x10];
10013         u8         reserved_at_10[0x10];
10014
10015         u8         reserved_at_20[0x10];
10016         u8         op_mod[0x10];
10017
10018         u8         reserved_at_40[0x20];
10019         u8         field_select[0x20];
10020
10021         struct mlx5_ifc_lagc_bits ctx;
10022 };
10023
10024 struct mlx5_ifc_query_lag_out_bits {
10025         u8         status[0x8];
10026         u8         reserved_at_8[0x18];
10027
10028         u8         syndrome[0x20];
10029
10030         struct mlx5_ifc_lagc_bits ctx;
10031 };
10032
10033 struct mlx5_ifc_query_lag_in_bits {
10034         u8         opcode[0x10];
10035         u8         reserved_at_10[0x10];
10036
10037         u8         reserved_at_20[0x10];
10038         u8         op_mod[0x10];
10039
10040         u8         reserved_at_40[0x40];
10041 };
10042
10043 struct mlx5_ifc_destroy_lag_out_bits {
10044         u8         status[0x8];
10045         u8         reserved_at_8[0x18];
10046
10047         u8         syndrome[0x20];
10048
10049         u8         reserved_at_40[0x40];
10050 };
10051
10052 struct mlx5_ifc_destroy_lag_in_bits {
10053         u8         opcode[0x10];
10054         u8         reserved_at_10[0x10];
10055
10056         u8         reserved_at_20[0x10];
10057         u8         op_mod[0x10];
10058
10059         u8         reserved_at_40[0x40];
10060 };
10061
10062 struct mlx5_ifc_create_vport_lag_out_bits {
10063         u8         status[0x8];
10064         u8         reserved_at_8[0x18];
10065
10066         u8         syndrome[0x20];
10067
10068         u8         reserved_at_40[0x40];
10069 };
10070
10071 struct mlx5_ifc_create_vport_lag_in_bits {
10072         u8         opcode[0x10];
10073         u8         reserved_at_10[0x10];
10074
10075         u8         reserved_at_20[0x10];
10076         u8         op_mod[0x10];
10077
10078         u8         reserved_at_40[0x40];
10079 };
10080
10081 struct mlx5_ifc_destroy_vport_lag_out_bits {
10082         u8         status[0x8];
10083         u8         reserved_at_8[0x18];
10084
10085         u8         syndrome[0x20];
10086
10087         u8         reserved_at_40[0x40];
10088 };
10089
10090 struct mlx5_ifc_destroy_vport_lag_in_bits {
10091         u8         opcode[0x10];
10092         u8         reserved_at_10[0x10];
10093
10094         u8         reserved_at_20[0x10];
10095         u8         op_mod[0x10];
10096
10097         u8         reserved_at_40[0x40];
10098 };
10099
10100 struct mlx5_ifc_alloc_memic_in_bits {
10101         u8         opcode[0x10];
10102         u8         reserved_at_10[0x10];
10103
10104         u8         reserved_at_20[0x10];
10105         u8         op_mod[0x10];
10106
10107         u8         reserved_at_30[0x20];
10108
10109         u8         reserved_at_40[0x18];
10110         u8         log_memic_addr_alignment[0x8];
10111
10112         u8         range_start_addr[0x40];
10113
10114         u8         range_size[0x20];
10115
10116         u8         memic_size[0x20];
10117 };
10118
10119 struct mlx5_ifc_alloc_memic_out_bits {
10120         u8         status[0x8];
10121         u8         reserved_at_8[0x18];
10122
10123         u8         syndrome[0x20];
10124
10125         u8         memic_start_addr[0x40];
10126 };
10127
10128 struct mlx5_ifc_dealloc_memic_in_bits {
10129         u8         opcode[0x10];
10130         u8         reserved_at_10[0x10];
10131
10132         u8         reserved_at_20[0x10];
10133         u8         op_mod[0x10];
10134
10135         u8         reserved_at_40[0x40];
10136
10137         u8         memic_start_addr[0x40];
10138
10139         u8         memic_size[0x20];
10140
10141         u8         reserved_at_e0[0x20];
10142 };
10143
10144 struct mlx5_ifc_dealloc_memic_out_bits {
10145         u8         status[0x8];
10146         u8         reserved_at_8[0x18];
10147
10148         u8         syndrome[0x20];
10149
10150         u8         reserved_at_40[0x40];
10151 };
10152
10153 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
10154         u8         opcode[0x10];
10155         u8         uid[0x10];
10156
10157         u8         vhca_tunnel_id[0x10];
10158         u8         obj_type[0x10];
10159
10160         u8         obj_id[0x20];
10161
10162         u8         reserved_at_60[0x20];
10163 };
10164
10165 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
10166         u8         status[0x8];
10167         u8         reserved_at_8[0x18];
10168
10169         u8         syndrome[0x20];
10170
10171         u8         obj_id[0x20];
10172
10173         u8         reserved_at_60[0x20];
10174 };
10175
10176 struct mlx5_ifc_umem_bits {
10177         u8         reserved_at_0[0x80];
10178
10179         u8         reserved_at_80[0x1b];
10180         u8         log_page_size[0x5];
10181
10182         u8         page_offset[0x20];
10183
10184         u8         num_of_mtt[0x40];
10185
10186         struct mlx5_ifc_mtt_bits  mtt[0];
10187 };
10188
10189 struct mlx5_ifc_uctx_bits {
10190         u8         cap[0x20];
10191
10192         u8         reserved_at_20[0x160];
10193 };
10194
10195 struct mlx5_ifc_sw_icm_bits {
10196         u8         modify_field_select[0x40];
10197
10198         u8         reserved_at_40[0x18];
10199         u8         log_sw_icm_size[0x8];
10200
10201         u8         reserved_at_60[0x20];
10202
10203         u8         sw_icm_start_addr[0x40];
10204
10205         u8         reserved_at_c0[0x140];
10206 };
10207
10208 struct mlx5_ifc_geneve_tlv_option_bits {
10209         u8         modify_field_select[0x40];
10210
10211         u8         reserved_at_40[0x18];
10212         u8         geneve_option_fte_index[0x8];
10213
10214         u8         option_class[0x10];
10215         u8         option_type[0x8];
10216         u8         reserved_at_78[0x3];
10217         u8         option_data_length[0x5];
10218
10219         u8         reserved_at_80[0x180];
10220 };
10221
10222 struct mlx5_ifc_create_umem_in_bits {
10223         u8         opcode[0x10];
10224         u8         uid[0x10];
10225
10226         u8         reserved_at_20[0x10];
10227         u8         op_mod[0x10];
10228
10229         u8         reserved_at_40[0x40];
10230
10231         struct mlx5_ifc_umem_bits  umem;
10232 };
10233
10234 struct mlx5_ifc_create_uctx_in_bits {
10235         u8         opcode[0x10];
10236         u8         reserved_at_10[0x10];
10237
10238         u8         reserved_at_20[0x10];
10239         u8         op_mod[0x10];
10240
10241         u8         reserved_at_40[0x40];
10242
10243         struct mlx5_ifc_uctx_bits  uctx;
10244 };
10245
10246 struct mlx5_ifc_destroy_uctx_in_bits {
10247         u8         opcode[0x10];
10248         u8         reserved_at_10[0x10];
10249
10250         u8         reserved_at_20[0x10];
10251         u8         op_mod[0x10];
10252
10253         u8         reserved_at_40[0x10];
10254         u8         uid[0x10];
10255
10256         u8         reserved_at_60[0x20];
10257 };
10258
10259 struct mlx5_ifc_create_sw_icm_in_bits {
10260         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
10261         struct mlx5_ifc_sw_icm_bits                   sw_icm;
10262 };
10263
10264 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
10265         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
10266         struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
10267 };
10268
10269 struct mlx5_ifc_mtrc_string_db_param_bits {
10270         u8         string_db_base_address[0x20];
10271
10272         u8         reserved_at_20[0x8];
10273         u8         string_db_size[0x18];
10274 };
10275
10276 struct mlx5_ifc_mtrc_cap_bits {
10277         u8         trace_owner[0x1];
10278         u8         trace_to_memory[0x1];
10279         u8         reserved_at_2[0x4];
10280         u8         trc_ver[0x2];
10281         u8         reserved_at_8[0x14];
10282         u8         num_string_db[0x4];
10283
10284         u8         first_string_trace[0x8];
10285         u8         num_string_trace[0x8];
10286         u8         reserved_at_30[0x28];
10287
10288         u8         log_max_trace_buffer_size[0x8];
10289
10290         u8         reserved_at_60[0x20];
10291
10292         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
10293
10294         u8         reserved_at_280[0x180];
10295 };
10296
10297 struct mlx5_ifc_mtrc_conf_bits {
10298         u8         reserved_at_0[0x1c];
10299         u8         trace_mode[0x4];
10300         u8         reserved_at_20[0x18];
10301         u8         log_trace_buffer_size[0x8];
10302         u8         trace_mkey[0x20];
10303         u8         reserved_at_60[0x3a0];
10304 };
10305
10306 struct mlx5_ifc_mtrc_stdb_bits {
10307         u8         string_db_index[0x4];
10308         u8         reserved_at_4[0x4];
10309         u8         read_size[0x18];
10310         u8         start_offset[0x20];
10311         u8         string_db_data[0];
10312 };
10313
10314 struct mlx5_ifc_mtrc_ctrl_bits {
10315         u8         trace_status[0x2];
10316         u8         reserved_at_2[0x2];
10317         u8         arm_event[0x1];
10318         u8         reserved_at_5[0xb];
10319         u8         modify_field_select[0x10];
10320         u8         reserved_at_20[0x2b];
10321         u8         current_timestamp52_32[0x15];
10322         u8         current_timestamp31_0[0x20];
10323         u8         reserved_at_80[0x180];
10324 };
10325
10326 struct mlx5_ifc_host_params_context_bits {
10327         u8         host_number[0x8];
10328         u8         reserved_at_8[0x7];
10329         u8         host_pf_disabled[0x1];
10330         u8         host_num_of_vfs[0x10];
10331
10332         u8         host_total_vfs[0x10];
10333         u8         host_pci_bus[0x10];
10334
10335         u8         reserved_at_40[0x10];
10336         u8         host_pci_device[0x10];
10337
10338         u8         reserved_at_60[0x10];
10339         u8         host_pci_function[0x10];
10340
10341         u8         reserved_at_80[0x180];
10342 };
10343
10344 struct mlx5_ifc_query_esw_functions_in_bits {
10345         u8         opcode[0x10];
10346         u8         reserved_at_10[0x10];
10347
10348         u8         reserved_at_20[0x10];
10349         u8         op_mod[0x10];
10350
10351         u8         reserved_at_40[0x40];
10352 };
10353
10354 struct mlx5_ifc_query_esw_functions_out_bits {
10355         u8         status[0x8];
10356         u8         reserved_at_8[0x18];
10357
10358         u8         syndrome[0x20];
10359
10360         u8         reserved_at_40[0x40];
10361
10362         struct mlx5_ifc_host_params_context_bits host_params_context;
10363
10364         u8         reserved_at_280[0x180];
10365         u8         host_sf_enable[0][0x40];
10366 };
10367
10368 struct mlx5_ifc_sf_partition_bits {
10369         u8         reserved_at_0[0x10];
10370         u8         log_num_sf[0x8];
10371         u8         log_sf_bar_size[0x8];
10372 };
10373
10374 struct mlx5_ifc_query_sf_partitions_out_bits {
10375         u8         status[0x8];
10376         u8         reserved_at_8[0x18];
10377
10378         u8         syndrome[0x20];
10379
10380         u8         reserved_at_40[0x18];
10381         u8         num_sf_partitions[0x8];
10382
10383         u8         reserved_at_60[0x20];
10384
10385         struct mlx5_ifc_sf_partition_bits sf_partition[0];
10386 };
10387
10388 struct mlx5_ifc_query_sf_partitions_in_bits {
10389         u8         opcode[0x10];
10390         u8         reserved_at_10[0x10];
10391
10392         u8         reserved_at_20[0x10];
10393         u8         op_mod[0x10];
10394
10395         u8         reserved_at_40[0x40];
10396 };
10397
10398 struct mlx5_ifc_dealloc_sf_out_bits {
10399         u8         status[0x8];
10400         u8         reserved_at_8[0x18];
10401
10402         u8         syndrome[0x20];
10403
10404         u8         reserved_at_40[0x40];
10405 };
10406
10407 struct mlx5_ifc_dealloc_sf_in_bits {
10408         u8         opcode[0x10];
10409         u8         reserved_at_10[0x10];
10410
10411         u8         reserved_at_20[0x10];
10412         u8         op_mod[0x10];
10413
10414         u8         reserved_at_40[0x10];
10415         u8         function_id[0x10];
10416
10417         u8         reserved_at_60[0x20];
10418 };
10419
10420 struct mlx5_ifc_alloc_sf_out_bits {
10421         u8         status[0x8];
10422         u8         reserved_at_8[0x18];
10423
10424         u8         syndrome[0x20];
10425
10426         u8         reserved_at_40[0x40];
10427 };
10428
10429 struct mlx5_ifc_alloc_sf_in_bits {
10430         u8         opcode[0x10];
10431         u8         reserved_at_10[0x10];
10432
10433         u8         reserved_at_20[0x10];
10434         u8         op_mod[0x10];
10435
10436         u8         reserved_at_40[0x10];
10437         u8         function_id[0x10];
10438
10439         u8         reserved_at_60[0x20];
10440 };
10441
10442 struct mlx5_ifc_affiliated_event_header_bits {
10443         u8         reserved_at_0[0x10];
10444         u8         obj_type[0x10];
10445
10446         u8         obj_id[0x20];
10447 };
10448
10449 enum {
10450         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
10451 };
10452
10453 enum {
10454         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10455 };
10456
10457 struct mlx5_ifc_encryption_key_obj_bits {
10458         u8         modify_field_select[0x40];
10459
10460         u8         reserved_at_40[0x14];
10461         u8         key_size[0x4];
10462         u8         reserved_at_58[0x4];
10463         u8         key_type[0x4];
10464
10465         u8         reserved_at_60[0x8];
10466         u8         pd[0x18];
10467
10468         u8         reserved_at_80[0x180];
10469         u8         key[8][0x20];
10470
10471         u8         reserved_at_300[0x500];
10472 };
10473
10474 struct mlx5_ifc_create_encryption_key_in_bits {
10475         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10476         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10477 };
10478
10479 enum {
10480         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10481         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10482 };
10483
10484 enum {
10485         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
10486 };
10487
10488 struct mlx5_ifc_tls_static_params_bits {
10489         u8         const_2[0x2];
10490         u8         tls_version[0x4];
10491         u8         const_1[0x2];
10492         u8         reserved_at_8[0x14];
10493         u8         encryption_standard[0x4];
10494
10495         u8         reserved_at_20[0x20];
10496
10497         u8         initial_record_number[0x40];
10498
10499         u8         resync_tcp_sn[0x20];
10500
10501         u8         gcm_iv[0x20];
10502
10503         u8         implicit_iv[0x40];
10504
10505         u8         reserved_at_100[0x8];
10506         u8         dek_index[0x18];
10507
10508         u8         reserved_at_120[0xe0];
10509 };
10510
10511 struct mlx5_ifc_tls_progress_params_bits {
10512         u8         reserved_at_0[0x8];
10513         u8         tisn[0x18];
10514
10515         u8         next_record_tcp_sn[0x20];
10516
10517         u8         hw_resync_tcp_sn[0x20];
10518
10519         u8         record_tracker_state[0x2];
10520         u8         auth_state[0x2];
10521         u8         reserved_at_64[0x4];
10522         u8         hw_offset_record_number[0x18];
10523 };
10524
10525 #endif /* MLX5_IFC_H */