2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/radix-tree.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
50 #include <linux/mlx5/device.h>
51 #include <linux/mlx5/doorbell.h>
52 #include <linux/mlx5/srq.h>
53 #include <linux/timecounter.h>
54 #include <linux/ptp_clock_kernel.h>
57 MLX5_BOARD_ID_LEN = 64,
58 MLX5_MAX_NAME_LEN = 16,
62 /* one minute for the sake of bringup. Generally, commands must always
63 * complete and we may need to increase this timeout value
65 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
66 MLX5_CMD_WQ_MAX_NAME = 32,
72 CMD_STATUS_SUCCESS = 0,
78 MLX5_SQP_IEEE_1588 = 2,
80 MLX5_SQP_SYNC_UMR = 4,
88 MLX5_EQ_VEC_PAGES = 0,
90 MLX5_EQ_VEC_ASYNC = 2,
91 MLX5_EQ_VEC_PFAULT = 3,
92 MLX5_EQ_VEC_COMP_BASE,
96 MLX5_MAX_IRQ_NAME = 32
100 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
101 MLX5_ATOMIC_MODE_CX = 2 << 16,
102 MLX5_ATOMIC_MODE_8B = 3 << 16,
103 MLX5_ATOMIC_MODE_16B = 4 << 16,
104 MLX5_ATOMIC_MODE_32B = 5 << 16,
105 MLX5_ATOMIC_MODE_64B = 6 << 16,
106 MLX5_ATOMIC_MODE_128B = 7 << 16,
107 MLX5_ATOMIC_MODE_256B = 8 << 16,
111 MLX5_REG_QPTS = 0x4002,
112 MLX5_REG_QETCR = 0x4005,
113 MLX5_REG_QTCT = 0x400a,
114 MLX5_REG_QPDPM = 0x4013,
115 MLX5_REG_QCAM = 0x4019,
116 MLX5_REG_DCBX_PARAM = 0x4020,
117 MLX5_REG_DCBX_APP = 0x4021,
118 MLX5_REG_FPGA_CAP = 0x4022,
119 MLX5_REG_FPGA_CTRL = 0x4023,
120 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
121 MLX5_REG_PCAP = 0x5001,
122 MLX5_REG_PMTU = 0x5003,
123 MLX5_REG_PTYS = 0x5004,
124 MLX5_REG_PAOS = 0x5006,
125 MLX5_REG_PFCC = 0x5007,
126 MLX5_REG_PPCNT = 0x5008,
127 MLX5_REG_PPTB = 0x500b,
128 MLX5_REG_PBMC = 0x500c,
129 MLX5_REG_PMAOS = 0x5012,
130 MLX5_REG_PUDE = 0x5009,
131 MLX5_REG_PMPE = 0x5010,
132 MLX5_REG_PELC = 0x500e,
133 MLX5_REG_PVLC = 0x500f,
134 MLX5_REG_PCMR = 0x5041,
135 MLX5_REG_PMLP = 0x5002,
136 MLX5_REG_PCAM = 0x507f,
137 MLX5_REG_NODE_DESC = 0x6001,
138 MLX5_REG_HOST_ENDIANNESS = 0x7004,
139 MLX5_REG_MCIA = 0x9014,
140 MLX5_REG_MLCR = 0x902b,
141 MLX5_REG_MPCNT = 0x9051,
142 MLX5_REG_MTPPS = 0x9053,
143 MLX5_REG_MTPPSE = 0x9054,
144 MLX5_REG_MCQI = 0x9061,
145 MLX5_REG_MCC = 0x9062,
146 MLX5_REG_MCDA = 0x9063,
147 MLX5_REG_MCAM = 0x907f,
150 enum mlx5_qpts_trust_state {
151 MLX5_QPTS_TRUST_PCP = 1,
152 MLX5_QPTS_TRUST_DSCP = 2,
155 enum mlx5_dcbx_oper_mode {
156 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
157 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
160 enum mlx5_dct_atomic_mode {
161 MLX5_ATOMIC_MODE_DCT_OFF = 20,
162 MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF,
163 MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF,
164 MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF,
168 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
169 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
172 enum mlx5_page_fault_resume_flags {
173 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
174 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
175 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
176 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
185 enum port_state_policy {
186 MLX5_POLICY_DOWN = 0,
188 MLX5_POLICY_FOLLOW = 2,
189 MLX5_POLICY_INVALID = 0xffffffff
192 struct mlx5_field_desc {
197 struct mlx5_rsc_debug {
198 struct mlx5_core_dev *dev;
200 enum dbg_rsc_type type;
202 struct mlx5_field_desc fields[0];
205 enum mlx5_dev_event {
206 MLX5_DEV_EVENT_SYS_ERROR,
207 MLX5_DEV_EVENT_PORT_UP,
208 MLX5_DEV_EVENT_PORT_DOWN,
209 MLX5_DEV_EVENT_PORT_INITIALIZED,
210 MLX5_DEV_EVENT_LID_CHANGE,
211 MLX5_DEV_EVENT_PKEY_CHANGE,
212 MLX5_DEV_EVENT_GUID_CHANGE,
213 MLX5_DEV_EVENT_CLIENT_REREG,
215 MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT,
218 enum mlx5_port_status {
226 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
231 struct mlx5_bfreg_info {
233 int num_low_latency_bfregs;
237 * protect bfreg allocation data structs
243 u32 num_static_sys_pages;
244 u32 total_num_bfregs;
248 struct mlx5_cmd_first {
252 struct mlx5_cmd_msg {
253 struct list_head list;
254 struct cmd_msg_cache *parent;
256 struct mlx5_cmd_first first;
257 struct mlx5_cmd_mailbox *next;
260 struct mlx5_cmd_debug {
261 struct dentry *dbg_root;
262 struct dentry *dbg_in;
263 struct dentry *dbg_out;
264 struct dentry *dbg_outlen;
265 struct dentry *dbg_status;
266 struct dentry *dbg_run;
274 struct cmd_msg_cache {
275 /* protect block chain allocations
278 struct list_head head;
279 unsigned int max_inbox_size;
280 unsigned int num_ent;
284 MLX5_NUM_COMMAND_CACHES = 5,
287 struct mlx5_cmd_stats {
292 struct dentry *count;
293 /* protect command average calculations */
299 dma_addr_t alloc_dma;
310 /* protect command queue allocations
312 spinlock_t alloc_lock;
314 /* protect token allocations
316 spinlock_t token_lock;
318 unsigned long bitmask;
319 char wq_name[MLX5_CMD_WQ_MAX_NAME];
320 struct workqueue_struct *wq;
321 struct semaphore sem;
322 struct semaphore pages_sem;
324 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
325 struct dma_pool *pool;
326 struct mlx5_cmd_debug dbg;
327 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
328 int checksum_disabled;
329 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
332 struct mlx5_port_caps {
339 struct mlx5_cmd_mailbox {
342 struct mlx5_cmd_mailbox *next;
345 struct mlx5_buf_list {
350 struct mlx5_frag_buf {
351 struct mlx5_buf_list *frags;
357 struct mlx5_frag_buf_ctrl {
358 struct mlx5_frag_buf frag_buf;
367 struct mlx5_eq_tasklet {
368 struct list_head list;
369 struct list_head process_list;
370 struct tasklet_struct task;
371 /* lock on completion tasklet list */
375 struct mlx5_eq_pagefault {
376 struct work_struct work;
377 /* Pagefaults lock */
379 struct workqueue_struct *wq;
383 struct mlx5_cq_table {
384 /* protect radix tree */
386 struct radix_tree_root tree;
390 struct mlx5_core_dev *dev;
391 struct mlx5_cq_table cq_table;
392 __be32 __iomem *doorbell;
394 struct mlx5_frag_buf buf;
400 struct list_head list;
402 struct mlx5_rsc_debug *dbg;
403 enum mlx5_eq_type type;
405 struct mlx5_eq_tasklet tasklet_ctx;
406 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
407 struct mlx5_eq_pagefault pf_ctx;
412 struct mlx5_core_psv {
424 struct mlx5_core_sig_ctx {
425 struct mlx5_core_psv psv_memory;
426 struct mlx5_core_psv psv_wire;
427 struct ib_sig_err err_item;
428 bool sig_status_checked;
438 struct mlx5_core_mkey {
446 #define MLX5_24BIT_MASK ((1 << 24) - 1)
449 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
450 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
451 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
455 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT,
458 struct mlx5_core_rsc_common {
459 enum mlx5_res_type res;
461 struct completion free;
464 struct mlx5_core_srq {
465 struct mlx5_core_rsc_common common; /* must be first */
469 size_t max_avail_gather;
471 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
474 struct completion free;
477 struct mlx5_eq_table {
478 void __iomem *update_ci;
479 void __iomem *update_arm_ci;
480 struct list_head comp_eqs_list;
481 struct mlx5_eq pages_eq;
482 struct mlx5_eq async_eq;
483 struct mlx5_eq cmd_eq;
484 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
485 struct mlx5_eq pfault_eq;
487 int num_comp_vectors;
493 struct mlx5_uars_page {
497 struct list_head list;
499 unsigned long *reg_bitmap; /* for non fast path bf regs */
500 unsigned long *fp_bitmap;
501 unsigned int reg_avail;
502 unsigned int fp_avail;
503 struct kref ref_count;
504 struct mlx5_core_dev *mdev;
507 struct mlx5_bfreg_head {
508 /* protect blue flame registers allocations */
510 struct list_head list;
513 struct mlx5_bfreg_data {
514 struct mlx5_bfreg_head reg_head;
515 struct mlx5_bfreg_head wc_head;
518 struct mlx5_sq_bfreg {
520 struct mlx5_uars_page *up;
526 struct mlx5_core_health {
527 struct health_buffer __iomem *health;
528 __be32 __iomem *health_counter;
529 struct timer_list timer;
533 /* wq spinlock to synchronize draining */
535 struct workqueue_struct *wq;
537 struct work_struct work;
538 struct delayed_work recover_work;
541 struct mlx5_qp_table {
542 /* protect radix tree
545 struct radix_tree_root tree;
548 struct mlx5_srq_table {
549 /* protect radix tree
552 struct radix_tree_root tree;
555 struct mlx5_mkey_table {
556 /* protect radix tree
559 struct radix_tree_root tree;
562 struct mlx5_vf_context {
566 enum port_state_policy policy;
569 struct mlx5_core_sriov {
570 struct mlx5_vf_context *vfs_ctx;
575 struct mlx5_irq_info {
577 char name[MLX5_MAX_IRQ_NAME];
580 struct mlx5_fc_stats {
581 struct rb_root counters;
582 struct list_head addlist;
583 /* protect addlist add/splice operations */
584 spinlock_t addlist_lock;
586 struct workqueue_struct *wq;
587 struct delayed_work work;
588 unsigned long next_query;
589 unsigned long sampling_interval; /* jiffies */
595 struct mlx5_pagefault;
597 struct mlx5_rate_limit {
603 struct mlx5_rl_entry {
604 struct mlx5_rate_limit rl;
609 struct mlx5_rl_table {
610 /* protect rate limit table */
611 struct mutex rl_lock;
615 struct mlx5_rl_entry *rl_entry;
618 enum port_module_event_status_type {
619 MLX5_MODULE_STATUS_PLUGGED = 0x1,
620 MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
621 MLX5_MODULE_STATUS_ERROR = 0x3,
622 MLX5_MODULE_STATUS_NUM = 0x3,
625 enum port_module_event_error_type {
626 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED,
627 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE,
628 MLX5_MODULE_EVENT_ERROR_BUS_STUCK,
629 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT,
630 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST,
631 MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER,
632 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE,
633 MLX5_MODULE_EVENT_ERROR_BAD_CABLE,
634 MLX5_MODULE_EVENT_ERROR_UNKNOWN,
635 MLX5_MODULE_EVENT_ERROR_NUM,
638 struct mlx5_port_module_event_stats {
639 u64 status_counters[MLX5_MODULE_STATUS_NUM];
640 u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
644 char name[MLX5_MAX_NAME_LEN];
645 struct mlx5_eq_table eq_table;
646 struct mlx5_irq_info *irq_info;
649 struct workqueue_struct *pg_wq;
650 struct rb_root page_root;
653 struct list_head free_list;
656 struct mlx5_core_health health;
658 struct mlx5_srq_table srq_table;
660 /* start: qp staff */
661 struct mlx5_qp_table qp_table;
662 struct dentry *qp_debugfs;
663 struct dentry *eq_debugfs;
664 struct dentry *cq_debugfs;
665 struct dentry *cmdif_debugfs;
668 /* start: mkey staff */
669 struct mlx5_mkey_table mkey_table;
670 /* end: mkey staff */
672 /* start: alloc staff */
673 /* protect buffer alocation according to numa node */
674 struct mutex alloc_mutex;
677 struct mutex pgdir_mutex;
678 struct list_head pgdir_list;
679 /* end: alloc staff */
680 struct dentry *dbg_root;
682 /* protect mkey key part */
683 spinlock_t mkey_lock;
686 struct list_head dev_list;
687 struct list_head ctx_list;
690 struct list_head waiting_events_list;
691 bool is_accum_events;
693 struct mlx5_flow_steering *steering;
694 struct mlx5_mpfs *mpfs;
695 struct mlx5_eswitch *eswitch;
696 struct mlx5_core_sriov sriov;
697 struct mlx5_lag *lag;
698 unsigned long pci_dev_data;
699 struct mlx5_fc_stats fc_stats;
700 struct mlx5_rl_table rl_table;
702 struct mlx5_port_module_event_stats pme_stats;
704 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
705 void (*pfault)(struct mlx5_core_dev *dev,
707 struct mlx5_pagefault *pfault);
709 struct srcu_struct pfault_srcu;
711 struct mlx5_bfreg_data bfregs;
712 struct mlx5_uars_page *uar;
715 enum mlx5_device_state {
716 MLX5_DEVICE_STATE_UP,
717 MLX5_DEVICE_STATE_INTERNAL_ERROR,
720 enum mlx5_interface_state {
721 MLX5_INTERFACE_STATE_UP = BIT(0),
724 enum mlx5_pci_status {
725 MLX5_PCI_STATUS_DISABLED,
726 MLX5_PCI_STATUS_ENABLED,
729 enum mlx5_pagefault_type_flags {
730 MLX5_PFAULT_REQUESTOR = 1 << 0,
731 MLX5_PFAULT_WRITE = 1 << 1,
732 MLX5_PFAULT_RDMA = 1 << 2,
735 /* Contains the details of a pagefault. */
736 struct mlx5_pagefault {
742 /* Initiator or send message responder pagefault details. */
744 /* Received packet size, only valid for responders. */
747 * Number of resource holding WQE, depends on type.
751 * WQE index. Refers to either the send queue or
752 * receive queue, according to event_subtype.
756 /* RDMA responder pagefault details */
760 * Received packet size, minimal size page fault
761 * resolution required for forward progress.
770 struct work_struct work;
774 struct list_head tirs_list;
778 struct mlx5e_resources {
781 struct mlx5_core_mkey mkey;
782 struct mlx5_sq_bfreg bfreg;
785 #define MLX5_MAX_RESERVED_GIDS 8
787 struct mlx5_rsvd_gids {
793 #define MAX_PIN_NUM 8
795 u8 pin_caps[MAX_PIN_NUM];
796 struct work_struct out_work;
797 u64 start[MAX_PIN_NUM];
803 struct cyclecounter cycles;
804 struct timecounter tc;
805 struct hwtstamp_config hwtstamp_config;
807 unsigned long overflow_period;
808 struct delayed_work overflow_work;
809 struct mlx5_core_dev *mdev;
810 struct ptp_clock *ptp;
811 struct ptp_clock_info ptp_info;
812 struct mlx5_pps pps_info;
815 struct mlx5_core_dev {
816 struct pci_dev *pdev;
818 struct mutex pci_status_mutex;
819 enum mlx5_pci_status pci_status;
821 char board_id[MLX5_BOARD_ID_LEN];
823 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
825 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
826 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
827 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
828 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
829 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
830 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
832 phys_addr_t iseg_base;
833 struct mlx5_init_seg __iomem *iseg;
834 enum mlx5_device_state state;
835 /* sync interface state */
836 struct mutex intf_state_mutex;
837 unsigned long intf_state;
838 void (*event) (struct mlx5_core_dev *dev,
839 enum mlx5_dev_event event,
840 unsigned long param);
841 struct mlx5_priv priv;
842 struct mlx5_profile *profile;
845 struct mlx5e_resources mlx5e_res;
847 struct mlx5_rsvd_gids reserved_gids;
850 #ifdef CONFIG_MLX5_FPGA
851 struct mlx5_fpga_device *fpga;
853 #ifdef CONFIG_RFS_ACCEL
854 struct cpu_rmap *rmap;
856 struct mlx5_clock clock;
857 struct mlx5_ib_clock_info *clock_info;
858 struct page *clock_info_page;
864 struct mlx5_db_pgdir *pgdir;
865 struct mlx5_ib_user_db_page *user_page;
872 MLX5_COMP_EQ_SIZE = 1024,
876 MLX5_PTYS_IB = 1 << 0,
877 MLX5_PTYS_EN = 1 << 2,
880 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
883 MLX5_CMD_ENT_STATE_PENDING_COMP,
886 struct mlx5_cmd_work_ent {
888 struct mlx5_cmd_msg *in;
889 struct mlx5_cmd_msg *out;
892 mlx5_cmd_cbk_t callback;
893 struct delayed_work cb_timeout_work;
896 struct completion done;
897 struct mlx5_cmd *cmd;
898 struct work_struct work;
899 struct mlx5_cmd_layout *lay;
915 enum phy_port_state {
919 struct mlx5_hca_vport_context {
924 enum port_state_policy policy;
925 enum phy_port_state phys_state;
926 enum ib_port_state vport_state;
927 u8 port_physical_state;
936 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
941 u16 qkey_violation_counter;
942 u16 pkey_violation_counter;
946 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset)
948 return buf->frags->buf + offset;
951 #define STRUCT_FIELD(header, field) \
952 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
953 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
955 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
957 return pci_get_drvdata(pdev);
960 extern struct dentry *mlx5_debugfs_root;
962 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
964 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
967 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
969 return ioread32be(&dev->iseg->fw_rev) >> 16;
972 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
974 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
977 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
979 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
982 static inline u32 mlx5_base_mkey(const u32 key)
984 return key & 0xffffff00u;
987 static inline void mlx5_fill_fbc_offset(u8 log_stride, u8 log_sz,
989 struct mlx5_frag_buf_ctrl *fbc)
991 fbc->log_stride = log_stride;
992 fbc->log_sz = log_sz;
993 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
994 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
995 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
996 fbc->strides_offset = strides_offset;
999 static inline void mlx5_fill_fbc(u8 log_stride, u8 log_sz,
1000 struct mlx5_frag_buf_ctrl *fbc)
1002 mlx5_fill_fbc_offset(log_stride, log_sz, 0, fbc);
1005 static inline void mlx5_core_init_cq_frag_buf(struct mlx5_frag_buf_ctrl *fbc,
1008 mlx5_fill_fbc(6 + MLX5_GET(cqc, cqc, cqe_sz),
1009 MLX5_GET(cqc, cqc, log_cq_size),
1013 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
1018 ix += fbc->strides_offset;
1019 frag = ix >> fbc->log_frag_strides;
1021 return fbc->frag_buf.frags[frag].buf +
1022 ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
1025 int mlx5_cmd_init(struct mlx5_core_dev *dev);
1026 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
1027 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
1028 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
1030 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1032 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1033 void *out, int out_size, mlx5_cmd_cbk_t callback,
1035 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1036 void *out, int out_size);
1037 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
1039 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
1040 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
1041 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
1042 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1043 int mlx5_health_init(struct mlx5_core_dev *dev);
1044 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1045 void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
1046 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1047 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1048 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
1049 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1050 struct mlx5_frag_buf *buf, int node);
1051 int mlx5_buf_alloc(struct mlx5_core_dev *dev,
1052 int size, struct mlx5_frag_buf *buf);
1053 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1054 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1055 struct mlx5_frag_buf *buf, int node);
1056 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1057 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1058 gfp_t flags, int npages);
1059 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1060 struct mlx5_cmd_mailbox *head);
1061 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1062 struct mlx5_srq_attr *in);
1063 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
1064 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1065 struct mlx5_srq_attr *out);
1066 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1067 u16 lwm, int is_srq);
1068 void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
1069 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
1070 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
1071 struct mlx5_core_mkey *mkey,
1073 u32 *out, int outlen,
1074 mlx5_cmd_cbk_t callback, void *context);
1075 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
1076 struct mlx5_core_mkey *mkey,
1077 u32 *in, int inlen);
1078 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
1079 struct mlx5_core_mkey *mkey);
1080 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
1081 u32 *out, int outlen);
1082 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
1084 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1085 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1086 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
1087 u16 opmod, u8 port);
1088 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1089 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1090 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1091 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1092 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1094 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1095 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1096 void mlx5_register_debugfs(void);
1097 void mlx5_unregister_debugfs(void);
1099 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas);
1100 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1101 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1102 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1103 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1104 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
1105 unsigned int *irqn);
1106 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1107 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1109 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1110 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1111 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1112 int size_in, void *data_out, int size_out,
1113 u16 reg_num, int arg, int write);
1115 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1116 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1118 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1120 const char *mlx5_command_str(int command);
1121 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1122 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1123 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1124 int npsvs, u32 *sig_index);
1125 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1126 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1127 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1128 struct mlx5_odp_caps *odp_caps);
1129 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1130 u8 port_num, void *out, size_t sz);
1131 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1132 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token,
1133 u32 wq_num, u8 type, int error);
1136 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1137 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1138 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1139 struct mlx5_rate_limit *rl);
1140 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1141 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1142 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1143 struct mlx5_rate_limit *rl_1);
1144 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1145 bool map_wc, bool fast_path);
1146 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1148 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1149 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1150 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1151 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1153 static inline int fw_initializing(struct mlx5_core_dev *dev)
1155 return ioread32be(&dev->iseg->initializing) >> 31;
1158 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1163 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1165 return mkey_idx << 8;
1168 static inline u8 mlx5_mkey_variant(u32 mkey)
1174 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
1175 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
1179 MR_CACHE_LAST_STD_ENTRY = 20,
1180 MLX5_IMR_MTT_CACHE_ENTRY,
1181 MLX5_IMR_KSM_CACHE_ENTRY,
1182 MAX_MR_CACHE_ENTRIES
1186 MLX5_INTERFACE_PROTOCOL_IB = 0,
1187 MLX5_INTERFACE_PROTOCOL_ETH = 1,
1190 struct mlx5_interface {
1191 void * (*add)(struct mlx5_core_dev *dev);
1192 void (*remove)(struct mlx5_core_dev *dev, void *context);
1193 int (*attach)(struct mlx5_core_dev *dev, void *context);
1194 void (*detach)(struct mlx5_core_dev *dev, void *context);
1195 void (*event)(struct mlx5_core_dev *dev, void *context,
1196 enum mlx5_dev_event event, unsigned long param);
1197 void (*pfault)(struct mlx5_core_dev *dev,
1199 struct mlx5_pagefault *pfault);
1200 void * (*get_dev)(void *context);
1202 struct list_head list;
1205 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1206 int mlx5_register_interface(struct mlx5_interface *intf);
1207 void mlx5_unregister_interface(struct mlx5_interface *intf);
1208 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1210 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1211 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1212 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1213 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1214 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1218 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1219 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1221 #ifndef CONFIG_MLX5_CORE_IPOIB
1223 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1224 struct ib_device *ibdev,
1226 void (*setup)(struct net_device *))
1228 return ERR_PTR(-EOPNOTSUPP);
1231 static inline void mlx5_rdma_netdev_free(struct net_device *netdev) {}
1233 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1234 struct ib_device *ibdev,
1236 void (*setup)(struct net_device *));
1237 void mlx5_rdma_netdev_free(struct net_device *netdev);
1238 #endif /* CONFIG_MLX5_CORE_IPOIB */
1240 struct mlx5_profile {
1246 } mr_cache[MAX_MR_CACHE_ENTRIES];
1250 MLX5_PCI_DEV_IS_VF = 1 << 0,
1253 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1255 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1258 #define MLX5_TOTAL_VPORTS(mdev) (1 + pci_sriov_get_totalvfs((mdev)->pdev))
1259 #define MLX5_VPORT_MANAGER(mdev) \
1260 (MLX5_CAP_GEN(mdev, vport_group_manager) && \
1261 (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \
1262 mlx5_core_is_pf(mdev))
1264 static inline int mlx5_get_gid_table_len(u16 param)
1267 pr_warn("gid table length is zero\n");
1271 return 8 * (1 << param);
1274 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1276 return !!(dev->priv.rl_table.max_size);
1279 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1281 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1282 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1285 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1287 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1290 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1292 return mlx5_core_is_mp_slave(dev) ||
1293 mlx5_core_is_mp_master(dev);
1296 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1298 if (!mlx5_core_mp_enabled(dev))
1301 return MLX5_CAP_GEN(dev, native_port_num);
1305 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1308 static inline const struct cpumask *
1309 mlx5_get_vector_affinity_hint(struct mlx5_core_dev *dev, int vector)
1311 return dev->priv.irq_info[vector].mask;
1314 #endif /* MLX5_DRIVER_H */