2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock_types.h>
40 #include <linux/semaphore.h>
41 #include <linux/slab.h>
42 #include <linux/vmalloc.h>
43 #include <linux/radix-tree.h>
45 #include <linux/mlx5/device.h>
46 #include <linux/mlx5/doorbell.h>
49 MLX5_BOARD_ID_LEN = 64,
50 MLX5_MAX_NAME_LEN = 16,
54 /* one minute for the sake of bringup. Generally, commands must always
55 * complete and we may need to increase this timeout value
57 MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000,
58 MLX5_CMD_WQ_MAX_NAME = 32,
64 CMD_STATUS_SUCCESS = 0,
70 MLX5_SQP_IEEE_1588 = 2,
72 MLX5_SQP_SYNC_UMR = 4,
80 MLX5_EQ_VEC_PAGES = 0,
82 MLX5_EQ_VEC_ASYNC = 2,
83 MLX5_EQ_VEC_COMP_BASE,
87 MLX5_MAX_IRQ_NAME = 32
91 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
92 MLX5_ATOMIC_MODE_CX = 2 << 16,
93 MLX5_ATOMIC_MODE_8B = 3 << 16,
94 MLX5_ATOMIC_MODE_16B = 4 << 16,
95 MLX5_ATOMIC_MODE_32B = 5 << 16,
96 MLX5_ATOMIC_MODE_64B = 6 << 16,
97 MLX5_ATOMIC_MODE_128B = 7 << 16,
98 MLX5_ATOMIC_MODE_256B = 8 << 16,
102 MLX5_REG_PCAP = 0x5001,
103 MLX5_REG_PMTU = 0x5003,
104 MLX5_REG_PTYS = 0x5004,
105 MLX5_REG_PAOS = 0x5006,
106 MLX5_REG_PMAOS = 0x5012,
107 MLX5_REG_PUDE = 0x5009,
108 MLX5_REG_PMPE = 0x5010,
109 MLX5_REG_PELC = 0x500e,
110 MLX5_REG_PMLP = 0, /* TBD */
111 MLX5_REG_NODE_DESC = 0x6001,
112 MLX5_REG_HOST_ENDIANNESS = 0x7004,
115 enum mlx5_page_fault_resume_flags {
116 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
117 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
118 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
119 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
128 struct mlx5_field_desc {
133 struct mlx5_rsc_debug {
134 struct mlx5_core_dev *dev;
136 enum dbg_rsc_type type;
138 struct mlx5_field_desc fields[0];
141 enum mlx5_dev_event {
142 MLX5_DEV_EVENT_SYS_ERROR,
143 MLX5_DEV_EVENT_PORT_UP,
144 MLX5_DEV_EVENT_PORT_DOWN,
145 MLX5_DEV_EVENT_PORT_INITIALIZED,
146 MLX5_DEV_EVENT_LID_CHANGE,
147 MLX5_DEV_EVENT_PKEY_CHANGE,
148 MLX5_DEV_EVENT_GUID_CHANGE,
149 MLX5_DEV_EVENT_CLIENT_REREG,
152 struct mlx5_uuar_info {
153 struct mlx5_uar *uars;
155 int num_low_latency_uuars;
156 unsigned long *bitmap;
161 * protect uuar allocation data structs
169 void __iomem *regreg;
171 struct mlx5_uar *uar;
172 unsigned long offset;
174 /* protect blue flame buffer selection when needed
178 /* serialize 64 bit writes when done as two 32 bit accesses
184 struct mlx5_cmd_first {
188 struct mlx5_cmd_msg {
189 struct list_head list;
190 struct cache_ent *cache;
192 struct mlx5_cmd_first first;
193 struct mlx5_cmd_mailbox *next;
196 struct mlx5_cmd_debug {
197 struct dentry *dbg_root;
198 struct dentry *dbg_in;
199 struct dentry *dbg_out;
200 struct dentry *dbg_outlen;
201 struct dentry *dbg_status;
202 struct dentry *dbg_run;
211 /* protect block chain allocations
214 struct list_head head;
217 struct cmd_msg_cache {
218 struct cache_ent large;
219 struct cache_ent med;
223 struct mlx5_cmd_stats {
228 struct dentry *count;
229 /* protect command average calculations */
235 dma_addr_t alloc_dma;
246 /* protect command queue allocations
248 spinlock_t alloc_lock;
250 /* protect token allocations
252 spinlock_t token_lock;
254 unsigned long bitmask;
255 char wq_name[MLX5_CMD_WQ_MAX_NAME];
256 struct workqueue_struct *wq;
257 struct semaphore sem;
258 struct semaphore pages_sem;
260 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
261 struct pci_pool *pool;
262 struct mlx5_cmd_debug dbg;
263 struct cmd_msg_cache cache;
264 int checksum_disabled;
265 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
268 struct mlx5_port_caps {
274 struct mlx5_cmd_mailbox {
277 struct mlx5_cmd_mailbox *next;
280 struct mlx5_buf_list {
286 struct mlx5_buf_list direct;
293 struct mlx5_core_dev *dev;
294 __be32 __iomem *doorbell;
302 struct list_head list;
304 struct mlx5_rsc_debug *dbg;
307 struct mlx5_core_psv {
319 struct mlx5_core_sig_ctx {
320 struct mlx5_core_psv psv_memory;
321 struct mlx5_core_psv psv_wire;
322 struct ib_sig_err err_item;
323 bool sig_status_checked;
328 struct mlx5_core_mr {
339 struct mlx5_core_rsc_common {
340 enum mlx5_res_type res;
342 struct completion free;
345 struct mlx5_core_srq {
349 int max_avail_gather;
351 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
354 struct completion free;
357 struct mlx5_eq_table {
358 void __iomem *update_ci;
359 void __iomem *update_arm_ci;
360 struct list_head comp_eqs_list;
361 struct mlx5_eq pages_eq;
362 struct mlx5_eq async_eq;
363 struct mlx5_eq cmd_eq;
364 int num_comp_vectors;
372 struct list_head bf_list;
373 unsigned free_bf_bmap;
374 void __iomem *wc_map;
379 struct mlx5_core_health {
380 struct health_buffer __iomem *health;
381 __be32 __iomem *health_counter;
382 struct timer_list timer;
383 struct list_head list;
388 struct mlx5_cq_table {
389 /* protect radix tree
392 struct radix_tree_root tree;
395 struct mlx5_qp_table {
396 /* protect radix tree
399 struct radix_tree_root tree;
402 struct mlx5_srq_table {
403 /* protect radix tree
406 struct radix_tree_root tree;
409 struct mlx5_mr_table {
410 /* protect radix tree
413 struct radix_tree_root tree;
416 struct mlx5_irq_info {
418 char name[MLX5_MAX_IRQ_NAME];
422 char name[MLX5_MAX_NAME_LEN];
423 struct mlx5_eq_table eq_table;
424 struct msix_entry *msix_arr;
425 struct mlx5_irq_info *irq_info;
426 struct mlx5_uuar_info uuari;
427 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
430 struct workqueue_struct *pg_wq;
431 struct rb_root page_root;
434 struct list_head free_list;
436 struct mlx5_core_health health;
438 struct mlx5_srq_table srq_table;
440 /* start: qp staff */
441 struct mlx5_qp_table qp_table;
442 struct dentry *qp_debugfs;
443 struct dentry *eq_debugfs;
444 struct dentry *cq_debugfs;
445 struct dentry *cmdif_debugfs;
448 /* start: cq staff */
449 struct mlx5_cq_table cq_table;
452 /* start: mr staff */
453 struct mlx5_mr_table mr_table;
456 /* start: alloc staff */
457 struct mutex pgdir_mutex;
458 struct list_head pgdir_list;
459 /* end: alloc staff */
460 struct dentry *dbg_root;
462 /* protect mkey key part */
463 spinlock_t mkey_lock;
466 struct list_head dev_list;
467 struct list_head ctx_list;
471 struct mlx5_core_dev {
472 struct pci_dev *pdev;
474 char board_id[MLX5_BOARD_ID_LEN];
476 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
477 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
478 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
479 phys_addr_t iseg_base;
480 struct mlx5_init_seg __iomem *iseg;
481 void (*event) (struct mlx5_core_dev *dev,
482 enum mlx5_dev_event event,
483 unsigned long param);
484 struct mlx5_priv priv;
485 struct mlx5_profile *profile;
492 struct mlx5_db_pgdir *pgdir;
493 struct mlx5_ib_user_db_page *user_page;
500 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
504 MLX5_COMP_EQ_SIZE = 1024,
508 MLX5_PTYS_IB = 1 << 0,
509 MLX5_PTYS_EN = 1 << 2,
512 struct mlx5_db_pgdir {
513 struct list_head list;
514 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
519 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
521 struct mlx5_cmd_work_ent {
522 struct mlx5_cmd_msg *in;
523 struct mlx5_cmd_msg *out;
526 mlx5_cmd_cbk_t callback;
529 struct completion done;
530 struct mlx5_cmd *cmd;
531 struct work_struct work;
532 struct mlx5_cmd_layout *lay;
547 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
549 return buf->direct.buf + offset;
552 extern struct workqueue_struct *mlx5_core_wq;
554 #define STRUCT_FIELD(header, field) \
555 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
556 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
559 size_t struct_offset_bytes;
560 size_t struct_size_bytes;
565 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
567 return pci_get_drvdata(pdev);
570 extern struct dentry *mlx5_debugfs_root;
572 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
574 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
577 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
579 return ioread32be(&dev->iseg->fw_rev) >> 16;
582 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
584 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
587 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
589 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
592 static inline void *mlx5_vzalloc(unsigned long size)
596 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
602 static inline u32 mlx5_base_mkey(const u32 key)
604 return key & 0xffffff00u;
607 int mlx5_cmd_init(struct mlx5_core_dev *dev);
608 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
609 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
610 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
611 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
612 int mlx5_cmd_status_to_err_v2(void *ptr);
613 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
614 enum mlx5_cap_mode cap_mode);
615 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
617 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
618 void *out, int out_size, mlx5_cmd_cbk_t callback,
620 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
621 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
622 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
623 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
624 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
625 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
626 void mlx5_health_cleanup(void);
627 void __init mlx5_health_init(void);
628 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
629 void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
630 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
631 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
632 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
633 gfp_t flags, int npages);
634 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
635 struct mlx5_cmd_mailbox *head);
636 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
637 struct mlx5_create_srq_mbox_in *in, int inlen);
638 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
639 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
640 struct mlx5_query_srq_mbox_out *out);
641 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
642 u16 lwm, int is_srq);
643 void mlx5_init_mr_table(struct mlx5_core_dev *dev);
644 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
645 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
646 struct mlx5_create_mkey_mbox_in *in, int inlen,
647 mlx5_cmd_cbk_t callback, void *context,
648 struct mlx5_create_mkey_mbox_out *out);
649 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr);
650 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
651 struct mlx5_query_mkey_mbox_out *out, int outlen);
652 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
654 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
655 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
656 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, void *inb, void *outb,
658 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
659 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
660 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
661 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
662 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
664 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
665 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
666 void mlx5_register_debugfs(void);
667 void mlx5_unregister_debugfs(void);
668 int mlx5_eq_init(struct mlx5_core_dev *dev);
669 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
670 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
671 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
672 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
673 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
674 void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
676 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
677 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
678 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector);
679 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
680 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
681 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
682 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
683 int mlx5_start_eqs(struct mlx5_core_dev *dev);
684 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
685 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
686 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
687 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
689 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
690 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
691 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
692 int size_in, void *data_out, int size_out,
693 u16 reg_num, int arg, int write);
695 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
696 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
697 int ptys_size, int proto_mask);
698 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
699 u32 *proto_cap, int proto_mask);
700 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
701 u32 *proto_admin, int proto_mask);
702 int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
705 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
706 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
707 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
708 struct mlx5_query_eq_mbox_out *out, int outlen);
709 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
710 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
711 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
712 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
713 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
714 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
716 const char *mlx5_command_str(int command);
717 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
718 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
719 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
720 int npsvs, u32 *sig_index);
721 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
722 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
723 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
724 struct mlx5_odp_caps *odp_caps);
726 static inline u32 mlx5_mkey_to_idx(u32 mkey)
731 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
733 return mkey_idx << 8;
736 static inline u8 mlx5_mkey_variant(u32 mkey)
742 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
743 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
747 MAX_MR_CACHE_ENTRIES = 16,
751 MLX5_INTERFACE_PROTOCOL_IB = 0,
752 MLX5_INTERFACE_PROTOCOL_ETH = 1,
755 struct mlx5_interface {
756 void * (*add)(struct mlx5_core_dev *dev);
757 void (*remove)(struct mlx5_core_dev *dev, void *context);
758 void (*event)(struct mlx5_core_dev *dev, void *context,
759 enum mlx5_dev_event event, unsigned long param);
760 void * (*get_dev)(void *context);
762 struct list_head list;
765 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
766 int mlx5_register_interface(struct mlx5_interface *intf);
767 void mlx5_unregister_interface(struct mlx5_interface *intf);
769 struct mlx5_profile {
775 } mr_cache[MAX_MR_CACHE_ENTRIES];
778 #endif /* MLX5_DRIVER_H */