2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
52 #include <linux/mlx5/device.h>
53 #include <linux/mlx5/doorbell.h>
54 #include <linux/mlx5/eq.h>
55 #include <linux/timecounter.h>
56 #include <linux/ptp_clock_kernel.h>
57 #include <net/devlink.h>
60 MLX5_BOARD_ID_LEN = 64,
64 /* one minute for the sake of bringup. Generally, commands must always
65 * complete and we may need to increase this timeout value
67 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
68 MLX5_CMD_WQ_MAX_NAME = 32,
74 CMD_STATUS_SUCCESS = 0,
80 MLX5_SQP_IEEE_1588 = 2,
82 MLX5_SQP_SYNC_UMR = 4,
90 MLX5_ATOMIC_MODE_OFFSET = 16,
91 MLX5_ATOMIC_MODE_IB_COMP = 1,
92 MLX5_ATOMIC_MODE_CX = 2,
93 MLX5_ATOMIC_MODE_8B = 3,
94 MLX5_ATOMIC_MODE_16B = 4,
95 MLX5_ATOMIC_MODE_32B = 5,
96 MLX5_ATOMIC_MODE_64B = 6,
97 MLX5_ATOMIC_MODE_128B = 7,
98 MLX5_ATOMIC_MODE_256B = 8,
102 MLX5_REG_QPTS = 0x4002,
103 MLX5_REG_QETCR = 0x4005,
104 MLX5_REG_QTCT = 0x400a,
105 MLX5_REG_QPDPM = 0x4013,
106 MLX5_REG_QCAM = 0x4019,
107 MLX5_REG_DCBX_PARAM = 0x4020,
108 MLX5_REG_DCBX_APP = 0x4021,
109 MLX5_REG_FPGA_CAP = 0x4022,
110 MLX5_REG_FPGA_CTRL = 0x4023,
111 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
112 MLX5_REG_CORE_DUMP = 0x402e,
113 MLX5_REG_PCAP = 0x5001,
114 MLX5_REG_PMTU = 0x5003,
115 MLX5_REG_PTYS = 0x5004,
116 MLX5_REG_PAOS = 0x5006,
117 MLX5_REG_PFCC = 0x5007,
118 MLX5_REG_PPCNT = 0x5008,
119 MLX5_REG_PPTB = 0x500b,
120 MLX5_REG_PBMC = 0x500c,
121 MLX5_REG_PMAOS = 0x5012,
122 MLX5_REG_PUDE = 0x5009,
123 MLX5_REG_PMPE = 0x5010,
124 MLX5_REG_PELC = 0x500e,
125 MLX5_REG_PVLC = 0x500f,
126 MLX5_REG_PCMR = 0x5041,
127 MLX5_REG_PMLP = 0x5002,
128 MLX5_REG_PPLM = 0x5023,
129 MLX5_REG_PCAM = 0x507f,
130 MLX5_REG_NODE_DESC = 0x6001,
131 MLX5_REG_HOST_ENDIANNESS = 0x7004,
132 MLX5_REG_MCIA = 0x9014,
133 MLX5_REG_MLCR = 0x902b,
134 MLX5_REG_MTRC_CAP = 0x9040,
135 MLX5_REG_MTRC_CONF = 0x9041,
136 MLX5_REG_MTRC_STDB = 0x9042,
137 MLX5_REG_MTRC_CTRL = 0x9043,
138 MLX5_REG_MPEIN = 0x9050,
139 MLX5_REG_MPCNT = 0x9051,
140 MLX5_REG_MTPPS = 0x9053,
141 MLX5_REG_MTPPSE = 0x9054,
142 MLX5_REG_MPEGC = 0x9056,
143 MLX5_REG_MCQS = 0x9060,
144 MLX5_REG_MCQI = 0x9061,
145 MLX5_REG_MCC = 0x9062,
146 MLX5_REG_MCDA = 0x9063,
147 MLX5_REG_MCAM = 0x907f,
150 enum mlx5_qpts_trust_state {
151 MLX5_QPTS_TRUST_PCP = 1,
152 MLX5_QPTS_TRUST_DSCP = 2,
155 enum mlx5_dcbx_oper_mode {
156 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
157 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
161 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
162 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
163 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
164 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
167 enum mlx5_page_fault_resume_flags {
168 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
169 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
170 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
171 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
180 enum port_state_policy {
181 MLX5_POLICY_DOWN = 0,
183 MLX5_POLICY_FOLLOW = 2,
184 MLX5_POLICY_INVALID = 0xffffffff
187 enum mlx5_coredev_type {
192 struct mlx5_field_desc {
196 struct mlx5_rsc_debug {
197 struct mlx5_core_dev *dev;
199 enum dbg_rsc_type type;
201 struct mlx5_field_desc fields[0];
204 enum mlx5_dev_event {
205 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
206 MLX5_DEV_EVENT_PORT_AFFINITY = 129,
209 enum mlx5_port_status {
214 struct mlx5_bfreg_info {
216 int num_low_latency_bfregs;
220 * protect bfreg allocation data structs
226 u32 num_static_sys_pages;
227 u32 total_num_bfregs;
231 struct mlx5_cmd_first {
235 struct mlx5_cmd_msg {
236 struct list_head list;
237 struct cmd_msg_cache *parent;
239 struct mlx5_cmd_first first;
240 struct mlx5_cmd_mailbox *next;
243 struct mlx5_cmd_debug {
244 struct dentry *dbg_root;
252 struct cmd_msg_cache {
253 /* protect block chain allocations
256 struct list_head head;
257 unsigned int max_inbox_size;
258 unsigned int num_ent;
262 MLX5_NUM_COMMAND_CACHES = 5,
265 struct mlx5_cmd_stats {
269 /* protect command average calculations */
277 dma_addr_t alloc_dma;
288 /* protect command queue allocations
290 spinlock_t alloc_lock;
292 /* protect token allocations
294 spinlock_t token_lock;
296 unsigned long bitmask;
297 char wq_name[MLX5_CMD_WQ_MAX_NAME];
298 struct workqueue_struct *wq;
299 struct semaphore sem;
300 struct semaphore pages_sem;
302 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
303 struct dma_pool *pool;
304 struct mlx5_cmd_debug dbg;
305 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
306 int checksum_disabled;
307 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
310 struct mlx5_port_caps {
317 struct mlx5_cmd_mailbox {
320 struct mlx5_cmd_mailbox *next;
323 struct mlx5_buf_list {
328 struct mlx5_frag_buf {
329 struct mlx5_buf_list *frags;
335 struct mlx5_frag_buf_ctrl {
336 struct mlx5_buf_list *frags;
345 struct mlx5_core_psv {
357 struct mlx5_core_sig_ctx {
358 struct mlx5_core_psv psv_memory;
359 struct mlx5_core_psv psv_wire;
360 struct ib_sig_err err_item;
361 bool sig_status_checked;
369 MLX5_MKEY_INDIRECT_DEVX,
372 struct mlx5_core_mkey {
380 #define MLX5_24BIT_MASK ((1 << 24) - 1)
383 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
384 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
385 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
389 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT,
392 struct mlx5_core_rsc_common {
393 enum mlx5_res_type res;
395 struct completion free;
398 struct mlx5_uars_page {
402 struct list_head list;
404 unsigned long *reg_bitmap; /* for non fast path bf regs */
405 unsigned long *fp_bitmap;
406 unsigned int reg_avail;
407 unsigned int fp_avail;
408 struct kref ref_count;
409 struct mlx5_core_dev *mdev;
412 struct mlx5_bfreg_head {
413 /* protect blue flame registers allocations */
415 struct list_head list;
418 struct mlx5_bfreg_data {
419 struct mlx5_bfreg_head reg_head;
420 struct mlx5_bfreg_head wc_head;
423 struct mlx5_sq_bfreg {
425 struct mlx5_uars_page *up;
431 struct mlx5_core_health {
432 struct health_buffer __iomem *health;
433 __be32 __iomem *health_counter;
434 struct timer_list timer;
440 /* wq spinlock to synchronize draining */
442 struct workqueue_struct *wq;
444 struct work_struct fatal_report_work;
445 struct work_struct report_work;
446 struct delayed_work recover_work;
447 struct devlink_health_reporter *fw_reporter;
448 struct devlink_health_reporter *fw_fatal_reporter;
451 struct mlx5_qp_table {
452 struct notifier_block nb;
454 /* protect radix tree
457 struct radix_tree_root tree;
460 struct mlx5_vf_context {
464 enum port_state_policy policy;
467 struct mlx5_core_sriov {
468 struct mlx5_vf_context *vfs_ctx;
473 struct mlx5_fc_pool {
474 struct mlx5_core_dev *dev;
475 struct mutex pool_lock; /* protects pool lists */
476 struct list_head fully_used;
477 struct list_head partially_used;
478 struct list_head unused;
484 struct mlx5_fc_stats {
485 spinlock_t counters_idr_lock; /* protects counters_idr */
486 struct idr counters_idr;
487 struct list_head counters;
488 struct llist_head addlist;
489 struct llist_head dellist;
491 struct workqueue_struct *wq;
492 struct delayed_work work;
493 unsigned long next_query;
494 unsigned long sampling_interval; /* jiffies */
496 struct mlx5_fc_pool fc_pool;
504 struct mlx5_eq_table;
505 struct mlx5_irq_table;
507 struct mlx5_rate_limit {
513 struct mlx5_rl_entry {
514 struct mlx5_rate_limit rl;
519 struct mlx5_rl_table {
520 /* protect rate limit table */
521 struct mutex rl_lock;
525 struct mlx5_rl_entry *rl_entry;
528 struct mlx5_core_roce {
529 struct mlx5_flow_table *ft;
530 struct mlx5_flow_group *fg;
531 struct mlx5_flow_handle *allow_rule;
535 /* IRQ table valid only for real pci devices PF or VF */
536 struct mlx5_irq_table *irq_table;
537 struct mlx5_eq_table *eq_table;
540 struct mlx5_nb pg_nb;
541 struct workqueue_struct *pg_wq;
542 struct rb_root page_root;
545 struct list_head free_list;
549 struct mlx5_core_health health;
551 /* start: qp staff */
552 struct mlx5_qp_table qp_table;
553 struct dentry *qp_debugfs;
554 struct dentry *eq_debugfs;
555 struct dentry *cq_debugfs;
556 struct dentry *cmdif_debugfs;
559 /* start: alloc staff */
560 /* protect buffer alocation according to numa node */
561 struct mutex alloc_mutex;
564 struct mutex pgdir_mutex;
565 struct list_head pgdir_list;
566 /* end: alloc staff */
567 struct dentry *dbg_root;
569 /* protect mkey key part */
570 spinlock_t mkey_lock;
573 struct list_head dev_list;
574 struct list_head ctx_list;
576 struct mlx5_events *events;
578 struct mlx5_flow_steering *steering;
579 struct mlx5_mpfs *mpfs;
580 struct mlx5_eswitch *eswitch;
581 struct mlx5_core_sriov sriov;
582 struct mlx5_lag *lag;
583 struct mlx5_devcom *devcom;
584 struct mlx5_core_roce roce;
585 struct mlx5_fc_stats fc_stats;
586 struct mlx5_rl_table rl_table;
588 struct mlx5_bfreg_data bfregs;
589 struct mlx5_uars_page *uar;
592 enum mlx5_device_state {
593 MLX5_DEVICE_STATE_UNINITIALIZED,
594 MLX5_DEVICE_STATE_UP,
595 MLX5_DEVICE_STATE_INTERNAL_ERROR,
598 enum mlx5_interface_state {
599 MLX5_INTERFACE_STATE_UP = BIT(0),
602 enum mlx5_pci_status {
603 MLX5_PCI_STATUS_DISABLED,
604 MLX5_PCI_STATUS_ENABLED,
607 enum mlx5_pagefault_type_flags {
608 MLX5_PFAULT_REQUESTOR = 1 << 0,
609 MLX5_PFAULT_WRITE = 1 << 1,
610 MLX5_PFAULT_RDMA = 1 << 2,
614 /* protects tirs list changes while tirs refresh */
615 struct mutex list_lock;
616 struct list_head tirs_list;
620 struct mlx5e_resources {
623 struct mlx5_core_mkey mkey;
624 struct mlx5_sq_bfreg bfreg;
627 enum mlx5_sw_icm_type {
628 MLX5_SW_ICM_TYPE_STEERING,
629 MLX5_SW_ICM_TYPE_HEADER_MODIFY,
632 #define MLX5_MAX_RESERVED_GIDS 8
634 struct mlx5_rsvd_gids {
640 #define MAX_PIN_NUM 8
642 u8 pin_caps[MAX_PIN_NUM];
643 struct work_struct out_work;
644 u64 start[MAX_PIN_NUM];
649 struct mlx5_core_dev *mdev;
650 struct mlx5_nb pps_nb;
652 struct cyclecounter cycles;
653 struct timecounter tc;
654 struct hwtstamp_config hwtstamp_config;
656 unsigned long overflow_period;
657 struct delayed_work overflow_work;
658 struct ptp_clock *ptp;
659 struct ptp_clock_info ptp_info;
660 struct mlx5_pps pps_info;
664 struct mlx5_fw_tracer;
669 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
670 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
672 struct mlx5_core_dev {
673 struct device *device;
674 enum mlx5_coredev_type coredev_type;
675 struct pci_dev *pdev;
677 struct mutex pci_status_mutex;
678 enum mlx5_pci_status pci_status;
680 char board_id[MLX5_BOARD_ID_LEN];
682 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
684 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
685 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
686 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
687 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
688 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
689 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
693 phys_addr_t iseg_base;
694 struct mlx5_init_seg __iomem *iseg;
695 phys_addr_t bar_addr;
696 enum mlx5_device_state state;
697 /* sync interface state */
698 struct mutex intf_state_mutex;
699 unsigned long intf_state;
700 struct mlx5_priv priv;
701 struct mlx5_profile *profile;
704 struct mlx5e_resources mlx5e_res;
706 struct mlx5_vxlan *vxlan;
707 struct mlx5_geneve *geneve;
709 struct mlx5_rsvd_gids reserved_gids;
712 #ifdef CONFIG_MLX5_FPGA
713 struct mlx5_fpga_device *fpga;
715 struct mlx5_clock clock;
716 struct mlx5_ib_clock_info *clock_info;
717 struct mlx5_fw_tracer *tracer;
719 struct mlx5_hv_vhca *hv_vhca;
725 struct mlx5_db_pgdir *pgdir;
726 struct mlx5_ib_user_db_page *user_page;
733 MLX5_COMP_EQ_SIZE = 1024,
737 MLX5_PTYS_IB = 1 << 0,
738 MLX5_PTYS_EN = 1 << 2,
741 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
744 MLX5_CMD_ENT_STATE_PENDING_COMP,
747 struct mlx5_cmd_work_ent {
749 struct mlx5_cmd_msg *in;
750 struct mlx5_cmd_msg *out;
753 mlx5_cmd_cbk_t callback;
754 struct delayed_work cb_timeout_work;
757 struct completion done;
758 struct mlx5_cmd *cmd;
759 struct work_struct work;
760 struct mlx5_cmd_layout *lay;
776 enum phy_port_state {
780 struct mlx5_hca_vport_context {
785 enum port_state_policy policy;
786 enum phy_port_state phys_state;
787 enum ib_port_state vport_state;
788 u8 port_physical_state;
797 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
802 u16 qkey_violation_counter;
803 u16 pkey_violation_counter;
807 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset)
809 return buf->frags->buf + offset;
812 #define STRUCT_FIELD(header, field) \
813 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
814 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
816 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
818 return pci_get_drvdata(pdev);
821 extern struct dentry *mlx5_debugfs_root;
823 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
825 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
828 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
830 return ioread32be(&dev->iseg->fw_rev) >> 16;
833 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
835 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
838 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
840 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
843 static inline u32 mlx5_base_mkey(const u32 key)
845 return key & 0xffffff00u;
848 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
849 u8 log_stride, u8 log_sz,
851 struct mlx5_frag_buf_ctrl *fbc)
854 fbc->log_stride = log_stride;
855 fbc->log_sz = log_sz;
856 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
857 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
858 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
859 fbc->strides_offset = strides_offset;
862 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
863 u8 log_stride, u8 log_sz,
864 struct mlx5_frag_buf_ctrl *fbc)
866 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
869 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
874 ix += fbc->strides_offset;
875 frag = ix >> fbc->log_frag_strides;
877 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
881 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
883 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
885 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
888 int mlx5_cmd_init(struct mlx5_core_dev *dev);
889 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
890 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
891 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
893 struct mlx5_async_ctx {
894 struct mlx5_core_dev *dev;
895 atomic_t num_inflight;
896 struct wait_queue_head wait;
899 struct mlx5_async_work;
901 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
903 struct mlx5_async_work {
904 struct mlx5_async_ctx *ctx;
905 mlx5_async_cbk_t user_callback;
908 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
909 struct mlx5_async_ctx *ctx);
910 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
911 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
912 void *out, int out_size, mlx5_async_cbk_t callback,
913 struct mlx5_async_work *work);
915 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
917 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
918 void *out, int out_size);
919 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
921 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
922 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
923 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
924 void mlx5_health_flush(struct mlx5_core_dev *dev);
925 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
926 int mlx5_health_init(struct mlx5_core_dev *dev);
927 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
928 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
929 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
930 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
931 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
932 struct mlx5_frag_buf *buf, int node);
933 int mlx5_buf_alloc(struct mlx5_core_dev *dev,
934 int size, struct mlx5_frag_buf *buf);
935 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
936 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
937 struct mlx5_frag_buf *buf, int node);
938 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
939 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
940 gfp_t flags, int npages);
941 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
942 struct mlx5_cmd_mailbox *head);
943 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
944 struct mlx5_core_mkey *mkey,
945 struct mlx5_async_ctx *async_ctx, u32 *in,
946 int inlen, u32 *out, int outlen,
947 mlx5_async_cbk_t callback,
948 struct mlx5_async_work *context);
949 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
950 struct mlx5_core_mkey *mkey,
952 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
953 struct mlx5_core_mkey *mkey);
954 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
955 u32 *out, int outlen);
956 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
957 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
958 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
959 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
960 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
961 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
962 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
963 s32 npages, bool ec_function);
964 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
965 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
966 void mlx5_register_debugfs(void);
967 void mlx5_unregister_debugfs(void);
969 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas);
970 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
971 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
973 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
974 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
976 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
977 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
978 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
979 int size_in, void *data_out, int size_out,
980 u16 reg_num, int arg, int write);
982 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
983 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
985 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
987 const char *mlx5_command_str(int command);
988 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
989 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
990 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
991 int npsvs, u32 *sig_index);
992 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
993 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
994 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
995 struct mlx5_odp_caps *odp_caps);
996 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
997 u8 port_num, void *out, size_t sz);
999 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1000 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1001 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1002 struct mlx5_rate_limit *rl);
1003 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1004 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1005 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1006 struct mlx5_rate_limit *rl_1);
1007 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1008 bool map_wc, bool fast_path);
1009 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1011 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev);
1013 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector);
1014 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1015 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1016 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1017 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1019 static inline int fw_initializing(struct mlx5_core_dev *dev)
1021 return ioread32be(&dev->iseg->initializing) >> 31;
1024 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1029 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1031 return mkey_idx << 8;
1034 static inline u8 mlx5_mkey_variant(u32 mkey)
1040 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
1041 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
1045 MR_CACHE_LAST_STD_ENTRY = 20,
1046 MLX5_IMR_MTT_CACHE_ENTRY,
1047 MLX5_IMR_KSM_CACHE_ENTRY,
1048 MAX_MR_CACHE_ENTRIES
1052 MLX5_INTERFACE_PROTOCOL_IB = 0,
1053 MLX5_INTERFACE_PROTOCOL_ETH = 1,
1056 struct mlx5_interface {
1057 void * (*add)(struct mlx5_core_dev *dev);
1058 void (*remove)(struct mlx5_core_dev *dev, void *context);
1059 int (*attach)(struct mlx5_core_dev *dev, void *context);
1060 void (*detach)(struct mlx5_core_dev *dev, void *context);
1062 struct list_head list;
1065 int mlx5_register_interface(struct mlx5_interface *intf);
1066 void mlx5_unregister_interface(struct mlx5_interface *intf);
1067 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1068 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1069 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1070 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1072 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1074 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1075 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1076 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1077 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1078 bool mlx5_lag_is_multipath(struct mlx5_core_dev *dev);
1079 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1080 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1081 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1085 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1086 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1087 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1088 u64 length, u16 uid, phys_addr_t *addr, u32 *obj_id);
1089 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1090 u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1092 #ifdef CONFIG_MLX5_CORE_IPOIB
1093 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1094 struct ib_device *ibdev,
1096 void (*setup)(struct net_device *));
1097 #endif /* CONFIG_MLX5_CORE_IPOIB */
1098 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1099 struct ib_device *device,
1100 struct rdma_netdev_alloc_params *params);
1102 struct mlx5_profile {
1108 } mr_cache[MAX_MR_CACHE_ENTRIES];
1112 MLX5_PCI_DEV_IS_VF = 1 << 0,
1115 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1117 return dev->coredev_type == MLX5_COREDEV_PF;
1120 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1122 return dev->coredev_type == MLX5_COREDEV_VF;
1125 static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev)
1127 return dev->caps.embedded_cpu;
1131 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1133 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1136 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1138 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1141 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1143 return dev->priv.sriov.max_vfs;
1146 static inline int mlx5_get_gid_table_len(u16 param)
1149 pr_warn("gid table length is zero\n");
1153 return 8 * (1 << param);
1156 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1158 return !!(dev->priv.rl_table.max_size);
1161 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1163 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1164 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1167 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1169 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1172 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1174 return mlx5_core_is_mp_slave(dev) ||
1175 mlx5_core_is_mp_master(dev);
1178 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1180 if (!mlx5_core_mp_enabled(dev))
1183 return MLX5_CAP_GEN(dev, native_port_num);
1187 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1190 static inline bool mlx5_is_roce_enabled(struct mlx5_core_dev *dev)
1192 struct devlink *devlink = priv_to_devlink(dev);
1193 union devlink_param_value val;
1195 devlink_param_driverinit_value_get(devlink,
1196 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
1201 #endif /* MLX5_DRIVER_H */