2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock_types.h>
40 #include <linux/semaphore.h>
41 #include <linux/slab.h>
42 #include <linux/vmalloc.h>
43 #include <linux/radix-tree.h>
44 #include <linux/workqueue.h>
45 #include <linux/interrupt.h>
47 #include <linux/mlx5/device.h>
48 #include <linux/mlx5/doorbell.h>
49 #include <linux/mlx5/srq.h>
52 MLX5_RQ_BITMASK_VSD = 1 << 1,
56 MLX5_BOARD_ID_LEN = 64,
57 MLX5_MAX_NAME_LEN = 16,
61 /* one minute for the sake of bringup. Generally, commands must always
62 * complete and we may need to increase this timeout value
64 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
65 MLX5_CMD_WQ_MAX_NAME = 32,
71 CMD_STATUS_SUCCESS = 0,
77 MLX5_SQP_IEEE_1588 = 2,
79 MLX5_SQP_SYNC_UMR = 4,
87 MLX5_EQ_VEC_PAGES = 0,
89 MLX5_EQ_VEC_ASYNC = 2,
90 MLX5_EQ_VEC_COMP_BASE,
94 MLX5_MAX_IRQ_NAME = 32
98 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
99 MLX5_ATOMIC_MODE_CX = 2 << 16,
100 MLX5_ATOMIC_MODE_8B = 3 << 16,
101 MLX5_ATOMIC_MODE_16B = 4 << 16,
102 MLX5_ATOMIC_MODE_32B = 5 << 16,
103 MLX5_ATOMIC_MODE_64B = 6 << 16,
104 MLX5_ATOMIC_MODE_128B = 7 << 16,
105 MLX5_ATOMIC_MODE_256B = 8 << 16,
109 MLX5_REG_QETCR = 0x4005,
110 MLX5_REG_QTCT = 0x400a,
111 MLX5_REG_PCAP = 0x5001,
112 MLX5_REG_PMTU = 0x5003,
113 MLX5_REG_PTYS = 0x5004,
114 MLX5_REG_PAOS = 0x5006,
115 MLX5_REG_PFCC = 0x5007,
116 MLX5_REG_PPCNT = 0x5008,
117 MLX5_REG_PMAOS = 0x5012,
118 MLX5_REG_PUDE = 0x5009,
119 MLX5_REG_PMPE = 0x5010,
120 MLX5_REG_PELC = 0x500e,
121 MLX5_REG_PVLC = 0x500f,
122 MLX5_REG_PCMR = 0x5041,
123 MLX5_REG_PMLP = 0x5002,
124 MLX5_REG_NODE_DESC = 0x6001,
125 MLX5_REG_HOST_ENDIANNESS = 0x7004,
126 MLX5_REG_MCIA = 0x9014,
127 MLX5_REG_MLCR = 0x902b,
131 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
132 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
135 enum mlx5_page_fault_resume_flags {
136 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
137 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
138 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
139 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
148 struct mlx5_field_desc {
153 struct mlx5_rsc_debug {
154 struct mlx5_core_dev *dev;
156 enum dbg_rsc_type type;
158 struct mlx5_field_desc fields[0];
161 enum mlx5_dev_event {
162 MLX5_DEV_EVENT_SYS_ERROR,
163 MLX5_DEV_EVENT_PORT_UP,
164 MLX5_DEV_EVENT_PORT_DOWN,
165 MLX5_DEV_EVENT_PORT_INITIALIZED,
166 MLX5_DEV_EVENT_LID_CHANGE,
167 MLX5_DEV_EVENT_PKEY_CHANGE,
168 MLX5_DEV_EVENT_GUID_CHANGE,
169 MLX5_DEV_EVENT_CLIENT_REREG,
172 enum mlx5_port_status {
177 struct mlx5_uuar_info {
178 struct mlx5_uar *uars;
180 int num_low_latency_uuars;
181 unsigned long *bitmap;
186 * protect uuar allocation data structs
194 void __iomem *regreg;
196 struct mlx5_uar *uar;
197 unsigned long offset;
199 /* protect blue flame buffer selection when needed
203 /* serialize 64 bit writes when done as two 32 bit accesses
209 struct mlx5_cmd_first {
213 struct mlx5_cmd_msg {
214 struct list_head list;
215 struct cache_ent *cache;
217 struct mlx5_cmd_first first;
218 struct mlx5_cmd_mailbox *next;
221 struct mlx5_cmd_debug {
222 struct dentry *dbg_root;
223 struct dentry *dbg_in;
224 struct dentry *dbg_out;
225 struct dentry *dbg_outlen;
226 struct dentry *dbg_status;
227 struct dentry *dbg_run;
236 /* protect block chain allocations
239 struct list_head head;
242 struct cmd_msg_cache {
243 struct cache_ent large;
244 struct cache_ent med;
248 struct mlx5_cmd_stats {
253 struct dentry *count;
254 /* protect command average calculations */
260 dma_addr_t alloc_dma;
271 /* protect command queue allocations
273 spinlock_t alloc_lock;
275 /* protect token allocations
277 spinlock_t token_lock;
279 unsigned long bitmask;
280 char wq_name[MLX5_CMD_WQ_MAX_NAME];
281 struct workqueue_struct *wq;
282 struct semaphore sem;
283 struct semaphore pages_sem;
285 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
286 struct pci_pool *pool;
287 struct mlx5_cmd_debug dbg;
288 struct cmd_msg_cache cache;
289 int checksum_disabled;
290 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
293 struct mlx5_port_caps {
299 struct mlx5_cmd_mailbox {
302 struct mlx5_cmd_mailbox *next;
305 struct mlx5_buf_list {
311 struct mlx5_buf_list direct;
317 struct mlx5_eq_tasklet {
318 struct list_head list;
319 struct list_head process_list;
320 struct tasklet_struct task;
321 /* lock on completion tasklet list */
326 struct mlx5_core_dev *dev;
327 __be32 __iomem *doorbell;
335 struct list_head list;
337 struct mlx5_rsc_debug *dbg;
338 struct mlx5_eq_tasklet tasklet_ctx;
341 struct mlx5_core_psv {
353 struct mlx5_core_sig_ctx {
354 struct mlx5_core_psv psv_memory;
355 struct mlx5_core_psv psv_wire;
356 struct ib_sig_err err_item;
357 bool sig_status_checked;
362 struct mlx5_core_mkey {
370 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
371 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
372 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
377 struct mlx5_core_rsc_common {
378 enum mlx5_res_type res;
380 struct completion free;
383 struct mlx5_core_srq {
384 struct mlx5_core_rsc_common common; /* must be first */
388 int max_avail_gather;
390 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
393 struct completion free;
396 struct mlx5_eq_table {
397 void __iomem *update_ci;
398 void __iomem *update_arm_ci;
399 struct list_head comp_eqs_list;
400 struct mlx5_eq pages_eq;
401 struct mlx5_eq async_eq;
402 struct mlx5_eq cmd_eq;
403 int num_comp_vectors;
411 struct list_head bf_list;
412 unsigned free_bf_bmap;
413 void __iomem *bf_map;
418 struct mlx5_core_health {
419 struct health_buffer __iomem *health;
420 __be32 __iomem *health_counter;
421 struct timer_list timer;
425 struct workqueue_struct *wq;
426 struct work_struct work;
429 struct mlx5_cq_table {
430 /* protect radix tree
433 struct radix_tree_root tree;
436 struct mlx5_qp_table {
437 /* protect radix tree
440 struct radix_tree_root tree;
443 struct mlx5_srq_table {
444 /* protect radix tree
447 struct radix_tree_root tree;
450 struct mlx5_mkey_table {
451 /* protect radix tree
454 struct radix_tree_root tree;
457 struct mlx5_vf_context {
461 struct mlx5_core_sriov {
462 struct mlx5_vf_context *vfs_ctx;
467 struct mlx5_irq_info {
469 char name[MLX5_MAX_IRQ_NAME];
472 struct mlx5_fc_stats {
473 struct list_head list;
474 struct list_head addlist;
475 /* protect addlist add/splice operations */
476 spinlock_t addlist_lock;
478 struct workqueue_struct *wq;
479 struct delayed_work work;
480 unsigned long next_query;
486 char name[MLX5_MAX_NAME_LEN];
487 struct mlx5_eq_table eq_table;
488 struct msix_entry *msix_arr;
489 struct mlx5_irq_info *irq_info;
490 struct mlx5_uuar_info uuari;
491 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
494 struct workqueue_struct *pg_wq;
495 struct rb_root page_root;
498 struct list_head free_list;
501 struct mlx5_core_health health;
503 struct mlx5_srq_table srq_table;
505 /* start: qp staff */
506 struct mlx5_qp_table qp_table;
507 struct dentry *qp_debugfs;
508 struct dentry *eq_debugfs;
509 struct dentry *cq_debugfs;
510 struct dentry *cmdif_debugfs;
513 /* start: cq staff */
514 struct mlx5_cq_table cq_table;
517 /* start: mkey staff */
518 struct mlx5_mkey_table mkey_table;
519 /* end: mkey staff */
521 /* start: alloc staff */
522 /* protect buffer alocation according to numa node */
523 struct mutex alloc_mutex;
526 struct mutex pgdir_mutex;
527 struct list_head pgdir_list;
528 /* end: alloc staff */
529 struct dentry *dbg_root;
531 /* protect mkey key part */
532 spinlock_t mkey_lock;
535 struct list_head dev_list;
536 struct list_head ctx_list;
539 struct mlx5_eswitch *eswitch;
540 struct mlx5_core_sriov sriov;
541 unsigned long pci_dev_data;
542 struct mlx5_flow_root_namespace *root_ns;
543 struct mlx5_flow_root_namespace *fdb_root_ns;
544 struct mlx5_flow_root_namespace *esw_egress_root_ns;
545 struct mlx5_flow_root_namespace *esw_ingress_root_ns;
547 struct mlx5_fc_stats fc_stats;
550 enum mlx5_device_state {
551 MLX5_DEVICE_STATE_UP,
552 MLX5_DEVICE_STATE_INTERNAL_ERROR,
555 enum mlx5_interface_state {
556 MLX5_INTERFACE_STATE_DOWN = BIT(0),
557 MLX5_INTERFACE_STATE_UP = BIT(1),
558 MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2),
561 enum mlx5_pci_status {
562 MLX5_PCI_STATUS_DISABLED,
563 MLX5_PCI_STATUS_ENABLED,
566 struct mlx5_core_dev {
567 struct pci_dev *pdev;
569 struct mutex pci_status_mutex;
570 enum mlx5_pci_status pci_status;
572 char board_id[MLX5_BOARD_ID_LEN];
574 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
575 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
576 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
577 phys_addr_t iseg_base;
578 struct mlx5_init_seg __iomem *iseg;
579 enum mlx5_device_state state;
580 /* sync interface state */
581 struct mutex intf_state_mutex;
582 unsigned long intf_state;
583 void (*event) (struct mlx5_core_dev *dev,
584 enum mlx5_dev_event event,
585 unsigned long param);
586 struct mlx5_priv priv;
587 struct mlx5_profile *profile;
590 #ifdef CONFIG_RFS_ACCEL
591 struct cpu_rmap *rmap;
598 struct mlx5_db_pgdir *pgdir;
599 struct mlx5_ib_user_db_page *user_page;
606 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
610 MLX5_COMP_EQ_SIZE = 1024,
614 MLX5_PTYS_IB = 1 << 0,
615 MLX5_PTYS_EN = 1 << 2,
618 struct mlx5_db_pgdir {
619 struct list_head list;
620 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
625 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
627 struct mlx5_cmd_work_ent {
628 struct mlx5_cmd_msg *in;
629 struct mlx5_cmd_msg *out;
632 mlx5_cmd_cbk_t callback;
635 struct completion done;
636 struct mlx5_cmd *cmd;
637 struct work_struct work;
638 struct mlx5_cmd_layout *lay;
653 enum port_state_policy {
654 MLX5_POLICY_DOWN = 0,
656 MLX5_POLICY_FOLLOW = 2,
657 MLX5_POLICY_INVALID = 0xffffffff
660 enum phy_port_state {
664 struct mlx5_hca_vport_context {
669 enum port_state_policy policy;
670 enum phy_port_state phys_state;
671 enum ib_port_state vport_state;
672 u8 port_physical_state;
681 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
686 u16 qkey_violation_counter;
687 u16 pkey_violation_counter;
691 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
693 return buf->direct.buf + offset;
696 extern struct workqueue_struct *mlx5_core_wq;
698 #define STRUCT_FIELD(header, field) \
699 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
700 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
702 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
704 return pci_get_drvdata(pdev);
707 extern struct dentry *mlx5_debugfs_root;
709 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
711 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
714 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
716 return ioread32be(&dev->iseg->fw_rev) >> 16;
719 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
721 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
724 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
726 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
729 static inline void *mlx5_vzalloc(unsigned long size)
733 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
739 static inline u32 mlx5_base_mkey(const u32 key)
741 return key & 0xffffff00u;
744 int mlx5_cmd_init(struct mlx5_core_dev *dev);
745 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
746 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
747 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
748 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
749 int mlx5_cmd_status_to_err_v2(void *ptr);
750 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
751 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
753 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
754 void *out, int out_size, mlx5_cmd_cbk_t callback,
756 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
757 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
758 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
759 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
760 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar,
762 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
763 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
764 int mlx5_health_init(struct mlx5_core_dev *dev);
765 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
766 void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
767 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
768 struct mlx5_buf *buf, int node);
769 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
770 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
771 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
772 gfp_t flags, int npages);
773 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
774 struct mlx5_cmd_mailbox *head);
775 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
776 struct mlx5_srq_attr *in);
777 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
778 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
779 struct mlx5_srq_attr *out);
780 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
781 u16 lwm, int is_srq);
782 void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
783 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
784 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
785 struct mlx5_core_mkey *mkey,
786 struct mlx5_create_mkey_mbox_in *in, int inlen,
787 mlx5_cmd_cbk_t callback, void *context,
788 struct mlx5_create_mkey_mbox_out *out);
789 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
790 struct mlx5_core_mkey *mkey);
791 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
792 struct mlx5_query_mkey_mbox_out *out, int outlen);
793 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
795 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
796 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
797 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
799 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
800 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
801 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
802 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
803 int mlx5_sriov_init(struct mlx5_core_dev *dev);
804 int mlx5_sriov_cleanup(struct mlx5_core_dev *dev);
805 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
807 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
808 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
809 void mlx5_register_debugfs(void);
810 void mlx5_unregister_debugfs(void);
811 int mlx5_eq_init(struct mlx5_core_dev *dev);
812 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
813 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
814 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
815 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
816 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
817 void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
819 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
820 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
821 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec);
822 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
823 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
824 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
825 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
826 int mlx5_start_eqs(struct mlx5_core_dev *dev);
827 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
828 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
830 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
831 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
833 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
834 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
835 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
836 int size_in, void *data_out, int size_out,
837 u16 reg_num, int arg, int write);
839 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
840 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
841 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
842 struct mlx5_query_eq_mbox_out *out, int outlen);
843 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
844 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
845 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
846 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
847 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
848 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
850 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
852 const char *mlx5_command_str(int command);
853 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
854 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
855 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
856 int npsvs, u32 *sig_index);
857 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
858 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
859 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
860 struct mlx5_odp_caps *odp_caps);
861 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
862 u8 port_num, void *out, size_t sz);
864 static inline int fw_initializing(struct mlx5_core_dev *dev)
866 return ioread32be(&dev->iseg->initializing) >> 31;
869 static inline u32 mlx5_mkey_to_idx(u32 mkey)
874 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
876 return mkey_idx << 8;
879 static inline u8 mlx5_mkey_variant(u32 mkey)
885 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
886 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
890 MAX_MR_CACHE_ENTRIES = 16,
894 MLX5_INTERFACE_PROTOCOL_IB = 0,
895 MLX5_INTERFACE_PROTOCOL_ETH = 1,
898 struct mlx5_interface {
899 void * (*add)(struct mlx5_core_dev *dev);
900 void (*remove)(struct mlx5_core_dev *dev, void *context);
901 void (*event)(struct mlx5_core_dev *dev, void *context,
902 enum mlx5_dev_event event, unsigned long param);
903 void * (*get_dev)(void *context);
905 struct list_head list;
908 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
909 int mlx5_register_interface(struct mlx5_interface *intf);
910 void mlx5_unregister_interface(struct mlx5_interface *intf);
911 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
913 struct mlx5_profile {
919 } mr_cache[MAX_MR_CACHE_ENTRIES];
923 MLX5_PCI_DEV_IS_VF = 1 << 0,
926 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
928 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
931 static inline int mlx5_get_gid_table_len(u16 param)
934 pr_warn("gid table length is zero\n");
938 return 8 * (1 << param);
942 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
945 #endif /* MLX5_DRIVER_H */