2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51 #include <linux/auxiliary_bus.h>
53 #include <linux/mlx5/device.h>
54 #include <linux/mlx5/doorbell.h>
55 #include <linux/mlx5/eq.h>
56 #include <linux/timecounter.h>
57 #include <linux/ptp_clock_kernel.h>
58 #include <net/devlink.h>
60 #define MLX5_ADEV_NAME "mlx5_core"
62 #define MLX5_IRQ_EQ_CTRL (U8_MAX)
65 MLX5_BOARD_ID_LEN = 64,
69 MLX5_CMD_WQ_MAX_NAME = 32,
75 CMD_STATUS_SUCCESS = 0,
81 MLX5_SQP_IEEE_1588 = 2,
83 MLX5_SQP_SYNC_UMR = 4,
91 MLX5_ATOMIC_MODE_OFFSET = 16,
92 MLX5_ATOMIC_MODE_IB_COMP = 1,
93 MLX5_ATOMIC_MODE_CX = 2,
94 MLX5_ATOMIC_MODE_8B = 3,
95 MLX5_ATOMIC_MODE_16B = 4,
96 MLX5_ATOMIC_MODE_32B = 5,
97 MLX5_ATOMIC_MODE_64B = 6,
98 MLX5_ATOMIC_MODE_128B = 7,
99 MLX5_ATOMIC_MODE_256B = 8,
103 MLX5_REG_QPTS = 0x4002,
104 MLX5_REG_QETCR = 0x4005,
105 MLX5_REG_QTCT = 0x400a,
106 MLX5_REG_QPDPM = 0x4013,
107 MLX5_REG_QCAM = 0x4019,
108 MLX5_REG_DCBX_PARAM = 0x4020,
109 MLX5_REG_DCBX_APP = 0x4021,
110 MLX5_REG_FPGA_CAP = 0x4022,
111 MLX5_REG_FPGA_CTRL = 0x4023,
112 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
113 MLX5_REG_CORE_DUMP = 0x402e,
114 MLX5_REG_PCAP = 0x5001,
115 MLX5_REG_PMTU = 0x5003,
116 MLX5_REG_PTYS = 0x5004,
117 MLX5_REG_PAOS = 0x5006,
118 MLX5_REG_PFCC = 0x5007,
119 MLX5_REG_PPCNT = 0x5008,
120 MLX5_REG_PPTB = 0x500b,
121 MLX5_REG_PBMC = 0x500c,
122 MLX5_REG_PMAOS = 0x5012,
123 MLX5_REG_PUDE = 0x5009,
124 MLX5_REG_PMPE = 0x5010,
125 MLX5_REG_PELC = 0x500e,
126 MLX5_REG_PVLC = 0x500f,
127 MLX5_REG_PCMR = 0x5041,
128 MLX5_REG_PDDR = 0x5031,
129 MLX5_REG_PMLP = 0x5002,
130 MLX5_REG_PPLM = 0x5023,
131 MLX5_REG_PCAM = 0x507f,
132 MLX5_REG_NODE_DESC = 0x6001,
133 MLX5_REG_HOST_ENDIANNESS = 0x7004,
134 MLX5_REG_MCIA = 0x9014,
135 MLX5_REG_MFRL = 0x9028,
136 MLX5_REG_MLCR = 0x902b,
137 MLX5_REG_MRTC = 0x902d,
138 MLX5_REG_MTRC_CAP = 0x9040,
139 MLX5_REG_MTRC_CONF = 0x9041,
140 MLX5_REG_MTRC_STDB = 0x9042,
141 MLX5_REG_MTRC_CTRL = 0x9043,
142 MLX5_REG_MPEIN = 0x9050,
143 MLX5_REG_MPCNT = 0x9051,
144 MLX5_REG_MTPPS = 0x9053,
145 MLX5_REG_MTPPSE = 0x9054,
146 MLX5_REG_MTUTC = 0x9055,
147 MLX5_REG_MPEGC = 0x9056,
148 MLX5_REG_MCQS = 0x9060,
149 MLX5_REG_MCQI = 0x9061,
150 MLX5_REG_MCC = 0x9062,
151 MLX5_REG_MCDA = 0x9063,
152 MLX5_REG_MCAM = 0x907f,
153 MLX5_REG_MIRC = 0x9162,
154 MLX5_REG_SBCAM = 0xB01F,
155 MLX5_REG_RESOURCE_DUMP = 0xC000,
156 MLX5_REG_DTOR = 0xC00E,
159 enum mlx5_qpts_trust_state {
160 MLX5_QPTS_TRUST_PCP = 1,
161 MLX5_QPTS_TRUST_DSCP = 2,
164 enum mlx5_dcbx_oper_mode {
165 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
166 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
170 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
171 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
172 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
173 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
176 enum mlx5_page_fault_resume_flags {
177 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
178 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
179 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
180 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
189 enum port_state_policy {
190 MLX5_POLICY_DOWN = 0,
192 MLX5_POLICY_FOLLOW = 2,
193 MLX5_POLICY_INVALID = 0xffffffff
196 enum mlx5_coredev_type {
202 struct mlx5_field_desc {
206 struct mlx5_rsc_debug {
207 struct mlx5_core_dev *dev;
209 enum dbg_rsc_type type;
211 struct mlx5_field_desc fields[];
214 enum mlx5_dev_event {
215 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
216 MLX5_DEV_EVENT_PORT_AFFINITY = 129,
219 enum mlx5_port_status {
224 enum mlx5_cmdif_state {
225 MLX5_CMDIF_STATE_UNINITIALIZED,
227 MLX5_CMDIF_STATE_DOWN,
230 struct mlx5_cmd_first {
234 struct mlx5_cmd_msg {
235 struct list_head list;
236 struct cmd_msg_cache *parent;
238 struct mlx5_cmd_first first;
239 struct mlx5_cmd_mailbox *next;
242 struct mlx5_cmd_debug {
243 struct dentry *dbg_root;
251 struct cmd_msg_cache {
252 /* protect block chain allocations
255 struct list_head head;
256 unsigned int max_inbox_size;
257 unsigned int num_ent;
261 MLX5_NUM_COMMAND_CACHES = 5,
264 struct mlx5_cmd_stats {
267 /* number of times command failed */
269 /* number of times command failed on bad status returned by FW */
270 u64 failed_mbox_status;
271 /* last command failed returned errno */
272 u32 last_failed_errno;
273 /* last bad status returned by FW */
274 u8 last_failed_mbox_status;
275 /* last command failed syndrome returned by FW */
276 u32 last_failed_syndrome;
278 /* protect command average calculations */
285 enum mlx5_cmdif_state state;
287 dma_addr_t alloc_dma;
298 /* protect command queue allocations
300 spinlock_t alloc_lock;
302 /* protect token allocations
304 spinlock_t token_lock;
306 unsigned long bitmask;
307 char wq_name[MLX5_CMD_WQ_MAX_NAME];
308 struct workqueue_struct *wq;
309 struct semaphore sem;
310 struct semaphore pages_sem;
313 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
314 struct dma_pool *pool;
315 struct mlx5_cmd_debug dbg;
316 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
317 int checksum_disabled;
318 struct mlx5_cmd_stats *stats;
321 struct mlx5_cmd_mailbox {
324 struct mlx5_cmd_mailbox *next;
327 struct mlx5_buf_list {
332 struct mlx5_frag_buf {
333 struct mlx5_buf_list *frags;
339 struct mlx5_frag_buf_ctrl {
340 struct mlx5_buf_list *frags;
349 struct mlx5_core_psv {
361 struct mlx5_core_sig_ctx {
362 struct mlx5_core_psv psv_memory;
363 struct mlx5_core_psv psv_wire;
364 struct ib_sig_err err_item;
365 bool sig_status_checked;
370 #define MLX5_24BIT_MASK ((1 << 24) - 1)
373 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
374 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
375 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
379 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT,
382 struct mlx5_core_rsc_common {
383 enum mlx5_res_type res;
385 struct completion free;
388 struct mlx5_uars_page {
392 struct list_head list;
394 unsigned long *reg_bitmap; /* for non fast path bf regs */
395 unsigned long *fp_bitmap;
396 unsigned int reg_avail;
397 unsigned int fp_avail;
398 struct kref ref_count;
399 struct mlx5_core_dev *mdev;
402 struct mlx5_bfreg_head {
403 /* protect blue flame registers allocations */
405 struct list_head list;
408 struct mlx5_bfreg_data {
409 struct mlx5_bfreg_head reg_head;
410 struct mlx5_bfreg_head wc_head;
413 struct mlx5_sq_bfreg {
415 struct mlx5_uars_page *up;
421 struct mlx5_core_health {
422 struct health_buffer __iomem *health;
423 __be32 __iomem *health_counter;
424 struct timer_list timer;
430 /* wq spinlock to synchronize draining */
432 struct workqueue_struct *wq;
434 struct work_struct fatal_report_work;
435 struct work_struct report_work;
436 struct devlink_health_reporter *fw_reporter;
437 struct devlink_health_reporter *fw_fatal_reporter;
438 struct delayed_work update_fw_log_ts_work;
441 struct mlx5_qp_table {
442 struct notifier_block nb;
444 /* protect radix tree
447 struct radix_tree_root tree;
451 MLX5_PF_NOTIFY_DISABLE_VF,
452 MLX5_PF_NOTIFY_ENABLE_VF,
455 struct mlx5_vf_context {
459 /* Valid bits are used to validate administrative guid only.
460 * Enabled after ndo_set_vf_guid
462 u8 port_guid_valid:1;
463 u8 node_guid_valid:1;
464 enum port_state_policy policy;
465 struct blocking_notifier_head notifier;
468 struct mlx5_core_sriov {
469 struct mlx5_vf_context *vfs_ctx;
474 struct mlx5_fc_pool {
475 struct mlx5_core_dev *dev;
476 struct mutex pool_lock; /* protects pool lists */
477 struct list_head fully_used;
478 struct list_head partially_used;
479 struct list_head unused;
485 struct mlx5_fc_stats {
486 spinlock_t counters_idr_lock; /* protects counters_idr */
487 struct idr counters_idr;
488 struct list_head counters;
489 struct llist_head addlist;
490 struct llist_head dellist;
492 struct workqueue_struct *wq;
493 struct delayed_work work;
494 unsigned long next_query;
495 unsigned long sampling_interval; /* jiffies */
499 bool bulk_query_alloc_failed;
500 unsigned long next_bulk_query_alloc;
501 struct mlx5_fc_pool fc_pool;
509 struct mlx5_fw_reset;
510 struct mlx5_eq_table;
511 struct mlx5_irq_table;
512 struct mlx5_vhca_state_notifier;
513 struct mlx5_sf_dev_table;
514 struct mlx5_sf_hw_table;
515 struct mlx5_sf_table;
517 struct mlx5_rate_limit {
523 struct mlx5_rl_entry {
524 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
531 struct mlx5_rl_table {
532 /* protect rate limit table */
533 struct mutex rl_lock;
537 struct mlx5_rl_entry *rl_entry;
541 struct mlx5_core_roce {
542 struct mlx5_flow_table *ft;
543 struct mlx5_flow_group *fg;
544 struct mlx5_flow_handle *allow_rule;
548 MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
549 MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
550 /* Set during device detach to block any further devices
551 * creation/deletion on drivers rescan. Unset during device attach.
553 MLX5_PRIV_FLAGS_DETACH = 1 << 2,
554 /* Distinguish between mlx5e_probe/remove called by module init/cleanup
555 * and called by other flows which can already hold devlink lock
557 MLX5_PRIV_FLAGS_MLX5E_LOCKED_FLOW = 1 << 3,
561 struct auxiliary_device adev;
562 struct mlx5_core_dev *mdev;
566 struct mlx5_debugfs_entries {
567 struct dentry *dbg_root;
568 struct dentry *qp_debugfs;
569 struct dentry *eq_debugfs;
570 struct dentry *cq_debugfs;
571 struct dentry *cmdif_debugfs;
572 struct dentry *pages_debugfs;
573 struct dentry *lag_debugfs;
578 /* IRQ table valid only for real pci devices PF or VF */
579 struct mlx5_irq_table *irq_table;
580 struct mlx5_eq_table *eq_table;
583 struct mlx5_nb pg_nb;
584 struct workqueue_struct *pg_wq;
585 struct xarray page_root_xa;
588 struct list_head free_list;
591 u32 fw_pages_alloc_failed;
592 u32 give_pages_dropped;
593 u32 reclaim_pages_discard;
595 struct mlx5_core_health health;
596 struct list_head traps;
598 struct mlx5_debugfs_entries dbg;
600 /* start: alloc staff */
601 /* protect buffer allocation according to numa node */
602 struct mutex alloc_mutex;
605 struct mutex pgdir_mutex;
606 struct list_head pgdir_list;
607 /* end: alloc staff */
609 struct list_head ctx_list;
611 struct mlx5_adev **adev;
614 struct mlx5_events *events;
616 struct mlx5_flow_steering *steering;
617 struct mlx5_mpfs *mpfs;
618 struct mlx5_eswitch *eswitch;
619 struct mlx5_core_sriov sriov;
620 struct mlx5_lag *lag;
622 struct mlx5_devcom *devcom;
623 struct mlx5_fw_reset *fw_reset;
624 struct mlx5_core_roce roce;
625 struct mlx5_fc_stats fc_stats;
626 struct mlx5_rl_table rl_table;
627 struct mlx5_ft_pool *ft_pool;
629 struct mlx5_bfreg_data bfregs;
630 struct mlx5_uars_page *uar;
631 #ifdef CONFIG_MLX5_SF
632 struct mlx5_vhca_state_notifier *vhca_state_notifier;
633 struct mlx5_sf_dev_table *sf_dev_table;
634 struct mlx5_core_dev *parent_mdev;
636 #ifdef CONFIG_MLX5_SF_MANAGER
637 struct mlx5_sf_hw_table *sf_hw_table;
638 struct mlx5_sf_table *sf_table;
642 enum mlx5_device_state {
643 MLX5_DEVICE_STATE_UP = 1,
644 MLX5_DEVICE_STATE_INTERNAL_ERROR,
647 enum mlx5_interface_state {
648 MLX5_INTERFACE_STATE_UP = BIT(0),
649 MLX5_BREAK_FW_WAIT = BIT(1),
652 enum mlx5_pci_status {
653 MLX5_PCI_STATUS_DISABLED,
654 MLX5_PCI_STATUS_ENABLED,
657 enum mlx5_pagefault_type_flags {
658 MLX5_PFAULT_REQUESTOR = 1 << 0,
659 MLX5_PFAULT_WRITE = 1 << 1,
660 MLX5_PFAULT_RDMA = 1 << 2,
664 /* protects tirs list changes while tirs refresh */
665 struct mutex list_lock;
666 struct list_head tirs_list;
670 struct mlx5e_resources {
671 struct mlx5e_hw_objs {
675 struct mlx5_sq_bfreg bfreg;
677 struct devlink_port dl_port;
678 struct net_device *uplink_netdev;
681 enum mlx5_sw_icm_type {
682 MLX5_SW_ICM_TYPE_STEERING,
683 MLX5_SW_ICM_TYPE_HEADER_MODIFY,
684 MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN,
687 #define MLX5_MAX_RESERVED_GIDS 8
689 struct mlx5_rsvd_gids {
695 #define MAX_PIN_NUM 8
697 u8 pin_caps[MAX_PIN_NUM];
698 struct work_struct out_work;
699 u64 start[MAX_PIN_NUM];
704 struct cyclecounter cycles;
705 struct timecounter tc;
707 unsigned long overflow_period;
708 struct delayed_work overflow_work;
712 struct mlx5_nb pps_nb;
714 struct hwtstamp_config hwtstamp_config;
715 struct ptp_clock *ptp;
716 struct ptp_clock_info ptp_info;
717 struct mlx5_pps pps_info;
718 struct mlx5_timer timer;
722 struct mlx5_fw_tracer;
727 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
728 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
731 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
732 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
736 MKEY_CACHE_LAST_STD_ENTRY = 20,
737 MLX5_IMR_MTT_CACHE_ENTRY,
738 MLX5_IMR_KSM_CACHE_ENTRY,
739 MAX_MKEY_CACHE_ENTRIES
742 struct mlx5_profile {
748 } mr_cache[MAX_MKEY_CACHE_ENTRIES];
751 struct mlx5_hca_cap {
752 u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
753 u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
756 struct mlx5_core_dev {
757 struct device *device;
758 enum mlx5_coredev_type coredev_type;
759 struct pci_dev *pdev;
761 struct mutex pci_status_mutex;
762 enum mlx5_pci_status pci_status;
764 char board_id[MLX5_BOARD_ID_LEN];
767 struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
768 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
769 u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
770 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
771 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
774 struct mlx5_timeouts *timeouts;
776 phys_addr_t iseg_base;
777 struct mlx5_init_seg __iomem *iseg;
778 phys_addr_t bar_addr;
779 enum mlx5_device_state state;
780 /* sync interface state */
781 struct mutex intf_state_mutex;
782 unsigned long intf_state;
783 struct mlx5_priv priv;
784 struct mlx5_profile profile;
786 struct mlx5e_resources mlx5e_res;
788 struct mlx5_vxlan *vxlan;
789 struct mlx5_geneve *geneve;
791 struct mlx5_rsvd_gids reserved_gids;
794 #ifdef CONFIG_MLX5_FPGA
795 struct mlx5_fpga_device *fpga;
797 struct mlx5_clock clock;
798 struct mlx5_ib_clock_info *clock_info;
799 struct mlx5_fw_tracer *tracer;
800 struct mlx5_rsc_dump *rsc_dump;
802 struct mlx5_hv_vhca *hv_vhca;
808 struct mlx5_db_pgdir *pgdir;
809 struct mlx5_ib_user_db_page *user_page;
816 MLX5_COMP_EQ_SIZE = 1024,
820 MLX5_PTYS_IB = 1 << 0,
821 MLX5_PTYS_EN = 1 << 2,
824 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
827 MLX5_CMD_ENT_STATE_PENDING_COMP,
830 struct mlx5_cmd_work_ent {
832 struct mlx5_cmd_msg *in;
833 struct mlx5_cmd_msg *out;
836 mlx5_cmd_cbk_t callback;
837 struct delayed_work cb_timeout_work;
840 struct completion handling;
841 struct completion done;
842 struct mlx5_cmd *cmd;
843 struct work_struct work;
844 struct mlx5_cmd_layout *lay;
853 /* Track the max comp handlers */
862 enum phy_port_state {
866 struct mlx5_hca_vport_context {
871 enum port_state_policy policy;
872 enum phy_port_state phys_state;
873 enum ib_port_state vport_state;
874 u8 port_physical_state;
883 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
888 u16 qkey_violation_counter;
889 u16 pkey_violation_counter;
893 #define STRUCT_FIELD(header, field) \
894 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
895 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
897 extern struct dentry *mlx5_debugfs_root;
899 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
901 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
904 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
906 return ioread32be(&dev->iseg->fw_rev) >> 16;
909 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
911 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
914 static inline u32 mlx5_base_mkey(const u32 key)
916 return key & 0xffffff00u;
919 static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
921 return ((u32)1 << log_sz) << log_stride;
924 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
925 u8 log_stride, u8 log_sz,
927 struct mlx5_frag_buf_ctrl *fbc)
930 fbc->log_stride = log_stride;
931 fbc->log_sz = log_sz;
932 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
933 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
934 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
935 fbc->strides_offset = strides_offset;
938 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
939 u8 log_stride, u8 log_sz,
940 struct mlx5_frag_buf_ctrl *fbc)
942 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
945 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
950 ix += fbc->strides_offset;
951 frag = ix >> fbc->log_frag_strides;
953 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
957 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
959 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
961 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
965 CMD_ALLOWED_OPCODE_ALL,
968 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
969 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
970 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
972 struct mlx5_async_ctx {
973 struct mlx5_core_dev *dev;
974 atomic_t num_inflight;
975 struct wait_queue_head wait;
978 struct mlx5_async_work;
980 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
982 struct mlx5_async_work {
983 struct mlx5_async_ctx *ctx;
984 mlx5_async_cbk_t user_callback;
985 u16 opcode; /* cmd opcode */
986 void *out; /* pointer to the cmd output buffer */
989 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
990 struct mlx5_async_ctx *ctx);
991 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
992 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
993 void *out, int out_size, mlx5_async_cbk_t callback,
994 struct mlx5_async_work *work);
995 void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out);
996 int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size);
997 int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out);
998 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1001 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \
1003 mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \
1004 MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \
1007 #define mlx5_cmd_exec_in(dev, ifc_cmd, in) \
1009 u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \
1010 mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \
1013 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1014 void *out, int out_size);
1015 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
1017 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
1018 void mlx5_health_flush(struct mlx5_core_dev *dev);
1019 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1020 int mlx5_health_init(struct mlx5_core_dev *dev);
1021 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1022 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1023 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1024 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1025 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1026 struct mlx5_frag_buf *buf, int node);
1027 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1028 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1029 gfp_t flags, int npages);
1030 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1031 struct mlx5_cmd_mailbox *head);
1032 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1034 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1035 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1037 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1038 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1039 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1040 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1041 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1042 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1043 void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev);
1044 void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev);
1045 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1046 s32 npages, bool ec_function);
1047 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1048 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1049 void mlx5_register_debugfs(void);
1050 void mlx5_unregister_debugfs(void);
1052 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1053 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1054 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn);
1055 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1056 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1058 struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev);
1059 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1060 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1061 int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
1062 void *data_out, int size_out, u16 reg_id, int arg,
1063 int write, bool verbose);
1064 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1065 int size_in, void *data_out, int size_out,
1066 u16 reg_num, int arg, int write);
1068 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1071 static inline int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db)
1073 return mlx5_db_alloc_node(dev, db, dev->priv.numa_node);
1076 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1078 const char *mlx5_command_str(int command);
1079 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1080 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1081 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1082 int npsvs, u32 *sig_index);
1083 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1084 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1085 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1086 struct mlx5_odp_caps *odp_caps);
1088 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1089 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1090 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1091 struct mlx5_rate_limit *rl);
1092 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1093 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1094 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1095 bool dedicated_entry, u16 *index);
1096 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1097 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1098 struct mlx5_rate_limit *rl_1);
1099 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1100 bool map_wc, bool fast_path);
1101 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1103 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev);
1105 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector);
1106 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1107 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1108 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1109 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1111 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1116 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1118 return mkey_idx << 8;
1121 static inline u8 mlx5_mkey_variant(u32 mkey)
1126 /* Async-atomic event notifier used by mlx5 core to forward FW
1127 * evetns received from event queue to mlx5 consumers.
1128 * Optimise event queue dipatching.
1130 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1131 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1133 /* Async-atomic event notifier used for forwarding
1134 * evetns from the event queue into the to mlx5 events dispatcher,
1135 * eswitch, clock and others.
1137 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1138 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1140 /* Blocking event notifier used to forward SW events, used for slow path */
1141 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1142 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1143 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1146 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1148 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1149 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1150 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1151 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1152 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1153 bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1154 bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1155 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1156 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1157 struct net_device *slave);
1158 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1162 struct mlx5_core_dev *mlx5_lag_get_peer_mdev(struct mlx5_core_dev *dev);
1163 u8 mlx5_lag_get_num_ports(struct mlx5_core_dev *dev);
1164 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1165 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1166 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1167 u64 length, u32 log_alignment, u16 uid,
1168 phys_addr_t *addr, u32 *obj_id);
1169 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1170 u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1172 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev);
1173 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev);
1175 int mlx5_sriov_blocking_notifier_register(struct mlx5_core_dev *mdev,
1177 struct notifier_block *nb);
1178 void mlx5_sriov_blocking_notifier_unregister(struct mlx5_core_dev *mdev,
1180 struct notifier_block *nb);
1181 #ifdef CONFIG_MLX5_CORE_IPOIB
1182 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1183 struct ib_device *ibdev,
1185 void (*setup)(struct net_device *));
1186 #endif /* CONFIG_MLX5_CORE_IPOIB */
1187 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1188 struct ib_device *device,
1189 struct rdma_netdev_alloc_params *params);
1192 MLX5_PCI_DEV_IS_VF = 1 << 0,
1195 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1197 return dev->coredev_type == MLX5_COREDEV_PF;
1200 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1202 return dev->coredev_type == MLX5_COREDEV_VF;
1205 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1207 return dev->caps.embedded_cpu;
1211 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1213 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1216 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1218 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1221 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1223 return dev->priv.sriov.max_vfs;
1226 static inline int mlx5_get_gid_table_len(u16 param)
1229 pr_warn("gid table length is zero\n");
1233 return 8 * (1 << param);
1236 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1238 return !!(dev->priv.rl_table.max_size);
1241 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1243 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1244 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1247 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1249 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1252 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1254 return mlx5_core_is_mp_slave(dev) ||
1255 mlx5_core_is_mp_master(dev);
1258 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1260 if (!mlx5_core_mp_enabled(dev))
1263 return MLX5_CAP_GEN(dev, native_port_num);
1266 static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1268 int idx = MLX5_CAP_GEN(dev, native_port_num);
1270 if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1273 return PCI_FUNC(dev->pdev->devfn);
1277 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1280 static inline bool mlx5_is_roce_init_enabled(struct mlx5_core_dev *dev)
1282 struct devlink *devlink = priv_to_devlink(dev);
1283 union devlink_param_value val;
1286 err = devlink_param_driverinit_value_get(devlink,
1287 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
1289 return err ? MLX5_CAP_GEN(dev, roce) : val.vbool;
1292 #endif /* MLX5_DRIVER_H */