2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock_types.h>
40 #include <linux/semaphore.h>
41 #include <linux/slab.h>
42 #include <linux/vmalloc.h>
43 #include <linux/radix-tree.h>
44 #include <linux/workqueue.h>
45 #include <linux/mempool.h>
46 #include <linux/interrupt.h>
47 #include <linux/idr.h>
49 #include <linux/mlx5/device.h>
50 #include <linux/mlx5/doorbell.h>
51 #include <linux/mlx5/srq.h>
54 MLX5_BOARD_ID_LEN = 64,
55 MLX5_MAX_NAME_LEN = 16,
59 /* one minute for the sake of bringup. Generally, commands must always
60 * complete and we may need to increase this timeout value
62 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
63 MLX5_CMD_WQ_MAX_NAME = 32,
69 CMD_STATUS_SUCCESS = 0,
75 MLX5_SQP_IEEE_1588 = 2,
77 MLX5_SQP_SYNC_UMR = 4,
85 MLX5_EQ_VEC_PAGES = 0,
87 MLX5_EQ_VEC_ASYNC = 2,
88 MLX5_EQ_VEC_PFAULT = 3,
89 MLX5_EQ_VEC_COMP_BASE,
93 MLX5_MAX_IRQ_NAME = 32
97 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
98 MLX5_ATOMIC_MODE_CX = 2 << 16,
99 MLX5_ATOMIC_MODE_8B = 3 << 16,
100 MLX5_ATOMIC_MODE_16B = 4 << 16,
101 MLX5_ATOMIC_MODE_32B = 5 << 16,
102 MLX5_ATOMIC_MODE_64B = 6 << 16,
103 MLX5_ATOMIC_MODE_128B = 7 << 16,
104 MLX5_ATOMIC_MODE_256B = 8 << 16,
108 MLX5_REG_QETCR = 0x4005,
109 MLX5_REG_QTCT = 0x400a,
110 MLX5_REG_DCBX_PARAM = 0x4020,
111 MLX5_REG_DCBX_APP = 0x4021,
112 MLX5_REG_FPGA_CAP = 0x4022,
113 MLX5_REG_FPGA_CTRL = 0x4023,
114 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
115 MLX5_REG_PCAP = 0x5001,
116 MLX5_REG_PMTU = 0x5003,
117 MLX5_REG_PTYS = 0x5004,
118 MLX5_REG_PAOS = 0x5006,
119 MLX5_REG_PFCC = 0x5007,
120 MLX5_REG_PPCNT = 0x5008,
121 MLX5_REG_PMAOS = 0x5012,
122 MLX5_REG_PUDE = 0x5009,
123 MLX5_REG_PMPE = 0x5010,
124 MLX5_REG_PELC = 0x500e,
125 MLX5_REG_PVLC = 0x500f,
126 MLX5_REG_PCMR = 0x5041,
127 MLX5_REG_PMLP = 0x5002,
128 MLX5_REG_PCAM = 0x507f,
129 MLX5_REG_NODE_DESC = 0x6001,
130 MLX5_REG_HOST_ENDIANNESS = 0x7004,
131 MLX5_REG_MCIA = 0x9014,
132 MLX5_REG_MLCR = 0x902b,
133 MLX5_REG_MPCNT = 0x9051,
134 MLX5_REG_MTPPS = 0x9053,
135 MLX5_REG_MTPPSE = 0x9054,
136 MLX5_REG_MCQI = 0x9061,
137 MLX5_REG_MCC = 0x9062,
138 MLX5_REG_MCDA = 0x9063,
139 MLX5_REG_MCAM = 0x907f,
142 enum mlx5_dcbx_oper_mode {
143 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
144 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
148 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
149 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
152 enum mlx5_page_fault_resume_flags {
153 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
154 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
155 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
156 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
165 enum port_state_policy {
166 MLX5_POLICY_DOWN = 0,
168 MLX5_POLICY_FOLLOW = 2,
169 MLX5_POLICY_INVALID = 0xffffffff
172 struct mlx5_field_desc {
177 struct mlx5_rsc_debug {
178 struct mlx5_core_dev *dev;
180 enum dbg_rsc_type type;
182 struct mlx5_field_desc fields[0];
185 enum mlx5_dev_event {
186 MLX5_DEV_EVENT_SYS_ERROR,
187 MLX5_DEV_EVENT_PORT_UP,
188 MLX5_DEV_EVENT_PORT_DOWN,
189 MLX5_DEV_EVENT_PORT_INITIALIZED,
190 MLX5_DEV_EVENT_LID_CHANGE,
191 MLX5_DEV_EVENT_PKEY_CHANGE,
192 MLX5_DEV_EVENT_GUID_CHANGE,
193 MLX5_DEV_EVENT_CLIENT_REREG,
197 enum mlx5_port_status {
205 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
210 struct mlx5_bfreg_info {
212 int num_low_latency_bfregs;
216 * protect bfreg allocation data structs
224 struct mlx5_cmd_first {
228 struct mlx5_cmd_msg {
229 struct list_head list;
230 struct cmd_msg_cache *parent;
232 struct mlx5_cmd_first first;
233 struct mlx5_cmd_mailbox *next;
236 struct mlx5_cmd_debug {
237 struct dentry *dbg_root;
238 struct dentry *dbg_in;
239 struct dentry *dbg_out;
240 struct dentry *dbg_outlen;
241 struct dentry *dbg_status;
242 struct dentry *dbg_run;
250 struct cmd_msg_cache {
251 /* protect block chain allocations
254 struct list_head head;
255 unsigned int max_inbox_size;
256 unsigned int num_ent;
260 MLX5_NUM_COMMAND_CACHES = 5,
263 struct mlx5_cmd_stats {
268 struct dentry *count;
269 /* protect command average calculations */
275 dma_addr_t alloc_dma;
286 /* protect command queue allocations
288 spinlock_t alloc_lock;
290 /* protect token allocations
292 spinlock_t token_lock;
294 unsigned long bitmask;
295 char wq_name[MLX5_CMD_WQ_MAX_NAME];
296 struct workqueue_struct *wq;
297 struct semaphore sem;
298 struct semaphore pages_sem;
300 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
301 struct pci_pool *pool;
302 struct mlx5_cmd_debug dbg;
303 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
304 int checksum_disabled;
305 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
308 struct mlx5_port_caps {
315 struct mlx5_cmd_mailbox {
318 struct mlx5_cmd_mailbox *next;
321 struct mlx5_buf_list {
327 struct mlx5_buf_list direct;
333 struct mlx5_frag_buf {
334 struct mlx5_buf_list *frags;
340 struct mlx5_eq_tasklet {
341 struct list_head list;
342 struct list_head process_list;
343 struct tasklet_struct task;
344 /* lock on completion tasklet list */
348 struct mlx5_eq_pagefault {
349 struct work_struct work;
350 /* Pagefaults lock */
352 struct workqueue_struct *wq;
357 struct mlx5_core_dev *dev;
358 __be32 __iomem *doorbell;
366 struct list_head list;
368 struct mlx5_rsc_debug *dbg;
369 enum mlx5_eq_type type;
371 struct mlx5_eq_tasklet tasklet_ctx;
372 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
373 struct mlx5_eq_pagefault pf_ctx;
378 struct mlx5_core_psv {
390 struct mlx5_core_sig_ctx {
391 struct mlx5_core_psv psv_memory;
392 struct mlx5_core_psv psv_wire;
393 struct ib_sig_err err_item;
394 bool sig_status_checked;
404 struct mlx5_core_mkey {
412 #define MLX5_24BIT_MASK ((1 << 24) - 1)
415 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
416 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
417 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
422 struct mlx5_core_rsc_common {
423 enum mlx5_res_type res;
425 struct completion free;
428 struct mlx5_core_srq {
429 struct mlx5_core_rsc_common common; /* must be first */
433 int max_avail_gather;
435 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
438 struct completion free;
441 struct mlx5_eq_table {
442 void __iomem *update_ci;
443 void __iomem *update_arm_ci;
444 struct list_head comp_eqs_list;
445 struct mlx5_eq pages_eq;
446 struct mlx5_eq async_eq;
447 struct mlx5_eq cmd_eq;
448 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
449 struct mlx5_eq pfault_eq;
451 int num_comp_vectors;
457 struct mlx5_uars_page {
461 struct list_head list;
463 unsigned long *reg_bitmap; /* for non fast path bf regs */
464 unsigned long *fp_bitmap;
465 unsigned int reg_avail;
466 unsigned int fp_avail;
467 struct kref ref_count;
468 struct mlx5_core_dev *mdev;
471 struct mlx5_bfreg_head {
472 /* protect blue flame registers allocations */
474 struct list_head list;
477 struct mlx5_bfreg_data {
478 struct mlx5_bfreg_head reg_head;
479 struct mlx5_bfreg_head wc_head;
482 struct mlx5_sq_bfreg {
484 struct mlx5_uars_page *up;
490 struct mlx5_core_health {
491 struct health_buffer __iomem *health;
492 __be32 __iomem *health_counter;
493 struct timer_list timer;
497 /* wq spinlock to synchronize draining */
499 struct workqueue_struct *wq;
501 struct work_struct work;
502 struct delayed_work recover_work;
505 struct mlx5_cq_table {
506 /* protect radix tree
509 struct radix_tree_root tree;
512 struct mlx5_qp_table {
513 /* protect radix tree
516 struct radix_tree_root tree;
519 struct mlx5_srq_table {
520 /* protect radix tree
523 struct radix_tree_root tree;
526 struct mlx5_mkey_table {
527 /* protect radix tree
530 struct radix_tree_root tree;
533 struct mlx5_vf_context {
537 enum port_state_policy policy;
540 struct mlx5_core_sriov {
541 struct mlx5_vf_context *vfs_ctx;
546 struct mlx5_irq_info {
548 char name[MLX5_MAX_IRQ_NAME];
551 struct mlx5_fc_stats {
552 struct rb_root counters;
553 struct list_head addlist;
554 /* protect addlist add/splice operations */
555 spinlock_t addlist_lock;
557 struct workqueue_struct *wq;
558 struct delayed_work work;
559 unsigned long next_query;
560 unsigned long sampling_interval; /* jiffies */
565 struct mlx5_pagefault;
567 struct mlx5_rl_entry {
573 struct mlx5_rl_table {
574 /* protect rate limit table */
575 struct mutex rl_lock;
579 struct mlx5_rl_entry *rl_entry;
582 enum port_module_event_status_type {
583 MLX5_MODULE_STATUS_PLUGGED = 0x1,
584 MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
585 MLX5_MODULE_STATUS_ERROR = 0x3,
586 MLX5_MODULE_STATUS_NUM = 0x3,
589 enum port_module_event_error_type {
590 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED,
591 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE,
592 MLX5_MODULE_EVENT_ERROR_BUS_STUCK,
593 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT,
594 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST,
595 MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER,
596 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE,
597 MLX5_MODULE_EVENT_ERROR_BAD_CABLE,
598 MLX5_MODULE_EVENT_ERROR_UNKNOWN,
599 MLX5_MODULE_EVENT_ERROR_NUM,
602 struct mlx5_port_module_event_stats {
603 u64 status_counters[MLX5_MODULE_STATUS_NUM];
604 u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
608 char name[MLX5_MAX_NAME_LEN];
609 struct mlx5_eq_table eq_table;
610 struct msix_entry *msix_arr;
611 struct mlx5_irq_info *irq_info;
614 struct workqueue_struct *pg_wq;
615 struct rb_root page_root;
618 struct list_head free_list;
621 struct mlx5_core_health health;
623 struct mlx5_srq_table srq_table;
625 /* start: qp staff */
626 struct mlx5_qp_table qp_table;
627 struct dentry *qp_debugfs;
628 struct dentry *eq_debugfs;
629 struct dentry *cq_debugfs;
630 struct dentry *cmdif_debugfs;
633 /* start: cq staff */
634 struct mlx5_cq_table cq_table;
637 /* start: mkey staff */
638 struct mlx5_mkey_table mkey_table;
639 /* end: mkey staff */
641 /* start: alloc staff */
642 /* protect buffer alocation according to numa node */
643 struct mutex alloc_mutex;
646 struct mutex pgdir_mutex;
647 struct list_head pgdir_list;
648 /* end: alloc staff */
649 struct dentry *dbg_root;
651 /* protect mkey key part */
652 spinlock_t mkey_lock;
655 struct list_head dev_list;
656 struct list_head ctx_list;
659 struct mlx5_flow_steering *steering;
660 struct mlx5_eswitch *eswitch;
661 struct mlx5_core_sriov sriov;
662 struct mlx5_lag *lag;
663 unsigned long pci_dev_data;
664 struct mlx5_fc_stats fc_stats;
665 struct mlx5_rl_table rl_table;
667 struct mlx5_port_module_event_stats pme_stats;
669 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
670 void (*pfault)(struct mlx5_core_dev *dev,
672 struct mlx5_pagefault *pfault);
674 struct srcu_struct pfault_srcu;
676 struct mlx5_bfreg_data bfregs;
677 struct mlx5_uars_page *uar;
680 enum mlx5_device_state {
681 MLX5_DEVICE_STATE_UP,
682 MLX5_DEVICE_STATE_INTERNAL_ERROR,
685 enum mlx5_interface_state {
686 MLX5_INTERFACE_STATE_DOWN = BIT(0),
687 MLX5_INTERFACE_STATE_UP = BIT(1),
688 MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2),
691 enum mlx5_pci_status {
692 MLX5_PCI_STATUS_DISABLED,
693 MLX5_PCI_STATUS_ENABLED,
696 enum mlx5_pagefault_type_flags {
697 MLX5_PFAULT_REQUESTOR = 1 << 0,
698 MLX5_PFAULT_WRITE = 1 << 1,
699 MLX5_PFAULT_RDMA = 1 << 2,
702 /* Contains the details of a pagefault. */
703 struct mlx5_pagefault {
709 /* Initiator or send message responder pagefault details. */
711 /* Received packet size, only valid for responders. */
714 * Number of resource holding WQE, depends on type.
718 * WQE index. Refers to either the send queue or
719 * receive queue, according to event_subtype.
723 /* RDMA responder pagefault details */
727 * Received packet size, minimal size page fault
728 * resolution required for forward progress.
737 struct work_struct work;
741 struct list_head tirs_list;
745 struct mlx5e_resources {
748 struct mlx5_core_mkey mkey;
749 struct mlx5_sq_bfreg bfreg;
752 #define MLX5_MAX_RESERVED_GIDS 8
754 struct mlx5_rsvd_gids {
760 struct mlx5_core_dev {
761 struct pci_dev *pdev;
763 struct mutex pci_status_mutex;
764 enum mlx5_pci_status pci_status;
766 char board_id[MLX5_BOARD_ID_LEN];
768 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
770 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
771 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
772 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
773 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
775 phys_addr_t iseg_base;
776 struct mlx5_init_seg __iomem *iseg;
777 enum mlx5_device_state state;
778 /* sync interface state */
779 struct mutex intf_state_mutex;
780 unsigned long intf_state;
781 void (*event) (struct mlx5_core_dev *dev,
782 enum mlx5_dev_event event,
783 unsigned long param);
784 struct mlx5_priv priv;
785 struct mlx5_profile *profile;
788 struct mlx5e_resources mlx5e_res;
790 struct mlx5_rsvd_gids reserved_gids;
793 #ifdef CONFIG_MLX5_FPGA
794 struct mlx5_fpga_device *fpga;
796 #ifdef CONFIG_RFS_ACCEL
797 struct cpu_rmap *rmap;
804 struct mlx5_db_pgdir *pgdir;
805 struct mlx5_ib_user_db_page *user_page;
812 MLX5_COMP_EQ_SIZE = 1024,
816 MLX5_PTYS_IB = 1 << 0,
817 MLX5_PTYS_EN = 1 << 2,
820 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
823 MLX5_CMD_ENT_STATE_PENDING_COMP,
826 struct mlx5_cmd_work_ent {
828 struct mlx5_cmd_msg *in;
829 struct mlx5_cmd_msg *out;
832 mlx5_cmd_cbk_t callback;
833 struct delayed_work cb_timeout_work;
836 struct completion done;
837 struct mlx5_cmd *cmd;
838 struct work_struct work;
839 struct mlx5_cmd_layout *lay;
855 enum phy_port_state {
859 struct mlx5_hca_vport_context {
864 enum port_state_policy policy;
865 enum phy_port_state phys_state;
866 enum ib_port_state vport_state;
867 u8 port_physical_state;
876 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
881 u16 qkey_violation_counter;
882 u16 pkey_violation_counter;
886 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
888 return buf->direct.buf + offset;
891 extern struct workqueue_struct *mlx5_core_wq;
893 #define STRUCT_FIELD(header, field) \
894 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
895 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
897 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
899 return pci_get_drvdata(pdev);
902 extern struct dentry *mlx5_debugfs_root;
904 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
906 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
909 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
911 return ioread32be(&dev->iseg->fw_rev) >> 16;
914 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
916 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
919 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
921 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
924 static inline u32 mlx5_base_mkey(const u32 key)
926 return key & 0xffffff00u;
929 int mlx5_cmd_init(struct mlx5_core_dev *dev);
930 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
931 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
932 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
934 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
936 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
937 void *out, int out_size, mlx5_cmd_cbk_t callback,
939 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
940 void *out, int out_size);
941 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
943 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
944 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
945 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
946 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
947 int mlx5_health_init(struct mlx5_core_dev *dev);
948 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
949 void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
950 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
951 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
952 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
953 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
954 struct mlx5_buf *buf, int node);
955 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
956 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
957 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
958 struct mlx5_frag_buf *buf, int node);
959 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
960 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
961 gfp_t flags, int npages);
962 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
963 struct mlx5_cmd_mailbox *head);
964 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
965 struct mlx5_srq_attr *in);
966 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
967 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
968 struct mlx5_srq_attr *out);
969 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
970 u16 lwm, int is_srq);
971 void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
972 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
973 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
974 struct mlx5_core_mkey *mkey,
976 u32 *out, int outlen,
977 mlx5_cmd_cbk_t callback, void *context);
978 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
979 struct mlx5_core_mkey *mkey,
981 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
982 struct mlx5_core_mkey *mkey);
983 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
984 u32 *out, int outlen);
985 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
987 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
988 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
989 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
991 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
992 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
993 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
994 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
995 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
997 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
998 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
999 void mlx5_register_debugfs(void);
1000 void mlx5_unregister_debugfs(void);
1001 int mlx5_eq_init(struct mlx5_core_dev *dev);
1002 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
1003 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
1004 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1005 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
1006 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1007 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1008 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1009 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
1010 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
1011 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
1012 int nent, u64 mask, const char *name,
1013 enum mlx5_eq_type type);
1014 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1015 int mlx5_start_eqs(struct mlx5_core_dev *dev);
1016 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
1017 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
1018 unsigned int *irqn);
1019 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1020 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1022 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1023 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1024 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1025 int size_in, void *data_out, int size_out,
1026 u16 reg_num, int arg, int write);
1028 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1029 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1030 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1031 u32 *out, int outlen);
1032 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1033 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1034 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1035 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1036 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1037 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1039 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1041 const char *mlx5_command_str(int command);
1042 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1043 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1044 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1045 int npsvs, u32 *sig_index);
1046 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1047 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1048 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1049 struct mlx5_odp_caps *odp_caps);
1050 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1051 u8 port_num, void *out, size_t sz);
1052 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1053 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token,
1054 u32 wq_num, u8 type, int error);
1057 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1058 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1059 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index);
1060 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate);
1061 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1062 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1063 bool map_wc, bool fast_path);
1064 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1066 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1067 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1068 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1069 const u8 *mac, bool vlan, u16 vlan_id);
1071 static inline int fw_initializing(struct mlx5_core_dev *dev)
1073 return ioread32be(&dev->iseg->initializing) >> 31;
1076 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1081 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1083 return mkey_idx << 8;
1086 static inline u8 mlx5_mkey_variant(u32 mkey)
1092 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
1093 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
1097 MAX_UMR_CACHE_ENTRY = 20,
1098 MLX5_IMR_MTT_CACHE_ENTRY,
1099 MLX5_IMR_KSM_CACHE_ENTRY,
1100 MAX_MR_CACHE_ENTRIES
1104 MLX5_INTERFACE_PROTOCOL_IB = 0,
1105 MLX5_INTERFACE_PROTOCOL_ETH = 1,
1108 struct mlx5_interface {
1109 void * (*add)(struct mlx5_core_dev *dev);
1110 void (*remove)(struct mlx5_core_dev *dev, void *context);
1111 int (*attach)(struct mlx5_core_dev *dev, void *context);
1112 void (*detach)(struct mlx5_core_dev *dev, void *context);
1113 void (*event)(struct mlx5_core_dev *dev, void *context,
1114 enum mlx5_dev_event event, unsigned long param);
1115 void (*pfault)(struct mlx5_core_dev *dev,
1117 struct mlx5_pagefault *pfault);
1118 void * (*get_dev)(void *context);
1120 struct list_head list;
1123 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1124 int mlx5_register_interface(struct mlx5_interface *intf);
1125 void mlx5_unregister_interface(struct mlx5_interface *intf);
1126 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1128 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1129 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1130 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1131 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1132 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1133 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1135 #ifndef CONFIG_MLX5_CORE_IPOIB
1137 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1138 struct ib_device *ibdev,
1140 void (*setup)(struct net_device *))
1142 return ERR_PTR(-EOPNOTSUPP);
1145 static inline void mlx5_rdma_netdev_free(struct net_device *netdev) {}
1147 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1148 struct ib_device *ibdev,
1150 void (*setup)(struct net_device *));
1151 void mlx5_rdma_netdev_free(struct net_device *netdev);
1152 #endif /* CONFIG_MLX5_CORE_IPOIB */
1154 struct mlx5_profile {
1160 } mr_cache[MAX_MR_CACHE_ENTRIES];
1164 MLX5_PCI_DEV_IS_VF = 1 << 0,
1167 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1169 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1172 static inline int mlx5_get_gid_table_len(u16 param)
1175 pr_warn("gid table length is zero\n");
1179 return 8 * (1 << param);
1182 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1184 return !!(dev->priv.rl_table.max_size);
1188 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1191 #endif /* MLX5_DRIVER_H */