2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/types.h>
37 #include <rdma/ib_verbs.h>
39 #if defined(__LITTLE_ENDIAN)
40 #define MLX5_SET_HOST_ENDIANNESS 0
41 #elif defined(__BIG_ENDIAN)
42 #define MLX5_SET_HOST_ENDIANNESS 0x80
44 #error Host endianness not defined
48 MLX5_MAX_COMMANDS = 32,
49 MLX5_CMD_DATA_BLOCK_SIZE = 512,
50 MLX5_PCI_CMD_XPORT = 7,
54 MLX5_EXTENDED_UD_AV = 0x80000000,
58 MLX5_CQ_STATE_ARMED = 9,
59 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
60 MLX5_CQ_STATE_FIRED = 0xa,
64 MLX5_STAT_RATE_OFFSET = 5,
68 MLX5_INLINE_SEG = 0x80000000,
72 MLX5_PERM_LOCAL_READ = 1 << 2,
73 MLX5_PERM_LOCAL_WRITE = 1 << 3,
74 MLX5_PERM_REMOTE_READ = 1 << 4,
75 MLX5_PERM_REMOTE_WRITE = 1 << 5,
76 MLX5_PERM_ATOMIC = 1 << 6,
77 MLX5_PERM_UMR_EN = 1 << 7,
81 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
82 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
83 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
84 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
85 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
89 MLX5_ACCESS_MODE_PA = 0,
90 MLX5_ACCESS_MODE_MTT = 1,
91 MLX5_ACCESS_MODE_KLM = 2
95 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
96 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
97 MLX5_MKEY_BSF_EN = 1 << 30,
98 MLX5_MKEY_LEN64 = 1 << 31,
107 MLX5_BF_REGS_PER_PAGE = 4,
108 MLX5_MAX_UAR_PAGES = 1 << 8,
109 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
110 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
114 MLX5_MKEY_MASK_LEN = 1ull << 0,
115 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
116 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
117 MLX5_MKEY_MASK_PD = 1ull << 7,
118 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
119 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
120 MLX5_MKEY_MASK_KEY = 1ull << 13,
121 MLX5_MKEY_MASK_QPN = 1ull << 14,
122 MLX5_MKEY_MASK_LR = 1ull << 17,
123 MLX5_MKEY_MASK_LW = 1ull << 18,
124 MLX5_MKEY_MASK_RR = 1ull << 19,
125 MLX5_MKEY_MASK_RW = 1ull << 20,
126 MLX5_MKEY_MASK_A = 1ull << 21,
127 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
128 MLX5_MKEY_MASK_FREE = 1ull << 29,
132 MLX5_EVENT_TYPE_COMP = 0x0,
134 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
135 MLX5_EVENT_TYPE_COMM_EST = 0x02,
136 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
137 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
138 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
140 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
141 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
142 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
143 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
144 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
145 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
147 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
148 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
149 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
150 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
152 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
153 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
155 MLX5_EVENT_TYPE_CMD = 0x0a,
156 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
160 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
161 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
162 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
163 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
164 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
165 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
166 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
170 MLX5_DEV_CAP_FLAG_RC = 1LL << 0,
171 MLX5_DEV_CAP_FLAG_UC = 1LL << 1,
172 MLX5_DEV_CAP_FLAG_UD = 1LL << 2,
173 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
174 MLX5_DEV_CAP_FLAG_SRQ = 1LL << 6,
175 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
176 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
177 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
178 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
179 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
180 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
181 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
182 MLX5_DEV_CAP_FLAG_RESIZE_SRQ = 1LL << 32,
183 MLX5_DEV_CAP_FLAG_REMOTE_FENCE = 1LL << 38,
184 MLX5_DEV_CAP_FLAG_TLP_HINTS = 1LL << 39,
185 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
186 MLX5_DEV_CAP_FLAG_DCT = 1LL << 41,
187 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
191 MLX5_OPCODE_NOP = 0x00,
192 MLX5_OPCODE_SEND_INVAL = 0x01,
193 MLX5_OPCODE_RDMA_WRITE = 0x08,
194 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
195 MLX5_OPCODE_SEND = 0x0a,
196 MLX5_OPCODE_SEND_IMM = 0x0b,
197 MLX5_OPCODE_RDMA_READ = 0x10,
198 MLX5_OPCODE_ATOMIC_CS = 0x11,
199 MLX5_OPCODE_ATOMIC_FA = 0x12,
200 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
201 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
202 MLX5_OPCODE_BIND_MW = 0x18,
203 MLX5_OPCODE_CONFIG_CMD = 0x1f,
205 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
206 MLX5_RECV_OPCODE_SEND = 0x01,
207 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
208 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
210 MLX5_CQE_OPCODE_ERROR = 0x1e,
211 MLX5_CQE_OPCODE_RESIZE = 0x16,
213 MLX5_OPCODE_SET_PSV = 0x20,
214 MLX5_OPCODE_GET_PSV = 0x21,
215 MLX5_OPCODE_CHECK_PSV = 0x22,
216 MLX5_OPCODE_RGET_PSV = 0x26,
217 MLX5_OPCODE_RCHECK_PSV = 0x27,
219 MLX5_OPCODE_UMR = 0x25,
224 MLX5_SET_PORT_RESET_QKEY = 0,
225 MLX5_SET_PORT_GUID0 = 16,
226 MLX5_SET_PORT_NODE_GUID = 17,
227 MLX5_SET_PORT_SYS_GUID = 18,
228 MLX5_SET_PORT_GID_TABLE = 19,
229 MLX5_SET_PORT_PKEY_TABLE = 20,
233 MLX5_MAX_PAGE_SHIFT = 31
237 MLX5_ADAPTER_PAGE_SHIFT = 12,
238 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
242 MLX5_CAP_OFF_DCT = 41,
243 MLX5_CAP_OFF_CMDIF_CSUM = 46,
246 struct mlx5_inbox_hdr {
252 struct mlx5_outbox_hdr {
258 struct mlx5_cmd_query_adapter_mbox_in {
259 struct mlx5_inbox_hdr hdr;
263 struct mlx5_cmd_query_adapter_mbox_out {
264 struct mlx5_outbox_hdr hdr;
268 __be16 vsd_vendor_id;
273 struct mlx5_hca_cap {
292 u8 log_max_bsf_list_sz;
293 u8 log_max_klm_list_sz;
295 u8 log_max_ra_req_dc;
297 u8 log_max_ra_res_dc;
299 u8 log_max_ra_req_qp;
301 u8 log_max_ra_res_qp;
306 u8 local_ca_ack_delay;
311 __be16 stat_rate_support;
318 __be16 bf_log_bf_reg_size;
320 __be16 max_desc_sz_sq;
322 __be16 max_desc_sz_rq;
324 __be16 max_desc_sz_sq_dc;
333 __be16 log_uar_page_sz;
335 u8 log_max_atomic_size_qp;
337 u8 log_max_atomic_size_dc;
342 struct mlx5_cmd_query_hca_cap_mbox_in {
343 struct mlx5_inbox_hdr hdr;
348 struct mlx5_cmd_query_hca_cap_mbox_out {
349 struct mlx5_outbox_hdr hdr;
351 struct mlx5_hca_cap hca_cap;
355 struct mlx5_cmd_set_hca_cap_mbox_in {
356 struct mlx5_inbox_hdr hdr;
358 struct mlx5_hca_cap hca_cap;
362 struct mlx5_cmd_set_hca_cap_mbox_out {
363 struct mlx5_outbox_hdr hdr;
368 struct mlx5_cmd_init_hca_mbox_in {
369 struct mlx5_inbox_hdr hdr;
375 struct mlx5_cmd_init_hca_mbox_out {
376 struct mlx5_outbox_hdr hdr;
380 struct mlx5_cmd_teardown_hca_mbox_in {
381 struct mlx5_inbox_hdr hdr;
387 struct mlx5_cmd_teardown_hca_mbox_out {
388 struct mlx5_outbox_hdr hdr;
392 struct mlx5_cmd_layout {
408 struct health_buffer {
409 __be32 assert_var[5];
411 __be32 assert_exit_ptr;
412 __be32 assert_callra;
422 struct mlx5_init_seg {
424 __be32 cmdif_rev_fw_sub;
427 __be32 cmdq_addr_l_sz;
430 struct health_buffer health;
432 __be32 health_counter;
435 __be32 ieee1588_clk_type;
439 struct mlx5_eqe_comp {
444 struct mlx5_eqe_qp_srq {
449 struct mlx5_eqe_cq_err {
455 struct mlx5_eqe_dropped_packet {
458 struct mlx5_eqe_port_state {
463 struct mlx5_eqe_gpio {
468 struct mlx5_eqe_congestion {
474 struct mlx5_eqe_stall_vl {
479 struct mlx5_eqe_cmd {
484 struct mlx5_eqe_page_req {
493 struct mlx5_eqe_cmd cmd;
494 struct mlx5_eqe_comp comp;
495 struct mlx5_eqe_qp_srq qp_srq;
496 struct mlx5_eqe_cq_err cq_err;
497 struct mlx5_eqe_dropped_packet dp;
498 struct mlx5_eqe_port_state port;
499 struct mlx5_eqe_gpio gpio;
500 struct mlx5_eqe_congestion cong;
501 struct mlx5_eqe_stall_vl stall_vl;
502 struct mlx5_eqe_page_req req_pages;
517 struct mlx5_cmd_prot_block {
518 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
528 struct mlx5_err_cqe {
534 __be32 s_wqe_opcode_qpn;
548 __be32 imm_inval_pkey;
558 struct mlx5_wqe_srq_next_seg {
560 __be16 next_wqe_index;
571 union mlx5_ext_cqe inl_grh;
572 struct mlx5_cqe64 cqe64;
575 struct mlx5_srq_ctx {
590 struct mlx5_create_srq_mbox_in {
591 struct mlx5_inbox_hdr hdr;
594 struct mlx5_srq_ctx ctx;
599 struct mlx5_create_srq_mbox_out {
600 struct mlx5_outbox_hdr hdr;
605 struct mlx5_destroy_srq_mbox_in {
606 struct mlx5_inbox_hdr hdr;
611 struct mlx5_destroy_srq_mbox_out {
612 struct mlx5_outbox_hdr hdr;
616 struct mlx5_query_srq_mbox_in {
617 struct mlx5_inbox_hdr hdr;
622 struct mlx5_query_srq_mbox_out {
623 struct mlx5_outbox_hdr hdr;
625 struct mlx5_srq_ctx ctx;
630 struct mlx5_arm_srq_mbox_in {
631 struct mlx5_inbox_hdr hdr;
637 struct mlx5_arm_srq_mbox_out {
638 struct mlx5_outbox_hdr hdr;
642 struct mlx5_cq_context {
649 __be32 log_sz_usr_page;
656 __be32 last_notified_index;
657 __be32 solicit_producer_index;
658 __be32 consumer_counter;
659 __be32 producer_counter;
661 __be64 db_record_addr;
664 struct mlx5_create_cq_mbox_in {
665 struct mlx5_inbox_hdr hdr;
668 struct mlx5_cq_context ctx;
673 struct mlx5_create_cq_mbox_out {
674 struct mlx5_outbox_hdr hdr;
679 struct mlx5_destroy_cq_mbox_in {
680 struct mlx5_inbox_hdr hdr;
685 struct mlx5_destroy_cq_mbox_out {
686 struct mlx5_outbox_hdr hdr;
690 struct mlx5_query_cq_mbox_in {
691 struct mlx5_inbox_hdr hdr;
696 struct mlx5_query_cq_mbox_out {
697 struct mlx5_outbox_hdr hdr;
699 struct mlx5_cq_context ctx;
704 struct mlx5_modify_cq_mbox_in {
705 struct mlx5_inbox_hdr hdr;
708 struct mlx5_cq_context ctx;
713 struct mlx5_modify_cq_mbox_out {
714 struct mlx5_outbox_hdr hdr;
718 struct mlx5_enable_hca_mbox_in {
719 struct mlx5_inbox_hdr hdr;
723 struct mlx5_enable_hca_mbox_out {
724 struct mlx5_outbox_hdr hdr;
728 struct mlx5_disable_hca_mbox_in {
729 struct mlx5_inbox_hdr hdr;
733 struct mlx5_disable_hca_mbox_out {
734 struct mlx5_outbox_hdr hdr;
738 struct mlx5_eq_context {
744 __be32 log_sz_usr_page;
749 __be32 consumer_counter;
750 __be32 produser_counter;
754 struct mlx5_create_eq_mbox_in {
755 struct mlx5_inbox_hdr hdr;
759 struct mlx5_eq_context ctx;
766 struct mlx5_create_eq_mbox_out {
767 struct mlx5_outbox_hdr hdr;
773 struct mlx5_destroy_eq_mbox_in {
774 struct mlx5_inbox_hdr hdr;
780 struct mlx5_destroy_eq_mbox_out {
781 struct mlx5_outbox_hdr hdr;
785 struct mlx5_map_eq_mbox_in {
786 struct mlx5_inbox_hdr hdr;
794 struct mlx5_map_eq_mbox_out {
795 struct mlx5_outbox_hdr hdr;
799 struct mlx5_query_eq_mbox_in {
800 struct mlx5_inbox_hdr hdr;
806 struct mlx5_query_eq_mbox_out {
807 struct mlx5_outbox_hdr hdr;
809 struct mlx5_eq_context ctx;
812 struct mlx5_mkey_seg {
813 /* This is a two bit field occupying bits 31-30.
814 * bit 31 is always 0,
815 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
826 __be32 bsfs_octo_size;
834 struct mlx5_query_special_ctxs_mbox_in {
835 struct mlx5_inbox_hdr hdr;
839 struct mlx5_query_special_ctxs_mbox_out {
840 struct mlx5_outbox_hdr hdr;
841 __be32 dump_fill_mkey;
842 __be32 reserved_lkey;
845 struct mlx5_create_mkey_mbox_in {
846 struct mlx5_inbox_hdr hdr;
847 __be32 input_mkey_index;
849 struct mlx5_mkey_seg seg;
851 __be32 xlat_oct_act_size;
857 struct mlx5_create_mkey_mbox_out {
858 struct mlx5_outbox_hdr hdr;
863 struct mlx5_destroy_mkey_mbox_in {
864 struct mlx5_inbox_hdr hdr;
869 struct mlx5_destroy_mkey_mbox_out {
870 struct mlx5_outbox_hdr hdr;
874 struct mlx5_query_mkey_mbox_in {
875 struct mlx5_inbox_hdr hdr;
879 struct mlx5_query_mkey_mbox_out {
880 struct mlx5_outbox_hdr hdr;
884 struct mlx5_modify_mkey_mbox_in {
885 struct mlx5_inbox_hdr hdr;
890 struct mlx5_modify_mkey_mbox_out {
891 struct mlx5_outbox_hdr hdr;
895 struct mlx5_dump_mkey_mbox_in {
896 struct mlx5_inbox_hdr hdr;
899 struct mlx5_dump_mkey_mbox_out {
900 struct mlx5_outbox_hdr hdr;
904 struct mlx5_mad_ifc_mbox_in {
905 struct mlx5_inbox_hdr hdr;
913 struct mlx5_mad_ifc_mbox_out {
914 struct mlx5_outbox_hdr hdr;
919 struct mlx5_access_reg_mbox_in {
920 struct mlx5_inbox_hdr hdr;
927 struct mlx5_access_reg_mbox_out {
928 struct mlx5_outbox_hdr hdr;
933 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
936 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
939 #endif /* MLX5_DEVICE_H */