2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/types.h>
37 #include <rdma/ib_verbs.h>
39 #if defined(__LITTLE_ENDIAN)
40 #define MLX5_SET_HOST_ENDIANNESS 0
41 #elif defined(__BIG_ENDIAN)
42 #define MLX5_SET_HOST_ENDIANNESS 0x80
44 #error Host endianness not defined
48 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
49 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
50 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
51 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
52 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
53 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
54 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
55 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
56 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
58 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
59 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
60 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
61 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
62 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
64 /* insert a value to a struct */
65 #define MLX5_SET(typ, p, fld, v) do { \
66 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
67 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
68 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
69 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
70 << __mlx5_dw_bit_off(typ, fld))); \
73 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
74 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
75 __mlx5_mask(typ, fld))
77 #define MLX5_GET_PR(typ, p, fld) ({ \
78 u32 ___t = MLX5_GET(typ, p, fld); \
79 pr_debug(#fld " = 0x%x\n", ___t); \
83 #define MLX5_SET64(typ, p, fld, v) do { \
84 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
85 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
86 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
89 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
92 MLX5_MAX_COMMANDS = 32,
93 MLX5_CMD_DATA_BLOCK_SIZE = 512,
94 MLX5_PCI_CMD_XPORT = 7,
95 MLX5_MKEY_BSF_OCTO_SIZE = 4,
100 MLX5_EXTENDED_UD_AV = 0x80000000,
104 MLX5_CQ_STATE_ARMED = 9,
105 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
106 MLX5_CQ_STATE_FIRED = 0xa,
110 MLX5_STAT_RATE_OFFSET = 5,
114 MLX5_INLINE_SEG = 0x80000000,
118 MLX5_MIN_PKEY_TABLE_SIZE = 128,
119 MLX5_MAX_LOG_PKEY_TABLE = 5,
123 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
127 MLX5_PFAULT_SUBTYPE_WQE = 0,
128 MLX5_PFAULT_SUBTYPE_RDMA = 1,
132 MLX5_PERM_LOCAL_READ = 1 << 2,
133 MLX5_PERM_LOCAL_WRITE = 1 << 3,
134 MLX5_PERM_REMOTE_READ = 1 << 4,
135 MLX5_PERM_REMOTE_WRITE = 1 << 5,
136 MLX5_PERM_ATOMIC = 1 << 6,
137 MLX5_PERM_UMR_EN = 1 << 7,
141 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
142 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
143 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
144 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
145 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
149 MLX5_ACCESS_MODE_PA = 0,
150 MLX5_ACCESS_MODE_MTT = 1,
151 MLX5_ACCESS_MODE_KLM = 2
155 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
156 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
157 MLX5_MKEY_BSF_EN = 1 << 30,
158 MLX5_MKEY_LEN64 = 1 << 31,
167 MLX5_BF_REGS_PER_PAGE = 4,
168 MLX5_MAX_UAR_PAGES = 1 << 8,
169 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
170 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
174 MLX5_MKEY_MASK_LEN = 1ull << 0,
175 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
176 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
177 MLX5_MKEY_MASK_PD = 1ull << 7,
178 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
179 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
180 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
181 MLX5_MKEY_MASK_KEY = 1ull << 13,
182 MLX5_MKEY_MASK_QPN = 1ull << 14,
183 MLX5_MKEY_MASK_LR = 1ull << 17,
184 MLX5_MKEY_MASK_LW = 1ull << 18,
185 MLX5_MKEY_MASK_RR = 1ull << 19,
186 MLX5_MKEY_MASK_RW = 1ull << 20,
187 MLX5_MKEY_MASK_A = 1ull << 21,
188 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
189 MLX5_MKEY_MASK_FREE = 1ull << 29,
193 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
195 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
196 MLX5_UMR_CHECK_FREE = (2 << 5),
198 MLX5_UMR_INLINE = (1 << 7),
201 #define MLX5_UMR_MTT_ALIGNMENT 0x40
202 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
203 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
206 MLX5_EVENT_TYPE_COMP = 0x0,
208 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
209 MLX5_EVENT_TYPE_COMM_EST = 0x02,
210 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
211 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
212 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
214 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
215 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
216 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
217 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
218 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
219 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
221 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
222 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
223 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
224 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
226 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
227 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
229 MLX5_EVENT_TYPE_CMD = 0x0a,
230 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
232 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
236 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
237 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
238 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
239 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
240 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
241 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
242 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
246 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
247 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
248 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
249 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
250 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
251 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
252 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
253 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
254 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
255 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
256 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
257 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
261 MLX5_OPCODE_NOP = 0x00,
262 MLX5_OPCODE_SEND_INVAL = 0x01,
263 MLX5_OPCODE_RDMA_WRITE = 0x08,
264 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
265 MLX5_OPCODE_SEND = 0x0a,
266 MLX5_OPCODE_SEND_IMM = 0x0b,
267 MLX5_OPCODE_RDMA_READ = 0x10,
268 MLX5_OPCODE_ATOMIC_CS = 0x11,
269 MLX5_OPCODE_ATOMIC_FA = 0x12,
270 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
271 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
272 MLX5_OPCODE_BIND_MW = 0x18,
273 MLX5_OPCODE_CONFIG_CMD = 0x1f,
275 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
276 MLX5_RECV_OPCODE_SEND = 0x01,
277 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
278 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
280 MLX5_CQE_OPCODE_ERROR = 0x1e,
281 MLX5_CQE_OPCODE_RESIZE = 0x16,
283 MLX5_OPCODE_SET_PSV = 0x20,
284 MLX5_OPCODE_GET_PSV = 0x21,
285 MLX5_OPCODE_CHECK_PSV = 0x22,
286 MLX5_OPCODE_RGET_PSV = 0x26,
287 MLX5_OPCODE_RCHECK_PSV = 0x27,
289 MLX5_OPCODE_UMR = 0x25,
294 MLX5_SET_PORT_RESET_QKEY = 0,
295 MLX5_SET_PORT_GUID0 = 16,
296 MLX5_SET_PORT_NODE_GUID = 17,
297 MLX5_SET_PORT_SYS_GUID = 18,
298 MLX5_SET_PORT_GID_TABLE = 19,
299 MLX5_SET_PORT_PKEY_TABLE = 20,
303 MLX5_MAX_PAGE_SHIFT = 31
307 MLX5_ADAPTER_PAGE_SHIFT = 12,
308 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
312 MLX5_CAP_OFF_CMDIF_CSUM = 46,
316 HCA_CAP_OPMOD_GET_MAX = 0,
317 HCA_CAP_OPMOD_GET_CUR = 1,
318 HCA_CAP_OPMOD_GET_ODP_MAX = 4,
319 HCA_CAP_OPMOD_GET_ODP_CUR = 5
322 struct mlx5_inbox_hdr {
328 struct mlx5_outbox_hdr {
334 struct mlx5_cmd_query_adapter_mbox_in {
335 struct mlx5_inbox_hdr hdr;
339 struct mlx5_cmd_query_adapter_mbox_out {
340 struct mlx5_outbox_hdr hdr;
344 __be16 vsd_vendor_id;
349 enum mlx5_odp_transport_cap_bits {
350 MLX5_ODP_SUPPORT_SEND = 1 << 31,
351 MLX5_ODP_SUPPORT_RECV = 1 << 30,
352 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
353 MLX5_ODP_SUPPORT_READ = 1 << 28,
356 struct mlx5_odp_caps {
362 } per_transport_caps;
363 char reserved2[0xe4];
366 struct mlx5_cmd_init_hca_mbox_in {
367 struct mlx5_inbox_hdr hdr;
373 struct mlx5_cmd_init_hca_mbox_out {
374 struct mlx5_outbox_hdr hdr;
378 struct mlx5_cmd_teardown_hca_mbox_in {
379 struct mlx5_inbox_hdr hdr;
385 struct mlx5_cmd_teardown_hca_mbox_out {
386 struct mlx5_outbox_hdr hdr;
390 struct mlx5_cmd_layout {
406 struct health_buffer {
407 __be32 assert_var[5];
409 __be32 assert_exit_ptr;
410 __be32 assert_callra;
420 struct mlx5_init_seg {
422 __be32 cmdif_rev_fw_sub;
425 __be32 cmdq_addr_l_sz;
428 struct health_buffer health;
430 __be32 health_counter;
433 __be32 ieee1588_clk_type;
437 struct mlx5_eqe_comp {
442 struct mlx5_eqe_qp_srq {
447 struct mlx5_eqe_cq_err {
453 struct mlx5_eqe_port_state {
458 struct mlx5_eqe_gpio {
463 struct mlx5_eqe_congestion {
469 struct mlx5_eqe_stall_vl {
474 struct mlx5_eqe_cmd {
479 struct mlx5_eqe_page_req {
486 struct mlx5_eqe_page_fault {
487 __be32 bytes_committed;
493 __be16 packet_length;
499 __be16 packet_length;
509 struct mlx5_eqe_cmd cmd;
510 struct mlx5_eqe_comp comp;
511 struct mlx5_eqe_qp_srq qp_srq;
512 struct mlx5_eqe_cq_err cq_err;
513 struct mlx5_eqe_port_state port;
514 struct mlx5_eqe_gpio gpio;
515 struct mlx5_eqe_congestion cong;
516 struct mlx5_eqe_stall_vl stall_vl;
517 struct mlx5_eqe_page_req req_pages;
518 struct mlx5_eqe_page_fault page_fault;
533 struct mlx5_cmd_prot_block {
534 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
544 struct mlx5_err_cqe {
550 __be32 s_wqe_opcode_qpn;
564 __be32 imm_inval_pkey;
574 struct mlx5_sig_err_cqe {
576 __be32 expected_trans_sig;
577 __be32 actual_trans_sig;
578 __be32 expected_reftag;
579 __be32 actual_reftag;
591 struct mlx5_wqe_srq_next_seg {
593 __be16 next_wqe_index;
604 union mlx5_ext_cqe inl_grh;
605 struct mlx5_cqe64 cqe64;
608 struct mlx5_srq_ctx {
623 struct mlx5_create_srq_mbox_in {
624 struct mlx5_inbox_hdr hdr;
627 struct mlx5_srq_ctx ctx;
632 struct mlx5_create_srq_mbox_out {
633 struct mlx5_outbox_hdr hdr;
638 struct mlx5_destroy_srq_mbox_in {
639 struct mlx5_inbox_hdr hdr;
644 struct mlx5_destroy_srq_mbox_out {
645 struct mlx5_outbox_hdr hdr;
649 struct mlx5_query_srq_mbox_in {
650 struct mlx5_inbox_hdr hdr;
655 struct mlx5_query_srq_mbox_out {
656 struct mlx5_outbox_hdr hdr;
658 struct mlx5_srq_ctx ctx;
663 struct mlx5_arm_srq_mbox_in {
664 struct mlx5_inbox_hdr hdr;
670 struct mlx5_arm_srq_mbox_out {
671 struct mlx5_outbox_hdr hdr;
675 struct mlx5_cq_context {
682 __be32 log_sz_usr_page;
689 __be32 last_notified_index;
690 __be32 solicit_producer_index;
691 __be32 consumer_counter;
692 __be32 producer_counter;
694 __be64 db_record_addr;
697 struct mlx5_create_cq_mbox_in {
698 struct mlx5_inbox_hdr hdr;
701 struct mlx5_cq_context ctx;
706 struct mlx5_create_cq_mbox_out {
707 struct mlx5_outbox_hdr hdr;
712 struct mlx5_destroy_cq_mbox_in {
713 struct mlx5_inbox_hdr hdr;
718 struct mlx5_destroy_cq_mbox_out {
719 struct mlx5_outbox_hdr hdr;
723 struct mlx5_query_cq_mbox_in {
724 struct mlx5_inbox_hdr hdr;
729 struct mlx5_query_cq_mbox_out {
730 struct mlx5_outbox_hdr hdr;
732 struct mlx5_cq_context ctx;
737 struct mlx5_modify_cq_mbox_in {
738 struct mlx5_inbox_hdr hdr;
741 struct mlx5_cq_context ctx;
746 struct mlx5_modify_cq_mbox_out {
747 struct mlx5_outbox_hdr hdr;
751 struct mlx5_enable_hca_mbox_in {
752 struct mlx5_inbox_hdr hdr;
756 struct mlx5_enable_hca_mbox_out {
757 struct mlx5_outbox_hdr hdr;
761 struct mlx5_disable_hca_mbox_in {
762 struct mlx5_inbox_hdr hdr;
766 struct mlx5_disable_hca_mbox_out {
767 struct mlx5_outbox_hdr hdr;
771 struct mlx5_eq_context {
777 __be32 log_sz_usr_page;
782 __be32 consumer_counter;
783 __be32 produser_counter;
787 struct mlx5_create_eq_mbox_in {
788 struct mlx5_inbox_hdr hdr;
792 struct mlx5_eq_context ctx;
799 struct mlx5_create_eq_mbox_out {
800 struct mlx5_outbox_hdr hdr;
806 struct mlx5_destroy_eq_mbox_in {
807 struct mlx5_inbox_hdr hdr;
813 struct mlx5_destroy_eq_mbox_out {
814 struct mlx5_outbox_hdr hdr;
818 struct mlx5_map_eq_mbox_in {
819 struct mlx5_inbox_hdr hdr;
827 struct mlx5_map_eq_mbox_out {
828 struct mlx5_outbox_hdr hdr;
832 struct mlx5_query_eq_mbox_in {
833 struct mlx5_inbox_hdr hdr;
839 struct mlx5_query_eq_mbox_out {
840 struct mlx5_outbox_hdr hdr;
842 struct mlx5_eq_context ctx;
846 MLX5_MKEY_STATUS_FREE = 1 << 6,
849 struct mlx5_mkey_seg {
850 /* This is a two bit field occupying bits 31-30.
851 * bit 31 is always 0,
852 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
863 __be32 bsfs_octo_size;
871 struct mlx5_query_special_ctxs_mbox_in {
872 struct mlx5_inbox_hdr hdr;
876 struct mlx5_query_special_ctxs_mbox_out {
877 struct mlx5_outbox_hdr hdr;
878 __be32 dump_fill_mkey;
879 __be32 reserved_lkey;
882 struct mlx5_create_mkey_mbox_in {
883 struct mlx5_inbox_hdr hdr;
884 __be32 input_mkey_index;
886 struct mlx5_mkey_seg seg;
888 __be32 xlat_oct_act_size;
894 struct mlx5_create_mkey_mbox_out {
895 struct mlx5_outbox_hdr hdr;
900 struct mlx5_destroy_mkey_mbox_in {
901 struct mlx5_inbox_hdr hdr;
906 struct mlx5_destroy_mkey_mbox_out {
907 struct mlx5_outbox_hdr hdr;
911 struct mlx5_query_mkey_mbox_in {
912 struct mlx5_inbox_hdr hdr;
916 struct mlx5_query_mkey_mbox_out {
917 struct mlx5_outbox_hdr hdr;
921 struct mlx5_modify_mkey_mbox_in {
922 struct mlx5_inbox_hdr hdr;
927 struct mlx5_modify_mkey_mbox_out {
928 struct mlx5_outbox_hdr hdr;
932 struct mlx5_dump_mkey_mbox_in {
933 struct mlx5_inbox_hdr hdr;
936 struct mlx5_dump_mkey_mbox_out {
937 struct mlx5_outbox_hdr hdr;
941 struct mlx5_mad_ifc_mbox_in {
942 struct mlx5_inbox_hdr hdr;
950 struct mlx5_mad_ifc_mbox_out {
951 struct mlx5_outbox_hdr hdr;
956 struct mlx5_access_reg_mbox_in {
957 struct mlx5_inbox_hdr hdr;
964 struct mlx5_access_reg_mbox_out {
965 struct mlx5_outbox_hdr hdr;
970 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
973 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
976 struct mlx5_allocate_psv_in {
977 struct mlx5_inbox_hdr hdr;
982 struct mlx5_allocate_psv_out {
983 struct mlx5_outbox_hdr hdr;
988 struct mlx5_destroy_psv_in {
989 struct mlx5_inbox_hdr hdr;
994 struct mlx5_destroy_psv_out {
995 struct mlx5_outbox_hdr hdr;
999 #endif /* MLX5_DEVICE_H */