include/linux/mlx5/device.h

   1 /*
   2  * Copyright (c) 2013, Mellanox Technologies inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX5_DEVICE_H
  34 #define MLX5_DEVICE_H
  35
  36 #include <linux/types.h>
  37 #include <rdma/ib_verbs.h>
  38
  39 #if defined(__LITTLE_ENDIAN)
  40 #define MLX5_SET_HOST_ENDIANNESS        0
  41 #elif defined(__BIG_ENDIAN)
  42 #define MLX5_SET_HOST_ENDIANNESS        0x80
  43 #else
  44 #error Host endianness not defined
  45 #endif
  46
  47 /* helper macros */
  48 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
  49 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
  50 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
  51 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
  52 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
  53 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
  54 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
  55 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
  56 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
  57
  58 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
  59 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
  60 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
  61 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
  62 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
  63
  64 /* insert a value to a struct */
  65 #define MLX5_SET(typ, p, fld, v) do { \
  66         BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
  67         *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
  68         cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
  69                      (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
  70                      << __mlx5_dw_bit_off(typ, fld))); \
  71 } while (0)
  72
  73 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
  74 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
  75 __mlx5_mask(typ, fld))
  76
  77 #define MLX5_GET_PR(typ, p, fld) ({ \
  78         u32 ___t = MLX5_GET(typ, p, fld); \
  79         pr_debug(#fld " = 0x%x\n", ___t); \
  80         ___t; \
  81 })
  82
  83 #define MLX5_SET64(typ, p, fld, v) do { \
  84         BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
  85         BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
  86         *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
  87 } while (0)
  88
  89 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
  90
  91 enum {
  92         MLX5_MAX_COMMANDS               = 32,
  93         MLX5_CMD_DATA_BLOCK_SIZE        = 512,
  94         MLX5_PCI_CMD_XPORT              = 7,
  95         MLX5_MKEY_BSF_OCTO_SIZE         = 4,
  96         MLX5_MAX_PSVS                   = 4,
  97 };
  98
  99 enum {
 100         MLX5_EXTENDED_UD_AV             = 0x80000000,
 101 };
 102
 103 enum {
 104         MLX5_CQ_STATE_ARMED             = 9,
 105         MLX5_CQ_STATE_ALWAYS_ARMED      = 0xb,
 106         MLX5_CQ_STATE_FIRED             = 0xa,
 107 };
 108
 109 enum {
 110         MLX5_STAT_RATE_OFFSET   = 5,
 111 };
 112
 113 enum {
 114         MLX5_INLINE_SEG = 0x80000000,
 115 };
 116
 117 enum {
 118         MLX5_MIN_PKEY_TABLE_SIZE = 128,
 119         MLX5_MAX_LOG_PKEY_TABLE  = 5,
 120 };
 121
 122 enum {
 123         MLX5_PERM_LOCAL_READ    = 1 << 2,
 124         MLX5_PERM_LOCAL_WRITE   = 1 << 3,
 125         MLX5_PERM_REMOTE_READ   = 1 << 4,
 126         MLX5_PERM_REMOTE_WRITE  = 1 << 5,
 127         MLX5_PERM_ATOMIC        = 1 << 6,
 128         MLX5_PERM_UMR_EN        = 1 << 7,
 129 };
 130
 131 enum {
 132         MLX5_PCIE_CTRL_SMALL_FENCE      = 1 << 0,
 133         MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
 134         MLX5_PCIE_CTRL_NO_SNOOP         = 1 << 3,
 135         MLX5_PCIE_CTRL_TLP_PROCE_EN     = 1 << 6,
 136         MLX5_PCIE_CTRL_TPH_MASK         = 3 << 4,
 137 };
 138
 139 enum {
 140         MLX5_ACCESS_MODE_PA     = 0,
 141         MLX5_ACCESS_MODE_MTT    = 1,
 142         MLX5_ACCESS_MODE_KLM    = 2
 143 };
 144
 145 enum {
 146         MLX5_MKEY_REMOTE_INVAL  = 1 << 24,
 147         MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
 148         MLX5_MKEY_BSF_EN        = 1 << 30,
 149         MLX5_MKEY_LEN64         = 1 << 31,
 150 };
 151
 152 enum {
 153         MLX5_EN_RD      = (u64)1,
 154         MLX5_EN_WR      = (u64)2
 155 };
 156
 157 enum {
 158         MLX5_BF_REGS_PER_PAGE           = 4,
 159         MLX5_MAX_UAR_PAGES              = 1 << 8,
 160         MLX5_NON_FP_BF_REGS_PER_PAGE    = 2,
 161         MLX5_MAX_UUARS  = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
 162 };
 163
 164 enum {
 165         MLX5_MKEY_MASK_LEN              = 1ull << 0,
 166         MLX5_MKEY_MASK_PAGE_SIZE        = 1ull << 1,
 167         MLX5_MKEY_MASK_START_ADDR       = 1ull << 6,
 168         MLX5_MKEY_MASK_PD               = 1ull << 7,
 169         MLX5_MKEY_MASK_EN_RINVAL        = 1ull << 8,
 170         MLX5_MKEY_MASK_EN_SIGERR        = 1ull << 9,
 171         MLX5_MKEY_MASK_BSF_EN           = 1ull << 12,
 172         MLX5_MKEY_MASK_KEY              = 1ull << 13,
 173         MLX5_MKEY_MASK_QPN              = 1ull << 14,
 174         MLX5_MKEY_MASK_LR               = 1ull << 17,
 175         MLX5_MKEY_MASK_LW               = 1ull << 18,
 176         MLX5_MKEY_MASK_RR               = 1ull << 19,
 177         MLX5_MKEY_MASK_RW               = 1ull << 20,
 178         MLX5_MKEY_MASK_A                = 1ull << 21,
 179         MLX5_MKEY_MASK_SMALL_FENCE      = 1ull << 23,
 180         MLX5_MKEY_MASK_FREE             = 1ull << 29,
 181 };
 182
 183 enum {
 184         MLX5_UMR_TRANSLATION_OFFSET_EN  = (1 << 4),
 185
 186         MLX5_UMR_CHECK_NOT_FREE         = (1 << 5),
 187         MLX5_UMR_CHECK_FREE             = (2 << 5),
 188
 189         MLX5_UMR_INLINE                 = (1 << 7),
 190 };
 191
 192 enum mlx5_event {
 193         MLX5_EVENT_TYPE_COMP               = 0x0,
 194
 195         MLX5_EVENT_TYPE_PATH_MIG           = 0x01,
 196         MLX5_EVENT_TYPE_COMM_EST           = 0x02,
 197         MLX5_EVENT_TYPE_SQ_DRAINED         = 0x03,
 198         MLX5_EVENT_TYPE_SRQ_LAST_WQE       = 0x13,
 199         MLX5_EVENT_TYPE_SRQ_RQ_LIMIT       = 0x14,
 200
 201         MLX5_EVENT_TYPE_CQ_ERROR           = 0x04,
 202         MLX5_EVENT_TYPE_WQ_CATAS_ERROR     = 0x05,
 203         MLX5_EVENT_TYPE_PATH_MIG_FAILED    = 0x07,
 204         MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
 205         MLX5_EVENT_TYPE_WQ_ACCESS_ERROR    = 0x11,
 206         MLX5_EVENT_TYPE_SRQ_CATAS_ERROR    = 0x12,
 207
 208         MLX5_EVENT_TYPE_INTERNAL_ERROR     = 0x08,
 209         MLX5_EVENT_TYPE_PORT_CHANGE        = 0x09,
 210         MLX5_EVENT_TYPE_GPIO_EVENT         = 0x15,
 211         MLX5_EVENT_TYPE_REMOTE_CONFIG      = 0x19,
 212
 213         MLX5_EVENT_TYPE_DB_BF_CONGESTION   = 0x1a,
 214         MLX5_EVENT_TYPE_STALL_EVENT        = 0x1b,
 215
 216         MLX5_EVENT_TYPE_CMD                = 0x0a,
 217         MLX5_EVENT_TYPE_PAGE_REQUEST       = 0xb,
 218 };
 219
 220 enum {
 221         MLX5_PORT_CHANGE_SUBTYPE_DOWN           = 1,
 222         MLX5_PORT_CHANGE_SUBTYPE_ACTIVE         = 4,
 223         MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED    = 5,
 224         MLX5_PORT_CHANGE_SUBTYPE_LID            = 6,
 225         MLX5_PORT_CHANGE_SUBTYPE_PKEY           = 7,
 226         MLX5_PORT_CHANGE_SUBTYPE_GUID           = 8,
 227         MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG   = 9,
 228 };
 229
 230 enum {
 231         MLX5_DEV_CAP_FLAG_XRC           = 1LL <<  3,
 232         MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL <<  8,
 233         MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL <<  9,
 234         MLX5_DEV_CAP_FLAG_APM           = 1LL << 17,
 235         MLX5_DEV_CAP_FLAG_ATOMIC        = 1LL << 18,
 236         MLX5_DEV_CAP_FLAG_BLOCK_MCAST   = 1LL << 23,
 237         MLX5_DEV_CAP_FLAG_CQ_MODER      = 1LL << 29,
 238         MLX5_DEV_CAP_FLAG_RESIZE_CQ     = 1LL << 30,
 239         MLX5_DEV_CAP_FLAG_DCT           = 1LL << 37,
 240         MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
 241         MLX5_DEV_CAP_FLAG_CMDIF_CSUM    = 3LL << 46,
 242 };
 243
 244 enum {
 245         MLX5_OPCODE_NOP                 = 0x00,
 246         MLX5_OPCODE_SEND_INVAL          = 0x01,
 247         MLX5_OPCODE_RDMA_WRITE          = 0x08,
 248         MLX5_OPCODE_RDMA_WRITE_IMM      = 0x09,
 249         MLX5_OPCODE_SEND                = 0x0a,
 250         MLX5_OPCODE_SEND_IMM            = 0x0b,
 251         MLX5_OPCODE_RDMA_READ           = 0x10,
 252         MLX5_OPCODE_ATOMIC_CS           = 0x11,
 253         MLX5_OPCODE_ATOMIC_FA           = 0x12,
 254         MLX5_OPCODE_ATOMIC_MASKED_CS    = 0x14,
 255         MLX5_OPCODE_ATOMIC_MASKED_FA    = 0x15,
 256         MLX5_OPCODE_BIND_MW             = 0x18,
 257         MLX5_OPCODE_CONFIG_CMD          = 0x1f,
 258
 259         MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
 260         MLX5_RECV_OPCODE_SEND           = 0x01,
 261         MLX5_RECV_OPCODE_SEND_IMM       = 0x02,
 262         MLX5_RECV_OPCODE_SEND_INVAL     = 0x03,
 263
 264         MLX5_CQE_OPCODE_ERROR           = 0x1e,
 265         MLX5_CQE_OPCODE_RESIZE          = 0x16,
 266
 267         MLX5_OPCODE_SET_PSV             = 0x20,
 268         MLX5_OPCODE_GET_PSV             = 0x21,
 269         MLX5_OPCODE_CHECK_PSV           = 0x22,
 270         MLX5_OPCODE_RGET_PSV            = 0x26,
 271         MLX5_OPCODE_RCHECK_PSV          = 0x27,
 272
 273         MLX5_OPCODE_UMR                 = 0x25,
 274
 275 };
 276
 277 enum {
 278         MLX5_SET_PORT_RESET_QKEY        = 0,
 279         MLX5_SET_PORT_GUID0             = 16,
 280         MLX5_SET_PORT_NODE_GUID         = 17,
 281         MLX5_SET_PORT_SYS_GUID          = 18,
 282         MLX5_SET_PORT_GID_TABLE         = 19,
 283         MLX5_SET_PORT_PKEY_TABLE        = 20,
 284 };
 285
 286 enum {
 287         MLX5_MAX_PAGE_SHIFT             = 31
 288 };
 289
 290 enum {
 291         MLX5_ADAPTER_PAGE_SHIFT         = 12,
 292         MLX5_ADAPTER_PAGE_SIZE          = 1 << MLX5_ADAPTER_PAGE_SHIFT,
 293 };
 294
 295 enum {
 296         MLX5_CAP_OFF_CMDIF_CSUM         = 46,
 297 };
 298
 299 enum {
 300         HCA_CAP_OPMOD_GET_MAX   = 0,
 301         HCA_CAP_OPMOD_GET_CUR   = 1,
 302 };
 303
 304 struct mlx5_inbox_hdr {
 305         __be16          opcode;
 306         u8              rsvd[4];
 307         __be16          opmod;
 308 };
 309
 310 struct mlx5_outbox_hdr {
 311         u8              status;
 312         u8              rsvd[3];
 313         __be32          syndrome;
 314 };
 315
 316 struct mlx5_cmd_query_adapter_mbox_in {
 317         struct mlx5_inbox_hdr   hdr;
 318         u8                      rsvd[8];
 319 };
 320
 321 struct mlx5_cmd_query_adapter_mbox_out {
 322         struct mlx5_outbox_hdr  hdr;
 323         u8                      rsvd0[24];
 324         u8                      intapin;
 325         u8                      rsvd1[13];
 326         __be16                  vsd_vendor_id;
 327         u8                      vsd[208];
 328         u8                      vsd_psid[16];
 329 };
 330
 331 struct mlx5_cmd_init_hca_mbox_in {
 332         struct mlx5_inbox_hdr   hdr;
 333         u8                      rsvd0[2];
 334         __be16                  profile;
 335         u8                      rsvd1[4];
 336 };
 337
 338 struct mlx5_cmd_init_hca_mbox_out {
 339         struct mlx5_outbox_hdr  hdr;
 340         u8                      rsvd[8];
 341 };
 342
 343 struct mlx5_cmd_teardown_hca_mbox_in {
 344         struct mlx5_inbox_hdr   hdr;
 345         u8                      rsvd0[2];
 346         __be16                  profile;
 347         u8                      rsvd1[4];
 348 };
 349
 350 struct mlx5_cmd_teardown_hca_mbox_out {
 351         struct mlx5_outbox_hdr  hdr;
 352         u8                      rsvd[8];
 353 };
 354
 355 struct mlx5_cmd_layout {
 356         u8              type;
 357         u8              rsvd0[3];
 358         __be32          inlen;
 359         __be64          in_ptr;
 360         __be32          in[4];
 361         __be32          out[4];
 362         __be64          out_ptr;
 363         __be32          outlen;
 364         u8              token;
 365         u8              sig;
 366         u8              rsvd1;
 367         u8              status_own;
 368 };
 369
 370
 371 struct health_buffer {
 372         __be32          assert_var[5];
 373         __be32          rsvd0[3];
 374         __be32          assert_exit_ptr;
 375         __be32          assert_callra;
 376         __be32          rsvd1[2];
 377         __be32          fw_ver;
 378         __be32          hw_id;
 379         __be32          rsvd2;
 380         u8              irisc_index;
 381         u8              synd;
 382         __be16          ext_sync;
 383 };
 384
 385 struct mlx5_init_seg {
 386         __be32                  fw_rev;
 387         __be32                  cmdif_rev_fw_sub;
 388         __be32                  rsvd0[2];
 389         __be32                  cmdq_addr_h;
 390         __be32                  cmdq_addr_l_sz;
 391         __be32                  cmd_dbell;
 392         __be32                  rsvd1[121];
 393         struct health_buffer    health;
 394         __be32                  rsvd2[884];
 395         __be32                  health_counter;
 396         __be32                  rsvd3[1019];
 397         __be64                  ieee1588_clk;
 398         __be32                  ieee1588_clk_type;
 399         __be32                  clr_intx;
 400 };
 401
 402 struct mlx5_eqe_comp {
 403         __be32  reserved[6];
 404         __be32  cqn;
 405 };
 406
 407 struct mlx5_eqe_qp_srq {
 408         __be32  reserved[6];
 409         __be32  qp_srq_n;
 410 };
 411
 412 struct mlx5_eqe_cq_err {
 413         __be32  cqn;
 414         u8      reserved1[7];
 415         u8      syndrome;
 416 };
 417
 418 struct mlx5_eqe_port_state {
 419         u8      reserved0[8];
 420         u8      port;
 421 };
 422
 423 struct mlx5_eqe_gpio {
 424         __be32  reserved0[2];
 425         __be64  gpio_event;
 426 };
 427
 428 struct mlx5_eqe_congestion {
 429         u8      type;
 430         u8      rsvd0;
 431         u8      congestion_level;
 432 };
 433
 434 struct mlx5_eqe_stall_vl {
 435         u8      rsvd0[3];
 436         u8      port_vl;
 437 };
 438
 439 struct mlx5_eqe_cmd {
 440         __be32  vector;
 441         __be32  rsvd[6];
 442 };
 443
 444 struct mlx5_eqe_page_req {
 445         u8              rsvd0[2];
 446         __be16          func_id;
 447         __be32          num_pages;
 448         __be32          rsvd1[5];
 449 };
 450
 451 union ev_data {
 452         __be32                          raw[7];
 453         struct mlx5_eqe_cmd             cmd;
 454         struct mlx5_eqe_comp            comp;
 455         struct mlx5_eqe_qp_srq          qp_srq;
 456         struct mlx5_eqe_cq_err          cq_err;
 457         struct mlx5_eqe_port_state      port;
 458         struct mlx5_eqe_gpio            gpio;
 459         struct mlx5_eqe_congestion      cong;
 460         struct mlx5_eqe_stall_vl        stall_vl;
 461         struct mlx5_eqe_page_req        req_pages;
 462 } __packed;
 463
 464 struct mlx5_eqe {
 465         u8              rsvd0;
 466         u8              type;
 467         u8              rsvd1;
 468         u8              sub_type;
 469         __be32          rsvd2[7];
 470         union ev_data   data;
 471         __be16          rsvd3;
 472         u8              signature;
 473         u8              owner;
 474 } __packed;
 475
 476 struct mlx5_cmd_prot_block {
 477         u8              data[MLX5_CMD_DATA_BLOCK_SIZE];
 478         u8              rsvd0[48];
 479         __be64          next;
 480         __be32          block_num;
 481         u8              rsvd1;
 482         u8              token;
 483         u8              ctrl_sig;
 484         u8              sig;
 485 };
 486
 487 struct mlx5_err_cqe {
 488         u8      rsvd0[32];
 489         __be32  srqn;
 490         u8      rsvd1[18];
 491         u8      vendor_err_synd;
 492         u8      syndrome;
 493         __be32  s_wqe_opcode_qpn;
 494         __be16  wqe_counter;
 495         u8      signature;
 496         u8      op_own;
 497 };
 498
 499 struct mlx5_cqe64 {
 500         u8              rsvd0[17];
 501         u8              ml_path;
 502         u8              rsvd20[4];
 503         __be16          slid;
 504         __be32          flags_rqpn;
 505         u8              rsvd28[4];
 506         __be32          srqn;
 507         __be32          imm_inval_pkey;
 508         u8              rsvd40[4];
 509         __be32          byte_cnt;
 510         __be64          timestamp;
 511         __be32          sop_drop_qpn;
 512         __be16          wqe_counter;
 513         u8              signature;
 514         u8              op_own;
 515 };
 516
 517 struct mlx5_sig_err_cqe {
 518         u8              rsvd0[16];
 519         __be32          expected_trans_sig;
 520         __be32          actual_trans_sig;
 521         __be32          expected_reftag;
 522         __be32          actual_reftag;
 523         __be16          syndrome;
 524         u8              rsvd22[2];
 525         __be32          mkey;
 526         __be64          err_offset;
 527         u8              rsvd30[8];
 528         __be32          qpn;
 529         u8              rsvd38[2];
 530         u8              signature;
 531         u8              op_own;
 532 };
 533
 534 struct mlx5_wqe_srq_next_seg {
 535         u8                      rsvd0[2];
 536         __be16                  next_wqe_index;
 537         u8                      signature;
 538         u8                      rsvd1[11];
 539 };
 540
 541 union mlx5_ext_cqe {
 542         struct ib_grh   grh;
 543         u8              inl[64];
 544 };
 545
 546 struct mlx5_cqe128 {
 547         union mlx5_ext_cqe      inl_grh;
 548         struct mlx5_cqe64       cqe64;
 549 };
 550
 551 struct mlx5_srq_ctx {
 552         u8                      state_log_sz;
 553         u8                      rsvd0[3];
 554         __be32                  flags_xrcd;
 555         __be32                  pgoff_cqn;
 556         u8                      rsvd1[4];
 557         u8                      log_pg_sz;
 558         u8                      rsvd2[7];
 559         __be32                  pd;
 560         __be16                  lwm;
 561         __be16                  wqe_cnt;
 562         u8                      rsvd3[8];
 563         __be64                  db_record;
 564 };
 565
 566 struct mlx5_create_srq_mbox_in {
 567         struct mlx5_inbox_hdr   hdr;
 568         __be32                  input_srqn;
 569         u8                      rsvd0[4];
 570         struct mlx5_srq_ctx     ctx;
 571         u8                      rsvd1[208];
 572         __be64                  pas[0];
 573 };
 574
 575 struct mlx5_create_srq_mbox_out {
 576         struct mlx5_outbox_hdr  hdr;
 577         __be32                  srqn;
 578         u8                      rsvd[4];
 579 };
 580
 581 struct mlx5_destroy_srq_mbox_in {
 582         struct mlx5_inbox_hdr   hdr;
 583         __be32                  srqn;
 584         u8                      rsvd[4];
 585 };
 586
 587 struct mlx5_destroy_srq_mbox_out {
 588         struct mlx5_outbox_hdr  hdr;
 589         u8                      rsvd[8];
 590 };
 591
 592 struct mlx5_query_srq_mbox_in {
 593         struct mlx5_inbox_hdr   hdr;
 594         __be32                  srqn;
 595         u8                      rsvd0[4];
 596 };
 597
 598 struct mlx5_query_srq_mbox_out {
 599         struct mlx5_outbox_hdr  hdr;
 600         u8                      rsvd0[8];
 601         struct mlx5_srq_ctx     ctx;
 602         u8                      rsvd1[32];
 603         __be64                  pas[0];
 604 };
 605
 606 struct mlx5_arm_srq_mbox_in {
 607         struct mlx5_inbox_hdr   hdr;
 608         __be32                  srqn;
 609         __be16                  rsvd;
 610         __be16                  lwm;
 611 };
 612
 613 struct mlx5_arm_srq_mbox_out {
 614         struct mlx5_outbox_hdr  hdr;
 615         u8                      rsvd[8];
 616 };
 617
 618 struct mlx5_cq_context {
 619         u8                      status;
 620         u8                      cqe_sz_flags;
 621         u8                      st;
 622         u8                      rsvd3;
 623         u8                      rsvd4[6];
 624         __be16                  page_offset;
 625         __be32                  log_sz_usr_page;
 626         __be16                  cq_period;
 627         __be16                  cq_max_count;
 628         __be16                  rsvd20;
 629         __be16                  c_eqn;
 630         u8                      log_pg_sz;
 631         u8                      rsvd25[7];
 632         __be32                  last_notified_index;
 633         __be32                  solicit_producer_index;
 634         __be32                  consumer_counter;
 635         __be32                  producer_counter;
 636         u8                      rsvd48[8];
 637         __be64                  db_record_addr;
 638 };
 639
 640 struct mlx5_create_cq_mbox_in {
 641         struct mlx5_inbox_hdr   hdr;
 642         __be32                  input_cqn;
 643         u8                      rsvdx[4];
 644         struct mlx5_cq_context  ctx;
 645         u8                      rsvd6[192];
 646         __be64                  pas[0];
 647 };
 648
 649 struct mlx5_create_cq_mbox_out {
 650         struct mlx5_outbox_hdr  hdr;
 651         __be32                  cqn;
 652         u8                      rsvd0[4];
 653 };
 654
 655 struct mlx5_destroy_cq_mbox_in {
 656         struct mlx5_inbox_hdr   hdr;
 657         __be32                  cqn;
 658         u8                      rsvd0[4];
 659 };
 660
 661 struct mlx5_destroy_cq_mbox_out {
 662         struct mlx5_outbox_hdr  hdr;
 663         u8                      rsvd0[8];
 664 };
 665
 666 struct mlx5_query_cq_mbox_in {
 667         struct mlx5_inbox_hdr   hdr;
 668         __be32                  cqn;
 669         u8                      rsvd0[4];
 670 };
 671
 672 struct mlx5_query_cq_mbox_out {
 673         struct mlx5_outbox_hdr  hdr;
 674         u8                      rsvd0[8];
 675         struct mlx5_cq_context  ctx;
 676         u8                      rsvd6[16];
 677         __be64                  pas[0];
 678 };
 679
 680 struct mlx5_modify_cq_mbox_in {
 681         struct mlx5_inbox_hdr   hdr;
 682         __be32                  cqn;
 683         __be32                  field_select;
 684         struct mlx5_cq_context  ctx;
 685         u8                      rsvd[192];
 686         __be64                  pas[0];
 687 };
 688
 689 struct mlx5_modify_cq_mbox_out {
 690         struct mlx5_outbox_hdr  hdr;
 691         u8                      rsvd[8];
 692 };
 693
 694 struct mlx5_enable_hca_mbox_in {
 695         struct mlx5_inbox_hdr   hdr;
 696         u8                      rsvd[8];
 697 };
 698
 699 struct mlx5_enable_hca_mbox_out {
 700         struct mlx5_outbox_hdr  hdr;
 701         u8                      rsvd[8];
 702 };
 703
 704 struct mlx5_disable_hca_mbox_in {
 705         struct mlx5_inbox_hdr   hdr;
 706         u8                      rsvd[8];
 707 };
 708
 709 struct mlx5_disable_hca_mbox_out {
 710         struct mlx5_outbox_hdr  hdr;
 711         u8                      rsvd[8];
 712 };
 713
 714 struct mlx5_eq_context {
 715         u8                      status;
 716         u8                      ec_oi;
 717         u8                      st;
 718         u8                      rsvd2[7];
 719         __be16                  page_pffset;
 720         __be32                  log_sz_usr_page;
 721         u8                      rsvd3[7];
 722         u8                      intr;
 723         u8                      log_page_size;
 724         u8                      rsvd4[15];
 725         __be32                  consumer_counter;
 726         __be32                  produser_counter;
 727         u8                      rsvd5[16];
 728 };
 729
 730 struct mlx5_create_eq_mbox_in {
 731         struct mlx5_inbox_hdr   hdr;
 732         u8                      rsvd0[3];
 733         u8                      input_eqn;
 734         u8                      rsvd1[4];
 735         struct mlx5_eq_context  ctx;
 736         u8                      rsvd2[8];
 737         __be64                  events_mask;
 738         u8                      rsvd3[176];
 739         __be64                  pas[0];
 740 };
 741
 742 struct mlx5_create_eq_mbox_out {
 743         struct mlx5_outbox_hdr  hdr;
 744         u8                      rsvd0[3];
 745         u8                      eq_number;
 746         u8                      rsvd1[4];
 747 };
 748
 749 struct mlx5_destroy_eq_mbox_in {
 750         struct mlx5_inbox_hdr   hdr;
 751         u8                      rsvd0[3];
 752         u8                      eqn;
 753         u8                      rsvd1[4];
 754 };
 755
 756 struct mlx5_destroy_eq_mbox_out {
 757         struct mlx5_outbox_hdr  hdr;
 758         u8                      rsvd[8];
 759 };
 760
 761 struct mlx5_map_eq_mbox_in {
 762         struct mlx5_inbox_hdr   hdr;
 763         __be64                  mask;
 764         u8                      mu;
 765         u8                      rsvd0[2];
 766         u8                      eqn;
 767         u8                      rsvd1[24];
 768 };
 769
 770 struct mlx5_map_eq_mbox_out {
 771         struct mlx5_outbox_hdr  hdr;
 772         u8                      rsvd[8];
 773 };
 774
 775 struct mlx5_query_eq_mbox_in {
 776         struct mlx5_inbox_hdr   hdr;
 777         u8                      rsvd0[3];
 778         u8                      eqn;
 779         u8                      rsvd1[4];
 780 };
 781
 782 struct mlx5_query_eq_mbox_out {
 783         struct mlx5_outbox_hdr  hdr;
 784         u8                      rsvd[8];
 785         struct mlx5_eq_context  ctx;
 786 };
 787
 788 enum {
 789         MLX5_MKEY_STATUS_FREE = 1 << 6,
 790 };
 791
 792 struct mlx5_mkey_seg {
 793         /* This is a two bit field occupying bits 31-30.
 794          * bit 31 is always 0,
 795          * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
 796          */
 797         u8              status;
 798         u8              pcie_control;
 799         u8              flags;
 800         u8              version;
 801         __be32          qpn_mkey7_0;
 802         u8              rsvd1[4];
 803         __be32          flags_pd;
 804         __be64          start_addr;
 805         __be64          len;
 806         __be32          bsfs_octo_size;
 807         u8              rsvd2[16];
 808         __be32          xlt_oct_size;
 809         u8              rsvd3[3];
 810         u8              log2_page_size;
 811         u8              rsvd4[4];
 812 };
 813
 814 struct mlx5_query_special_ctxs_mbox_in {
 815         struct mlx5_inbox_hdr   hdr;
 816         u8                      rsvd[8];
 817 };
 818
 819 struct mlx5_query_special_ctxs_mbox_out {
 820         struct mlx5_outbox_hdr  hdr;
 821         __be32                  dump_fill_mkey;
 822         __be32                  reserved_lkey;
 823 };
 824
 825 struct mlx5_create_mkey_mbox_in {
 826         struct mlx5_inbox_hdr   hdr;
 827         __be32                  input_mkey_index;
 828         u8                      rsvd0[4];
 829         struct mlx5_mkey_seg    seg;
 830         u8                      rsvd1[16];
 831         __be32                  xlat_oct_act_size;
 832         __be32                  rsvd2;
 833         u8                      rsvd3[168];
 834         __be64                  pas[0];
 835 };
 836
 837 struct mlx5_create_mkey_mbox_out {
 838         struct mlx5_outbox_hdr  hdr;
 839         __be32                  mkey;
 840         u8                      rsvd[4];
 841 };
 842
 843 struct mlx5_destroy_mkey_mbox_in {
 844         struct mlx5_inbox_hdr   hdr;
 845         __be32                  mkey;
 846         u8                      rsvd[4];
 847 };
 848
 849 struct mlx5_destroy_mkey_mbox_out {
 850         struct mlx5_outbox_hdr  hdr;
 851         u8                      rsvd[8];
 852 };
 853
 854 struct mlx5_query_mkey_mbox_in {
 855         struct mlx5_inbox_hdr   hdr;
 856         __be32                  mkey;
 857 };
 858
 859 struct mlx5_query_mkey_mbox_out {
 860         struct mlx5_outbox_hdr  hdr;
 861         __be64                  pas[0];
 862 };
 863
 864 struct mlx5_modify_mkey_mbox_in {
 865         struct mlx5_inbox_hdr   hdr;
 866         __be32                  mkey;
 867         __be64                  pas[0];
 868 };
 869
 870 struct mlx5_modify_mkey_mbox_out {
 871         struct mlx5_outbox_hdr  hdr;
 872         u8                      rsvd[8];
 873 };
 874
 875 struct mlx5_dump_mkey_mbox_in {
 876         struct mlx5_inbox_hdr   hdr;
 877 };
 878
 879 struct mlx5_dump_mkey_mbox_out {
 880         struct mlx5_outbox_hdr  hdr;
 881         __be32                  mkey;
 882 };
 883
 884 struct mlx5_mad_ifc_mbox_in {
 885         struct mlx5_inbox_hdr   hdr;
 886         __be16                  remote_lid;
 887         u8                      rsvd0;
 888         u8                      port;
 889         u8                      rsvd1[4];
 890         u8                      data[256];
 891 };
 892
 893 struct mlx5_mad_ifc_mbox_out {
 894         struct mlx5_outbox_hdr  hdr;
 895         u8                      rsvd[8];
 896         u8                      data[256];
 897 };
 898
 899 struct mlx5_access_reg_mbox_in {
 900         struct mlx5_inbox_hdr           hdr;
 901         u8                              rsvd0[2];
 902         __be16                          register_id;
 903         __be32                          arg;
 904         __be32                          data[0];
 905 };
 906
 907 struct mlx5_access_reg_mbox_out {
 908         struct mlx5_outbox_hdr          hdr;
 909         u8                              rsvd[8];
 910         __be32                          data[0];
 911 };
 912
 913 #define MLX5_ATTR_EXTENDED_PORT_INFO    cpu_to_be16(0xff90)
 914
 915 enum {
 916         MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO        = 1 <<  0
 917 };
 918
 919 struct mlx5_allocate_psv_in {
 920         struct mlx5_inbox_hdr   hdr;
 921         __be32                  npsv_pd;
 922         __be32                  rsvd_psv0;
 923 };
 924
 925 struct mlx5_allocate_psv_out {
 926         struct mlx5_outbox_hdr  hdr;
 927         u8                      rsvd[8];
 928         __be32                  psv_idx[4];
 929 };
 930
 931 struct mlx5_destroy_psv_in {
 932         struct mlx5_inbox_hdr   hdr;
 933         __be32                  psv_number;
 934         u8                      rsvd[4];
 935 };
 936
 937 struct mlx5_destroy_psv_out {
 938         struct mlx5_outbox_hdr  hdr;
 939         u8                      rsvd[8];
 940 };
 941
 942 #endif /* MLX5_DEVICE_H */