include/linux/mlx5/device.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX5_DEVICE_H
  34 #define MLX5_DEVICE_H
  35
  36 #include <linux/types.h>
  37 #include <rdma/ib_verbs.h>
  38 #include <linux/mlx5/mlx5_ifc.h>
  39 #include <linux/bitfield.h>
  40
  41 #if defined(__LITTLE_ENDIAN)
  42 #define MLX5_SET_HOST_ENDIANNESS        0
  43 #elif defined(__BIG_ENDIAN)
  44 #define MLX5_SET_HOST_ENDIANNESS        0x80
  45 #else
  46 #error Host endianness not defined
  47 #endif
  48
  49 /* helper macros */
  50 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
  51 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
  52 #define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld))
  53 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
  54 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
  55 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
  56 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
  57 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
  58 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
  59 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
  60 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
  61 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
  62 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
  63
  64 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
  65 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
  66 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
  67 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
  68 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
  69 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
  70 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
  71 #define MLX5_ADDR_OF(typ, p, fld) ((void *)((uint8_t *)(p) + MLX5_BYTE_OFF(typ, fld)))
  72
  73 /* insert a value to a struct */
  74 #define MLX5_SET(typ, p, fld, v) do { \
  75         u32 _v = v; \
  76         BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
  77         *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
  78         cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
  79                      (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \
  80                      << __mlx5_dw_bit_off(typ, fld))); \
  81 } while (0)
  82
  83 #define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \
  84         BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 32); \
  85         MLX5_SET(typ, p, fld[idx], v); \
  86 } while (0)
  87
  88 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
  89         BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
  90         *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
  91         cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
  92                      (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
  93                      << __mlx5_dw_bit_off(typ, fld))); \
  94 } while (0)
  95
  96 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
  97 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
  98 __mlx5_mask(typ, fld))
  99
 100 #define MLX5_GET_PR(typ, p, fld) ({ \
 101         u32 ___t = MLX5_GET(typ, p, fld); \
 102         pr_debug(#fld " = 0x%x\n", ___t); \
 103         ___t; \
 104 })
 105
 106 #define __MLX5_SET64(typ, p, fld, v) do { \
 107         BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
 108         *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
 109 } while (0)
 110
 111 #define MLX5_SET64(typ, p, fld, v) do { \
 112         BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
 113         __MLX5_SET64(typ, p, fld, v); \
 114 } while (0)
 115
 116 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
 117         BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
 118         __MLX5_SET64(typ, p, fld[idx], v); \
 119 } while (0)
 120
 121 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
 122
 123 #define MLX5_GET64_PR(typ, p, fld) ({ \
 124         u64 ___t = MLX5_GET64(typ, p, fld); \
 125         pr_debug(#fld " = 0x%llx\n", ___t); \
 126         ___t; \
 127 })
 128
 129 #define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
 130 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
 131 __mlx5_mask16(typ, fld))
 132
 133 #define MLX5_SET16(typ, p, fld, v) do { \
 134         u16 _v = v; \
 135         BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16);             \
 136         *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
 137         cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
 138                      (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
 139                      << __mlx5_16_bit_off(typ, fld))); \
 140 } while (0)
 141
 142 /* Big endian getters */
 143 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
 144         __mlx5_64_off(typ, fld)))
 145
 146 #define MLX5_GET_BE(type_t, typ, p, fld) ({                               \
 147                 type_t tmp;                                               \
 148                 switch (sizeof(tmp)) {                                    \
 149                 case sizeof(u8):                                          \
 150                         tmp = (__force type_t)MLX5_GET(typ, p, fld);      \
 151                         break;                                            \
 152                 case sizeof(u16):                                         \
 153                         tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
 154                         break;                                            \
 155                 case sizeof(u32):                                         \
 156                         tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
 157                         break;                                            \
 158                 case sizeof(u64):                                         \
 159                         tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
 160                         break;                                            \
 161                         }                                                 \
 162                 tmp;                                                      \
 163                 })
 164
 165 enum mlx5_inline_modes {
 166         MLX5_INLINE_MODE_NONE,
 167         MLX5_INLINE_MODE_L2,
 168         MLX5_INLINE_MODE_IP,
 169         MLX5_INLINE_MODE_TCP_UDP,
 170 };
 171
 172 enum {
 173         MLX5_MAX_COMMANDS               = 32,
 174         MLX5_CMD_DATA_BLOCK_SIZE        = 512,
 175         MLX5_PCI_CMD_XPORT              = 7,
 176         MLX5_MKEY_BSF_OCTO_SIZE         = 4,
 177         MLX5_MAX_PSVS                   = 4,
 178 };
 179
 180 enum {
 181         MLX5_EXTENDED_UD_AV             = 0x80000000,
 182 };
 183
 184 enum {
 185         MLX5_CQ_STATE_ARMED             = 9,
 186         MLX5_CQ_STATE_ALWAYS_ARMED      = 0xb,
 187         MLX5_CQ_STATE_FIRED             = 0xa,
 188 };
 189
 190 enum {
 191         MLX5_STAT_RATE_OFFSET   = 5,
 192 };
 193
 194 enum {
 195         MLX5_INLINE_SEG = 0x80000000,
 196 };
 197
 198 enum {
 199         MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
 200 };
 201
 202 enum {
 203         MLX5_MIN_PKEY_TABLE_SIZE = 128,
 204         MLX5_MAX_LOG_PKEY_TABLE  = 5,
 205 };
 206
 207 enum {
 208         MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
 209 };
 210
 211 enum {
 212         MLX5_PFAULT_SUBTYPE_WQE = 0,
 213         MLX5_PFAULT_SUBTYPE_RDMA = 1,
 214 };
 215
 216 enum wqe_page_fault_type {
 217         MLX5_WQE_PF_TYPE_RMP = 0,
 218         MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE = 1,
 219         MLX5_WQE_PF_TYPE_RESP = 2,
 220         MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC = 3,
 221 };
 222
 223 enum {
 224         MLX5_PERM_LOCAL_READ    = 1 << 2,
 225         MLX5_PERM_LOCAL_WRITE   = 1 << 3,
 226         MLX5_PERM_REMOTE_READ   = 1 << 4,
 227         MLX5_PERM_REMOTE_WRITE  = 1 << 5,
 228         MLX5_PERM_ATOMIC        = 1 << 6,
 229         MLX5_PERM_UMR_EN        = 1 << 7,
 230 };
 231
 232 enum {
 233         MLX5_PCIE_CTRL_SMALL_FENCE      = 1 << 0,
 234         MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
 235         MLX5_PCIE_CTRL_NO_SNOOP         = 1 << 3,
 236         MLX5_PCIE_CTRL_TLP_PROCE_EN     = 1 << 6,
 237         MLX5_PCIE_CTRL_TPH_MASK         = 3 << 4,
 238 };
 239
 240 enum {
 241         MLX5_EN_RD      = (u64)1,
 242         MLX5_EN_WR      = (u64)2
 243 };
 244
 245 enum {
 246         MLX5_ADAPTER_PAGE_SHIFT         = 12,
 247         MLX5_ADAPTER_PAGE_SIZE          = 1 << MLX5_ADAPTER_PAGE_SHIFT,
 248 };
 249
 250 enum {
 251         MLX5_BFREGS_PER_UAR             = 4,
 252         MLX5_MAX_UARS                   = 1 << 8,
 253         MLX5_NON_FP_BFREGS_PER_UAR      = 2,
 254         MLX5_FP_BFREGS_PER_UAR          = MLX5_BFREGS_PER_UAR -
 255                                           MLX5_NON_FP_BFREGS_PER_UAR,
 256         MLX5_MAX_BFREGS                 = MLX5_MAX_UARS *
 257                                           MLX5_NON_FP_BFREGS_PER_UAR,
 258         MLX5_UARS_IN_PAGE               = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
 259         MLX5_NON_FP_BFREGS_IN_PAGE      = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
 260         MLX5_MIN_DYN_BFREGS             = 512,
 261         MLX5_MAX_DYN_BFREGS             = 1024,
 262 };
 263
 264 enum {
 265         MLX5_MKEY_MASK_LEN              = 1ull << 0,
 266         MLX5_MKEY_MASK_PAGE_SIZE        = 1ull << 1,
 267         MLX5_MKEY_MASK_START_ADDR       = 1ull << 6,
 268         MLX5_MKEY_MASK_PD               = 1ull << 7,
 269         MLX5_MKEY_MASK_EN_RINVAL        = 1ull << 8,
 270         MLX5_MKEY_MASK_EN_SIGERR        = 1ull << 9,
 271         MLX5_MKEY_MASK_BSF_EN           = 1ull << 12,
 272         MLX5_MKEY_MASK_KEY              = 1ull << 13,
 273         MLX5_MKEY_MASK_QPN              = 1ull << 14,
 274         MLX5_MKEY_MASK_LR               = 1ull << 17,
 275         MLX5_MKEY_MASK_LW               = 1ull << 18,
 276         MLX5_MKEY_MASK_RR               = 1ull << 19,
 277         MLX5_MKEY_MASK_RW               = 1ull << 20,
 278         MLX5_MKEY_MASK_A                = 1ull << 21,
 279         MLX5_MKEY_MASK_SMALL_FENCE      = 1ull << 23,
 280         MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE   = 1ull << 25,
 281         MLX5_MKEY_MASK_FREE                     = 1ull << 29,
 282         MLX5_MKEY_MASK_RELAXED_ORDERING_READ    = 1ull << 47,
 283 };
 284
 285 enum {
 286         MLX5_UMR_TRANSLATION_OFFSET_EN  = (1 << 4),
 287
 288         MLX5_UMR_CHECK_NOT_FREE         = (1 << 5),
 289         MLX5_UMR_CHECK_FREE             = (2 << 5),
 290
 291         MLX5_UMR_INLINE                 = (1 << 7),
 292 };
 293
 294 #define MLX5_UMR_FLEX_ALIGNMENT 0x40
 295 #define MLX5_UMR_MTT_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_FLEX_ALIGNMENT / sizeof(struct mlx5_mtt))
 296 #define MLX5_UMR_KLM_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_FLEX_ALIGNMENT / sizeof(struct mlx5_klm))
 297
 298 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
 299
 300 enum {
 301         MLX5_EVENT_QUEUE_TYPE_QP = 0,
 302         MLX5_EVENT_QUEUE_TYPE_RQ = 1,
 303         MLX5_EVENT_QUEUE_TYPE_SQ = 2,
 304         MLX5_EVENT_QUEUE_TYPE_DCT = 6,
 305 };
 306
 307 /* mlx5 components can subscribe to any one of these events via
 308  * mlx5_eq_notifier_register API.
 309  */
 310 enum mlx5_event {
 311         /* Special value to subscribe to any event */
 312         MLX5_EVENT_TYPE_NOTIFY_ANY         = 0x0,
 313         /* HW events enum start: comp events are not subscribable */
 314         MLX5_EVENT_TYPE_COMP               = 0x0,
 315         /* HW Async events enum start: subscribable events */
 316         MLX5_EVENT_TYPE_PATH_MIG           = 0x01,
 317         MLX5_EVENT_TYPE_COMM_EST           = 0x02,
 318         MLX5_EVENT_TYPE_SQ_DRAINED         = 0x03,
 319         MLX5_EVENT_TYPE_SRQ_LAST_WQE       = 0x13,
 320         MLX5_EVENT_TYPE_SRQ_RQ_LIMIT       = 0x14,
 321
 322         MLX5_EVENT_TYPE_CQ_ERROR           = 0x04,
 323         MLX5_EVENT_TYPE_WQ_CATAS_ERROR     = 0x05,
 324         MLX5_EVENT_TYPE_PATH_MIG_FAILED    = 0x07,
 325         MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
 326         MLX5_EVENT_TYPE_WQ_ACCESS_ERROR    = 0x11,
 327         MLX5_EVENT_TYPE_SRQ_CATAS_ERROR    = 0x12,
 328         MLX5_EVENT_TYPE_OBJECT_CHANGE      = 0x27,
 329
 330         MLX5_EVENT_TYPE_INTERNAL_ERROR     = 0x08,
 331         MLX5_EVENT_TYPE_PORT_CHANGE        = 0x09,
 332         MLX5_EVENT_TYPE_GPIO_EVENT         = 0x15,
 333         MLX5_EVENT_TYPE_PORT_MODULE_EVENT  = 0x16,
 334         MLX5_EVENT_TYPE_TEMP_WARN_EVENT    = 0x17,
 335         MLX5_EVENT_TYPE_XRQ_ERROR          = 0x18,
 336         MLX5_EVENT_TYPE_REMOTE_CONFIG      = 0x19,
 337         MLX5_EVENT_TYPE_GENERAL_EVENT      = 0x22,
 338         MLX5_EVENT_TYPE_MONITOR_COUNTER    = 0x24,
 339         MLX5_EVENT_TYPE_PPS_EVENT          = 0x25,
 340
 341         MLX5_EVENT_TYPE_DB_BF_CONGESTION   = 0x1a,
 342         MLX5_EVENT_TYPE_STALL_EVENT        = 0x1b,
 343
 344         MLX5_EVENT_TYPE_CMD                = 0x0a,
 345         MLX5_EVENT_TYPE_PAGE_REQUEST       = 0xb,
 346
 347         MLX5_EVENT_TYPE_PAGE_FAULT         = 0xc,
 348         MLX5_EVENT_TYPE_NIC_VPORT_CHANGE   = 0xd,
 349
 350         MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 0xe,
 351         MLX5_EVENT_TYPE_VHCA_STATE_CHANGE = 0xf,
 352
 353         MLX5_EVENT_TYPE_DCT_DRAINED        = 0x1c,
 354         MLX5_EVENT_TYPE_DCT_KEY_VIOLATION  = 0x1d,
 355
 356         MLX5_EVENT_TYPE_FPGA_ERROR         = 0x20,
 357         MLX5_EVENT_TYPE_FPGA_QP_ERROR      = 0x21,
 358
 359         MLX5_EVENT_TYPE_DEVICE_TRACER      = 0x26,
 360
 361         MLX5_EVENT_TYPE_MAX                = 0x100,
 362 };
 363
 364 enum mlx5_driver_event {
 365         MLX5_DRIVER_EVENT_TYPE_TRAP = 0,
 366         MLX5_DRIVER_EVENT_UPLINK_NETDEV,
 367 };
 368
 369 enum {
 370         MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0x0,
 371         MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 0x1,
 372         MLX5_TRACER_SUBTYPE_STRINGS_DB_UPDATE = 0x2,
 373 };
 374
 375 enum {
 376         MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
 377         MLX5_GENERAL_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5,
 378         MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT = 0x7,
 379         MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT = 0x8,
 380 };
 381
 382 enum {
 383         MLX5_PORT_CHANGE_SUBTYPE_DOWN           = 1,
 384         MLX5_PORT_CHANGE_SUBTYPE_ACTIVE         = 4,
 385         MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED    = 5,
 386         MLX5_PORT_CHANGE_SUBTYPE_LID            = 6,
 387         MLX5_PORT_CHANGE_SUBTYPE_PKEY           = 7,
 388         MLX5_PORT_CHANGE_SUBTYPE_GUID           = 8,
 389         MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG   = 9,
 390 };
 391
 392 enum {
 393         MLX5_ROCE_VERSION_1             = 0,
 394         MLX5_ROCE_VERSION_2             = 2,
 395 };
 396
 397 enum {
 398         MLX5_ROCE_VERSION_1_CAP         = 1 << MLX5_ROCE_VERSION_1,
 399         MLX5_ROCE_VERSION_2_CAP         = 1 << MLX5_ROCE_VERSION_2,
 400 };
 401
 402 enum {
 403         MLX5_ROCE_L3_TYPE_IPV4          = 0,
 404         MLX5_ROCE_L3_TYPE_IPV6          = 1,
 405 };
 406
 407 enum {
 408         MLX5_ROCE_L3_TYPE_IPV4_CAP      = 1 << 1,
 409         MLX5_ROCE_L3_TYPE_IPV6_CAP      = 1 << 2,
 410 };
 411
 412 enum {
 413         MLX5_OPCODE_NOP                 = 0x00,
 414         MLX5_OPCODE_SEND_INVAL          = 0x01,
 415         MLX5_OPCODE_RDMA_WRITE          = 0x08,
 416         MLX5_OPCODE_RDMA_WRITE_IMM      = 0x09,
 417         MLX5_OPCODE_SEND                = 0x0a,
 418         MLX5_OPCODE_SEND_IMM            = 0x0b,
 419         MLX5_OPCODE_LSO                 = 0x0e,
 420         MLX5_OPCODE_RDMA_READ           = 0x10,
 421         MLX5_OPCODE_ATOMIC_CS           = 0x11,
 422         MLX5_OPCODE_ATOMIC_FA           = 0x12,
 423         MLX5_OPCODE_ATOMIC_MASKED_CS    = 0x14,
 424         MLX5_OPCODE_ATOMIC_MASKED_FA    = 0x15,
 425         MLX5_OPCODE_BIND_MW             = 0x18,
 426         MLX5_OPCODE_CONFIG_CMD          = 0x1f,
 427         MLX5_OPCODE_ENHANCED_MPSW       = 0x29,
 428
 429         MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
 430         MLX5_RECV_OPCODE_SEND           = 0x01,
 431         MLX5_RECV_OPCODE_SEND_IMM       = 0x02,
 432         MLX5_RECV_OPCODE_SEND_INVAL     = 0x03,
 433
 434         MLX5_CQE_OPCODE_ERROR           = 0x1e,
 435         MLX5_CQE_OPCODE_RESIZE          = 0x16,
 436
 437         MLX5_OPCODE_SET_PSV             = 0x20,
 438         MLX5_OPCODE_GET_PSV             = 0x21,
 439         MLX5_OPCODE_CHECK_PSV           = 0x22,
 440         MLX5_OPCODE_DUMP                = 0x23,
 441         MLX5_OPCODE_RGET_PSV            = 0x26,
 442         MLX5_OPCODE_RCHECK_PSV          = 0x27,
 443
 444         MLX5_OPCODE_UMR                 = 0x25,
 445
 446         MLX5_OPCODE_FLOW_TBL_ACCESS     = 0x2c,
 447
 448         MLX5_OPCODE_ACCESS_ASO          = 0x2d,
 449 };
 450
 451 enum {
 452         MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x1,
 453         MLX5_OPC_MOD_TLS_TIR_STATIC_PARAMS = 0x2,
 454 };
 455
 456 enum {
 457         MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x1,
 458         MLX5_OPC_MOD_TLS_TIR_PROGRESS_PARAMS = 0x2,
 459 };
 460
 461 struct mlx5_wqe_tls_static_params_seg {
 462         u8     ctx[MLX5_ST_SZ_BYTES(tls_static_params)];
 463 };
 464
 465 struct mlx5_wqe_tls_progress_params_seg {
 466         __be32 tis_tir_num;
 467         u8     ctx[MLX5_ST_SZ_BYTES(tls_progress_params)];
 468 };
 469
 470 enum {
 471         MLX5_SET_PORT_RESET_QKEY        = 0,
 472         MLX5_SET_PORT_GUID0             = 16,
 473         MLX5_SET_PORT_NODE_GUID         = 17,
 474         MLX5_SET_PORT_SYS_GUID          = 18,
 475         MLX5_SET_PORT_GID_TABLE         = 19,
 476         MLX5_SET_PORT_PKEY_TABLE        = 20,
 477 };
 478
 479 enum {
 480         MLX5_BW_NO_LIMIT   = 0,
 481         MLX5_100_MBPS_UNIT = 3,
 482         MLX5_GBPS_UNIT     = 4,
 483 };
 484
 485 enum {
 486         MLX5_MAX_PAGE_SHIFT             = 31
 487 };
 488
 489 enum {
 490         /*
 491          * Max wqe size for rdma read is 512 bytes, so this
 492          * limits our max_sge_rd as the wqe needs to fit:
 493          * - ctrl segment (16 bytes)
 494          * - rdma segment (16 bytes)
 495          * - scatter elements (16 bytes each)
 496          */
 497         MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
 498 };
 499
 500 enum mlx5_odp_transport_cap_bits {
 501         MLX5_ODP_SUPPORT_SEND    = 1 << 31,
 502         MLX5_ODP_SUPPORT_RECV    = 1 << 30,
 503         MLX5_ODP_SUPPORT_WRITE   = 1 << 29,
 504         MLX5_ODP_SUPPORT_READ    = 1 << 28,
 505 };
 506
 507 struct mlx5_odp_caps {
 508         char reserved[0x10];
 509         struct {
 510                 __be32                  rc_odp_caps;
 511                 __be32                  uc_odp_caps;
 512                 __be32                  ud_odp_caps;
 513         } per_transport_caps;
 514         char reserved2[0xe4];
 515 };
 516
 517 struct mlx5_cmd_layout {
 518         u8              type;
 519         u8              rsvd0[3];
 520         __be32          inlen;
 521         __be64          in_ptr;
 522         __be32          in[4];
 523         __be32          out[4];
 524         __be64          out_ptr;
 525         __be32          outlen;
 526         u8              token;
 527         u8              sig;
 528         u8              rsvd1;
 529         u8              status_own;
 530 };
 531
 532 enum mlx5_rfr_severity_bit_offsets {
 533         MLX5_RFR_BIT_OFFSET = 0x7,
 534 };
 535
 536 struct health_buffer {
 537         __be32          assert_var[6];
 538         __be32          rsvd0[2];
 539         __be32          assert_exit_ptr;
 540         __be32          assert_callra;
 541         __be32          rsvd1[1];
 542         __be32          time;
 543         __be32          fw_ver;
 544         __be32          hw_id;
 545         u8              rfr_severity;
 546         u8              rsvd2[3];
 547         u8              irisc_index;
 548         u8              synd;
 549         __be16          ext_synd;
 550 };
 551
 552 enum mlx5_initializing_bit_offsets {
 553         MLX5_FW_RESET_SUPPORTED_OFFSET = 30,
 554 };
 555
 556 enum mlx5_cmd_addr_l_sz_offset {
 557         MLX5_NIC_IFC_OFFSET = 8,
 558 };
 559
 560 struct mlx5_init_seg {
 561         __be32                  fw_rev;
 562         __be32                  cmdif_rev_fw_sub;
 563         __be32                  rsvd0[2];
 564         __be32                  cmdq_addr_h;
 565         __be32                  cmdq_addr_l_sz;
 566         __be32                  cmd_dbell;
 567         __be32                  rsvd1[120];
 568         __be32                  initializing;
 569         struct health_buffer    health;
 570         __be32                  rsvd2[878];
 571         __be32                  cmd_exec_to;
 572         __be32                  cmd_q_init_to;
 573         __be32                  internal_timer_h;
 574         __be32                  internal_timer_l;
 575         __be32                  rsvd3[2];
 576         __be32                  health_counter;
 577         __be32                  rsvd4[11];
 578         __be32                  real_time_h;
 579         __be32                  real_time_l;
 580         __be32                  rsvd5[1006];
 581         __be64                  ieee1588_clk;
 582         __be32                  ieee1588_clk_type;
 583         __be32                  clr_intx;
 584 };
 585
 586 struct mlx5_eqe_comp {
 587         __be32  reserved[6];
 588         __be32  cqn;
 589 };
 590
 591 struct mlx5_eqe_qp_srq {
 592         __be32  reserved1[5];
 593         u8      type;
 594         u8      reserved2[3];
 595         __be32  qp_srq_n;
 596 };
 597
 598 struct mlx5_eqe_cq_err {
 599         __be32  cqn;
 600         u8      reserved1[7];
 601         u8      syndrome;
 602 };
 603
 604 struct mlx5_eqe_xrq_err {
 605         __be32  reserved1[5];
 606         __be32  type_xrqn;
 607         __be32  reserved2;
 608 };
 609
 610 struct mlx5_eqe_port_state {
 611         u8      reserved0[8];
 612         u8      port;
 613 };
 614
 615 struct mlx5_eqe_gpio {
 616         __be32  reserved0[2];
 617         __be64  gpio_event;
 618 };
 619
 620 struct mlx5_eqe_congestion {
 621         u8      type;
 622         u8      rsvd0;
 623         u8      congestion_level;
 624 };
 625
 626 struct mlx5_eqe_stall_vl {
 627         u8      rsvd0[3];
 628         u8      port_vl;
 629 };
 630
 631 struct mlx5_eqe_cmd {
 632         __be32  vector;
 633         __be32  rsvd[6];
 634 };
 635
 636 struct mlx5_eqe_page_req {
 637         __be16          ec_function;
 638         __be16          func_id;
 639         __be32          num_pages;
 640         __be32          rsvd1[5];
 641 };
 642
 643 struct mlx5_eqe_page_fault {
 644         __be32 bytes_committed;
 645         union {
 646                 struct {
 647                         u16     reserved1;
 648                         __be16  wqe_index;
 649                         u16     reserved2;
 650                         __be16  packet_length;
 651                         __be32  token;
 652                         u8      reserved4[8];
 653                         __be32  pftype_wq;
 654                 } __packed wqe;
 655                 struct {
 656                         __be32  r_key;
 657                         u16     reserved1;
 658                         __be16  packet_length;
 659                         __be32  rdma_op_len;
 660                         __be64  rdma_va;
 661                         __be32  pftype_token;
 662                 } __packed rdma;
 663         } __packed;
 664 } __packed;
 665
 666 struct mlx5_eqe_vport_change {
 667         u8              rsvd0[2];
 668         __be16          vport_num;
 669         __be32          rsvd1[6];
 670 } __packed;
 671
 672 struct mlx5_eqe_port_module {
 673         u8        reserved_at_0[1];
 674         u8        module;
 675         u8        reserved_at_2[1];
 676         u8        module_status;
 677         u8        reserved_at_4[2];
 678         u8        error_type;
 679 } __packed;
 680
 681 struct mlx5_eqe_pps {
 682         u8              rsvd0[3];
 683         u8              pin;
 684         u8              rsvd1[4];
 685         union {
 686                 struct {
 687                         __be32          time_sec;
 688                         __be32          time_nsec;
 689                 };
 690                 struct {
 691                         __be64          time_stamp;
 692                 };
 693         };
 694         u8              rsvd2[12];
 695 } __packed;
 696
 697 struct mlx5_eqe_dct {
 698         __be32  reserved[6];
 699         __be32  dctn;
 700 };
 701
 702 struct mlx5_eqe_temp_warning {
 703         __be64 sensor_warning_msb;
 704         __be64 sensor_warning_lsb;
 705 } __packed;
 706
 707 struct mlx5_eqe_obj_change {
 708         u8      rsvd0[2];
 709         __be16  obj_type;
 710         __be32  obj_id;
 711 } __packed;
 712
 713 #define SYNC_RST_STATE_MASK    0xf
 714
 715 enum sync_rst_state_type {
 716         MLX5_SYNC_RST_STATE_RESET_REQUEST       = 0x0,
 717         MLX5_SYNC_RST_STATE_RESET_NOW           = 0x1,
 718         MLX5_SYNC_RST_STATE_RESET_ABORT         = 0x2,
 719 };
 720
 721 struct mlx5_eqe_sync_fw_update {
 722         u8 reserved_at_0[3];
 723         u8 sync_rst_state;
 724 };
 725
 726 struct mlx5_eqe_vhca_state {
 727         __be16 ec_function;
 728         __be16 function_id;
 729 } __packed;
 730
 731 union ev_data {
 732         __be32                          raw[7];
 733         struct mlx5_eqe_cmd             cmd;
 734         struct mlx5_eqe_comp            comp;
 735         struct mlx5_eqe_qp_srq          qp_srq;
 736         struct mlx5_eqe_cq_err          cq_err;
 737         struct mlx5_eqe_port_state      port;
 738         struct mlx5_eqe_gpio            gpio;
 739         struct mlx5_eqe_congestion      cong;
 740         struct mlx5_eqe_stall_vl        stall_vl;
 741         struct mlx5_eqe_page_req        req_pages;
 742         struct mlx5_eqe_page_fault      page_fault;
 743         struct mlx5_eqe_vport_change    vport_change;
 744         struct mlx5_eqe_port_module     port_module;
 745         struct mlx5_eqe_pps             pps;
 746         struct mlx5_eqe_dct             dct;
 747         struct mlx5_eqe_temp_warning    temp_warning;
 748         struct mlx5_eqe_xrq_err         xrq_err;
 749         struct mlx5_eqe_sync_fw_update  sync_fw_update;
 750         struct mlx5_eqe_vhca_state      vhca_state;
 751         struct mlx5_eqe_obj_change      obj_change;
 752 } __packed;
 753
 754 struct mlx5_eqe {
 755         u8              rsvd0;
 756         u8              type;
 757         u8              rsvd1;
 758         u8              sub_type;
 759         __be32          rsvd2[7];
 760         union ev_data   data;
 761         __be16          rsvd3;
 762         u8              signature;
 763         u8              owner;
 764 } __packed;
 765
 766 struct mlx5_cmd_prot_block {
 767         u8              data[MLX5_CMD_DATA_BLOCK_SIZE];
 768         u8              rsvd0[48];
 769         __be64          next;
 770         __be32          block_num;
 771         u8              rsvd1;
 772         u8              token;
 773         u8              ctrl_sig;
 774         u8              sig;
 775 };
 776
 777 enum {
 778         MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
 779 };
 780
 781 struct mlx5_err_cqe {
 782         u8      rsvd0[32];
 783         __be32  srqn;
 784         u8      rsvd1[18];
 785         u8      vendor_err_synd;
 786         u8      syndrome;
 787         __be32  s_wqe_opcode_qpn;
 788         __be16  wqe_counter;
 789         u8      signature;
 790         u8      op_own;
 791 };
 792
 793 struct mlx5_cqe64 {
 794         u8              tls_outer_l3_tunneled;
 795         u8              rsvd0;
 796         __be16          wqe_id;
 797         union {
 798                 struct {
 799                         u8      tcppsh_abort_dupack;
 800                         u8      min_ttl;
 801                         __be16  tcp_win;
 802                         __be32  ack_seq_num;
 803                 } lro;
 804                 struct {
 805                         u8      reserved0:1;
 806                         u8      match:1;
 807                         u8      flush:1;
 808                         u8      reserved3:5;
 809                         u8      header_size;
 810                         __be16  header_entry_index;
 811                         __be32  data_offset;
 812                 } shampo;
 813         };
 814         __be32          rss_hash_result;
 815         u8              rss_hash_type;
 816         u8              ml_path;
 817         u8              rsvd20[2];
 818         __be16          check_sum;
 819         __be16          slid;
 820         __be32          flags_rqpn;
 821         u8              hds_ip_ext;
 822         u8              l4_l3_hdr_type;
 823         __be16          vlan_info;
 824         __be32          srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
 825         union {
 826                 __be32 immediate;
 827                 __be32 inval_rkey;
 828                 __be32 pkey;
 829                 __be32 ft_metadata;
 830         };
 831         u8              rsvd40[4];
 832         __be32          byte_cnt;
 833         __be32          timestamp_h;
 834         __be32          timestamp_l;
 835         __be32          sop_drop_qpn;
 836         __be16          wqe_counter;
 837         union {
 838                 u8      signature;
 839                 u8      validity_iteration_count;
 840         };
 841         u8              op_own;
 842 };
 843
 844 struct mlx5_mini_cqe8 {
 845         union {
 846                 __be32 rx_hash_result;
 847                 struct {
 848                         __be16 checksum;
 849                         __be16 stridx;
 850                 };
 851                 struct {
 852                         __be16 wqe_counter;
 853                         u8  s_wqe_opcode;
 854                         u8  reserved;
 855                 } s_wqe_info;
 856         };
 857         __be32 byte_cnt;
 858 };
 859
 860 enum {
 861         MLX5_NO_INLINE_DATA,
 862         MLX5_INLINE_DATA32_SEG,
 863         MLX5_INLINE_DATA64_SEG,
 864         MLX5_COMPRESSED,
 865 };
 866
 867 enum {
 868         MLX5_CQE_FORMAT_CSUM = 0x1,
 869         MLX5_CQE_FORMAT_CSUM_STRIDX = 0x3,
 870 };
 871
 872 enum {
 873         MLX5_CQE_COMPRESS_LAYOUT_BASIC = 0,
 874         MLX5_CQE_COMPRESS_LAYOUT_ENHANCED = 1,
 875 };
 876
 877 #define MLX5_MINI_CQE_ARRAY_SIZE 8
 878
 879 static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
 880 {
 881         return (cqe->op_own >> 2) & 0x3;
 882 }
 883
 884 static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe)
 885 {
 886         return cqe->op_own >> 4;
 887 }
 888
 889 static inline u8 get_cqe_enhanced_num_mini_cqes(struct mlx5_cqe64 *cqe)
 890 {
 891         /* num_of_mini_cqes is zero based */
 892         return get_cqe_opcode(cqe) + 1;
 893 }
 894
 895 static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
 896 {
 897         return (cqe->lro.tcppsh_abort_dupack >> 6) & 1;
 898 }
 899
 900 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
 901 {
 902         return (cqe->l4_l3_hdr_type >> 4) & 0x7;
 903 }
 904
 905 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
 906 {
 907         return cqe->tls_outer_l3_tunneled & 0x1;
 908 }
 909
 910 static inline u8 get_cqe_tls_offload(struct mlx5_cqe64 *cqe)
 911 {
 912         return (cqe->tls_outer_l3_tunneled >> 3) & 0x3;
 913 }
 914
 915 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
 916 {
 917         return cqe->l4_l3_hdr_type & 0x1;
 918 }
 919
 920 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
 921 {
 922         u32 hi, lo;
 923
 924         hi = be32_to_cpu(cqe->timestamp_h);
 925         lo = be32_to_cpu(cqe->timestamp_l);
 926
 927         return (u64)lo | ((u64)hi << 32);
 928 }
 929
 930 static inline u16 get_cqe_flow_tag(struct mlx5_cqe64 *cqe)
 931 {
 932         return be32_to_cpu(cqe->sop_drop_qpn) & 0xFFF;
 933 }
 934
 935 #define MLX5_MPWQE_LOG_NUM_STRIDES_EXT_BASE     3
 936 #define MLX5_MPWQE_LOG_NUM_STRIDES_BASE         9
 937 #define MLX5_MPWQE_LOG_NUM_STRIDES_MAX          16
 938 #define MLX5_MPWQE_LOG_STRIDE_SZ_BASE           6
 939 #define MLX5_MPWQE_LOG_STRIDE_SZ_MAX            13
 940
 941 struct mpwrq_cqe_bc {
 942         __be16  filler_consumed_strides;
 943         __be16  byte_cnt;
 944 };
 945
 946 static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
 947 {
 948         struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
 949
 950         return be16_to_cpu(bc->byte_cnt);
 951 }
 952
 953 static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
 954 {
 955         return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
 956 }
 957
 958 static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
 959 {
 960         struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
 961
 962         return mpwrq_get_cqe_bc_consumed_strides(bc);
 963 }
 964
 965 static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
 966 {
 967         struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
 968
 969         return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
 970 }
 971
 972 static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
 973 {
 974         return be16_to_cpu(cqe->wqe_counter);
 975 }
 976
 977 enum {
 978         CQE_L4_HDR_TYPE_NONE                    = 0x0,
 979         CQE_L4_HDR_TYPE_TCP_NO_ACK              = 0x1,
 980         CQE_L4_HDR_TYPE_UDP                     = 0x2,
 981         CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA         = 0x3,
 982         CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA        = 0x4,
 983 };
 984
 985 enum {
 986         CQE_RSS_HTYPE_IP        = GENMASK(3, 2),
 987         /* cqe->rss_hash_type[3:2] - IP destination selected for hash
 988          * (00 = none,  01 = IPv4, 10 = IPv6, 11 = Reserved)
 989          */
 990         CQE_RSS_IP_NONE         = 0x0,
 991         CQE_RSS_IPV4            = 0x1,
 992         CQE_RSS_IPV6            = 0x2,
 993         CQE_RSS_RESERVED        = 0x3,
 994
 995         CQE_RSS_HTYPE_L4        = GENMASK(7, 6),
 996         /* cqe->rss_hash_type[7:6] - L4 destination selected for hash
 997          * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI
 998          */
 999         CQE_RSS_L4_NONE         = 0x0,
1000         CQE_RSS_L4_TCP          = 0x1,
1001         CQE_RSS_L4_UDP          = 0x2,
1002         CQE_RSS_L4_IPSEC        = 0x3,
1003 };
1004
1005 enum {
1006         MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH        = 0x0,
1007         MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6       = 0x1,
1008         MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4       = 0x2,
1009 };
1010
1011 enum {
1012         CQE_L2_OK       = 1 << 0,
1013         CQE_L3_OK       = 1 << 1,
1014         CQE_L4_OK       = 1 << 2,
1015 };
1016
1017 enum {
1018         CQE_TLS_OFFLOAD_NOT_DECRYPTED           = 0x0,
1019         CQE_TLS_OFFLOAD_DECRYPTED               = 0x1,
1020         CQE_TLS_OFFLOAD_RESYNC                  = 0x2,
1021         CQE_TLS_OFFLOAD_ERROR                   = 0x3,
1022 };
1023
1024 struct mlx5_sig_err_cqe {
1025         u8              rsvd0[16];
1026         __be32          expected_trans_sig;
1027         __be32          actual_trans_sig;
1028         __be32          expected_reftag;
1029         __be32          actual_reftag;
1030         __be16          syndrome;
1031         u8              rsvd22[2];
1032         __be32          mkey;
1033         __be64          err_offset;
1034         u8              rsvd30[8];
1035         __be32          qpn;
1036         u8              rsvd38[2];
1037         u8              signature;
1038         u8              op_own;
1039 };
1040
1041 struct mlx5_wqe_srq_next_seg {
1042         u8                      rsvd0[2];
1043         __be16                  next_wqe_index;
1044         u8                      signature;
1045         u8                      rsvd1[11];
1046 };
1047
1048 union mlx5_ext_cqe {
1049         struct ib_grh   grh;
1050         u8              inl[64];
1051 };
1052
1053 struct mlx5_cqe128 {
1054         union mlx5_ext_cqe      inl_grh;
1055         struct mlx5_cqe64       cqe64;
1056 };
1057
1058 enum {
1059         MLX5_MKEY_STATUS_FREE = 1 << 6,
1060 };
1061
1062 enum {
1063         MLX5_MKEY_REMOTE_INVAL  = 1 << 24,
1064         MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
1065         MLX5_MKEY_BSF_EN        = 1 << 30,
1066 };
1067
1068 struct mlx5_mkey_seg {
1069         /* This is a two bit field occupying bits 31-30.
1070          * bit 31 is always 0,
1071          * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have translation
1072          */
1073         u8              status;
1074         u8              pcie_control;
1075         u8              flags;
1076         u8              version;
1077         __be32          qpn_mkey7_0;
1078         u8              rsvd1[4];
1079         __be32          flags_pd;
1080         __be64          start_addr;
1081         __be64          len;
1082         __be32          bsfs_octo_size;
1083         u8              rsvd2[16];
1084         __be32          xlt_oct_size;
1085         u8              rsvd3[3];
1086         u8              log2_page_size;
1087         u8              rsvd4[4];
1088 };
1089
1090 #define MLX5_ATTR_EXTENDED_PORT_INFO    cpu_to_be16(0xff90)
1091
1092 enum {
1093         MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO        = 1 <<  0
1094 };
1095
1096 enum {
1097         VPORT_STATE_DOWN                = 0x0,
1098         VPORT_STATE_UP                  = 0x1,
1099 };
1100
1101 enum {
1102         MLX5_VPORT_ADMIN_STATE_DOWN  = 0x0,
1103         MLX5_VPORT_ADMIN_STATE_UP    = 0x1,
1104         MLX5_VPORT_ADMIN_STATE_AUTO  = 0x2,
1105 };
1106
1107 enum {
1108         MLX5_VPORT_CVLAN_INSERT_WHEN_NO_CVLAN  = 0x1,
1109         MLX5_VPORT_CVLAN_INSERT_ALWAYS         = 0x3,
1110 };
1111
1112 enum {
1113         MLX5_L3_PROT_TYPE_IPV4          = 0,
1114         MLX5_L3_PROT_TYPE_IPV6          = 1,
1115 };
1116
1117 enum {
1118         MLX5_L4_PROT_TYPE_TCP           = 0,
1119         MLX5_L4_PROT_TYPE_UDP           = 1,
1120 };
1121
1122 enum {
1123         MLX5_HASH_FIELD_SEL_SRC_IP      = 1 << 0,
1124         MLX5_HASH_FIELD_SEL_DST_IP      = 1 << 1,
1125         MLX5_HASH_FIELD_SEL_L4_SPORT    = 1 << 2,
1126         MLX5_HASH_FIELD_SEL_L4_DPORT    = 1 << 3,
1127         MLX5_HASH_FIELD_SEL_IPSEC_SPI   = 1 << 4,
1128 };
1129
1130 enum {
1131         MLX5_MATCH_OUTER_HEADERS        = 1 << 0,
1132         MLX5_MATCH_MISC_PARAMETERS      = 1 << 1,
1133         MLX5_MATCH_INNER_HEADERS        = 1 << 2,
1134         MLX5_MATCH_MISC_PARAMETERS_2    = 1 << 3,
1135         MLX5_MATCH_MISC_PARAMETERS_3    = 1 << 4,
1136         MLX5_MATCH_MISC_PARAMETERS_4    = 1 << 5,
1137         MLX5_MATCH_MISC_PARAMETERS_5    = 1 << 6,
1138 };
1139
1140 enum {
1141         MLX5_FLOW_TABLE_TYPE_NIC_RCV    = 0,
1142         MLX5_FLOW_TABLE_TYPE_ESWITCH    = 4,
1143 };
1144
1145 enum {
1146         MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT       = 0,
1147         MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE  = 1,
1148         MLX5_FLOW_CONTEXT_DEST_TYPE_TIR         = 2,
1149 };
1150
1151 enum mlx5_list_type {
1152         MLX5_NVPRT_LIST_TYPE_UC   = 0x0,
1153         MLX5_NVPRT_LIST_TYPE_MC   = 0x1,
1154         MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
1155 };
1156
1157 enum {
1158         MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1159         MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM    = 0x1,
1160 };
1161
1162 enum mlx5_wol_mode {
1163         MLX5_WOL_DISABLE        = 0,
1164         MLX5_WOL_SECURED_MAGIC  = 1 << 1,
1165         MLX5_WOL_MAGIC          = 1 << 2,
1166         MLX5_WOL_ARP            = 1 << 3,
1167         MLX5_WOL_BROADCAST      = 1 << 4,
1168         MLX5_WOL_MULTICAST      = 1 << 5,
1169         MLX5_WOL_UNICAST        = 1 << 6,
1170         MLX5_WOL_PHY_ACTIVITY   = 1 << 7,
1171 };
1172
1173 enum mlx5_mpls_supported_fields {
1174         MLX5_FIELD_SUPPORT_MPLS_LABEL = 1 << 0,
1175         MLX5_FIELD_SUPPORT_MPLS_EXP   = 1 << 1,
1176         MLX5_FIELD_SUPPORT_MPLS_S_BOS = 1 << 2,
1177         MLX5_FIELD_SUPPORT_MPLS_TTL   = 1 << 3
1178 };
1179
1180 enum mlx5_flex_parser_protos {
1181         MLX5_FLEX_PROTO_GENEVE        = 1 << 3,
1182         MLX5_FLEX_PROTO_CW_MPLS_GRE   = 1 << 4,
1183         MLX5_FLEX_PROTO_CW_MPLS_UDP   = 1 << 5,
1184         MLX5_FLEX_PROTO_ICMP          = 1 << 8,
1185         MLX5_FLEX_PROTO_ICMPV6        = 1 << 9,
1186 };
1187
1188 /* MLX5 DEV CAPs */
1189
1190 /* TODO: EAT.ME */
1191 enum mlx5_cap_mode {
1192         HCA_CAP_OPMOD_GET_MAX   = 0,
1193         HCA_CAP_OPMOD_GET_CUR   = 1,
1194 };
1195
1196 /* Any new cap addition must update mlx5_hca_caps_alloc() to allocate
1197  * capability memory.
1198  */
1199 enum mlx5_cap_type {
1200         MLX5_CAP_GENERAL = 0,
1201         MLX5_CAP_ETHERNET_OFFLOADS,
1202         MLX5_CAP_ODP,
1203         MLX5_CAP_ATOMIC,
1204         MLX5_CAP_ROCE,
1205         MLX5_CAP_IPOIB_OFFLOADS,
1206         MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1207         MLX5_CAP_FLOW_TABLE,
1208         MLX5_CAP_ESWITCH_FLOW_TABLE,
1209         MLX5_CAP_ESWITCH,
1210         MLX5_CAP_RESERVED,
1211         MLX5_CAP_VECTOR_CALC,
1212         MLX5_CAP_QOS,
1213         MLX5_CAP_DEBUG,
1214         MLX5_CAP_RESERVED_14,
1215         MLX5_CAP_DEV_MEM,
1216         MLX5_CAP_RESERVED_16,
1217         MLX5_CAP_TLS,
1218         MLX5_CAP_VDPA_EMULATION = 0x13,
1219         MLX5_CAP_DEV_EVENT = 0x14,
1220         MLX5_CAP_IPSEC,
1221         MLX5_CAP_CRYPTO = 0x1a,
1222         MLX5_CAP_DEV_SHAMPO = 0x1d,
1223         MLX5_CAP_MACSEC = 0x1f,
1224         MLX5_CAP_GENERAL_2 = 0x20,
1225         MLX5_CAP_PORT_SELECTION = 0x25,
1226         MLX5_CAP_ADV_VIRTUALIZATION = 0x26,
1227         /* NUM OF CAP Types */
1228         MLX5_CAP_NUM
1229 };
1230
1231 enum mlx5_pcam_reg_groups {
1232         MLX5_PCAM_REGS_5000_TO_507F                 = 0x0,
1233 };
1234
1235 enum mlx5_pcam_feature_groups {
1236         MLX5_PCAM_FEATURE_ENHANCED_FEATURES         = 0x0,
1237 };
1238
1239 enum mlx5_mcam_reg_groups {
1240         MLX5_MCAM_REGS_FIRST_128                    = 0x0,
1241         MLX5_MCAM_REGS_0x9080_0x90FF                = 0x1,
1242         MLX5_MCAM_REGS_0x9100_0x917F                = 0x2,
1243         MLX5_MCAM_REGS_NUM                          = 0x3,
1244 };
1245
1246 enum mlx5_mcam_feature_groups {
1247         MLX5_MCAM_FEATURE_ENHANCED_FEATURES         = 0x0,
1248 };
1249
1250 enum mlx5_qcam_reg_groups {
1251         MLX5_QCAM_REGS_FIRST_128                    = 0x0,
1252 };
1253
1254 enum mlx5_qcam_feature_groups {
1255         MLX5_QCAM_FEATURE_ENHANCED_FEATURES         = 0x0,
1256 };
1257
1258 /* GET Dev Caps macros */
1259 #define MLX5_CAP_GEN(mdev, cap) \
1260         MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1261
1262 #define MLX5_CAP_GEN_64(mdev, cap) \
1263         MLX5_GET64(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1264
1265 #define MLX5_CAP_GEN_MAX(mdev, cap) \
1266         MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->max, cap)
1267
1268 #define MLX5_CAP_GEN_2(mdev, cap) \
1269         MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1270
1271 #define MLX5_CAP_GEN_2_64(mdev, cap) \
1272         MLX5_GET64(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1273
1274 #define MLX5_CAP_GEN_2_MAX(mdev, cap) \
1275         MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->max, cap)
1276
1277 #define MLX5_CAP_ETH(mdev, cap) \
1278         MLX5_GET(per_protocol_networking_offload_caps,\
1279                  mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->cur, cap)
1280
1281 #define MLX5_CAP_ETH_MAX(mdev, cap) \
1282         MLX5_GET(per_protocol_networking_offload_caps,\
1283                  mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->max, cap)
1284
1285 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \
1286         MLX5_GET(per_protocol_networking_offload_caps,\
1287                  mdev->caps.hca[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS]->cur, cap)
1288
1289 #define MLX5_CAP_ROCE(mdev, cap) \
1290         MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->cur, cap)
1291
1292 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
1293         MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->max, cap)
1294
1295 #define MLX5_CAP_ATOMIC(mdev, cap) \
1296         MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->cur, cap)
1297
1298 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1299         MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->max, cap)
1300
1301 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
1302         MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1303
1304 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \
1305         MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1306
1307 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1308         MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->max, cap)
1309
1310 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1311         MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1312
1313 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
1314         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1315
1316 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \
1317                 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1318
1319 #define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \
1320         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap)
1321
1322 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
1323         MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1324
1325 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
1326         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1327
1328 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
1329         MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1330
1331 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
1332         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1333
1334 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \
1335         MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
1336
1337 #define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \
1338         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_rdma.cap)
1339
1340 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \
1341         MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap)
1342
1343 #define MLX5_CAP_FLOWTABLE_RDMA_TX_MAX(mdev, cap) \
1344         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_rdma.cap)
1345
1346 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1347         MLX5_GET(flow_table_eswitch_cap, \
1348                  mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1349
1350 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1351         MLX5_GET(flow_table_eswitch_cap, \
1352                  mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->max, cap)
1353
1354 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1355         MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1356
1357 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1358         MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1359
1360 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1361         MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1362
1363 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1364         MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1365
1366 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1367         MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1368
1369 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1370         MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1371
1372 #define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2(mdev, cap) \
1373         MLX5_CAP_ESW_FLOWTABLE(mdev, ft_field_support_2_esw_fdb.cap)
1374
1375 #define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2_MAX(mdev, cap) \
1376         MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, ft_field_support_2_esw_fdb.cap)
1377
1378 #define MLX5_CAP_ESW(mdev, cap) \
1379         MLX5_GET(e_switch_cap, \
1380                  mdev->caps.hca[MLX5_CAP_ESWITCH]->cur, cap)
1381
1382 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \
1383         MLX5_GET64(flow_table_eswitch_cap, \
1384                 (mdev)->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1385
1386 #define MLX5_CAP_ESW_MAX(mdev, cap) \
1387         MLX5_GET(e_switch_cap, \
1388                  mdev->caps.hca[MLX5_CAP_ESWITCH]->max, cap)
1389
1390 #define MLX5_CAP_PORT_SELECTION(mdev, cap) \
1391         MLX5_GET(port_selection_cap, \
1392                  mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, cap)
1393
1394 #define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \
1395         MLX5_GET(port_selection_cap, \
1396                  mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->max, cap)
1397
1398 #define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \
1399         MLX5_GET(adv_virtualization_cap, \
1400                  mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->cur, cap)
1401
1402 #define MLX5_CAP_ADV_VIRTUALIZATION_MAX(mdev, cap) \
1403         MLX5_GET(adv_virtualization_cap, \
1404                  mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->max, cap)
1405
1406 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \
1407         MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap)
1408
1409 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION_MAX(mdev, cap) \
1410         MLX5_CAP_PORT_SELECTION_MAX(mdev, flow_table_properties_port_selection.cap)
1411
1412 #define MLX5_CAP_ODP(mdev, cap)\
1413         MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap)
1414
1415 #define MLX5_CAP_ODP_MAX(mdev, cap)\
1416         MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->max, cap)
1417
1418 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1419         MLX5_GET(vector_calc_cap, \
1420                  mdev->caps.hca[MLX5_CAP_VECTOR_CALC]->cur, cap)
1421
1422 #define MLX5_CAP_QOS(mdev, cap)\
1423         MLX5_GET(qos_cap, mdev->caps.hca[MLX5_CAP_QOS]->cur, cap)
1424
1425 #define MLX5_CAP_DEBUG(mdev, cap)\
1426         MLX5_GET(debug_cap, mdev->caps.hca[MLX5_CAP_DEBUG]->cur, cap)
1427
1428 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1429         MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1430
1431 #define MLX5_CAP_PCAM_REG(mdev, reg) \
1432         MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1433
1434 #define MLX5_CAP_MCAM_REG(mdev, reg) \
1435         MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_FIRST_128], \
1436                  mng_access_reg_cap_mask.access_regs.reg)
1437
1438 #define MLX5_CAP_MCAM_REG1(mdev, reg) \
1439         MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9080_0x90FF], \
1440                  mng_access_reg_cap_mask.access_regs1.reg)
1441
1442 #define MLX5_CAP_MCAM_REG2(mdev, reg) \
1443         MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \
1444                  mng_access_reg_cap_mask.access_regs2.reg)
1445
1446 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1447         MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1448
1449 #define MLX5_CAP_QCAM_REG(mdev, fld) \
1450         MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1451
1452 #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1453         MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1454
1455 #define MLX5_CAP_FPGA(mdev, cap) \
1456         MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1457
1458 #define MLX5_CAP64_FPGA(mdev, cap) \
1459         MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1460
1461 #define MLX5_CAP_DEV_MEM(mdev, cap)\
1462         MLX5_GET(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1463
1464 #define MLX5_CAP64_DEV_MEM(mdev, cap)\
1465         MLX5_GET64(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1466
1467 #define MLX5_CAP_TLS(mdev, cap) \
1468         MLX5_GET(tls_cap, (mdev)->caps.hca[MLX5_CAP_TLS]->cur, cap)
1469
1470 #define MLX5_CAP_DEV_EVENT(mdev, cap)\
1471         MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca[MLX5_CAP_DEV_EVENT]->cur, cap)
1472
1473 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\
1474         MLX5_GET(virtio_emulation_cap, \
1475                 (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1476
1477 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\
1478         MLX5_GET64(virtio_emulation_cap, \
1479                 (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1480
1481 #define MLX5_CAP_IPSEC(mdev, cap)\
1482         MLX5_GET(ipsec_cap, (mdev)->caps.hca[MLX5_CAP_IPSEC]->cur, cap)
1483
1484 #define MLX5_CAP_CRYPTO(mdev, cap)\
1485         MLX5_GET(crypto_cap, (mdev)->caps.hca[MLX5_CAP_CRYPTO]->cur, cap)
1486
1487 #define MLX5_CAP_DEV_SHAMPO(mdev, cap)\
1488         MLX5_GET(shampo_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_SHAMPO], cap)
1489
1490 #define MLX5_CAP_MACSEC(mdev, cap)\
1491         MLX5_GET(macsec_cap, (mdev)->caps.hca[MLX5_CAP_MACSEC]->cur, cap)
1492
1493 enum {
1494         MLX5_CMD_STAT_OK                        = 0x0,
1495         MLX5_CMD_STAT_INT_ERR                   = 0x1,
1496         MLX5_CMD_STAT_BAD_OP_ERR                = 0x2,
1497         MLX5_CMD_STAT_BAD_PARAM_ERR             = 0x3,
1498         MLX5_CMD_STAT_BAD_SYS_STATE_ERR         = 0x4,
1499         MLX5_CMD_STAT_BAD_RES_ERR               = 0x5,
1500         MLX5_CMD_STAT_RES_BUSY                  = 0x6,
1501         MLX5_CMD_STAT_LIM_ERR                   = 0x8,
1502         MLX5_CMD_STAT_BAD_RES_STATE_ERR         = 0x9,
1503         MLX5_CMD_STAT_IX_ERR                    = 0xa,
1504         MLX5_CMD_STAT_NO_RES_ERR                = 0xf,
1505         MLX5_CMD_STAT_BAD_INP_LEN_ERR           = 0x50,
1506         MLX5_CMD_STAT_BAD_OUTP_LEN_ERR          = 0x51,
1507         MLX5_CMD_STAT_BAD_QP_STATE_ERR          = 0x10,
1508         MLX5_CMD_STAT_BAD_PKT_ERR               = 0x30,
1509         MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR    = 0x40,
1510 };
1511
1512 enum {
1513         MLX5_IEEE_802_3_COUNTERS_GROUP        = 0x0,
1514         MLX5_RFC_2863_COUNTERS_GROUP          = 0x1,
1515         MLX5_RFC_2819_COUNTERS_GROUP          = 0x2,
1516         MLX5_RFC_3635_COUNTERS_GROUP          = 0x3,
1517         MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1518         MLX5_PER_PRIORITY_COUNTERS_GROUP      = 0x10,
1519         MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1520         MLX5_PHYSICAL_LAYER_COUNTERS_GROUP    = 0x12,
1521         MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP = 0x13,
1522         MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1523         MLX5_INFINIBAND_PORT_COUNTERS_GROUP   = 0x20,
1524 };
1525
1526 enum {
1527         MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP       = 0x0,
1528 };
1529
1530 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1531 {
1532         if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1533                 return 0;
1534         return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1535 }
1536
1537 #define MLX5_RDMA_RX_NUM_COUNTERS_PRIOS 2
1538 #define MLX5_RDMA_TX_NUM_COUNTERS_PRIOS 1
1539 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16
1540 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16
1541 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1542 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1543                                 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1544                                 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1545
1546 #endif /* MLX5_DEVICE_H */