2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/types.h>
37 #include <rdma/ib_verbs.h>
39 #if defined(__LITTLE_ENDIAN)
40 #define MLX5_SET_HOST_ENDIANNESS 0
41 #elif defined(__BIG_ENDIAN)
42 #define MLX5_SET_HOST_ENDIANNESS 0x80
44 #error Host endianness not defined
48 MLX5_MAX_COMMANDS = 32,
49 MLX5_CMD_DATA_BLOCK_SIZE = 512,
50 MLX5_PCI_CMD_XPORT = 7,
54 MLX5_EXTENDED_UD_AV = 0x80000000,
58 MLX5_CQ_STATE_ARMED = 9,
59 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
60 MLX5_CQ_STATE_FIRED = 0xa,
64 MLX5_STAT_RATE_OFFSET = 5,
68 MLX5_INLINE_SEG = 0x80000000,
72 MLX5_PERM_LOCAL_READ = 1 << 2,
73 MLX5_PERM_LOCAL_WRITE = 1 << 3,
74 MLX5_PERM_REMOTE_READ = 1 << 4,
75 MLX5_PERM_REMOTE_WRITE = 1 << 5,
76 MLX5_PERM_ATOMIC = 1 << 6,
77 MLX5_PERM_UMR_EN = 1 << 7,
81 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
82 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
83 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
84 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
85 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
89 MLX5_ACCESS_MODE_PA = 0,
90 MLX5_ACCESS_MODE_MTT = 1,
91 MLX5_ACCESS_MODE_KLM = 2
95 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
96 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
97 MLX5_MKEY_BSF_EN = 1 << 30,
98 MLX5_MKEY_LEN64 = 1 << 31,
107 MLX5_BF_REGS_PER_PAGE = 4,
108 MLX5_MAX_UAR_PAGES = 1 << 8,
109 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_BF_REGS_PER_PAGE,
113 MLX5_MKEY_MASK_LEN = 1ull << 0,
114 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
115 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
116 MLX5_MKEY_MASK_PD = 1ull << 7,
117 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
118 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
119 MLX5_MKEY_MASK_KEY = 1ull << 13,
120 MLX5_MKEY_MASK_QPN = 1ull << 14,
121 MLX5_MKEY_MASK_LR = 1ull << 17,
122 MLX5_MKEY_MASK_LW = 1ull << 18,
123 MLX5_MKEY_MASK_RR = 1ull << 19,
124 MLX5_MKEY_MASK_RW = 1ull << 20,
125 MLX5_MKEY_MASK_A = 1ull << 21,
126 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
127 MLX5_MKEY_MASK_FREE = 1ull << 29,
131 MLX5_EVENT_TYPE_COMP = 0x0,
133 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
134 MLX5_EVENT_TYPE_COMM_EST = 0x02,
135 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
136 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
137 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
139 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
140 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
141 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
142 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
143 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
144 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
146 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
147 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
148 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
149 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
151 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
152 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
154 MLX5_EVENT_TYPE_CMD = 0x0a,
155 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
159 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
160 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
161 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
162 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
163 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
164 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
165 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
169 MLX5_DEV_CAP_FLAG_RC = 1LL << 0,
170 MLX5_DEV_CAP_FLAG_UC = 1LL << 1,
171 MLX5_DEV_CAP_FLAG_UD = 1LL << 2,
172 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
173 MLX5_DEV_CAP_FLAG_SRQ = 1LL << 6,
174 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
175 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
176 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
177 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
178 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
179 MLX5_DEV_CAP_FLAG_RESIZE_SRQ = 1LL << 32,
180 MLX5_DEV_CAP_FLAG_REMOTE_FENCE = 1LL << 38,
181 MLX5_DEV_CAP_FLAG_TLP_HINTS = 1LL << 39,
182 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
183 MLX5_DEV_CAP_FLAG_DCT = 1LL << 41,
184 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 1LL << 46,
188 MLX5_OPCODE_NOP = 0x00,
189 MLX5_OPCODE_SEND_INVAL = 0x01,
190 MLX5_OPCODE_RDMA_WRITE = 0x08,
191 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
192 MLX5_OPCODE_SEND = 0x0a,
193 MLX5_OPCODE_SEND_IMM = 0x0b,
194 MLX5_OPCODE_RDMA_READ = 0x10,
195 MLX5_OPCODE_ATOMIC_CS = 0x11,
196 MLX5_OPCODE_ATOMIC_FA = 0x12,
197 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
198 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
199 MLX5_OPCODE_BIND_MW = 0x18,
200 MLX5_OPCODE_CONFIG_CMD = 0x1f,
202 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
203 MLX5_RECV_OPCODE_SEND = 0x01,
204 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
205 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
207 MLX5_CQE_OPCODE_ERROR = 0x1e,
208 MLX5_CQE_OPCODE_RESIZE = 0x16,
210 MLX5_OPCODE_SET_PSV = 0x20,
211 MLX5_OPCODE_GET_PSV = 0x21,
212 MLX5_OPCODE_CHECK_PSV = 0x22,
213 MLX5_OPCODE_RGET_PSV = 0x26,
214 MLX5_OPCODE_RCHECK_PSV = 0x27,
216 MLX5_OPCODE_UMR = 0x25,
221 MLX5_SET_PORT_RESET_QKEY = 0,
222 MLX5_SET_PORT_GUID0 = 16,
223 MLX5_SET_PORT_NODE_GUID = 17,
224 MLX5_SET_PORT_SYS_GUID = 18,
225 MLX5_SET_PORT_GID_TABLE = 19,
226 MLX5_SET_PORT_PKEY_TABLE = 20,
230 MLX5_MAX_PAGE_SHIFT = 31
233 struct mlx5_inbox_hdr {
239 struct mlx5_outbox_hdr {
245 struct mlx5_cmd_query_adapter_mbox_in {
246 struct mlx5_inbox_hdr hdr;
250 struct mlx5_cmd_query_adapter_mbox_out {
251 struct mlx5_outbox_hdr hdr;
255 __be16 vsd_vendor_id;
260 struct mlx5_hca_cap {
279 u8 log_max_bsf_list_sz;
280 u8 log_max_klm_list_sz;
282 u8 log_max_ra_req_dc;
284 u8 log_max_ra_res_dc;
286 u8 log_max_ra_req_qp;
288 u8 log_max_ra_res_qp;
293 u8 local_ca_ack_delay;
298 __be16 stat_rate_support;
305 __be16 bf_log_bf_reg_size;
307 __be16 max_desc_sz_sq;
309 __be16 max_desc_sz_rq;
311 __be16 max_desc_sz_sq_dc;
321 __be16 log_uar_page_sz;
323 u8 log_msx_atomic_size_qp;
325 u8 log_msx_atomic_size_dc;
330 struct mlx5_cmd_query_hca_cap_mbox_in {
331 struct mlx5_inbox_hdr hdr;
336 struct mlx5_cmd_query_hca_cap_mbox_out {
337 struct mlx5_outbox_hdr hdr;
339 struct mlx5_hca_cap hca_cap;
343 struct mlx5_cmd_set_hca_cap_mbox_in {
344 struct mlx5_inbox_hdr hdr;
346 struct mlx5_hca_cap hca_cap;
350 struct mlx5_cmd_set_hca_cap_mbox_out {
351 struct mlx5_outbox_hdr hdr;
356 struct mlx5_cmd_init_hca_mbox_in {
357 struct mlx5_inbox_hdr hdr;
363 struct mlx5_cmd_init_hca_mbox_out {
364 struct mlx5_outbox_hdr hdr;
368 struct mlx5_cmd_teardown_hca_mbox_in {
369 struct mlx5_inbox_hdr hdr;
375 struct mlx5_cmd_teardown_hca_mbox_out {
376 struct mlx5_outbox_hdr hdr;
380 struct mlx5_cmd_layout {
396 struct health_buffer {
397 __be32 assert_var[5];
399 __be32 assert_exit_ptr;
400 __be32 assert_callra;
410 struct mlx5_init_seg {
412 __be32 cmdif_rev_fw_sub;
415 __be32 cmdq_addr_l_sz;
418 struct health_buffer health;
420 __be32 health_counter;
423 __be32 ieee1588_clk_type;
427 struct mlx5_eqe_comp {
432 struct mlx5_eqe_qp_srq {
437 struct mlx5_eqe_cq_err {
443 struct mlx5_eqe_dropped_packet {
446 struct mlx5_eqe_port_state {
451 struct mlx5_eqe_gpio {
456 struct mlx5_eqe_congestion {
462 struct mlx5_eqe_stall_vl {
467 struct mlx5_eqe_cmd {
472 struct mlx5_eqe_page_req {
482 struct mlx5_eqe_cmd cmd;
483 struct mlx5_eqe_comp comp;
484 struct mlx5_eqe_qp_srq qp_srq;
485 struct mlx5_eqe_cq_err cq_err;
486 struct mlx5_eqe_dropped_packet dp;
487 struct mlx5_eqe_port_state port;
488 struct mlx5_eqe_gpio gpio;
489 struct mlx5_eqe_congestion cong;
490 struct mlx5_eqe_stall_vl stall_vl;
491 struct mlx5_eqe_page_req req_pages;
506 struct mlx5_cmd_prot_block {
507 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
517 struct mlx5_err_cqe {
523 __be32 s_wqe_opcode_qpn;
537 __be32 imm_inval_pkey;
547 struct mlx5_wqe_srq_next_seg {
549 __be16 next_wqe_index;
560 union mlx5_ext_cqe inl_grh;
561 struct mlx5_cqe64 cqe64;
564 struct mlx5_srq_ctx {
579 struct mlx5_create_srq_mbox_in {
580 struct mlx5_inbox_hdr hdr;
583 struct mlx5_srq_ctx ctx;
588 struct mlx5_create_srq_mbox_out {
589 struct mlx5_outbox_hdr hdr;
594 struct mlx5_destroy_srq_mbox_in {
595 struct mlx5_inbox_hdr hdr;
600 struct mlx5_destroy_srq_mbox_out {
601 struct mlx5_outbox_hdr hdr;
605 struct mlx5_query_srq_mbox_in {
606 struct mlx5_inbox_hdr hdr;
611 struct mlx5_query_srq_mbox_out {
612 struct mlx5_outbox_hdr hdr;
614 struct mlx5_srq_ctx ctx;
619 struct mlx5_arm_srq_mbox_in {
620 struct mlx5_inbox_hdr hdr;
626 struct mlx5_arm_srq_mbox_out {
627 struct mlx5_outbox_hdr hdr;
631 struct mlx5_cq_context {
638 __be32 log_sz_usr_page;
645 __be32 last_notified_index;
646 __be32 solicit_producer_index;
647 __be32 consumer_counter;
648 __be32 producer_counter;
650 __be64 db_record_addr;
653 struct mlx5_create_cq_mbox_in {
654 struct mlx5_inbox_hdr hdr;
657 struct mlx5_cq_context ctx;
662 struct mlx5_create_cq_mbox_out {
663 struct mlx5_outbox_hdr hdr;
668 struct mlx5_destroy_cq_mbox_in {
669 struct mlx5_inbox_hdr hdr;
674 struct mlx5_destroy_cq_mbox_out {
675 struct mlx5_outbox_hdr hdr;
679 struct mlx5_query_cq_mbox_in {
680 struct mlx5_inbox_hdr hdr;
685 struct mlx5_query_cq_mbox_out {
686 struct mlx5_outbox_hdr hdr;
688 struct mlx5_cq_context ctx;
693 struct mlx5_enable_hca_mbox_in {
694 struct mlx5_inbox_hdr hdr;
698 struct mlx5_enable_hca_mbox_out {
699 struct mlx5_outbox_hdr hdr;
703 struct mlx5_disable_hca_mbox_in {
704 struct mlx5_inbox_hdr hdr;
708 struct mlx5_disable_hca_mbox_out {
709 struct mlx5_outbox_hdr hdr;
713 struct mlx5_eq_context {
719 __be32 log_sz_usr_page;
724 __be32 consumer_counter;
725 __be32 produser_counter;
729 struct mlx5_create_eq_mbox_in {
730 struct mlx5_inbox_hdr hdr;
734 struct mlx5_eq_context ctx;
741 struct mlx5_create_eq_mbox_out {
742 struct mlx5_outbox_hdr hdr;
748 struct mlx5_destroy_eq_mbox_in {
749 struct mlx5_inbox_hdr hdr;
755 struct mlx5_destroy_eq_mbox_out {
756 struct mlx5_outbox_hdr hdr;
760 struct mlx5_map_eq_mbox_in {
761 struct mlx5_inbox_hdr hdr;
769 struct mlx5_map_eq_mbox_out {
770 struct mlx5_outbox_hdr hdr;
774 struct mlx5_query_eq_mbox_in {
775 struct mlx5_inbox_hdr hdr;
781 struct mlx5_query_eq_mbox_out {
782 struct mlx5_outbox_hdr hdr;
784 struct mlx5_eq_context ctx;
787 struct mlx5_mkey_seg {
788 /* This is a two bit field occupying bits 31-30.
789 * bit 31 is always 0,
790 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
801 __be32 bsfs_octo_size;
809 struct mlx5_query_special_ctxs_mbox_in {
810 struct mlx5_inbox_hdr hdr;
814 struct mlx5_query_special_ctxs_mbox_out {
815 struct mlx5_outbox_hdr hdr;
816 __be32 dump_fill_mkey;
817 __be32 reserved_lkey;
820 struct mlx5_create_mkey_mbox_in {
821 struct mlx5_inbox_hdr hdr;
822 __be32 input_mkey_index;
824 struct mlx5_mkey_seg seg;
826 __be32 xlat_oct_act_size;
827 __be32 bsf_coto_act_size;
832 struct mlx5_create_mkey_mbox_out {
833 struct mlx5_outbox_hdr hdr;
838 struct mlx5_destroy_mkey_mbox_in {
839 struct mlx5_inbox_hdr hdr;
844 struct mlx5_destroy_mkey_mbox_out {
845 struct mlx5_outbox_hdr hdr;
849 struct mlx5_query_mkey_mbox_in {
850 struct mlx5_inbox_hdr hdr;
854 struct mlx5_query_mkey_mbox_out {
855 struct mlx5_outbox_hdr hdr;
859 struct mlx5_modify_mkey_mbox_in {
860 struct mlx5_inbox_hdr hdr;
865 struct mlx5_modify_mkey_mbox_out {
866 struct mlx5_outbox_hdr hdr;
869 struct mlx5_dump_mkey_mbox_in {
870 struct mlx5_inbox_hdr hdr;
873 struct mlx5_dump_mkey_mbox_out {
874 struct mlx5_outbox_hdr hdr;
878 struct mlx5_mad_ifc_mbox_in {
879 struct mlx5_inbox_hdr hdr;
887 struct mlx5_mad_ifc_mbox_out {
888 struct mlx5_outbox_hdr hdr;
893 struct mlx5_access_reg_mbox_in {
894 struct mlx5_inbox_hdr hdr;
901 struct mlx5_access_reg_mbox_out {
902 struct mlx5_outbox_hdr hdr;
907 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
910 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
913 #endif /* MLX5_DEVICE_H */