2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/types.h>
38 #include <linux/mlx4/device.h>
40 #define MLX4_INVALID_LKEY 0x100
43 MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
44 MLX4_QP_OPTPAR_RRE = 1 << 1,
45 MLX4_QP_OPTPAR_RAE = 1 << 2,
46 MLX4_QP_OPTPAR_RWE = 1 << 3,
47 MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4,
48 MLX4_QP_OPTPAR_Q_KEY = 1 << 5,
49 MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
50 MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
51 MLX4_QP_OPTPAR_SRA_MAX = 1 << 8,
52 MLX4_QP_OPTPAR_RRA_MAX = 1 << 9,
53 MLX4_QP_OPTPAR_PM_STATE = 1 << 10,
54 MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12,
55 MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13,
56 MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
57 MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16,
58 MLX4_QP_OPTPAR_COUNTER_INDEX = 1 << 20
62 MLX4_QP_STATE_RST = 0,
63 MLX4_QP_STATE_INIT = 1,
64 MLX4_QP_STATE_RTR = 2,
65 MLX4_QP_STATE_RTS = 3,
66 MLX4_QP_STATE_SQER = 4,
67 MLX4_QP_STATE_SQD = 5,
68 MLX4_QP_STATE_ERR = 6,
69 MLX4_QP_STATE_SQ_DRAINING = 7,
83 MLX4_QP_PM_MIGRATED = 0x3,
84 MLX4_QP_PM_ARMED = 0x0,
85 MLX4_QP_PM_REARM = 0x1
90 MLX4_QP_BIT_SRE = 1 << 15,
91 MLX4_QP_BIT_SWE = 1 << 14,
92 MLX4_QP_BIT_SAE = 1 << 13,
94 MLX4_QP_BIT_RRE = 1 << 15,
95 MLX4_QP_BIT_RWE = 1 << 14,
96 MLX4_QP_BIT_RAE = 1 << 13,
97 MLX4_QP_BIT_RIC = 1 << 4,
101 MLX4_RSS_HASH_XOR = 0,
102 MLX4_RSS_HASH_TOP = 1,
104 MLX4_RSS_UDP_IPV6 = 1 << 0,
105 MLX4_RSS_UDP_IPV4 = 1 << 1,
106 MLX4_RSS_TCP_IPV6 = 1 << 2,
107 MLX4_RSS_IPV6 = 1 << 3,
108 MLX4_RSS_TCP_IPV4 = 1 << 4,
109 MLX4_RSS_IPV4 = 1 << 5,
111 /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */
112 MLX4_RSS_OFFSET_IN_QPC_PRI_PATH = 0x24,
113 /* offset of being RSS indirection QP within mlx4_qp_context.flags */
114 MLX4_RSS_QPC_FLAG_OFFSET = 13,
117 struct mlx4_rss_context {
127 struct mlx4_qp_path {
130 u8 disable_pkey_check;
139 __be32 tclass_flowlabel;
149 struct mlx4_qp_context {
159 struct mlx4_qp_path pri_path;
160 struct mlx4_qp_path alt_path;
163 __be32 next_send_psn;
166 __be32 last_acked_psn;
169 __be32 rnr_nextrecvpsn;
176 __be16 rq_wqe_counter;
177 __be16 sq_wqe_counter;
180 __be32 nummmcpeers_basemkey;
184 __be32 mtt_base_addr_l;
188 /* Which firmware version adds support for NEC (NoErrorCompletion) bit */
189 #define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
192 MLX4_WQE_CTRL_NEC = 1 << 29,
193 MLX4_WQE_CTRL_FENCE = 1 << 6,
194 MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2,
195 MLX4_WQE_CTRL_SOLICITED = 1 << 1,
196 MLX4_WQE_CTRL_IP_CSUM = 1 << 4,
197 MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5,
198 MLX4_WQE_CTRL_INS_VLAN = 1 << 6,
199 MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7,
200 MLX4_WQE_CTRL_FORCE_LOOPBACK = 1 << 0,
203 struct mlx4_wqe_ctrl_seg {
209 * High 24 bits are SRC remote buffer; low 8 bits are flags:
210 * [7] SO (strong ordering)
211 * [5] TCP/UDP checksum
213 * [3:2] C (generate completion queue entry)
214 * [1] SE (solicited event)
215 * [0] FL (force loopback)
219 __be16 srcrb_flags16[2];
222 * imm is immediate data for send/RDMA write w/ immediate;
223 * also invalidation key for send with invalidate; input
224 * modifier for WQEs on CCQs.
230 MLX4_WQE_MLX_VL15 = 1 << 17,
231 MLX4_WQE_MLX_SLR = 1 << 16
234 struct mlx4_wqe_mlx_seg {
244 * [15:12] static rate
248 * [0] FL (force loopback)
255 struct mlx4_wqe_datagram_seg {
263 struct mlx4_wqe_lso_seg {
268 struct mlx4_wqe_bind_seg {
278 MLX4_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
279 MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
280 MLX4_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
281 MLX4_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
282 MLX4_WQE_FMR_PERM_ATOMIC = 1 << 31
285 struct mlx4_wqe_fmr_seg {
296 struct mlx4_wqe_fmr_ext_seg {
302 __be32 wire_ref_tag_base;
303 __be32 mem_ref_tag_base;
306 struct mlx4_wqe_local_inval_seg {
315 struct mlx4_wqe_raddr_seg {
321 struct mlx4_wqe_atomic_seg {
326 struct mlx4_wqe_masked_atomic_seg {
329 __be64 swap_add_mask;
333 struct mlx4_wqe_data_seg {
340 MLX4_INLINE_ALIGN = 64,
341 MLX4_INLINE_SEG = 1 << 31,
344 struct mlx4_wqe_inline_seg {
348 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
349 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
350 struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
351 int sqd_event, struct mlx4_qp *qp);
353 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
354 struct mlx4_qp_context *context);
356 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
357 struct mlx4_qp_context *context,
358 struct mlx4_qp *qp, enum mlx4_qp_state *qp_state);
360 static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
362 return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
365 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp);
367 #endif /* MLX4_QP_H */