1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
26 #include <linux/sched.h>
27 #include <linux/pci.h>
28 #include <linux/mfd/rtsx_common.h>
30 #define MAX_RW_REG_CNT 1024
32 /* PCI Operation Register Address */
33 #define RTSX_HCBAR 0x00
34 #define RTSX_HCBCTLR 0x04
35 #define RTSX_HDBAR 0x08
36 #define RTSX_HDBCTLR 0x0C
37 #define RTSX_HAIMR 0x10
38 #define RTSX_BIPR 0x14
39 #define RTSX_BIER 0x18
41 /* Host command buffer control register */
42 #define STOP_CMD (0x01 << 28)
44 /* Host data buffer control register */
45 #define SDMA_MODE 0x00
46 #define ADMA_MODE (0x02 << 26)
47 #define STOP_DMA (0x01 << 28)
48 #define TRIG_DMA (0x01 << 31)
50 /* Host access internal memory register */
51 #define HAIMR_TRANS_START (0x01 << 31)
52 #define HAIMR_READ 0x00
53 #define HAIMR_WRITE (0x01 << 30)
54 #define HAIMR_READ_START (HAIMR_TRANS_START | HAIMR_READ)
55 #define HAIMR_WRITE_START (HAIMR_TRANS_START | HAIMR_WRITE)
56 #define HAIMR_TRANS_END (HAIMR_TRANS_START)
58 /* Bus interrupt pending register */
59 #define CMD_DONE_INT (1 << 31)
60 #define DATA_DONE_INT (1 << 30)
61 #define TRANS_OK_INT (1 << 29)
62 #define TRANS_FAIL_INT (1 << 28)
63 #define XD_INT (1 << 27)
64 #define MS_INT (1 << 26)
65 #define SD_INT (1 << 25)
66 #define GPIO0_INT (1 << 24)
67 #define OC_INT (1 << 23)
68 #define SD_WRITE_PROTECT (1 << 19)
69 #define XD_EXIST (1 << 18)
70 #define MS_EXIST (1 << 17)
71 #define SD_EXIST (1 << 16)
72 #define DELINK_INT GPIO0_INT
73 #define MS_OC_INT (1 << 23)
74 #define SD_OC_INT (1 << 22)
76 #define CARD_INT (XD_INT | MS_INT | SD_INT)
77 #define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT)
78 #define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | \
79 CARD_INT | GPIO0_INT | OC_INT)
81 #define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST)
83 /* Bus interrupt enable register */
84 #define CMD_DONE_INT_EN (1 << 31)
85 #define DATA_DONE_INT_EN (1 << 30)
86 #define TRANS_OK_INT_EN (1 << 29)
87 #define TRANS_FAIL_INT_EN (1 << 28)
88 #define XD_INT_EN (1 << 27)
89 #define MS_INT_EN (1 << 26)
90 #define SD_INT_EN (1 << 25)
91 #define GPIO0_INT_EN (1 << 24)
92 #define OC_INT_EN (1 << 23)
93 #define DELINK_INT_EN GPIO0_INT_EN
94 #define MS_OC_INT_EN (1 << 23)
95 #define SD_OC_INT_EN (1 << 22)
97 #define READ_REG_CMD 0
98 #define WRITE_REG_CMD 1
99 #define CHECK_REG_CMD 2
102 * macros for easy use
104 #define rtsx_pci_writel(pcr, reg, value) \
105 iowrite32(value, (pcr)->remap_addr + reg)
106 #define rtsx_pci_readl(pcr, reg) \
107 ioread32((pcr)->remap_addr + reg)
108 #define rtsx_pci_writew(pcr, reg, value) \
109 iowrite16(value, (pcr)->remap_addr + reg)
110 #define rtsx_pci_readw(pcr, reg) \
111 ioread16((pcr)->remap_addr + reg)
112 #define rtsx_pci_writeb(pcr, reg, value) \
113 iowrite8(value, (pcr)->remap_addr + reg)
114 #define rtsx_pci_readb(pcr, reg) \
115 ioread8((pcr)->remap_addr + reg)
117 #define rtsx_pci_read_config_byte(pcr, where, val) \
118 pci_read_config_byte((pcr)->pci, where, val)
120 #define rtsx_pci_write_config_byte(pcr, where, val) \
121 pci_write_config_byte((pcr)->pci, where, val)
123 #define rtsx_pci_read_config_dword(pcr, where, val) \
124 pci_read_config_dword((pcr)->pci, where, val)
126 #define rtsx_pci_write_config_dword(pcr, where, val) \
127 pci_write_config_dword((pcr)->pci, where, val)
129 #define STATE_TRANS_NONE 0
130 #define STATE_TRANS_CMD 1
131 #define STATE_TRANS_BUF 2
132 #define STATE_TRANS_SG 3
134 #define TRANS_NOT_READY 0
135 #define TRANS_RESULT_OK 1
136 #define TRANS_RESULT_FAIL 2
137 #define TRANS_NO_DEVICE 3
139 #define RTSX_RESV_BUF_LEN 4096
140 #define HOST_CMDS_BUF_LEN 1024
141 #define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
142 #define HOST_SG_TBL_ITEMS (HOST_SG_TBL_BUF_LEN / 8)
143 #define MAX_SG_ITEM_LEN 0x80000
145 #define HOST_TO_DEVICE 0
146 #define DEVICE_TO_HOST 1
149 #define RX_TUNING_CNT 3
154 #define SG_VALID 0x01
156 #define SG_NO_OP 0x00
157 #define SG_TRANS_DATA (0x02 << 4)
158 #define SG_LINK_DESC (0x03 << 4)
164 /* Card Clock Enable Register */
165 #define SD_CLK_EN 0x04
166 #define MS_CLK_EN 0x08
168 /* Card Select Register */
172 /* Card Output Enable Register */
173 #define SD_OUTPUT_EN 0x04
174 #define MS_OUTPUT_EN 0x08
176 /* CARD_SHARE_MODE */
177 #define CARD_SHARE_MASK 0x0F
178 #define CARD_SHARE_MULTI_LUN 0x00
179 #define CARD_SHARE_NORMAL 0x00
180 #define CARD_SHARE_48_SD 0x04
181 #define CARD_SHARE_48_MS 0x08
182 /* CARD_SHARE_MODE for barossa */
183 #define CARD_SHARE_BAROSSA_SD 0x01
184 #define CARD_SHARE_BAROSSA_MS 0x02
187 #define MS_DRIVE_8mA (0x01 << 6)
188 #define MMC_DRIVE_8mA (0x01 << 4)
189 #define XD_DRIVE_8mA (0x01 << 2)
190 #define GPIO_DRIVE_8mA 0x01
191 #define RTS5209_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\
192 XD_DRIVE_8mA | GPIO_DRIVE_8mA)
193 #define RTL8411_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\
195 #define RTSX_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | GPIO_DRIVE_8mA)
198 #define DRIVER_TYPE_A 0x05
199 #define DRIVER_TYPE_B 0x03
200 #define DRIVER_TYPE_C 0x02
201 #define DRIVER_TYPE_D 0x01
202 #define CFG_DRIVER_TYPE_A 0x02
203 #define CFG_DRIVER_TYPE_B 0x03
204 #define CFG_DRIVER_TYPE_C 0x01
205 #define CFG_DRIVER_TYPE_D 0x00
208 #define SSC_POWER_DOWN 0x01
209 #define SD_OC_POWER_DOWN 0x02
210 #define ALL_POWER_DOWN 0x07
211 #define OC_POWER_DOWN 0x06
214 #define CHANGE_CLK 0x01
217 #define BPP_ASIC_1V7 0x00
218 #define BPP_ASIC_1V8 0x01
219 #define BPP_ASIC_1V9 0x02
220 #define BPP_ASIC_2V0 0x03
221 #define BPP_ASIC_2V7 0x04
222 #define BPP_ASIC_2V8 0x05
223 #define BPP_ASIC_3V2 0x06
224 #define BPP_ASIC_3V3 0x07
225 #define BPP_REG_TUNED18 0x07
226 #define BPP_TUNED18_SHIFT_8402 5
227 #define BPP_TUNED18_SHIFT_8411 4
228 #define BPP_PAD_MASK 0x04
229 #define BPP_PAD_3V3 0x04
230 #define BPP_PAD_1V8 0x00
231 #define BPP_LDO_POWB 0x03
232 #define BPP_LDO_ON 0x00
233 #define BPP_LDO_SUSPEND 0x02
234 #define BPP_LDO_OFF 0x03
237 #define CD_DISABLE_MASK 0x07
238 #define MS_CD_DISABLE 0x04
239 #define SD_CD_DISABLE 0x02
240 #define XD_CD_DISABLE 0x01
241 #define CD_DISABLE 0x07
242 #define CD_ENABLE 0x00
243 #define MS_CD_EN_ONLY 0x03
244 #define SD_CD_EN_ONLY 0x05
245 #define XD_CD_EN_ONLY 0x06
246 #define FORCE_CD_LOW_MASK 0x38
247 #define FORCE_CD_XD_LOW 0x08
248 #define FORCE_CD_SD_LOW 0x10
249 #define FORCE_CD_MS_LOW 0x20
250 #define CD_AUTO_DISABLE 0x40
253 #define SD_CRC7_ERR 0x80
254 #define SD_CRC16_ERR 0x40
255 #define SD_CRC_WRITE_ERR 0x20
256 #define SD_CRC_WRITE_ERR_MASK 0x1C
257 #define GET_CRC_TIME_OUT 0x02
258 #define SD_TUNING_COMPARE_ERR 0x01
261 #define SD_RSP_80CLK_TIMEOUT 0x01
264 #define SD_CLK_TOGGLE_EN 0x80
265 #define SD_CLK_FORCE_STOP 0x40
266 #define SD_DAT3_STATUS 0x10
267 #define SD_DAT2_STATUS 0x08
268 #define SD_DAT1_STATUS 0x04
269 #define SD_DAT0_STATUS 0x02
270 #define SD_CMD_STATUS 0x01
273 #define SD_IO_USING_1V8 0x80
274 #define SD_IO_USING_3V3 0x7F
275 #define TYPE_A_DRIVING 0x00
276 #define TYPE_B_DRIVING 0x01
277 #define TYPE_C_DRIVING 0x02
278 #define TYPE_D_DRIVING 0x03
280 /* SD_SAMPLE_POINT_CTL */
281 #define DDR_FIX_RX_DAT 0x00
282 #define DDR_VAR_RX_DAT 0x80
283 #define DDR_FIX_RX_DAT_EDGE 0x00
284 #define DDR_FIX_RX_DAT_14_DELAY 0x40
285 #define DDR_FIX_RX_CMD 0x00
286 #define DDR_VAR_RX_CMD 0x20
287 #define DDR_FIX_RX_CMD_POS_EDGE 0x00
288 #define DDR_FIX_RX_CMD_14_DELAY 0x10
289 #define SD20_RX_POS_EDGE 0x00
290 #define SD20_RX_14_DELAY 0x08
291 #define SD20_RX_SEL_MASK 0x08
293 /* SD_PUSH_POINT_CTL */
294 #define DDR_FIX_TX_CMD_DAT 0x00
295 #define DDR_VAR_TX_CMD_DAT 0x80
296 #define DDR_FIX_TX_DAT_14_TSU 0x00
297 #define DDR_FIX_TX_DAT_12_TSU 0x40
298 #define DDR_FIX_TX_CMD_NEG_EDGE 0x00
299 #define DDR_FIX_TX_CMD_14_AHEAD 0x20
300 #define SD20_TX_NEG_EDGE 0x00
301 #define SD20_TX_14_AHEAD 0x10
302 #define SD20_TX_SEL_MASK 0x10
303 #define DDR_VAR_SDCLK_POL_SWAP 0x01
306 #define SD_TRANSFER_START 0x80
307 #define SD_TRANSFER_END 0x40
308 #define SD_STAT_IDLE 0x20
309 #define SD_TRANSFER_ERR 0x10
310 /* SD Transfer Mode definition */
311 #define SD_TM_NORMAL_WRITE 0x00
312 #define SD_TM_AUTO_WRITE_3 0x01
313 #define SD_TM_AUTO_WRITE_4 0x02
314 #define SD_TM_AUTO_READ_3 0x05
315 #define SD_TM_AUTO_READ_4 0x06
316 #define SD_TM_CMD_RSP 0x08
317 #define SD_TM_AUTO_WRITE_1 0x09
318 #define SD_TM_AUTO_WRITE_2 0x0A
319 #define SD_TM_NORMAL_READ 0x0C
320 #define SD_TM_AUTO_READ_1 0x0D
321 #define SD_TM_AUTO_READ_2 0x0E
322 #define SD_TM_AUTO_TUNING 0x0F
324 /* SD_VPTX_CTL / SD_VPRX_CTL */
325 #define PHASE_CHANGE 0x80
326 #define PHASE_NOT_RESET 0x40
328 /* SD_DCMPS_TX_CTL / SD_DCMPS_RX_CTL */
329 #define DCMPS_CHANGE 0x80
330 #define DCMPS_CHANGE_DONE 0x40
331 #define DCMPS_ERROR 0x20
332 #define DCMPS_CURRENT_PHASE 0x1F
334 /* SD Configure 1 Register */
335 #define SD_CLK_DIVIDE_0 0x00
336 #define SD_CLK_DIVIDE_256 0xC0
337 #define SD_CLK_DIVIDE_128 0x80
338 #define SD_BUS_WIDTH_1BIT 0x00
339 #define SD_BUS_WIDTH_4BIT 0x01
340 #define SD_BUS_WIDTH_8BIT 0x02
341 #define SD_ASYNC_FIFO_NOT_RST 0x10
342 #define SD_20_MODE 0x00
343 #define SD_DDR_MODE 0x04
344 #define SD_30_MODE 0x08
346 #define SD_CLK_DIVIDE_MASK 0xC0
349 #define SD_CMD_IDLE 0x80
352 #define SD_DATA_IDLE 0x80
355 #define DCM_RESET 0x08
356 #define DCM_LOCKED 0x04
357 #define DCM_208M 0x00
362 #define DRP_START 0x80
363 #define DRP_DONE 0x40
366 #define DRP_WRITE 0x80
367 #define DRP_READ 0x00
368 #define DCM_WRITE_ADDRESS_50 0x50
369 #define DCM_WRITE_ADDRESS_51 0x51
370 #define DCM_READ_ADDRESS_00 0x00
371 #define DCM_READ_ADDRESS_51 0x51
374 #define DMA_DONE_INT 0x80
375 #define SUSPEND_INT 0x40
376 #define LINK_RDY_INT 0x20
377 #define LINK_DOWN_INT 0x10
381 #define DMA_BUSY 0x04
382 #define DMA_DIR_TO_CARD 0x00
383 #define DMA_DIR_FROM_CARD 0x02
385 #define DMA_128 (0 << 4)
386 #define DMA_256 (1 << 4)
387 #define DMA_512 (2 << 4)
388 #define DMA_1024 (3 << 4)
389 #define DMA_PACK_SIZE_MASK 0x30
392 #define SSC_RSTB 0x80
393 #define SSC_8X_EN 0x40
394 #define SSC_FIX_FRAC 0x20
395 #define SSC_SEL_1M 0x00
396 #define SSC_SEL_2M 0x08
397 #define SSC_SEL_4M 0x10
398 #define SSC_SEL_8M 0x18
401 #define SSC_DEPTH_MASK 0x07
402 #define SSC_DEPTH_DISALBE 0x00
403 #define SSC_DEPTH_4M 0x01
404 #define SSC_DEPTH_2M 0x02
405 #define SSC_DEPTH_1M 0x03
406 #define SSC_DEPTH_500K 0x04
407 #define SSC_DEPTH_250K 0x05
409 /* System Clock Control Register */
410 #define CLK_LOW_FREQ 0x01
412 /* System Clock Divider Register */
413 #define CLK_DIV_1 0x01
414 #define CLK_DIV_2 0x02
415 #define CLK_DIV_4 0x03
416 #define CLK_DIV_8 0x04
419 #define SAMPLE_TIME_RISING 0x00
420 #define SAMPLE_TIME_FALLING 0x80
421 #define PUSH_TIME_DEFAULT 0x00
422 #define PUSH_TIME_ODD 0x40
423 #define NO_EXTEND_TOGGLE 0x00
424 #define EXTEND_TOGGLE_CHK 0x20
425 #define MS_BUS_WIDTH_1 0x00
426 #define MS_BUS_WIDTH_4 0x10
427 #define MS_BUS_WIDTH_8 0x18
428 #define MS_2K_SECTOR_MODE 0x04
429 #define MS_512_SECTOR_MODE 0x00
430 #define MS_TOGGLE_TIMEOUT_EN 0x00
431 #define MS_TOGGLE_TIMEOUT_DISEN 0x01
432 #define MS_NO_CHECK_INT 0x02
435 #define WAIT_INT 0x80
436 #define NO_WAIT_INT 0x00
437 #define NO_AUTO_READ_INT_REG 0x00
438 #define AUTO_READ_INT_REG 0x40
439 #define MS_CRC16_ERR 0x20
440 #define MS_RDY_TIMEOUT 0x10
441 #define MS_INT_CMDNK 0x08
442 #define MS_INT_BREQ 0x04
443 #define MS_INT_ERR 0x02
444 #define MS_INT_CED 0x01
447 #define MS_TRANSFER_START 0x80
448 #define MS_TRANSFER_END 0x40
449 #define MS_TRANSFER_ERR 0x20
450 #define MS_BS_STATE 0x10
451 #define MS_TM_READ_BYTES 0x00
452 #define MS_TM_NORMAL_READ 0x01
453 #define MS_TM_WRITE_BYTES 0x04
454 #define MS_TM_NORMAL_WRITE 0x05
455 #define MS_TM_AUTO_READ 0x08
456 #define MS_TM_AUTO_WRITE 0x0C
458 /* SD Configure 2 Register */
459 #define SD_CALCULATE_CRC7 0x00
460 #define SD_NO_CALCULATE_CRC7 0x80
461 #define SD_CHECK_CRC16 0x00
462 #define SD_NO_CHECK_CRC16 0x40
463 #define SD_NO_CHECK_WAIT_CRC_TO 0x20
464 #define SD_WAIT_BUSY_END 0x08
465 #define SD_NO_WAIT_BUSY_END 0x00
466 #define SD_CHECK_CRC7 0x00
467 #define SD_NO_CHECK_CRC7 0x04
468 #define SD_RSP_LEN_0 0x00
469 #define SD_RSP_LEN_6 0x01
470 #define SD_RSP_LEN_17 0x02
471 /* SD/MMC Response Type Definition */
472 #define SD_RSP_TYPE_R0 0x04
473 #define SD_RSP_TYPE_R1 0x01
474 #define SD_RSP_TYPE_R1b 0x09
475 #define SD_RSP_TYPE_R2 0x02
476 #define SD_RSP_TYPE_R3 0x05
477 #define SD_RSP_TYPE_R4 0x05
478 #define SD_RSP_TYPE_R5 0x01
479 #define SD_RSP_TYPE_R6 0x01
480 #define SD_RSP_TYPE_R7 0x01
483 #define SD_RSP_80CLK_TIMEOUT_EN 0x01
485 /* Card Transfer Reset Register */
486 #define SPI_STOP 0x01
490 #define SPI_CLR_ERR 0x10
491 #define XD_CLR_ERR 0x20
492 #define SD_CLR_ERR 0x40
493 #define MS_CLR_ERR 0x80
495 /* Card Data Source Register */
496 #define PINGPONG_BUFFER 0x01
497 #define RING_BUFFER 0x00
499 /* Card Power Control Register */
500 #define PMOS_STRG_MASK 0x10
501 #define PMOS_STRG_800mA 0x10
502 #define PMOS_STRG_400mA 0x00
503 #define SD_POWER_OFF 0x03
504 #define SD_PARTIAL_POWER_ON 0x01
505 #define SD_POWER_ON 0x00
506 #define SD_POWER_MASK 0x03
507 #define MS_POWER_OFF 0x0C
508 #define MS_PARTIAL_POWER_ON 0x04
509 #define MS_POWER_ON 0x00
510 #define MS_POWER_MASK 0x0C
511 #define BPP_POWER_OFF 0x0F
512 #define BPP_POWER_5_PERCENT_ON 0x0E
513 #define BPP_POWER_10_PERCENT_ON 0x0C
514 #define BPP_POWER_15_PERCENT_ON 0x08
515 #define BPP_POWER_ON 0x00
516 #define BPP_POWER_MASK 0x0F
517 #define SD_VCC_PARTIAL_POWER_ON 0x02
518 #define SD_VCC_POWER_ON 0x00
521 #define PWR_GATE_EN 0x01
522 #define LDO3318_PWR_MASK 0x06
524 #define LDO_SUSPEND 0x04
527 /* CARD_CLK_SOURCE */
528 #define CRC_FIX_CLK (0x00 << 0)
529 #define CRC_VAR_CLK0 (0x01 << 0)
530 #define CRC_VAR_CLK1 (0x02 << 0)
531 #define SD30_FIX_CLK (0x00 << 2)
532 #define SD30_VAR_CLK0 (0x01 << 2)
533 #define SD30_VAR_CLK1 (0x02 << 2)
534 #define SAMPLE_FIX_CLK (0x00 << 4)
535 #define SAMPLE_VAR_CLK0 (0x01 << 4)
536 #define SAMPLE_VAR_CLK1 (0x02 << 4)
538 /* HOST_SLEEP_STATE */
539 #define HOST_ENTER_S1 1
540 #define HOST_ENTER_S3 2
542 #define MS_CFG 0xFD40
543 #define MS_TPC 0xFD41
544 #define MS_TRANS_CFG 0xFD42
545 #define MS_TRANSFER 0xFD43
546 #define MS_INT_REG 0xFD44
547 #define MS_BYTE_CNT 0xFD45
548 #define MS_SECTOR_CNT_L 0xFD46
549 #define MS_SECTOR_CNT_H 0xFD47
550 #define MS_DBUS_H 0xFD48
552 #define SD_CFG1 0xFDA0
553 #define SD_CFG2 0xFDA1
554 #define SD_CFG3 0xFDA2
555 #define SD_STAT1 0xFDA3
556 #define SD_STAT2 0xFDA4
557 #define SD_BUS_STAT 0xFDA5
558 #define SD_PAD_CTL 0xFDA6
559 #define SD_SAMPLE_POINT_CTL 0xFDA7
560 #define SD_PUSH_POINT_CTL 0xFDA8
561 #define SD_CMD0 0xFDA9
562 #define SD_CMD1 0xFDAA
563 #define SD_CMD2 0xFDAB
564 #define SD_CMD3 0xFDAC
565 #define SD_CMD4 0xFDAD
566 #define SD_CMD5 0xFDAE
567 #define SD_BYTE_CNT_L 0xFDAF
568 #define SD_BYTE_CNT_H 0xFDB0
569 #define SD_BLOCK_CNT_L 0xFDB1
570 #define SD_BLOCK_CNT_H 0xFDB2
571 #define SD_TRANSFER 0xFDB3
572 #define SD_CMD_STATE 0xFDB5
573 #define SD_DATA_STATE 0xFDB6
577 #define DCM_DRP_CTL 0xFC23
578 #define DCM_DRP_TRIG 0xFC24
579 #define DCM_DRP_CFG 0xFC25
580 #define DCM_DRP_WR_DATA_L 0xFC26
581 #define DCM_DRP_WR_DATA_H 0xFC27
582 #define DCM_DRP_RD_DATA_L 0xFC28
583 #define DCM_DRP_RD_DATA_H 0xFC29
584 #define SD_VPCLK0_CTL 0xFC2A
585 #define SD_VPCLK1_CTL 0xFC2B
586 #define SD_DCMPS0_CTL 0xFC2C
587 #define SD_DCMPS1_CTL 0xFC2D
588 #define SD_VPTX_CTL SD_VPCLK0_CTL
589 #define SD_VPRX_CTL SD_VPCLK1_CTL
590 #define SD_DCMPS_TX_CTL SD_DCMPS0_CTL
591 #define SD_DCMPS_RX_CTL SD_DCMPS1_CTL
592 #define CARD_CLK_SOURCE 0xFC2E
594 #define CARD_PWR_CTL 0xFD50
595 #define CARD_CLK_SWITCH 0xFD51
596 #define RTL8411B_PACKAGE_MODE 0xFD51
597 #define CARD_SHARE_MODE 0xFD52
598 #define CARD_DRIVE_SEL 0xFD53
599 #define CARD_STOP 0xFD54
600 #define CARD_OE 0xFD55
601 #define CARD_AUTO_BLINK 0xFD56
602 #define CARD_GPIO_DIR 0xFD57
603 #define CARD_GPIO 0xFD58
604 #define CARD_DATA_SOURCE 0xFD5B
605 #define SD30_CLK_DRIVE_SEL 0xFD5A
606 #define CARD_SELECT 0xFD5C
607 #define SD30_DRIVE_SEL 0xFD5E
608 #define SD30_CMD_DRIVE_SEL 0xFD5E
609 #define SD30_DAT_DRIVE_SEL 0xFD5F
610 #define CARD_CLK_EN 0xFD69
611 #define SDIO_CTRL 0xFD6B
612 #define CD_PAD_CTL 0xFD73
614 #define FPDCTL 0xFC00
615 #define PDINFO 0xFC01
617 #define CLK_CTL 0xFC02
618 #define CLK_DIV 0xFC03
619 #define CLK_SEL 0xFC04
621 #define SSC_DIV_N_0 0xFC0F
622 #define SSC_DIV_N_1 0xFC10
623 #define SSC_CTL1 0xFC11
624 #define SSC_CTL2 0xFC12
628 #define FPGA_PULL_CTL 0xFC1D
629 #define OLT_LED_CTL 0xFC1E
630 #define GPIO_CTL 0xFC1F
632 #define LDO_CTL 0xFC1E
633 #define SYS_VER 0xFC32
635 #define CARD_PULL_CTL1 0xFD60
636 #define CARD_PULL_CTL2 0xFD61
637 #define CARD_PULL_CTL3 0xFD62
638 #define CARD_PULL_CTL4 0xFD63
639 #define CARD_PULL_CTL5 0xFD64
640 #define CARD_PULL_CTL6 0xFD65
642 /* PCI Express Related Registers */
643 #define IRQEN0 0xFE20
644 #define IRQSTAT0 0xFE21
645 #define IRQEN1 0xFE22
646 #define IRQSTAT1 0xFE23
647 #define TLPRIEN 0xFE24
648 #define TLPRISTAT 0xFE25
649 #define TLPTIEN 0xFE26
650 #define TLPTISTAT 0xFE27
651 #define DMATC0 0xFE28
652 #define DMATC1 0xFE29
653 #define DMATC2 0xFE2A
654 #define DMATC3 0xFE2B
655 #define DMACTL 0xFE2C
661 #define CFGADDR0 0xFE35
662 #define CFGADDR1 0xFE36
663 #define CFGDATA0 0xFE37
664 #define CFGDATA1 0xFE38
665 #define CFGDATA2 0xFE39
666 #define CFGDATA3 0xFE3A
667 #define CFGRWCTL 0xFE3B
668 #define PHYRWCTL 0xFE3C
669 #define PHYDATA0 0xFE3D
670 #define PHYDATA1 0xFE3E
671 #define PHYADDR 0xFE3F
672 #define MSGRXDATA0 0xFE40
673 #define MSGRXDATA1 0xFE41
674 #define MSGRXDATA2 0xFE42
675 #define MSGRXDATA3 0xFE43
676 #define MSGTXDATA0 0xFE44
677 #define MSGTXDATA1 0xFE45
678 #define MSGTXDATA2 0xFE46
679 #define MSGTXDATA3 0xFE47
680 #define MSGTXCTL 0xFE48
681 #define PETXCFG 0xFE49
682 #define LTR_CTL 0xFE4A
683 #define OBFF_CFG 0xFE4C
685 #define CDRESUMECTL 0xFE52
686 #define WAKE_SEL_CTL 0xFE54
687 #define PME_FORCE_CTL 0xFE56
688 #define ASPM_FORCE_CTL 0xFE57
689 #define PM_CLK_FORCE_CTL 0xFE58
690 #define FUNC_FORCE_CTL 0xFE59
691 #define PERST_GLITCH_WIDTH 0xFE5C
692 #define CHANGE_LINK_STATE 0xFE5B
693 #define RESET_LOAD_REG 0xFE5E
694 #define EFUSE_CONTENT 0xFE5F
695 #define HOST_SLEEP_STATE 0xFE60
696 #define SDIO_CFG 0xFE70
698 #define NFTS_TX_CTRL 0xFE72
700 #define PWR_GATE_CTRL 0xFE75
701 #define PWD_SUSPEND_EN 0xFE76
702 #define LDO_PWR_SEL 0xFE78
704 #define DUMMY_REG_RESET_0 0xFE90
706 #define AUTOLOAD_CFG_BASE 0xFF00
708 #define PM_CTRL1 0xFF44
709 #define PM_CTRL2 0xFF45
710 #define PM_CTRL3 0xFF46
711 #define PM_CTRL4 0xFF47
714 #define SRAM_BASE 0xE600
715 #define RBUF_BASE 0xF400
716 #define PPBUF_BASE1 0xF800
717 #define PPBUF_BASE2 0xFA00
718 #define IMAGE_FLAG_ADDR0 0xCE80
719 #define IMAGE_FLAG_ADDR1 0xCE81
723 #define PHY_RCR0 0x01
724 #define PHY_RCR1 0x02
725 #define PHY_RCR2 0x03
726 #define PHY_RTCR 0x04
728 #define PHY_TCR0 0x06
729 #define PHY_TCR1 0x07
730 #define PHY_TUNE 0x08
732 #define PHY_BPCR 0x0A
733 #define PHY_BIST 0x0B
734 #define PHY_RAW_L 0x0C
735 #define PHY_RAW_H 0x0D
736 #define PHY_RAW_DATA 0x0E
737 #define PHY_HOST_CLK_CTRL 0x0F
739 #define PHY_BACR 0x11
741 #define PHY_BCSR 0x13
743 #define PHY_BPNR2 0x15
744 #define PHY_BPNR 0x16
745 #define PHY_BRNR2 0x17
746 #define PHY_BENR 0x18
747 #define PHY_REG_REV 0x19
748 #define PHY_FLD0 0x1A
749 #define PHY_FLD1 0x1B
750 #define PHY_FLD2 0x1C
751 #define PHY_FLD3 0x1D
752 #define PHY_FLD4 0x1E
753 #define PHY_DUM_REG 0x1F
756 #define PCR_SETTING_REG1 0x724
757 #define PCR_SETTING_REG2 0x814
758 #define PCR_SETTING_REG3 0x747
760 #define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0)
765 struct rtsx_pcr *pcr;
769 int (*extra_init_hw)(struct rtsx_pcr *pcr);
770 int (*optimize_phy)(struct rtsx_pcr *pcr);
771 int (*turn_on_led)(struct rtsx_pcr *pcr);
772 int (*turn_off_led)(struct rtsx_pcr *pcr);
773 int (*enable_auto_blink)(struct rtsx_pcr *pcr);
774 int (*disable_auto_blink)(struct rtsx_pcr *pcr);
775 int (*card_power_on)(struct rtsx_pcr *pcr, int card);
776 int (*card_power_off)(struct rtsx_pcr *pcr, int card);
777 int (*switch_output_voltage)(struct rtsx_pcr *pcr,
779 unsigned int (*cd_deglitch)(struct rtsx_pcr *pcr);
780 int (*conv_clk_and_div_n)(int clk, int dir);
781 void (*fetch_vendor_settings)(struct rtsx_pcr *pcr);
782 void (*force_power_down)(struct rtsx_pcr *pcr, u8 pm_state);
785 enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN};
793 void __iomem *remap_addr;
796 /* host reserved buffer */
798 dma_addr_t rtsx_resv_buf_addr;
801 dma_addr_t host_cmds_addr;
804 void *host_sg_tbl_ptr;
805 dma_addr_t host_sg_tbl_addr;
811 unsigned int card_inserted;
812 unsigned int card_removed;
813 unsigned int card_exist;
815 struct delayed_work carddet_work;
816 struct delayed_work idle_work;
819 struct mutex pcr_mutex;
820 struct completion *done;
821 struct completion *finish_me;
823 unsigned int cur_clock;
827 #define EXTRA_CAPS_SD_SDR50 (1 << 0)
828 #define EXTRA_CAPS_SD_SDR104 (1 << 1)
829 #define EXTRA_CAPS_SD_DDR50 (1 << 2)
830 #define EXTRA_CAPS_MMC_HSDDR (1 << 3)
831 #define EXTRA_CAPS_MMC_HS200 (1 << 4)
832 #define EXTRA_CAPS_MMC_8BIT (1 << 5)
841 u8 sd30_drive_sel_1v8;
842 u8 sd30_drive_sel_3v3;
844 #define ASPM_L1_EN 0x02
847 #define PCR_MS_PMOS (1 << 0)
848 #define PCR_REVERSE_SOCKET (1 << 1)
851 const u32 *sd_pull_ctl_enable_tbl;
852 const u32 *sd_pull_ctl_disable_tbl;
853 const u32 *ms_pull_ctl_enable_tbl;
854 const u32 *ms_pull_ctl_disable_tbl;
856 const struct pcr_ops *ops;
857 enum PDEV_STAT state;
860 struct rtsx_slot *slots;
863 #define CHK_PCI_PID(pcr, pid) ((pcr)->pci->device == (pid))
864 #define PCI_VID(pcr) ((pcr)->pci->vendor)
865 #define PCI_PID(pcr) ((pcr)->pci->device)
867 void rtsx_pci_start_run(struct rtsx_pcr *pcr);
868 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data);
869 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data);
870 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
871 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
872 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr);
873 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
874 u8 cmd_type, u16 reg_addr, u8 mask, u8 data);
875 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr);
876 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout);
877 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
878 int num_sg, bool read, int timeout);
879 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
880 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
881 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card);
882 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card);
883 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
884 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
885 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card);
886 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card);
887 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card);
888 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage);
889 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr);
890 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr);
892 static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)
894 return (u8 *)(pcr->host_cmds_ptr);