1 /* SPDX-License-Identifier: GPL-2.0 */
3 * cs42l43 register definitions
5 * Copyright (c) 2022-2023 Cirrus Logic, Inc. and
6 * Cirrus Logic International Semiconductor Ltd.
9 #ifndef CS42L43_CORE_REGS_H
10 #define CS42L43_CORE_REGS_H
13 #define CS42L43_GEN_INT_STAT_1 0x000000C0
14 #define CS42L43_GEN_INT_MASK_1 0x000000C1
15 #define CS42L43_DEVID 0x00003000
16 #define CS42L43_REVID 0x00003004
17 #define CS42L43_RELID 0x0000300C
18 #define CS42L43_SFT_RESET 0x00003020
19 #define CS42L43_DRV_CTRL1 0x00006004
20 #define CS42L43_DRV_CTRL3 0x0000600C
21 #define CS42L43_DRV_CTRL4 0x00006010
22 #define CS42L43_DRV_CTRL_5 0x00006014
23 #define CS42L43_GPIO_CTRL1 0x00006034
24 #define CS42L43_GPIO_CTRL2 0x00006038
25 #define CS42L43_GPIO_STS 0x0000603C
26 #define CS42L43_GPIO_FN_SEL 0x00006040
27 #define CS42L43_MCLK_SRC_SEL 0x00007004
28 #define CS42L43_CCM_BLK_CLK_CONTROL 0x00007010
29 #define CS42L43_SAMPLE_RATE1 0x00007014
30 #define CS42L43_SAMPLE_RATE2 0x00007018
31 #define CS42L43_SAMPLE_RATE3 0x0000701C
32 #define CS42L43_SAMPLE_RATE4 0x00007020
33 #define CS42L43_PLL_CONTROL 0x00007034
34 #define CS42L43_FS_SELECT1 0x00007038
35 #define CS42L43_FS_SELECT2 0x0000703C
36 #define CS42L43_FS_SELECT3 0x00007040
37 #define CS42L43_FS_SELECT4 0x00007044
38 #define CS42L43_PDM_CONTROL 0x0000704C
39 #define CS42L43_ASP_CLK_CONFIG1 0x00007058
40 #define CS42L43_ASP_CLK_CONFIG2 0x0000705C
41 #define CS42L43_OSC_DIV_SEL 0x00007068
42 #define CS42L43_ADC_B_CTRL1 0x00008000
43 #define CS42L43_ADC_B_CTRL2 0x00008004
44 #define CS42L43_DECIM_HPF_WNF_CTRL1 0x0000803C
45 #define CS42L43_DECIM_HPF_WNF_CTRL2 0x00008040
46 #define CS42L43_DECIM_HPF_WNF_CTRL3 0x00008044
47 #define CS42L43_DECIM_HPF_WNF_CTRL4 0x00008048
48 #define CS42L43_DMIC_PDM_CTRL 0x0000804C
49 #define CS42L43_DECIM_VOL_CTRL_CH1_CH2 0x00008050
50 #define CS42L43_DECIM_VOL_CTRL_CH3_CH4 0x00008054
51 #define CS42L43_DECIM_VOL_CTRL_UPDATE 0x00008058
52 #define CS42L43_INTP_VOLUME_CTRL1 0x00009008
53 #define CS42L43_INTP_VOLUME_CTRL2 0x0000900C
54 #define CS42L43_AMP1_2_VOL_RAMP 0x00009010
55 #define CS42L43_ASP_CTRL 0x0000A000
56 #define CS42L43_ASP_FSYNC_CTRL1 0x0000A004
57 #define CS42L43_ASP_FSYNC_CTRL2 0x0000A008
58 #define CS42L43_ASP_FSYNC_CTRL3 0x0000A00C
59 #define CS42L43_ASP_FSYNC_CTRL4 0x0000A010
60 #define CS42L43_ASP_DATA_CTRL 0x0000A018
61 #define CS42L43_ASP_RX_EN 0x0000A020
62 #define CS42L43_ASP_TX_EN 0x0000A024
63 #define CS42L43_ASP_RX_CH1_CTRL 0x0000A028
64 #define CS42L43_ASP_RX_CH2_CTRL 0x0000A02C
65 #define CS42L43_ASP_RX_CH3_CTRL 0x0000A030
66 #define CS42L43_ASP_RX_CH4_CTRL 0x0000A034
67 #define CS42L43_ASP_RX_CH5_CTRL 0x0000A038
68 #define CS42L43_ASP_RX_CH6_CTRL 0x0000A03C
69 #define CS42L43_ASP_TX_CH1_CTRL 0x0000A068
70 #define CS42L43_ASP_TX_CH2_CTRL 0x0000A06C
71 #define CS42L43_ASP_TX_CH3_CTRL 0x0000A070
72 #define CS42L43_ASP_TX_CH4_CTRL 0x0000A074
73 #define CS42L43_ASP_TX_CH5_CTRL 0x0000A078
74 #define CS42L43_ASP_TX_CH6_CTRL 0x0000A07C
75 #define CS42L43_OTP_REVISION_ID 0x0000B02C
76 #define CS42L43_ASPTX1_INPUT 0x0000C200
77 #define CS42L43_ASPTX2_INPUT 0x0000C210
78 #define CS42L43_ASPTX3_INPUT 0x0000C220
79 #define CS42L43_ASPTX4_INPUT 0x0000C230
80 #define CS42L43_ASPTX5_INPUT 0x0000C240
81 #define CS42L43_ASPTX6_INPUT 0x0000C250
82 #define CS42L43_SWIRE_DP1_CH1_INPUT 0x0000C280
83 #define CS42L43_SWIRE_DP1_CH2_INPUT 0x0000C290
84 #define CS42L43_SWIRE_DP1_CH3_INPUT 0x0000C2A0
85 #define CS42L43_SWIRE_DP1_CH4_INPUT 0x0000C2B0
86 #define CS42L43_SWIRE_DP2_CH1_INPUT 0x0000C2C0
87 #define CS42L43_SWIRE_DP2_CH2_INPUT 0x0000C2D0
88 #define CS42L43_SWIRE_DP3_CH1_INPUT 0x0000C2E0
89 #define CS42L43_SWIRE_DP3_CH2_INPUT 0x0000C2F0
90 #define CS42L43_SWIRE_DP4_CH1_INPUT 0x0000C300
91 #define CS42L43_SWIRE_DP4_CH2_INPUT 0x0000C310
92 #define CS42L43_ASRC_INT1_INPUT1 0x0000C400
93 #define CS42L43_ASRC_INT2_INPUT1 0x0000C410
94 #define CS42L43_ASRC_INT3_INPUT1 0x0000C420
95 #define CS42L43_ASRC_INT4_INPUT1 0x0000C430
96 #define CS42L43_ASRC_DEC1_INPUT1 0x0000C440
97 #define CS42L43_ASRC_DEC2_INPUT1 0x0000C450
98 #define CS42L43_ASRC_DEC3_INPUT1 0x0000C460
99 #define CS42L43_ASRC_DEC4_INPUT1 0x0000C470
100 #define CS42L43_ISRC1INT1_INPUT1 0x0000C500
101 #define CS42L43_ISRC1INT2_INPUT1 0x0000C510
102 #define CS42L43_ISRC1DEC1_INPUT1 0x0000C520
103 #define CS42L43_ISRC1DEC2_INPUT1 0x0000C530
104 #define CS42L43_ISRC2INT1_INPUT1 0x0000C540
105 #define CS42L43_ISRC2INT2_INPUT1 0x0000C550
106 #define CS42L43_ISRC2DEC1_INPUT1 0x0000C560
107 #define CS42L43_ISRC2DEC2_INPUT1 0x0000C570
108 #define CS42L43_EQ1MIX_INPUT1 0x0000C580
109 #define CS42L43_EQ1MIX_INPUT2 0x0000C584
110 #define CS42L43_EQ1MIX_INPUT3 0x0000C588
111 #define CS42L43_EQ1MIX_INPUT4 0x0000C58C
112 #define CS42L43_EQ2MIX_INPUT1 0x0000C590
113 #define CS42L43_EQ2MIX_INPUT2 0x0000C594
114 #define CS42L43_EQ2MIX_INPUT3 0x0000C598
115 #define CS42L43_EQ2MIX_INPUT4 0x0000C59C
116 #define CS42L43_SPDIF1_INPUT1 0x0000C600
117 #define CS42L43_SPDIF2_INPUT1 0x0000C610
118 #define CS42L43_AMP1MIX_INPUT1 0x0000C620
119 #define CS42L43_AMP1MIX_INPUT2 0x0000C624
120 #define CS42L43_AMP1MIX_INPUT3 0x0000C628
121 #define CS42L43_AMP1MIX_INPUT4 0x0000C62C
122 #define CS42L43_AMP2MIX_INPUT1 0x0000C630
123 #define CS42L43_AMP2MIX_INPUT2 0x0000C634
124 #define CS42L43_AMP2MIX_INPUT3 0x0000C638
125 #define CS42L43_AMP2MIX_INPUT4 0x0000C63C
126 #define CS42L43_AMP3MIX_INPUT1 0x0000C640
127 #define CS42L43_AMP3MIX_INPUT2 0x0000C644
128 #define CS42L43_AMP3MIX_INPUT3 0x0000C648
129 #define CS42L43_AMP3MIX_INPUT4 0x0000C64C
130 #define CS42L43_AMP4MIX_INPUT1 0x0000C650
131 #define CS42L43_AMP4MIX_INPUT2 0x0000C654
132 #define CS42L43_AMP4MIX_INPUT3 0x0000C658
133 #define CS42L43_AMP4MIX_INPUT4 0x0000C65C
134 #define CS42L43_ASRC_INT_ENABLES 0x0000E000
135 #define CS42L43_ASRC_DEC_ENABLES 0x0000E004
136 #define CS42L43_PDNCNTL 0x00010000
137 #define CS42L43_RINGSENSE_DEB_CTRL 0x0001001C
138 #define CS42L43_TIPSENSE_DEB_CTRL 0x00010020
139 #define CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS 0x00010028
140 #define CS42L43_HS2 0x00010040
141 #define CS42L43_HS_STAT 0x00010048
142 #define CS42L43_MCU_SW_INTERRUPT 0x00010094
143 #define CS42L43_STEREO_MIC_CTRL 0x000100A4
144 #define CS42L43_STEREO_MIC_CLAMP_CTRL 0x000100C4
145 #define CS42L43_BLOCK_EN2 0x00010104
146 #define CS42L43_BLOCK_EN3 0x00010108
147 #define CS42L43_BLOCK_EN4 0x0001010C
148 #define CS42L43_BLOCK_EN5 0x00010110
149 #define CS42L43_BLOCK_EN6 0x00010114
150 #define CS42L43_BLOCK_EN7 0x00010118
151 #define CS42L43_BLOCK_EN8 0x0001011C
152 #define CS42L43_BLOCK_EN9 0x00010120
153 #define CS42L43_BLOCK_EN10 0x00010124
154 #define CS42L43_BLOCK_EN11 0x00010128
155 #define CS42L43_TONE_CH1_CTRL 0x00010134
156 #define CS42L43_TONE_CH2_CTRL 0x00010138
157 #define CS42L43_MIC_DETECT_CONTROL_1 0x00011074
158 #define CS42L43_DETECT_STATUS_1 0x0001107C
159 #define CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL 0x00011090
160 #define CS42L43_MIC_DETECT_CONTROL_ANDROID 0x000110B0
161 #define CS42L43_ISRC1_CTRL 0x00012004
162 #define CS42L43_ISRC2_CTRL 0x00013004
163 #define CS42L43_CTRL_REG 0x00014000
164 #define CS42L43_FDIV_FRAC 0x00014004
165 #define CS42L43_CAL_RATIO 0x00014008
166 #define CS42L43_SPI_CLK_CONFIG1 0x00016004
167 #define CS42L43_SPI_CONFIG1 0x00016010
168 #define CS42L43_SPI_CONFIG2 0x00016014
169 #define CS42L43_SPI_CONFIG3 0x00016018
170 #define CS42L43_SPI_CONFIG4 0x00016024
171 #define CS42L43_SPI_STATUS1 0x00016100
172 #define CS42L43_SPI_STATUS2 0x00016104
173 #define CS42L43_TRAN_CONFIG1 0x00016200
174 #define CS42L43_TRAN_CONFIG2 0x00016204
175 #define CS42L43_TRAN_CONFIG3 0x00016208
176 #define CS42L43_TRAN_CONFIG4 0x0001620C
177 #define CS42L43_TRAN_CONFIG5 0x00016220
178 #define CS42L43_TRAN_CONFIG6 0x00016224
179 #define CS42L43_TRAN_CONFIG7 0x00016228
180 #define CS42L43_TRAN_CONFIG8 0x0001622C
181 #define CS42L43_TRAN_STATUS1 0x00016300
182 #define CS42L43_TRAN_STATUS2 0x00016304
183 #define CS42L43_TRAN_STATUS3 0x00016308
184 #define CS42L43_TX_DATA 0x00016400
185 #define CS42L43_RX_DATA 0x00016600
186 #define CS42L43_DACCNFG1 0x00017000
187 #define CS42L43_DACCNFG2 0x00017004
188 #define CS42L43_HPPATHVOL 0x0001700C
189 #define CS42L43_PGAVOL 0x00017014
190 #define CS42L43_LOADDETRESULTS 0x00017018
191 #define CS42L43_LOADDETENA 0x00017024
192 #define CS42L43_CTRL 0x00017028
193 #define CS42L43_COEFF_DATA_IN0 0x00018000
194 #define CS42L43_COEFF_RD_WR0 0x00018008
195 #define CS42L43_INIT_DONE0 0x00018010
196 #define CS42L43_START_EQZ0 0x00018014
197 #define CS42L43_MUTE_EQ_IN0 0x0001801C
198 #define CS42L43_DECIM_INT 0x0001B000
199 #define CS42L43_EQ_INT 0x0001B004
200 #define CS42L43_ASP_INT 0x0001B008
201 #define CS42L43_PLL_INT 0x0001B00C
202 #define CS42L43_SOFT_INT 0x0001B010
203 #define CS42L43_SWIRE_INT 0x0001B014
204 #define CS42L43_MSM_INT 0x0001B018
205 #define CS42L43_ACC_DET_INT 0x0001B01C
206 #define CS42L43_I2C_TGT_INT 0x0001B020
207 #define CS42L43_SPI_MSTR_INT 0x0001B024
208 #define CS42L43_SW_TO_SPI_BRIDGE_INT 0x0001B028
209 #define CS42L43_OTP_INT 0x0001B02C
210 #define CS42L43_CLASS_D_AMP_INT 0x0001B030
211 #define CS42L43_GPIO_INT 0x0001B034
212 #define CS42L43_ASRC_INT 0x0001B038
213 #define CS42L43_HPOUT_INT 0x0001B03C
214 #define CS42L43_DECIM_MASK 0x0001B0A0
215 #define CS42L43_EQ_MIX_MASK 0x0001B0A4
216 #define CS42L43_ASP_MASK 0x0001B0A8
217 #define CS42L43_PLL_MASK 0x0001B0AC
218 #define CS42L43_SOFT_MASK 0x0001B0B0
219 #define CS42L43_SWIRE_MASK 0x0001B0B4
220 #define CS42L43_MSM_MASK 0x0001B0B8
221 #define CS42L43_ACC_DET_MASK 0x0001B0BC
222 #define CS42L43_I2C_TGT_MASK 0x0001B0C0
223 #define CS42L43_SPI_MSTR_MASK 0x0001B0C4
224 #define CS42L43_SW_TO_SPI_BRIDGE_MASK 0x0001B0C8
225 #define CS42L43_OTP_MASK 0x0001B0CC
226 #define CS42L43_CLASS_D_AMP_MASK 0x0001B0D0
227 #define CS42L43_GPIO_INT_MASK 0x0001B0D4
228 #define CS42L43_ASRC_MASK 0x0001B0D8
229 #define CS42L43_HPOUT_MASK 0x0001B0DC
230 #define CS42L43_DECIM_INT_SHADOW 0x0001B300
231 #define CS42L43_EQ_MIX_INT_SHADOW 0x0001B304
232 #define CS42L43_ASP_INT_SHADOW 0x0001B308
233 #define CS42L43_PLL_INT_SHADOW 0x0001B30C
234 #define CS42L43_SOFT_INT_SHADOW 0x0001B310
235 #define CS42L43_SWIRE_INT_SHADOW 0x0001B314
236 #define CS42L43_MSM_INT_SHADOW 0x0001B318
237 #define CS42L43_ACC_DET_INT_SHADOW 0x0001B31C
238 #define CS42L43_I2C_TGT_INT_SHADOW 0x0001B320
239 #define CS42L43_SPI_MSTR_INT_SHADOW 0x0001B324
240 #define CS42L43_SW_TO_SPI_BRIDGE_SHADOW 0x0001B328
241 #define CS42L43_OTP_INT_SHADOW 0x0001B32C
242 #define CS42L43_CLASS_D_AMP_INT_SHADOW 0x0001B330
243 #define CS42L43_GPIO_SHADOW 0x0001B334
244 #define CS42L43_ASRC_SHADOW 0x0001B338
245 #define CS42L43_HP_OUT_SHADOW 0x0001B33C
246 #define CS42L43_BOOT_CONTROL 0x00101000
247 #define CS42L43_BLOCK_EN 0x00101008
248 #define CS42L43_SHUTTER_CONTROL 0x0010100C
249 #define CS42L43_MCU_SW_REV 0x00114000
250 #define CS42L43_PATCH_START_ADDR 0x00114004
251 #define CS42L43_NEED_CONFIGS 0x0011400C
252 #define CS42L43_BOOT_STATUS 0x0011401C
253 #define CS42L43_FW_SH_BOOT_CFG_NEED_CONFIGS 0x0011F8F8
254 #define CS42L43_FW_MISSION_CTRL_NEED_CONFIGS 0x0011FE00
255 #define CS42L43_FW_MISSION_CTRL_HAVE_CONFIGS 0x0011FE04
256 #define CS42L43_FW_MISSION_CTRL_MM_CTRL_SELECTION 0x0011FE0C
257 #define CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG 0x0011FE10
258 #define CS42L43_MCU_RAM_MAX 0x0011FFFF
261 #define CS42L43_DEVID_VAL 0x00042A43
263 /* CS42L43_GEN_INT_STAT_1 */
264 #define CS42L43_INT_STAT_GEN1_MASK 0x00000001
265 #define CS42L43_INT_STAT_GEN1_SHIFT 0
267 /* CS42L43_SFT_RESET */
268 #define CS42L43_SFT_RESET_MASK 0xFF000000
269 #define CS42L43_SFT_RESET_SHIFT 24
271 #define CS42L43_SFT_RESET_VAL 0x5A000000
273 /* CS42L43_DRV_CTRL1 */
274 #define CS42L43_ASP_DOUT_DRV_MASK 0x00038000
275 #define CS42L43_ASP_DOUT_DRV_SHIFT 15
276 #define CS42L43_ASP_FSYNC_DRV_MASK 0x00000E00
277 #define CS42L43_ASP_FSYNC_DRV_SHIFT 9
278 #define CS42L43_ASP_BCLK_DRV_MASK 0x000001C0
279 #define CS42L43_ASP_BCLK_DRV_SHIFT 6
281 /* CS42L43_DRV_CTRL3 */
282 #define CS42L43_I2C_ADDR_DRV_MASK 0x30000000
283 #define CS42L43_I2C_ADDR_DRV_SHIFT 28
284 #define CS42L43_I2C_SDA_DRV_MASK 0x0C000000
285 #define CS42L43_I2C_SDA_DRV_SHIFT 26
286 #define CS42L43_PDMOUT2_CLK_DRV_MASK 0x00E00000
287 #define CS42L43_PDMOUT2_CLK_DRV_SHIFT 21
288 #define CS42L43_PDMOUT2_DATA_DRV_MASK 0x001C0000
289 #define CS42L43_PDMOUT2_DATA_DRV_SHIFT 18
290 #define CS42L43_PDMOUT1_CLK_DRV_MASK 0x00038000
291 #define CS42L43_PDMOUT1_CLK_DRV_SHIFT 15
292 #define CS42L43_PDMOUT1_DATA_DRV_MASK 0x00007000
293 #define CS42L43_PDMOUT1_DATA_DRV_SHIFT 12
294 #define CS42L43_SPI_MISO_DRV_MASK 0x00000038
295 #define CS42L43_SPI_MISO_DRV_SHIFT 3
297 /* CS42L43_DRV_CTRL4 */
298 #define CS42L43_GPIO3_DRV_MASK 0x00000E00
299 #define CS42L43_GPIO3_DRV_SHIFT 9
300 #define CS42L43_GPIO2_DRV_MASK 0x000001C0
301 #define CS42L43_GPIO2_DRV_SHIFT 6
302 #define CS42L43_GPIO1_DRV_MASK 0x00000038
303 #define CS42L43_GPIO1_DRV_SHIFT 3
305 /* CS42L43_DRV_CTRL_5 */
306 #define CS42L43_I2C_SCL_DRV_MASK 0x18000000
307 #define CS42L43_I2C_SCL_DRV_SHIFT 27
308 #define CS42L43_SPI_SCK_DRV_MASK 0x07000000
309 #define CS42L43_SPI_SCK_DRV_SHIFT 24
310 #define CS42L43_SPI_MOSI_DRV_MASK 0x00E00000
311 #define CS42L43_SPI_MOSI_DRV_SHIFT 21
312 #define CS42L43_SPI_SSB_DRV_MASK 0x001C0000
313 #define CS42L43_SPI_SSB_DRV_SHIFT 18
314 #define CS42L43_ASP_DIN_DRV_MASK 0x000001C0
315 #define CS42L43_ASP_DIN_DRV_SHIFT 6
317 /* CS42L43_GPIO_CTRL1 */
318 #define CS42L43_GPIO3_POL_MASK 0x00040000
319 #define CS42L43_GPIO3_POL_SHIFT 18
320 #define CS42L43_GPIO2_POL_MASK 0x00020000
321 #define CS42L43_GPIO2_POL_SHIFT 17
322 #define CS42L43_GPIO1_POL_MASK 0x00010000
323 #define CS42L43_GPIO1_POL_SHIFT 16
324 #define CS42L43_GPIO3_LVL_MASK 0x00000400
325 #define CS42L43_GPIO3_LVL_SHIFT 10
326 #define CS42L43_GPIO2_LVL_MASK 0x00000200
327 #define CS42L43_GPIO2_LVL_SHIFT 9
328 #define CS42L43_GPIO1_LVL_MASK 0x00000100
329 #define CS42L43_GPIO1_LVL_SHIFT 8
330 #define CS42L43_GPIO3_DIR_MASK 0x00000004
331 #define CS42L43_GPIO3_DIR_SHIFT 2
332 #define CS42L43_GPIO2_DIR_MASK 0x00000002
333 #define CS42L43_GPIO2_DIR_SHIFT 1
334 #define CS42L43_GPIO1_DIR_MASK 0x00000001
335 #define CS42L43_GPIO1_DIR_SHIFT 0
337 /* CS42L43_GPIO_CTRL2 */
338 #define CS42L43_GPIO3_DEGLITCH_BYP_MASK 0x00000004
339 #define CS42L43_GPIO3_DEGLITCH_BYP_SHIFT 2
340 #define CS42L43_GPIO2_DEGLITCH_BYP_MASK 0x00000002
341 #define CS42L43_GPIO2_DEGLITCH_BYP_SHIFT 1
342 #define CS42L43_GPIO1_DEGLITCH_BYP_MASK 0x00000001
343 #define CS42L43_GPIO1_DEGLITCH_BYP_SHIFT 0
345 /* CS42L43_GPIO_STS */
346 #define CS42L43_GPIO3_STS_MASK 0x00000004
347 #define CS42L43_GPIO3_STS_SHIFT 2
348 #define CS42L43_GPIO2_STS_MASK 0x00000002
349 #define CS42L43_GPIO2_STS_SHIFT 1
350 #define CS42L43_GPIO1_STS_MASK 0x00000001
351 #define CS42L43_GPIO1_STS_SHIFT 0
353 /* CS42L43_GPIO_FN_SEL */
354 #define CS42L43_GPIO3_FN_SEL_MASK 0x00000004
355 #define CS42L43_GPIO3_FN_SEL_SHIFT 2
356 #define CS42L43_GPIO1_FN_SEL_MASK 0x00000001
357 #define CS42L43_GPIO1_FN_SEL_SHIFT 0
359 /* CS42L43_MCLK_SRC_SEL */
360 #define CS42L43_OSC_PLL_MCLK_SEL_MASK 0x00000001
361 #define CS42L43_OSC_PLL_MCLK_SEL_SHIFT 0
363 /* CS42L43_SAMPLE_RATE1..CS42L43_SAMPLE_RATE4 */
364 #define CS42L43_SAMPLE_RATE_MASK 0x0000001F
365 #define CS42L43_SAMPLE_RATE_SHIFT 0
367 /* CS42L43_PLL_CONTROL */
368 #define CS42L43_PLL_REFCLK_EN_MASK 0x00000008
369 #define CS42L43_PLL_REFCLK_EN_SHIFT 3
370 #define CS42L43_PLL_REFCLK_DIV_MASK 0x00000006
371 #define CS42L43_PLL_REFCLK_DIV_SHIFT 1
372 #define CS42L43_PLL_REFCLK_SRC_MASK 0x00000001
373 #define CS42L43_PLL_REFCLK_SRC_SHIFT 0
375 /* CS42L43_FS_SELECT1 */
376 #define CS42L43_ASP_RATE_MASK 0x00000003
377 #define CS42L43_ASP_RATE_SHIFT 0
379 /* CS42L43_FS_SELECT2 */
380 #define CS42L43_ASRC_DEC_OUT_RATE_MASK 0x000000C0
381 #define CS42L43_ASRC_DEC_OUT_RATE_SHIFT 6
382 #define CS42L43_ASRC_INT_OUT_RATE_MASK 0x00000030
383 #define CS42L43_ASRC_INT_OUT_RATE_SHIFT 4
384 #define CS42L43_ASRC_DEC_IN_RATE_MASK 0x0000000C
385 #define CS42L43_ASRC_DEC_IN_RATE_SHIFT 2
386 #define CS42L43_ASRC_INT_IN_RATE_MASK 0x00000003
387 #define CS42L43_ASRC_INT_IN_RATE_SHIFT 0
389 /* CS42L43_FS_SELECT3 */
390 #define CS42L43_HPOUT_RATE_MASK 0x0000C000
391 #define CS42L43_HPOUT_RATE_SHIFT 14
392 #define CS42L43_EQZ_RATE_MASK 0x00003000
393 #define CS42L43_EQZ_RATE_SHIFT 12
394 #define CS42L43_DIAGGEN_RATE_MASK 0x00000C00
395 #define CS42L43_DIAGGEN_RATE_SHIFT 10
396 #define CS42L43_DECIM_CH4_RATE_MASK 0x00000300
397 #define CS42L43_DECIM_CH4_RATE_SHIFT 8
398 #define CS42L43_DECIM_CH3_RATE_MASK 0x000000C0
399 #define CS42L43_DECIM_CH3_RATE_SHIFT 6
400 #define CS42L43_DECIM_CH2_RATE_MASK 0x00000030
401 #define CS42L43_DECIM_CH2_RATE_SHIFT 4
402 #define CS42L43_DECIM_CH1_RATE_MASK 0x0000000C
403 #define CS42L43_DECIM_CH1_RATE_SHIFT 2
404 #define CS42L43_AMP1_2_RATE_MASK 0x00000003
405 #define CS42L43_AMP1_2_RATE_SHIFT 0
407 /* CS42L43_FS_SELECT4 */
408 #define CS42L43_SW_DP7_RATE_MASK 0x00C00000
409 #define CS42L43_SW_DP7_RATE_SHIFT 22
410 #define CS42L43_SW_DP6_RATE_MASK 0x00300000
411 #define CS42L43_SW_DP6_RATE_SHIFT 20
412 #define CS42L43_SPDIF_RATE_MASK 0x000C0000
413 #define CS42L43_SPDIF_RATE_SHIFT 18
414 #define CS42L43_SW_DP5_RATE_MASK 0x00030000
415 #define CS42L43_SW_DP5_RATE_SHIFT 16
416 #define CS42L43_SW_DP4_RATE_MASK 0x0000C000
417 #define CS42L43_SW_DP4_RATE_SHIFT 14
418 #define CS42L43_SW_DP3_RATE_MASK 0x00003000
419 #define CS42L43_SW_DP3_RATE_SHIFT 12
420 #define CS42L43_SW_DP2_RATE_MASK 0x00000C00
421 #define CS42L43_SW_DP2_RATE_SHIFT 10
422 #define CS42L43_SW_DP1_RATE_MASK 0x00000300
423 #define CS42L43_SW_DP1_RATE_SHIFT 8
424 #define CS42L43_ISRC2_LOW_RATE_MASK 0x000000C0
425 #define CS42L43_ISRC2_LOW_RATE_SHIFT 6
426 #define CS42L43_ISRC2_HIGH_RATE_MASK 0x00000030
427 #define CS42L43_ISRC2_HIGH_RATE_SHIFT 4
428 #define CS42L43_ISRC1_LOW_RATE_MASK 0x0000000C
429 #define CS42L43_ISRC1_LOW_RATE_SHIFT 2
430 #define CS42L43_ISRC1_HIGH_RATE_MASK 0x00000003
431 #define CS42L43_ISRC1_HIGH_RATE_SHIFT 0
433 /* CS42L43_PDM_CONTROL */
434 #define CS42L43_PDM2_CLK_DIV_MASK 0x0000000C
435 #define CS42L43_PDM2_CLK_DIV_SHIFT 2
436 #define CS42L43_PDM1_CLK_DIV_MASK 0x00000003
437 #define CS42L43_PDM1_CLK_DIV_SHIFT 0
439 /* CS42L43_ASP_CLK_CONFIG1 */
440 #define CS42L43_ASP_BCLK_N_MASK 0x03FF0000
441 #define CS42L43_ASP_BCLK_N_SHIFT 16
442 #define CS42L43_ASP_BCLK_M_MASK 0x000003FF
443 #define CS42L43_ASP_BCLK_M_SHIFT 0
445 /* CS42L43_ASP_CLK_CONFIG2 */
446 #define CS42L43_ASP_MASTER_MODE_MASK 0x00000002
447 #define CS42L43_ASP_MASTER_MODE_SHIFT 1
448 #define CS42L43_ASP_BCLK_INV_MASK 0x00000001
449 #define CS42L43_ASP_BCLK_INV_SHIFT 0
451 /* CS42L43_OSC_DIV_SEL */
452 #define CS42L43_OSC_DIV2_EN_MASK 0x00000001
453 #define CS42L43_OSC_DIV2_EN_SHIFT 0
455 /* CS42L43_ADC_B_CTRL1..CS42L43_ADC_B_CTRL1 */
456 #define CS42L43_PGA_WIDESWING_MODE_EN_MASK 0x00000080
457 #define CS42L43_PGA_WIDESWING_MODE_EN_SHIFT 7
458 #define CS42L43_ADC_AIN_SEL_MASK 0x00000010
459 #define CS42L43_ADC_AIN_SEL_SHIFT 4
460 #define CS42L43_ADC_PGA_GAIN_MASK 0x0000000F
461 #define CS42L43_ADC_PGA_GAIN_SHIFT 0
463 /* CS42L43_DECIM_HPF_WNF_CTRL1..CS42L43_DECIM_HPF_WNF_CTRL4 */
464 #define CS42L43_DECIM_WNF_CF_MASK 0x00000070
465 #define CS42L43_DECIM_WNF_CF_SHIFT 4
466 #define CS42L43_DECIM_WNF_EN_MASK 0x00000008
467 #define CS42L43_DECIM_WNF_EN_SHIFT 3
468 #define CS42L43_DECIM_HPF_CF_MASK 0x00000006
469 #define CS42L43_DECIM_HPF_CF_SHIFT 1
470 #define CS42L43_DECIM_HPF_EN_MASK 0x00000001
471 #define CS42L43_DECIM_HPF_EN_SHIFT 0
473 /* CS42L43_DMIC_PDM_CTRL */
474 #define CS42L43_PDM2R_INV_MASK 0x00000020
475 #define CS42L43_PDM2R_INV_SHIFT 5
476 #define CS42L43_PDM2L_INV_MASK 0x00000010
477 #define CS42L43_PDM2L_INV_SHIFT 4
478 #define CS42L43_PDM1R_INV_MASK 0x00000008
479 #define CS42L43_PDM1R_INV_SHIFT 3
480 #define CS42L43_PDM1L_INV_MASK 0x00000004
481 #define CS42L43_PDM1L_INV_SHIFT 2
483 /* CS42L43_DECIM_VOL_CTRL_CH1_CH2 */
484 #define CS42L43_DECIM2_MUTE_MASK 0x80000000
485 #define CS42L43_DECIM2_MUTE_SHIFT 31
486 #define CS42L43_DECIM2_VOL_MASK 0x3FC00000
487 #define CS42L43_DECIM2_VOL_SHIFT 22
488 #define CS42L43_DECIM2_VD_RAMP_MASK 0x00380000
489 #define CS42L43_DECIM2_VD_RAMP_SHIFT 19
490 #define CS42L43_DECIM2_VI_RAMP_MASK 0x00070000
491 #define CS42L43_DECIM2_VI_RAMP_SHIFT 16
492 #define CS42L43_DECIM1_MUTE_MASK 0x00008000
493 #define CS42L43_DECIM1_MUTE_SHIFT 15
494 #define CS42L43_DECIM1_VOL_MASK 0x00003FC0
495 #define CS42L43_DECIM1_VOL_SHIFT 6
496 #define CS42L43_DECIM1_VD_RAMP_MASK 0x00000038
497 #define CS42L43_DECIM1_VD_RAMP_SHIFT 3
498 #define CS42L43_DECIM1_VI_RAMP_MASK 0x00000007
499 #define CS42L43_DECIM1_VI_RAMP_SHIFT 0
501 /* CS42L43_DECIM_VOL_CTRL_CH3_CH4 */
502 #define CS42L43_DECIM4_MUTE_MASK 0x80000000
503 #define CS42L43_DECIM4_MUTE_SHIFT 31
504 #define CS42L43_DECIM4_VOL_MASK 0x3FC00000
505 #define CS42L43_DECIM4_VOL_SHIFT 22
506 #define CS42L43_DECIM4_VD_RAMP_MASK 0x00380000
507 #define CS42L43_DECIM4_VD_RAMP_SHIFT 19
508 #define CS42L43_DECIM4_VI_RAMP_MASK 0x00070000
509 #define CS42L43_DECIM4_VI_RAMP_SHIFT 16
510 #define CS42L43_DECIM3_MUTE_MASK 0x00008000
511 #define CS42L43_DECIM3_MUTE_SHIFT 15
512 #define CS42L43_DECIM3_VOL_MASK 0x00003FC0
513 #define CS42L43_DECIM3_VOL_SHIFT 6
514 #define CS42L43_DECIM3_VD_RAMP_MASK 0x00000038
515 #define CS42L43_DECIM3_VD_RAMP_SHIFT 3
516 #define CS42L43_DECIM3_VI_RAMP_MASK 0x00000007
517 #define CS42L43_DECIM3_VI_RAMP_SHIFT 0
519 /* CS42L43_DECIM_VOL_CTRL_UPDATE */
520 #define CS42L43_DECIM4_VOL_UPDATE_MASK 0x00000008
521 #define CS42L43_DECIM4_VOL_UPDATE_SHIFT 3
522 #define CS42L43_DECIM3_VOL_UPDATE_MASK 0x00000004
523 #define CS42L43_DECIM3_VOL_UPDATE_SHIFT 2
524 #define CS42L43_DECIM2_VOL_UPDATE_MASK 0x00000002
525 #define CS42L43_DECIM2_VOL_UPDATE_SHIFT 1
526 #define CS42L43_DECIM1_VOL_UPDATE_MASK 0x00000001
527 #define CS42L43_DECIM1_VOL_UPDATE_SHIFT 0
529 /* CS42L43_INTP_VOLUME_CTRL1..CS42L43_INTP_VOLUME_CTRL2 */
530 #define CS42L43_AMP1_2_VU_MASK 0x00000200
531 #define CS42L43_AMP1_2_VU_SHIFT 9
532 #define CS42L43_AMP_MUTE_MASK 0x00000100
533 #define CS42L43_AMP_MUTE_SHIFT 8
534 #define CS42L43_AMP_VOL_MASK 0x000000FF
535 #define CS42L43_AMP_VOL_SHIFT 0
537 /* CS42L43_AMP1_2_VOL_RAMP */
538 #define CS42L43_AMP1_2_VD_RAMP_MASK 0x00000070
539 #define CS42L43_AMP1_2_VD_RAMP_SHIFT 4
540 #define CS42L43_AMP1_2_VI_RAMP_MASK 0x00000007
541 #define CS42L43_AMP1_2_VI_RAMP_SHIFT 0
543 /* CS42L43_ASP_CTRL */
544 #define CS42L43_ASP_FSYNC_MODE_MASK 0x00000004
545 #define CS42L43_ASP_FSYNC_MODE_SHIFT 2
546 #define CS42L43_ASP_BCLK_EN_MASK 0x00000002
547 #define CS42L43_ASP_BCLK_EN_SHIFT 1
548 #define CS42L43_ASP_FSYNC_EN_MASK 0x00000001
549 #define CS42L43_ASP_FSYNC_EN_SHIFT 0
551 /* CS42L43_ASP_FSYNC_CTRL1 */
552 #define CS42L43_ASP_FSYNC_M_MASK 0x0007FFFF
553 #define CS42L43_ASP_FSYNC_M_SHIFT 0
555 /* CS42L43_ASP_FSYNC_CTRL3 */
556 #define CS42L43_ASP_FSYNC_IN_INV_MASK 0x00000002
557 #define CS42L43_ASP_FSYNC_IN_INV_SHIFT 1
558 #define CS42L43_ASP_FSYNC_OUT_INV_MASK 0x00000001
559 #define CS42L43_ASP_FSYNC_OUT_INV_SHIFT 0
561 /* CS42L43_ASP_FSYNC_CTRL4 */
562 #define CS42L43_ASP_NUM_BCLKS_PER_FSYNC_MASK 0x00001FFE
563 #define CS42L43_ASP_NUM_BCLKS_PER_FSYNC_SHIFT 1
565 /* CS42L43_ASP_DATA_CTRL */
566 #define CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK 0x00000008
567 #define CS42L43_ASP_FSYNC_FRAME_START_PHASE_SHIFT 3
568 #define CS42L43_ASP_FSYNC_FRAME_START_DLY_MASK 0x00000007
569 #define CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT 0
571 /* CS42L43_ASP_RX_EN */
572 #define CS42L43_ASP_RX_CH6_EN_MASK 0x00000020
573 #define CS42L43_ASP_RX_CH6_EN_SHIFT 5
574 #define CS42L43_ASP_RX_CH5_EN_MASK 0x00000010
575 #define CS42L43_ASP_RX_CH5_EN_SHIFT 4
576 #define CS42L43_ASP_RX_CH4_EN_MASK 0x00000008
577 #define CS42L43_ASP_RX_CH4_EN_SHIFT 3
578 #define CS42L43_ASP_RX_CH3_EN_MASK 0x00000004
579 #define CS42L43_ASP_RX_CH3_EN_SHIFT 2
580 #define CS42L43_ASP_RX_CH2_EN_MASK 0x00000002
581 #define CS42L43_ASP_RX_CH2_EN_SHIFT 1
582 #define CS42L43_ASP_RX_CH1_EN_MASK 0x00000001
583 #define CS42L43_ASP_RX_CH1_EN_SHIFT 0
585 /* CS42L43_ASP_TX_EN */
586 #define CS42L43_ASP_TX_CH6_EN_MASK 0x00000020
587 #define CS42L43_ASP_TX_CH6_EN_SHIFT 5
588 #define CS42L43_ASP_TX_CH5_EN_MASK 0x00000010
589 #define CS42L43_ASP_TX_CH5_EN_SHIFT 4
590 #define CS42L43_ASP_TX_CH4_EN_MASK 0x00000008
591 #define CS42L43_ASP_TX_CH4_EN_SHIFT 3
592 #define CS42L43_ASP_TX_CH3_EN_MASK 0x00000004
593 #define CS42L43_ASP_TX_CH3_EN_SHIFT 2
594 #define CS42L43_ASP_TX_CH2_EN_MASK 0x00000002
595 #define CS42L43_ASP_TX_CH2_EN_SHIFT 1
596 #define CS42L43_ASP_TX_CH1_EN_MASK 0x00000001
597 #define CS42L43_ASP_TX_CH1_EN_SHIFT 0
599 /* CS42L43_ASP_RX_CH1_CTRL..CS42L43_ASP_TX_CH6_CTRL */
600 #define CS42L43_ASP_CH_WIDTH_MASK 0x001F0000
601 #define CS42L43_ASP_CH_WIDTH_SHIFT 16
602 #define CS42L43_ASP_CH_SLOT_MASK 0x00001FFE
603 #define CS42L43_ASP_CH_SLOT_SHIFT 1
604 #define CS42L43_ASP_CH_SLOT_PHASE_MASK 0x00000001
605 #define CS42L43_ASP_CH_SLOT_PHASE_SHIFT 0
607 /* CS42L43_ASPTX1_INPUT..CS42L43_AMP4MIX_INPUT4 */
608 #define CS42L43_MIXER_VOL_MASK 0x00FE0000
609 #define CS42L43_MIXER_VOL_SHIFT 17
610 #define CS42L43_MIXER_SRC_MASK 0x000001FF
611 #define CS42L43_MIXER_SRC_SHIFT 0
613 /* CS42L43_ASRC_INT_ENABLES */
614 #define CS42L43_ASRC_INT4_EN_MASK 0x00000008
615 #define CS42L43_ASRC_INT4_EN_SHIFT 3
616 #define CS42L43_ASRC_INT3_EN_MASK 0x00000004
617 #define CS42L43_ASRC_INT3_EN_SHIFT 2
618 #define CS42L43_ASRC_INT2_EN_MASK 0x00000002
619 #define CS42L43_ASRC_INT2_EN_SHIFT 1
620 #define CS42L43_ASRC_INT1_EN_MASK 0x00000001
621 #define CS42L43_ASRC_INT1_EN_SHIFT 0
623 /* CS42L43_ASRC_DEC_ENABLES */
624 #define CS42L43_ASRC_DEC4_EN_MASK 0x00000008
625 #define CS42L43_ASRC_DEC4_EN_SHIFT 3
626 #define CS42L43_ASRC_DEC3_EN_MASK 0x00000004
627 #define CS42L43_ASRC_DEC3_EN_SHIFT 2
628 #define CS42L43_ASRC_DEC2_EN_MASK 0x00000002
629 #define CS42L43_ASRC_DEC2_EN_SHIFT 1
630 #define CS42L43_ASRC_DEC1_EN_MASK 0x00000001
631 #define CS42L43_ASRC_DEC1_EN_SHIFT 0
633 /* CS42L43_PDNCNTL */
634 #define CS42L43_RING_SENSE_EN_MASK 0x00000002
635 #define CS42L43_RING_SENSE_EN_SHIFT 1
637 /* CS42L43_RINGSENSE_DEB_CTRL */
638 #define CS42L43_RINGSENSE_INV_MASK 0x00000080
639 #define CS42L43_RINGSENSE_INV_SHIFT 7
640 #define CS42L43_RINGSENSE_PULLUP_PDNB_MASK 0x00000040
641 #define CS42L43_RINGSENSE_PULLUP_PDNB_SHIFT 6
642 #define CS42L43_RINGSENSE_FALLING_DB_TIME_MASK 0x00000038
643 #define CS42L43_RINGSENSE_FALLING_DB_TIME_SHIFT 3
644 #define CS42L43_RINGSENSE_RISING_DB_TIME_MASK 0x00000007
645 #define CS42L43_RINGSENSE_RISING_DB_TIME_SHIFT 0
647 /* CS42L43_TIPSENSE_DEB_CTRL */
648 #define CS42L43_TIPSENSE_INV_MASK 0x00000080
649 #define CS42L43_TIPSENSE_INV_SHIFT 7
650 #define CS42L43_TIPSENSE_FALLING_DB_TIME_MASK 0x00000038
651 #define CS42L43_TIPSENSE_FALLING_DB_TIME_SHIFT 3
652 #define CS42L43_TIPSENSE_RISING_DB_TIME_MASK 0x00000007
653 #define CS42L43_TIPSENSE_RISING_DB_TIME_SHIFT 0
655 /* CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS */
656 #define CS42L43_TIPSENSE_UNPLUG_DB_STS_MASK 0x00000008
657 #define CS42L43_TIPSENSE_UNPLUG_DB_STS_SHIFT 3
658 #define CS42L43_TIPSENSE_PLUG_DB_STS_MASK 0x00000004
659 #define CS42L43_TIPSENSE_PLUG_DB_STS_SHIFT 2
660 #define CS42L43_RINGSENSE_UNPLUG_DB_STS_MASK 0x00000002
661 #define CS42L43_RINGSENSE_UNPLUG_DB_STS_SHIFT 1
662 #define CS42L43_RINGSENSE_PLUG_DB_STS_MASK 0x00000001
663 #define CS42L43_RINGSENSE_PLUG_DB_STS_SHIFT 0
666 #define CS42L43_HS_CLAMP_DISABLE_MASK 0x10000000
667 #define CS42L43_HS_CLAMP_DISABLE_SHIFT 28
668 #define CS42L43_HSBIAS_RAMP_MASK 0x0C000000
669 #define CS42L43_HSBIAS_RAMP_SHIFT 26
670 #define CS42L43_HSDET_MODE_MASK 0x00018000
671 #define CS42L43_HSDET_MODE_SHIFT 15
672 #define CS42L43_HSDET_MANUAL_MODE_MASK 0x00006000
673 #define CS42L43_HSDET_MANUAL_MODE_SHIFT 13
674 #define CS42L43_AUTO_HSDET_TIME_MASK 0x00000700
675 #define CS42L43_AUTO_HSDET_TIME_SHIFT 8
676 #define CS42L43_AMP3_4_GNDREF_HS3_SEL_MASK 0x00000080
677 #define CS42L43_AMP3_4_GNDREF_HS3_SEL_SHIFT 7
678 #define CS42L43_AMP3_4_GNDREF_HS4_SEL_MASK 0x00000040
679 #define CS42L43_AMP3_4_GNDREF_HS4_SEL_SHIFT 6
680 #define CS42L43_HSBIAS_GNDREF_HS3_SEL_MASK 0x00000020
681 #define CS42L43_HSBIAS_GNDREF_HS3_SEL_SHIFT 5
682 #define CS42L43_HSBIAS_GNDREF_HS4_SEL_MASK 0x00000010
683 #define CS42L43_HSBIAS_GNDREF_HS4_SEL_SHIFT 4
684 #define CS42L43_HSBIAS_OUT_HS3_SEL_MASK 0x00000008
685 #define CS42L43_HSBIAS_OUT_HS3_SEL_SHIFT 3
686 #define CS42L43_HSBIAS_OUT_HS4_SEL_MASK 0x00000004
687 #define CS42L43_HSBIAS_OUT_HS4_SEL_SHIFT 2
688 #define CS42L43_HSGND_HS3_SEL_MASK 0x00000002
689 #define CS42L43_HSGND_HS3_SEL_SHIFT 1
690 #define CS42L43_HSGND_HS4_SEL_MASK 0x00000001
691 #define CS42L43_HSGND_HS4_SEL_SHIFT 0
693 /* CS42L43_HS_STAT */
694 #define CS42L43_HSDET_TYPE_STS_MASK 0x00000007
695 #define CS42L43_HSDET_TYPE_STS_SHIFT 0
697 /* CS42L43_MCU_SW_INTERRUPT */
698 #define CS42L43_CONTROL_IND_MASK 0x00000004
699 #define CS42L43_CONTROL_IND_SHIFT 2
700 #define CS42L43_CONFIGS_IND_MASK 0x00000002
701 #define CS42L43_CONFIGS_IND_SHIFT 1
702 #define CS42L43_PATCH_IND_MASK 0x00000001
703 #define CS42L43_PATCH_IND_SHIFT 0
705 /* CS42L43_STEREO_MIC_CTRL */
706 #define CS42L43_HS2_BIAS_SENSE_EN_MASK 0x00000020
707 #define CS42L43_HS2_BIAS_SENSE_EN_SHIFT 5
708 #define CS42L43_HS1_BIAS_SENSE_EN_MASK 0x00000010
709 #define CS42L43_HS1_BIAS_SENSE_EN_SHIFT 4
710 #define CS42L43_HS2_BIAS_EN_MASK 0x00000008
711 #define CS42L43_HS2_BIAS_EN_SHIFT 3
712 #define CS42L43_HS1_BIAS_EN_MASK 0x00000004
713 #define CS42L43_HS1_BIAS_EN_SHIFT 2
714 #define CS42L43_JACK_STEREO_CONFIG_MASK 0x00000003
715 #define CS42L43_JACK_STEREO_CONFIG_SHIFT 0
717 /* CS42L43_STEREO_MIC_CLAMP_CTRL */
718 #define CS42L43_SMIC_HPAMP_CLAMP_DIS_FRC_VAL_MASK 0x00000002
719 #define CS42L43_SMIC_HPAMP_CLAMP_DIS_FRC_VAL_SHIFT 1
720 #define CS42L43_SMIC_HPAMP_CLAMP_DIS_FRC_MASK 0x00000001
721 #define CS42L43_SMIC_HPAMP_CLAMP_DIS_FRC_SHIFT 0
723 /* CS42L43_BLOCK_EN2 */
724 #define CS42L43_SPI_MSTR_EN_MASK 0x00000001
725 #define CS42L43_SPI_MSTR_EN_SHIFT 0
727 /* CS42L43_BLOCK_EN3 */
728 #define CS42L43_PDM2_DIN_R_EN_MASK 0x00000020
729 #define CS42L43_PDM2_DIN_R_EN_SHIFT 5
730 #define CS42L43_PDM2_DIN_L_EN_MASK 0x00000010
731 #define CS42L43_PDM2_DIN_L_EN_SHIFT 4
732 #define CS42L43_PDM1_DIN_R_EN_MASK 0x00000008
733 #define CS42L43_PDM1_DIN_R_EN_SHIFT 3
734 #define CS42L43_PDM1_DIN_L_EN_MASK 0x00000004
735 #define CS42L43_PDM1_DIN_L_EN_SHIFT 2
736 #define CS42L43_ADC2_EN_MASK 0x00000002
737 #define CS42L43_ADC2_EN_SHIFT 1
738 #define CS42L43_ADC1_EN_MASK 0x00000001
739 #define CS42L43_ADC1_EN_SHIFT 0
741 /* CS42L43_BLOCK_EN4 */
742 #define CS42L43_ASRC_DEC_BANK_EN_MASK 0x00000002
743 #define CS42L43_ASRC_DEC_BANK_EN_SHIFT 1
744 #define CS42L43_ASRC_INT_BANK_EN_MASK 0x00000001
745 #define CS42L43_ASRC_INT_BANK_EN_SHIFT 0
747 /* CS42L43_BLOCK_EN5 */
748 #define CS42L43_ISRC2_BANK_EN_MASK 0x00000002
749 #define CS42L43_ISRC2_BANK_EN_SHIFT 1
750 #define CS42L43_ISRC1_BANK_EN_MASK 0x00000001
751 #define CS42L43_ISRC1_BANK_EN_SHIFT 0
753 /* CS42L43_BLOCK_EN6 */
754 #define CS42L43_MIXER_EN_MASK 0x00000001
755 #define CS42L43_MIXER_EN_SHIFT 0
757 /* CS42L43_BLOCK_EN7 */
758 #define CS42L43_EQ_EN_MASK 0x00000001
759 #define CS42L43_EQ_EN_SHIFT 0
761 /* CS42L43_BLOCK_EN8 */
762 #define CS42L43_HP_EN_MASK 0x00000001
763 #define CS42L43_HP_EN_SHIFT 0
765 /* CS42L43_BLOCK_EN9 */
766 #define CS42L43_TONE_EN_MASK 0x00000001
767 #define CS42L43_TONE_EN_SHIFT 0
769 /* CS42L43_BLOCK_EN10 */
770 #define CS42L43_AMP2_EN_MASK 0x00000002
771 #define CS42L43_AMP2_EN_SHIFT 1
772 #define CS42L43_AMP1_EN_MASK 0x00000001
773 #define CS42L43_AMP1_EN_SHIFT 0
775 /* CS42L43_BLOCK_EN11 */
776 #define CS42L43_SPDIF_EN_MASK 0x00000001
777 #define CS42L43_SPDIF_EN_SHIFT 0
779 /* CS42L43_TONE_CH1_CTRL..CS42L43_TONE_CH2_CTRL */
780 #define CS42L43_TONE_FREQ_MASK 0x00000070
781 #define CS42L43_TONE_FREQ_SHIFT 4
782 #define CS42L43_TONE_SEL_MASK 0x0000000F
783 #define CS42L43_TONE_SEL_SHIFT 0
785 /* CS42L43_MIC_DETECT_CONTROL_1 */
786 #define CS42L43_BUTTON_DETECT_MODE_MASK 0x00000018
787 #define CS42L43_BUTTON_DETECT_MODE_SHIFT 3
788 #define CS42L43_HSBIAS_MODE_MASK 0x00000006
789 #define CS42L43_HSBIAS_MODE_SHIFT 1
790 #define CS42L43_MIC_LVL_DET_DISABLE_MASK 0x00000001
791 #define CS42L43_MIC_LVL_DET_DISABLE_SHIFT 0
793 /* CS42L43_DETECT_STATUS_1 */
794 #define CS42L43_HSDET_DC_STS_MASK 0x01FF0000
795 #define CS42L43_HSDET_DC_STS_SHIFT 16
796 #define CS42L43_JACKDET_STS_MASK 0x00000080
797 #define CS42L43_JACKDET_STS_SHIFT 7
798 #define CS42L43_HSBIAS_CLAMP_STS_MASK 0x00000040
799 #define CS42L43_HSBIAS_CLAMP_STS_SHIFT 6
801 /* CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL */
802 #define CS42L43_JACKDET_MODE_MASK 0xC0000000
803 #define CS42L43_JACKDET_MODE_SHIFT 30
804 #define CS42L43_JACKDET_INV_MASK 0x20000000
805 #define CS42L43_JACKDET_INV_SHIFT 29
806 #define CS42L43_JACKDET_DB_TIME_MASK 0x03000000
807 #define CS42L43_JACKDET_DB_TIME_SHIFT 24
808 #define CS42L43_S0_AUTO_ADCMUTE_DISABLE_MASK 0x00800000
809 #define CS42L43_S0_AUTO_ADCMUTE_DISABLE_SHIFT 23
810 #define CS42L43_HSBIAS_SENSE_EN_MASK 0x00000080
811 #define CS42L43_HSBIAS_SENSE_EN_SHIFT 7
812 #define CS42L43_AUTO_HSBIAS_CLAMP_EN_MASK 0x00000040
813 #define CS42L43_AUTO_HSBIAS_CLAMP_EN_SHIFT 6
814 #define CS42L43_JACKDET_SENSE_EN_MASK 0x00000020
815 #define CS42L43_JACKDET_SENSE_EN_SHIFT 5
816 #define CS42L43_HSBIAS_SENSE_TRIP_MASK 0x00000007
817 #define CS42L43_HSBIAS_SENSE_TRIP_SHIFT 0
819 /* CS42L43_MIC_DETECT_CONTROL_ANDROID */
820 #define CS42L43_HSDET_LVL_COMBWIDTH_MASK 0xC0000000
821 #define CS42L43_HSDET_LVL_COMBWIDTH_SHIFT 30
822 #define CS42L43_HSDET_LVL2_THRESH_MASK 0x01FF0000
823 #define CS42L43_HSDET_LVL2_THRESH_SHIFT 16
824 #define CS42L43_HSDET_LVL1_THRESH_MASK 0x000001FF
825 #define CS42L43_HSDET_LVL1_THRESH_SHIFT 0
827 /* CS42L43_ISRC1_CTRL..CS42L43_ISRC2_CTRL */
828 #define CS42L43_ISRC_INT2_EN_MASK 0x00000200
829 #define CS42L43_ISRC_INT2_EN_SHIFT 9
830 #define CS42L43_ISRC_INT1_EN_MASK 0x00000100
831 #define CS42L43_ISRC_INT1_EN_SHIFT 8
832 #define CS42L43_ISRC_DEC2_EN_MASK 0x00000002
833 #define CS42L43_ISRC_DEC2_EN_SHIFT 1
834 #define CS42L43_ISRC_DEC1_EN_MASK 0x00000001
835 #define CS42L43_ISRC_DEC1_EN_SHIFT 0
837 /* CS42L43_CTRL_REG */
838 #define CS42L43_PLL_MODE_BYPASS_500_MASK 0x00000004
839 #define CS42L43_PLL_MODE_BYPASS_500_SHIFT 2
840 #define CS42L43_PLL_MODE_BYPASS_1029_MASK 0x00000002
841 #define CS42L43_PLL_MODE_BYPASS_1029_SHIFT 1
842 #define CS42L43_PLL_EN_MASK 0x00000001
843 #define CS42L43_PLL_EN_SHIFT 0
845 /* CS42L43_FDIV_FRAC */
846 #define CS42L43_PLL_DIV_INT_MASK 0xFF000000
847 #define CS42L43_PLL_DIV_INT_SHIFT 24
848 #define CS42L43_PLL_DIV_FRAC_BYTE2_MASK 0x00FF0000
849 #define CS42L43_PLL_DIV_FRAC_BYTE2_SHIFT 16
850 #define CS42L43_PLL_DIV_FRAC_BYTE1_MASK 0x0000FF00
851 #define CS42L43_PLL_DIV_FRAC_BYTE1_SHIFT 8
852 #define CS42L43_PLL_DIV_FRAC_BYTE0_MASK 0x000000FF
853 #define CS42L43_PLL_DIV_FRAC_BYTE0_SHIFT 0
855 /* CS42L43_CAL_RATIO */
856 #define CS42L43_PLL_CAL_RATIO_MASK 0x000000FF
857 #define CS42L43_PLL_CAL_RATIO_SHIFT 0
859 /* CS42L43_SPI_CLK_CONFIG1 */
860 #define CS42L43_SCLK_DIV_MASK 0x0000000F
861 #define CS42L43_SCLK_DIV_SHIFT 0
863 /* CS42L43_SPI_CONFIG1 */
864 #define CS42L43_SPI_SS_IDLE_DUR_MASK 0x0F000000
865 #define CS42L43_SPI_SS_IDLE_DUR_SHIFT 24
866 #define CS42L43_SPI_SS_DELAY_DUR_MASK 0x000F0000
867 #define CS42L43_SPI_SS_DELAY_DUR_SHIFT 16
868 #define CS42L43_SPI_THREE_WIRE_MASK 0x00000100
869 #define CS42L43_SPI_THREE_WIRE_SHIFT 8
870 #define CS42L43_SPI_DPHA_MASK 0x00000040
871 #define CS42L43_SPI_DPHA_SHIFT 6
872 #define CS42L43_SPI_CPHA_MASK 0x00000020
873 #define CS42L43_SPI_CPHA_SHIFT 5
874 #define CS42L43_SPI_CPOL_MASK 0x00000010
875 #define CS42L43_SPI_CPOL_SHIFT 4
876 #define CS42L43_SPI_SS_SEL_MASK 0x00000007
877 #define CS42L43_SPI_SS_SEL_SHIFT 0
879 /* CS42L43_SPI_CONFIG2 */
880 #define CS42L43_SPI_SS_FRC_MASK 0x00000001
881 #define CS42L43_SPI_SS_FRC_SHIFT 0
883 /* CS42L43_SPI_CONFIG3 */
884 #define CS42L43_SPI_WDT_ENA_MASK 0x00000001
885 #define CS42L43_SPI_WDT_ENA_SHIFT 0
887 /* CS42L43_SPI_CONFIG4 */
888 #define CS42L43_SPI_STALL_ENA_MASK 0x00010000
889 #define CS42L43_SPI_STALL_ENA_SHIFT 16
891 /* CS42L43_SPI_STATUS1 */
892 #define CS42L43_SPI_ABORT_STS_MASK 0x00000002
893 #define CS42L43_SPI_ABORT_STS_SHIFT 1
894 #define CS42L43_SPI_DONE_STS_MASK 0x00000001
895 #define CS42L43_SPI_DONE_STS_SHIFT 0
897 /* CS42L43_SPI_STATUS2 */
898 #define CS42L43_SPI_RX_DONE_STS_MASK 0x00000010
899 #define CS42L43_SPI_RX_DONE_STS_SHIFT 4
900 #define CS42L43_SPI_TX_DONE_STS_MASK 0x00000001
901 #define CS42L43_SPI_TX_DONE_STS_SHIFT 0
903 /* CS42L43_TRAN_CONFIG1 */
904 #define CS42L43_SPI_START_MASK 0x00000001
905 #define CS42L43_SPI_START_SHIFT 0
907 /* CS42L43_TRAN_CONFIG2 */
908 #define CS42L43_SPI_ABORT_MASK 0x00000001
909 #define CS42L43_SPI_ABORT_SHIFT 0
911 /* CS42L43_TRAN_CONFIG3 */
912 #define CS42L43_SPI_WORD_SIZE_MASK 0x00070000
913 #define CS42L43_SPI_WORD_SIZE_SHIFT 16
914 #define CS42L43_SPI_CMD_MASK 0x00000003
915 #define CS42L43_SPI_CMD_SHIFT 0
917 /* CS42L43_TRAN_CONFIG4 */
918 #define CS42L43_SPI_TX_LENGTH_MASK 0x0000FFFF
919 #define CS42L43_SPI_TX_LENGTH_SHIFT 0
921 /* CS42L43_TRAN_CONFIG5 */
922 #define CS42L43_SPI_RX_LENGTH_MASK 0x0000FFFF
923 #define CS42L43_SPI_RX_LENGTH_SHIFT 0
925 /* CS42L43_TRAN_CONFIG6 */
926 #define CS42L43_SPI_TX_BLOCK_LENGTH_MASK 0x0000000F
927 #define CS42L43_SPI_TX_BLOCK_LENGTH_SHIFT 0
929 /* CS42L43_TRAN_CONFIG7 */
930 #define CS42L43_SPI_RX_BLOCK_LENGTH_MASK 0x0000000F
931 #define CS42L43_SPI_RX_BLOCK_LENGTH_SHIFT 0
933 /* CS42L43_TRAN_CONFIG8 */
934 #define CS42L43_SPI_RX_DONE_MASK 0x00000010
935 #define CS42L43_SPI_RX_DONE_SHIFT 4
936 #define CS42L43_SPI_TX_DONE_MASK 0x00000001
937 #define CS42L43_SPI_TX_DONE_SHIFT 0
939 /* CS42L43_TRAN_STATUS1 */
940 #define CS42L43_SPI_BUSY_STS_MASK 0x00000100
941 #define CS42L43_SPI_BUSY_STS_SHIFT 8
942 #define CS42L43_SPI_RX_REQUEST_MASK 0x00000010
943 #define CS42L43_SPI_RX_REQUEST_SHIFT 4
944 #define CS42L43_SPI_TX_REQUEST_MASK 0x00000001
945 #define CS42L43_SPI_TX_REQUEST_SHIFT 0
947 /* CS42L43_TRAN_STATUS2 */
948 #define CS42L43_SPI_TX_BYTE_COUNT_MASK 0x0000FFFF
949 #define CS42L43_SPI_TX_BYTE_COUNT_SHIFT 0
951 /* CS42L43_TRAN_STATUS3 */
952 #define CS42L43_SPI_RX_BYTE_COUNT_MASK 0x0000FFFF
953 #define CS42L43_SPI_RX_BYTE_COUNT_SHIFT 0
955 /* CS42L43_TX_DATA */
956 #define CS42L43_SPI_TX_DATA_MASK 0xFFFFFFFF
957 #define CS42L43_SPI_TX_DATA_SHIFT 0
959 /* CS42L43_RX_DATA */
960 #define CS42L43_SPI_RX_DATA_MASK 0xFFFFFFFF
961 #define CS42L43_SPI_RX_DATA_SHIFT 0
963 /* CS42L43_DACCNFG1 */
964 #define CS42L43_HP_MSTR_VOL_CTRL_EN_MASK 0x00000008
965 #define CS42L43_HP_MSTR_VOL_CTRL_EN_SHIFT 3
966 #define CS42L43_AMP4_INV_MASK 0x00000002
967 #define CS42L43_AMP4_INV_SHIFT 1
968 #define CS42L43_AMP3_INV_MASK 0x00000001
969 #define CS42L43_AMP3_INV_SHIFT 0
971 /* CS42L43_DACCNFG2 */
972 #define CS42L43_HP_AUTO_CLAMP_DISABLE_MASK 0x00000002
973 #define CS42L43_HP_AUTO_CLAMP_DISABLE_SHIFT 1
974 #define CS42L43_HP_HPF_EN_MASK 0x00000001
975 #define CS42L43_HP_HPF_EN_SHIFT 0
977 /* CS42L43_HPPATHVOL */
978 #define CS42L43_AMP4_PATH_VOL_MASK 0x01FF0000
979 #define CS42L43_AMP4_PATH_VOL_SHIFT 16
980 #define CS42L43_AMP3_PATH_VOL_MASK 0x000001FF
981 #define CS42L43_AMP3_PATH_VOL_SHIFT 0
984 #define CS42L43_HP_PATH_VOL_RAMP_MASK 0x0003C000
985 #define CS42L43_HP_PATH_VOL_RAMP_SHIFT 14
986 #define CS42L43_HP_PATH_VOL_ZC_MASK 0x00002000
987 #define CS42L43_HP_PATH_VOL_ZC_SHIFT 13
988 #define CS42L43_HP_PATH_VOL_SFT_MASK 0x00001000
989 #define CS42L43_HP_PATH_VOL_SFT_SHIFT 12
990 #define CS42L43_HP_DIG_VOL_RAMP_MASK 0x00000F00
991 #define CS42L43_HP_DIG_VOL_RAMP_SHIFT 8
992 #define CS42L43_HP_ANA_VOL_RAMP_MASK 0x0000000F
993 #define CS42L43_HP_ANA_VOL_RAMP_SHIFT 0
995 /* CS42L43_LOADDETRESULTS */
996 #define CS42L43_AMP3_RES_DET_MASK 0x00000003
997 #define CS42L43_AMP3_RES_DET_SHIFT 0
999 /* CS42L43_LOADDETENA */
1000 #define CS42L43_HPLOAD_DET_EN_MASK 0x00000001
1001 #define CS42L43_HPLOAD_DET_EN_SHIFT 0
1004 #define CS42L43_ADPTPWR_MODE_MASK 0x00000007
1005 #define CS42L43_ADPTPWR_MODE_SHIFT 0
1007 /* CS42L43_COEFF_RD_WR0 */
1008 #define CS42L43_WRITE_MODE_MASK 0x00000002
1009 #define CS42L43_WRITE_MODE_SHIFT 1
1011 /* CS42L43_INIT_DONE0 */
1012 #define CS42L43_INITIALIZE_DONE_MASK 0x00000001
1013 #define CS42L43_INITIALIZE_DONE_SHIFT 0
1015 /* CS42L43_START_EQZ0 */
1016 #define CS42L43_START_FILTER_MASK 0x00000001
1017 #define CS42L43_START_FILTER_SHIFT 0
1019 /* CS42L43_MUTE_EQ_IN0 */
1020 #define CS42L43_MUTE_EQ_CH2_MASK 0x00000002
1021 #define CS42L43_MUTE_EQ_CH2_SHIFT 1
1022 #define CS42L43_MUTE_EQ_CH1_MASK 0x00000001
1023 #define CS42L43_MUTE_EQ_CH1_SHIFT 0
1025 /* CS42L43_PLL_INT */
1026 #define CS42L43_PLL_LOST_LOCK_INT_MASK 0x00000002
1027 #define CS42L43_PLL_LOST_LOCK_INT_SHIFT 1
1028 #define CS42L43_PLL_READY_INT_MASK 0x00000001
1029 #define CS42L43_PLL_READY_INT_SHIFT 0
1031 /* CS42L43_SOFT_INT */
1032 #define CS42L43_CONTROL_APPLIED_INT_MASK 0x00000010
1033 #define CS42L43_CONTROL_APPLIED_INT_SHIFT 4
1034 #define CS42L43_CONTROL_WARN_INT_MASK 0x00000008
1035 #define CS42L43_CONTROL_WARN_INT_SHIFT 3
1036 #define CS42L43_PATCH_WARN_INT_MASK 0x00000002
1037 #define CS42L43_PATCH_WARN_INT_SHIFT 1
1038 #define CS42L43_PATCH_APPLIED_INT_MASK 0x00000001
1039 #define CS42L43_PATCH_APPLIED_INT_SHIFT 0
1041 /* CS42L43_MSM_INT */
1042 #define CS42L43_HP_STARTUP_DONE_INT_MASK 0x00000800
1043 #define CS42L43_HP_STARTUP_DONE_INT_SHIFT 11
1044 #define CS42L43_HP_SHUTDOWN_DONE_INT_MASK 0x00000400
1045 #define CS42L43_HP_SHUTDOWN_DONE_INT_SHIFT 10
1046 #define CS42L43_HSDET_DONE_INT_MASK 0x00000200
1047 #define CS42L43_HSDET_DONE_INT_SHIFT 9
1048 #define CS42L43_TIPSENSE_UNPLUG_DB_INT_MASK 0x00000080
1049 #define CS42L43_TIPSENSE_UNPLUG_DB_INT_SHIFT 7
1050 #define CS42L43_TIPSENSE_PLUG_DB_INT_MASK 0x00000040
1051 #define CS42L43_TIPSENSE_PLUG_DB_INT_SHIFT 6
1052 #define CS42L43_RINGSENSE_UNPLUG_DB_INT_MASK 0x00000020
1053 #define CS42L43_RINGSENSE_UNPLUG_DB_INT_SHIFT 5
1054 #define CS42L43_RINGSENSE_PLUG_DB_INT_MASK 0x00000010
1055 #define CS42L43_RINGSENSE_PLUG_DB_INT_SHIFT 4
1056 #define CS42L43_TIPSENSE_UNPLUG_PDET_INT_MASK 0x00000008
1057 #define CS42L43_TIPSENSE_UNPLUG_PDET_INT_SHIFT 3
1058 #define CS42L43_TIPSENSE_PLUG_PDET_INT_MASK 0x00000004
1059 #define CS42L43_TIPSENSE_PLUG_PDET_INT_SHIFT 2
1060 #define CS42L43_RINGSENSE_UNPLUG_PDET_INT_MASK 0x00000002
1061 #define CS42L43_RINGSENSE_UNPLUG_PDET_INT_SHIFT 1
1062 #define CS42L43_RINGSENSE_PLUG_PDET_INT_MASK 0x00000001
1063 #define CS42L43_RINGSENSE_PLUG_PDET_INT_SHIFT 0
1065 /* CS42L43_ACC_DET_INT */
1066 #define CS42L43_HS2_BIAS_SENSE_INT_MASK 0x00000800
1067 #define CS42L43_HS2_BIAS_SENSE_INT_SHIFT 11
1068 #define CS42L43_HS1_BIAS_SENSE_INT_MASK 0x00000400
1069 #define CS42L43_HS1_BIAS_SENSE_INT_SHIFT 10
1070 #define CS42L43_DC_DETECT1_FALSE_INT_MASK 0x00000080
1071 #define CS42L43_DC_DETECT1_FALSE_INT_SHIFT 7
1072 #define CS42L43_DC_DETECT1_TRUE_INT_MASK 0x00000040
1073 #define CS42L43_DC_DETECT1_TRUE_INT_SHIFT 6
1074 #define CS42L43_HSBIAS_CLAMPED_INT_MASK 0x00000008
1075 #define CS42L43_HSBIAS_CLAMPED_INT_SHIFT 3
1076 #define CS42L43_HS3_4_BIAS_SENSE_INT_MASK 0x00000001
1077 #define CS42L43_HS3_4_BIAS_SENSE_INT_SHIFT 0
1079 /* CS42L43_SPI_MSTR_INT */
1080 #define CS42L43_IRQ_SPI_STALLING_INT_MASK 0x00000004
1081 #define CS42L43_IRQ_SPI_STALLING_INT_SHIFT 2
1082 #define CS42L43_IRQ_SPI_STS_INT_MASK 0x00000002
1083 #define CS42L43_IRQ_SPI_STS_INT_SHIFT 1
1084 #define CS42L43_IRQ_SPI_BLOCK_INT_MASK 0x00000001
1085 #define CS42L43_IRQ_SPI_BLOCK_INT_SHIFT 0
1087 /* CS42L43_SW_TO_SPI_BRIDGE_INT */
1088 #define CS42L43_SW2SPI_BUF_OVF_UDF_INT_MASK 0x00000001
1089 #define CS42L43_SW2SPI_BUF_OVF_UDF_INT_SHIFT 0
1091 /* CS42L43_CLASS_D_AMP_INT */
1092 #define CS42L43_AMP2_CLK_STOP_FAULT_INT_MASK 0x00002000
1093 #define CS42L43_AMP2_CLK_STOP_FAULT_INT_SHIFT 13
1094 #define CS42L43_AMP1_CLK_STOP_FAULT_INT_MASK 0x00001000
1095 #define CS42L43_AMP1_CLK_STOP_FAULT_INT_SHIFT 12
1096 #define CS42L43_AMP2_VDDSPK_FAULT_INT_MASK 0x00000800
1097 #define CS42L43_AMP2_VDDSPK_FAULT_INT_SHIFT 11
1098 #define CS42L43_AMP1_VDDSPK_FAULT_INT_MASK 0x00000400
1099 #define CS42L43_AMP1_VDDSPK_FAULT_INT_SHIFT 10
1100 #define CS42L43_AMP2_SHUTDOWN_DONE_INT_MASK 0x00000200
1101 #define CS42L43_AMP2_SHUTDOWN_DONE_INT_SHIFT 9
1102 #define CS42L43_AMP1_SHUTDOWN_DONE_INT_MASK 0x00000100
1103 #define CS42L43_AMP1_SHUTDOWN_DONE_INT_SHIFT 8
1104 #define CS42L43_AMP2_STARTUP_DONE_INT_MASK 0x00000080
1105 #define CS42L43_AMP2_STARTUP_DONE_INT_SHIFT 7
1106 #define CS42L43_AMP1_STARTUP_DONE_INT_MASK 0x00000040
1107 #define CS42L43_AMP1_STARTUP_DONE_INT_SHIFT 6
1108 #define CS42L43_AMP2_THERM_SHDN_INT_MASK 0x00000020
1109 #define CS42L43_AMP2_THERM_SHDN_INT_SHIFT 5
1110 #define CS42L43_AMP1_THERM_SHDN_INT_MASK 0x00000010
1111 #define CS42L43_AMP1_THERM_SHDN_INT_SHIFT 4
1112 #define CS42L43_AMP2_THERM_WARN_INT_MASK 0x00000008
1113 #define CS42L43_AMP2_THERM_WARN_INT_SHIFT 3
1114 #define CS42L43_AMP1_THERM_WARN_INT_MASK 0x00000004
1115 #define CS42L43_AMP1_THERM_WARN_INT_SHIFT 2
1116 #define CS42L43_AMP2_SCDET_INT_MASK 0x00000002
1117 #define CS42L43_AMP2_SCDET_INT_SHIFT 1
1118 #define CS42L43_AMP1_SCDET_INT_MASK 0x00000001
1119 #define CS42L43_AMP1_SCDET_INT_SHIFT 0
1121 /* CS42L43_GPIO_INT */
1122 #define CS42L43_GPIO3_FALL_INT_MASK 0x00000020
1123 #define CS42L43_GPIO3_FALL_INT_SHIFT 5
1124 #define CS42L43_GPIO3_RISE_INT_MASK 0x00000010
1125 #define CS42L43_GPIO3_RISE_INT_SHIFT 4
1126 #define CS42L43_GPIO2_FALL_INT_MASK 0x00000008
1127 #define CS42L43_GPIO2_FALL_INT_SHIFT 3
1128 #define CS42L43_GPIO2_RISE_INT_MASK 0x00000004
1129 #define CS42L43_GPIO2_RISE_INT_SHIFT 2
1130 #define CS42L43_GPIO1_FALL_INT_MASK 0x00000002
1131 #define CS42L43_GPIO1_FALL_INT_SHIFT 1
1132 #define CS42L43_GPIO1_RISE_INT_MASK 0x00000001
1133 #define CS42L43_GPIO1_RISE_INT_SHIFT 0
1135 /* CS42L43_HPOUT_INT */
1136 #define CS42L43_HP_ILIMIT_INT_MASK 0x00000002
1137 #define CS42L43_HP_ILIMIT_INT_SHIFT 1
1138 #define CS42L43_HP_LOADDET_DONE_INT_MASK 0x00000001
1139 #define CS42L43_HP_LOADDET_DONE_INT_SHIFT 0
1141 /* CS42L43_BOOT_CONTROL */
1142 #define CS42L43_LOCK_HW_STS_MASK 0x00000002
1143 #define CS42L43_LOCK_HW_STS_SHIFT 1
1145 /* CS42L43_BLOCK_EN */
1146 #define CS42L43_MCU_EN_MASK 0x00000001
1147 #define CS42L43_MCU_EN_SHIFT 0
1149 /* CS42L43_SHUTTER_CONTROL */
1150 #define CS42L43_STATUS_SPK_SHUTTER_MUTE_MASK 0x00008000
1151 #define CS42L43_STATUS_SPK_SHUTTER_MUTE_SHIFT 15
1152 #define CS42L43_SPK_SHUTTER_CFG_MASK 0x00000F00
1153 #define CS42L43_SPK_SHUTTER_CFG_SHIFT 8
1154 #define CS42L43_STATUS_MIC_SHUTTER_MUTE_MASK 0x00000080
1155 #define CS42L43_STATUS_MIC_SHUTTER_MUTE_SHIFT 7
1156 #define CS42L43_MIC_SHUTTER_CFG_MASK 0x0000000F
1157 #define CS42L43_MIC_SHUTTER_CFG_SHIFT 0
1159 /* CS42L43_MCU_SW_REV */
1160 #define CS42L43_BIOS_SUBMINOR_REV_MASK 0xFF000000
1161 #define CS42L43_BIOS_SUBMINOR_REV_SHIFT 24
1162 #define CS42L43_BIOS_MINOR_REV_MASK 0x00F00000
1163 #define CS42L43_BIOS_MINOR_REV_SHIFT 20
1164 #define CS42L43_BIOS_MAJOR_REV_MASK 0x000F0000
1165 #define CS42L43_BIOS_MAJOR_REV_SHIFT 16
1166 #define CS42L43_FW_SUBMINOR_REV_MASK 0x0000FF00
1167 #define CS42L43_FW_SUBMINOR_REV_SHIFT 8
1168 #define CS42L43_FW_MINOR_REV_MASK 0x000000F0
1169 #define CS42L43_FW_MINOR_REV_SHIFT 4
1170 #define CS42L43_FW_MAJOR_REV_MASK 0x0000000F
1171 #define CS42L43_FW_MAJOR_REV_SHIFT 0
1173 /* CS42L43_NEED_CONFIGS */
1174 #define CS42L43_FW_PATCH_NEED_CFG_MASK 0x80000000
1175 #define CS42L43_FW_PATCH_NEED_CFG_SHIFT 31
1177 /* CS42L43_FW_MISSION_CTRL_MM_CTRL_SELECTION */
1178 #define CS42L43_FW_MM_CTRL_MCU_SEL_MASK 0x00000001
1179 #define CS42L43_FW_MM_CTRL_MCU_SEL_SHIFT 0
1181 /* CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG */
1182 #define CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_DISABLE_VAL 0xF05AA50F
1184 #endif /* CS42L43_CORE_REGS_H */
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