5 * Please do not include this file in generic code. There is currently
6 * no requirement for any architecture to implement anything held
12 #include <linux/smp.h>
13 #include <linux/linkage.h>
14 #include <linux/cache.h>
15 #include <linux/spinlock.h>
16 #include <linux/cpumask.h>
17 #include <linux/gfp.h>
18 #include <linux/irqhandler.h>
19 #include <linux/irqreturn.h>
20 #include <linux/irqnr.h>
21 #include <linux/errno.h>
22 #include <linux/topology.h>
23 #include <linux/wait.h>
27 #include <asm/ptrace.h>
28 #include <asm/irq_regs.h>
33 enum irqchip_irq_state;
38 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
40 * IRQ_TYPE_NONE - default, unspecified type
41 * IRQ_TYPE_EDGE_RISING - rising edge triggered
42 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
43 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
44 * IRQ_TYPE_LEVEL_HIGH - high level triggered
45 * IRQ_TYPE_LEVEL_LOW - low level triggered
46 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
47 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
48 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
49 * to setup the HW to a sane default (used
50 * by irqdomain map() callbacks to synchronize
51 * the HW state and SW flags for a newly
52 * allocated descriptor).
54 * IRQ_TYPE_PROBE - Special flag for probing in progress
56 * Bits which can be modified via irq_set/clear/modify_status_flags()
57 * IRQ_LEVEL - Interrupt is level type. Will be also
58 * updated in the code when the above trigger
59 * bits are modified via irq_set_irq_type()
60 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
61 * it from affinity setting
62 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
63 * IRQ_NOREQUEST - Interrupt cannot be requested via
65 * IRQ_NOTHREAD - Interrupt cannot be threaded
66 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
68 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
69 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
70 * IRQ_NESTED_THREAD - Interrupt nests into another thread
71 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
72 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
73 * it from the spurious interrupt detection
74 * mechanism and from core side polling.
75 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable
78 IRQ_TYPE_NONE = 0x00000000,
79 IRQ_TYPE_EDGE_RISING = 0x00000001,
80 IRQ_TYPE_EDGE_FALLING = 0x00000002,
81 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
82 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
83 IRQ_TYPE_LEVEL_LOW = 0x00000008,
84 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
85 IRQ_TYPE_SENSE_MASK = 0x0000000f,
86 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
88 IRQ_TYPE_PROBE = 0x00000010,
91 IRQ_PER_CPU = (1 << 9),
92 IRQ_NOPROBE = (1 << 10),
93 IRQ_NOREQUEST = (1 << 11),
94 IRQ_NOAUTOEN = (1 << 12),
95 IRQ_NO_BALANCING = (1 << 13),
96 IRQ_MOVE_PCNTXT = (1 << 14),
97 IRQ_NESTED_THREAD = (1 << 15),
98 IRQ_NOTHREAD = (1 << 16),
99 IRQ_PER_CPU_DEVID = (1 << 17),
100 IRQ_IS_POLLED = (1 << 18),
101 IRQ_DISABLE_UNLAZY = (1 << 19),
104 #define IRQF_MODIFY_MASK \
105 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
106 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
107 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
108 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY)
110 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
113 * Return value for chip->irq_set_affinity()
115 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity
116 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity
117 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
118 * support stacked irqchips, which indicates skipping
119 * all descendent irqchips.
123 IRQ_SET_MASK_OK_NOCOPY,
124 IRQ_SET_MASK_OK_DONE,
131 * struct irq_common_data - per irq data shared by all irqchips
132 * @state_use_accessors: status information for irq chip functions.
133 * Use accessor functions to deal with it
134 * @node: node index useful for balancing
135 * @handler_data: per-IRQ data for the irq_chip methods
136 * @affinity: IRQ affinity on SMP. If this is an IPI
137 * related irq, then this is the mask of the
138 * CPUs to which an IPI can be sent.
139 * @msi_desc: MSI descriptor
140 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional.
142 struct irq_common_data {
143 unsigned int __private state_use_accessors;
148 struct msi_desc *msi_desc;
149 cpumask_var_t affinity;
150 #ifdef CONFIG_GENERIC_IRQ_IPI
151 unsigned int ipi_offset;
156 * struct irq_data - per irq chip data passed down to chip functions
157 * @mask: precomputed bitmask for accessing the chip registers
158 * @irq: interrupt number
159 * @hwirq: hardware interrupt number, local to the interrupt domain
160 * @common: point to data shared by all irqchips
161 * @chip: low level interrupt hardware access
162 * @domain: Interrupt translation domain; responsible for mapping
163 * between hwirq number and linux irq number.
164 * @parent_data: pointer to parent struct irq_data to support hierarchy
166 * @chip_data: platform-specific per-chip private data for the chip
167 * methods, to allow shared chip implementations
173 struct irq_common_data *common;
174 struct irq_chip *chip;
175 struct irq_domain *domain;
176 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
177 struct irq_data *parent_data;
183 * Bit masks for irq_common_data.state_use_accessors
185 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
186 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
187 * IRQD_ACTIVATED - Interrupt has already been activated
188 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
189 * IRQD_PER_CPU - Interrupt is per cpu
190 * IRQD_AFFINITY_SET - Interrupt affinity was set
191 * IRQD_LEVEL - Interrupt is level triggered
192 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
194 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
196 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
197 * IRQD_IRQ_MASKED - Masked state of the interrupt
198 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
199 * IRQD_WAKEUP_ARMED - Wakeup mode armed
200 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU
201 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel
204 IRQD_TRIGGER_MASK = 0xf,
205 IRQD_SETAFFINITY_PENDING = (1 << 8),
206 IRQD_ACTIVATED = (1 << 9),
207 IRQD_NO_BALANCING = (1 << 10),
208 IRQD_PER_CPU = (1 << 11),
209 IRQD_AFFINITY_SET = (1 << 12),
210 IRQD_LEVEL = (1 << 13),
211 IRQD_WAKEUP_STATE = (1 << 14),
212 IRQD_MOVE_PCNTXT = (1 << 15),
213 IRQD_IRQ_DISABLED = (1 << 16),
214 IRQD_IRQ_MASKED = (1 << 17),
215 IRQD_IRQ_INPROGRESS = (1 << 18),
216 IRQD_WAKEUP_ARMED = (1 << 19),
217 IRQD_FORWARDED_TO_VCPU = (1 << 20),
218 IRQD_AFFINITY_MANAGED = (1 << 21),
219 IRQD_IRQ_STARTED = (1 << 22),
222 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
224 static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
226 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING;
229 static inline bool irqd_is_per_cpu(struct irq_data *d)
231 return __irqd_to_state(d) & IRQD_PER_CPU;
234 static inline bool irqd_can_balance(struct irq_data *d)
236 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING));
239 static inline bool irqd_affinity_was_set(struct irq_data *d)
241 return __irqd_to_state(d) & IRQD_AFFINITY_SET;
244 static inline void irqd_mark_affinity_was_set(struct irq_data *d)
246 __irqd_to_state(d) |= IRQD_AFFINITY_SET;
249 static inline u32 irqd_get_trigger_type(struct irq_data *d)
251 return __irqd_to_state(d) & IRQD_TRIGGER_MASK;
255 * Must only be called inside irq_chip.irq_set_type() functions.
257 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
259 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK;
260 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK;
263 static inline bool irqd_is_level_type(struct irq_data *d)
265 return __irqd_to_state(d) & IRQD_LEVEL;
268 static inline bool irqd_is_wakeup_set(struct irq_data *d)
270 return __irqd_to_state(d) & IRQD_WAKEUP_STATE;
273 static inline bool irqd_can_move_in_process_context(struct irq_data *d)
275 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT;
278 static inline bool irqd_irq_disabled(struct irq_data *d)
280 return __irqd_to_state(d) & IRQD_IRQ_DISABLED;
283 static inline bool irqd_irq_masked(struct irq_data *d)
285 return __irqd_to_state(d) & IRQD_IRQ_MASKED;
288 static inline bool irqd_irq_inprogress(struct irq_data *d)
290 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS;
293 static inline bool irqd_is_wakeup_armed(struct irq_data *d)
295 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED;
298 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d)
300 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU;
303 static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d)
305 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU;
308 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d)
310 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU;
313 static inline bool irqd_affinity_is_managed(struct irq_data *d)
315 return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED;
318 static inline bool irqd_is_activated(struct irq_data *d)
320 return __irqd_to_state(d) & IRQD_ACTIVATED;
323 static inline void irqd_set_activated(struct irq_data *d)
325 __irqd_to_state(d) |= IRQD_ACTIVATED;
328 static inline void irqd_clr_activated(struct irq_data *d)
330 __irqd_to_state(d) &= ~IRQD_ACTIVATED;
333 static inline bool irqd_is_started(struct irq_data *d)
335 return __irqd_to_state(d) & IRQD_IRQ_STARTED;
338 #undef __irqd_to_state
340 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
346 * struct irq_chip - hardware interrupt chip descriptor
348 * @parent_device: pointer to parent device for irqchip
349 * @name: name for /proc/interrupts
350 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
351 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
352 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
353 * @irq_disable: disable the interrupt
354 * @irq_ack: start of a new interrupt
355 * @irq_mask: mask an interrupt source
356 * @irq_mask_ack: ack and mask an interrupt source
357 * @irq_unmask: unmask an interrupt source
358 * @irq_eoi: end of interrupt
359 * @irq_set_affinity: set the CPU affinity on SMP machines
360 * @irq_retrigger: resend an IRQ to the CPU
361 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
362 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
363 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
364 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
365 * @irq_cpu_online: configure an interrupt source for a secondary CPU
366 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
367 * @irq_suspend: function called from core code on suspend once per
368 * chip, when one or more interrupts are installed
369 * @irq_resume: function called from core code on resume once per chip,
370 * when one ore more interrupts are installed
371 * @irq_pm_shutdown: function called from core code on shutdown once per chip
372 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
373 * @irq_print_chip: optional to print special chip info in show_interrupts
374 * @irq_request_resources: optional to request resources before calling
375 * any other callback related to this irq
376 * @irq_release_resources: optional to release resources acquired with
377 * irq_request_resources
378 * @irq_compose_msi_msg: optional to compose message content for MSI
379 * @irq_write_msi_msg: optional to write message content for MSI
380 * @irq_get_irqchip_state: return the internal state of an interrupt
381 * @irq_set_irqchip_state: set the internal state of a interrupt
382 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
383 * @ipi_send_single: send a single IPI to destination cpus
384 * @ipi_send_mask: send an IPI to destination cpus in cpumask
385 * @flags: chip specific flags
388 struct device *parent_device;
390 unsigned int (*irq_startup)(struct irq_data *data);
391 void (*irq_shutdown)(struct irq_data *data);
392 void (*irq_enable)(struct irq_data *data);
393 void (*irq_disable)(struct irq_data *data);
395 void (*irq_ack)(struct irq_data *data);
396 void (*irq_mask)(struct irq_data *data);
397 void (*irq_mask_ack)(struct irq_data *data);
398 void (*irq_unmask)(struct irq_data *data);
399 void (*irq_eoi)(struct irq_data *data);
401 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
402 int (*irq_retrigger)(struct irq_data *data);
403 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
404 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
406 void (*irq_bus_lock)(struct irq_data *data);
407 void (*irq_bus_sync_unlock)(struct irq_data *data);
409 void (*irq_cpu_online)(struct irq_data *data);
410 void (*irq_cpu_offline)(struct irq_data *data);
412 void (*irq_suspend)(struct irq_data *data);
413 void (*irq_resume)(struct irq_data *data);
414 void (*irq_pm_shutdown)(struct irq_data *data);
416 void (*irq_calc_mask)(struct irq_data *data);
418 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
419 int (*irq_request_resources)(struct irq_data *data);
420 void (*irq_release_resources)(struct irq_data *data);
422 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
423 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
425 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state);
426 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state);
428 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info);
430 void (*ipi_send_single)(struct irq_data *data, unsigned int cpu);
431 void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest);
437 * irq_chip specific flags
439 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
440 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
441 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
442 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
444 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
445 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
446 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
449 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
450 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
451 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
452 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
453 IRQCHIP_SKIP_SET_WAKE = (1 << 4),
454 IRQCHIP_ONESHOT_SAFE = (1 << 5),
455 IRQCHIP_EOI_THREADED = (1 << 6),
458 #include <linux/irqdesc.h>
461 * Pick up the arch-dependent methods:
463 #include <asm/hw_irq.h>
465 #ifndef NR_IRQS_LEGACY
466 # define NR_IRQS_LEGACY 0
469 #ifndef ARCH_IRQ_INIT_FLAGS
470 # define ARCH_IRQ_INIT_FLAGS 0
473 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
476 extern int setup_irq(unsigned int irq, struct irqaction *new);
477 extern void remove_irq(unsigned int irq, struct irqaction *act);
478 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
479 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
481 extern void irq_cpu_online(void);
482 extern void irq_cpu_offline(void);
483 extern int irq_set_affinity_locked(struct irq_data *data,
484 const struct cpumask *cpumask, bool force);
485 extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info);
487 extern void irq_migrate_all_off_this_cpu(void);
489 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
490 void irq_move_irq(struct irq_data *data);
491 void irq_move_masked_irq(struct irq_data *data);
493 static inline void irq_move_irq(struct irq_data *data) { }
494 static inline void irq_move_masked_irq(struct irq_data *data) { }
497 extern int no_irq_affinity;
499 #ifdef CONFIG_HARDIRQS_SW_RESEND
500 int irq_set_parent(int irq, int parent_irq);
502 static inline int irq_set_parent(int irq, int parent_irq)
509 * Built-in IRQ handlers for various IRQ types,
510 * callable via desc->handle_irq()
512 extern void handle_level_irq(struct irq_desc *desc);
513 extern void handle_fasteoi_irq(struct irq_desc *desc);
514 extern void handle_edge_irq(struct irq_desc *desc);
515 extern void handle_edge_eoi_irq(struct irq_desc *desc);
516 extern void handle_simple_irq(struct irq_desc *desc);
517 extern void handle_untracked_irq(struct irq_desc *desc);
518 extern void handle_percpu_irq(struct irq_desc *desc);
519 extern void handle_percpu_devid_irq(struct irq_desc *desc);
520 extern void handle_bad_irq(struct irq_desc *desc);
521 extern void handle_nested_irq(unsigned int irq);
523 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
524 extern int irq_chip_pm_get(struct irq_data *data);
525 extern int irq_chip_pm_put(struct irq_data *data);
526 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
527 extern void irq_chip_enable_parent(struct irq_data *data);
528 extern void irq_chip_disable_parent(struct irq_data *data);
529 extern void irq_chip_ack_parent(struct irq_data *data);
530 extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
531 extern void irq_chip_mask_parent(struct irq_data *data);
532 extern void irq_chip_unmask_parent(struct irq_data *data);
533 extern void irq_chip_eoi_parent(struct irq_data *data);
534 extern int irq_chip_set_affinity_parent(struct irq_data *data,
535 const struct cpumask *dest,
537 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
538 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data,
540 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
543 /* Handling of unhandled and spurious interrupts: */
544 extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret);
547 /* Enable/disable irq debugging output: */
548 extern int noirqdebug_setup(char *str);
550 /* Checks whether the interrupt can be requested by request_irq(): */
551 extern int can_request_irq(unsigned int irq, unsigned long irqflags);
553 /* Dummy irq-chip implementations: */
554 extern struct irq_chip no_irq_chip;
555 extern struct irq_chip dummy_irq_chip;
558 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
559 irq_flow_handler_t handle, const char *name);
561 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
562 irq_flow_handler_t handle)
564 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
567 extern int irq_set_percpu_devid(unsigned int irq);
568 extern int irq_set_percpu_devid_partition(unsigned int irq,
569 const struct cpumask *affinity);
570 extern int irq_get_percpu_devid_partition(unsigned int irq,
571 struct cpumask *affinity);
574 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
578 irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
580 __irq_set_handler(irq, handle, 0, NULL);
584 * Set a highlevel chained flow handler for a given IRQ.
585 * (a chained handler is automatically enabled and set to
586 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
589 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
591 __irq_set_handler(irq, handle, 1, NULL);
595 * Set a highlevel chained flow handler and its data for a given IRQ.
596 * (a chained handler is automatically enabled and set to
597 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
600 irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
603 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
605 static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
607 irq_modify_status(irq, 0, set);
610 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
612 irq_modify_status(irq, clr, 0);
615 static inline void irq_set_noprobe(unsigned int irq)
617 irq_modify_status(irq, 0, IRQ_NOPROBE);
620 static inline void irq_set_probe(unsigned int irq)
622 irq_modify_status(irq, IRQ_NOPROBE, 0);
625 static inline void irq_set_nothread(unsigned int irq)
627 irq_modify_status(irq, 0, IRQ_NOTHREAD);
630 static inline void irq_set_thread(unsigned int irq)
632 irq_modify_status(irq, IRQ_NOTHREAD, 0);
635 static inline void irq_set_nested_thread(unsigned int irq, bool nest)
638 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
640 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
643 static inline void irq_set_percpu_devid_flags(unsigned int irq)
645 irq_set_status_flags(irq,
646 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
647 IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
650 /* Set/get chip/data for an IRQ: */
651 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
652 extern int irq_set_handler_data(unsigned int irq, void *data);
653 extern int irq_set_chip_data(unsigned int irq, void *data);
654 extern int irq_set_irq_type(unsigned int irq, unsigned int type);
655 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
656 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
657 struct msi_desc *entry);
658 extern struct irq_data *irq_get_irq_data(unsigned int irq);
660 static inline struct irq_chip *irq_get_chip(unsigned int irq)
662 struct irq_data *d = irq_get_irq_data(irq);
663 return d ? d->chip : NULL;
666 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
671 static inline void *irq_get_chip_data(unsigned int irq)
673 struct irq_data *d = irq_get_irq_data(irq);
674 return d ? d->chip_data : NULL;
677 static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
682 static inline void *irq_get_handler_data(unsigned int irq)
684 struct irq_data *d = irq_get_irq_data(irq);
685 return d ? d->common->handler_data : NULL;
688 static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
690 return d->common->handler_data;
693 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
695 struct irq_data *d = irq_get_irq_data(irq);
696 return d ? d->common->msi_desc : NULL;
699 static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d)
701 return d->common->msi_desc;
704 static inline u32 irq_get_trigger_type(unsigned int irq)
706 struct irq_data *d = irq_get_irq_data(irq);
707 return d ? irqd_get_trigger_type(d) : 0;
710 static inline int irq_common_data_get_node(struct irq_common_data *d)
719 static inline int irq_data_get_node(struct irq_data *d)
721 return irq_common_data_get_node(d->common);
724 static inline struct cpumask *irq_get_affinity_mask(int irq)
726 struct irq_data *d = irq_get_irq_data(irq);
728 return d ? d->common->affinity : NULL;
731 static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d)
733 return d->common->affinity;
736 unsigned int arch_dynirq_lower_bound(unsigned int from);
738 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
739 struct module *owner, const struct cpumask *affinity);
741 int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from,
742 unsigned int cnt, int node, struct module *owner,
743 const struct cpumask *affinity);
745 /* use macros to avoid needing export.h for THIS_MODULE */
746 #define irq_alloc_descs(irq, from, cnt, node) \
747 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL)
749 #define irq_alloc_desc(node) \
750 irq_alloc_descs(-1, 0, 1, node)
752 #define irq_alloc_desc_at(at, node) \
753 irq_alloc_descs(at, at, 1, node)
755 #define irq_alloc_desc_from(from, node) \
756 irq_alloc_descs(-1, from, 1, node)
758 #define irq_alloc_descs_from(from, cnt, node) \
759 irq_alloc_descs(-1, from, cnt, node)
761 #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \
762 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL)
764 #define devm_irq_alloc_desc(dev, node) \
765 devm_irq_alloc_descs(dev, -1, 0, 1, node)
767 #define devm_irq_alloc_desc_at(dev, at, node) \
768 devm_irq_alloc_descs(dev, at, at, 1, node)
770 #define devm_irq_alloc_desc_from(dev, from, node) \
771 devm_irq_alloc_descs(dev, -1, from, 1, node)
773 #define devm_irq_alloc_descs_from(dev, from, cnt, node) \
774 devm_irq_alloc_descs(dev, -1, from, cnt, node)
776 void irq_free_descs(unsigned int irq, unsigned int cnt);
777 static inline void irq_free_desc(unsigned int irq)
779 irq_free_descs(irq, 1);
782 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
783 unsigned int irq_alloc_hwirqs(int cnt, int node);
784 static inline unsigned int irq_alloc_hwirq(int node)
786 return irq_alloc_hwirqs(1, node);
788 void irq_free_hwirqs(unsigned int from, int cnt);
789 static inline void irq_free_hwirq(unsigned int irq)
791 return irq_free_hwirqs(irq, 1);
793 int arch_setup_hwirq(unsigned int irq, int node);
794 void arch_teardown_hwirq(unsigned int irq);
797 #ifdef CONFIG_GENERIC_IRQ_LEGACY
798 void irq_init_desc(unsigned int irq);
802 * struct irq_chip_regs - register offsets for struct irq_gci
803 * @enable: Enable register offset to reg_base
804 * @disable: Disable register offset to reg_base
805 * @mask: Mask register offset to reg_base
806 * @ack: Ack register offset to reg_base
807 * @eoi: Eoi register offset to reg_base
808 * @type: Type configuration register offset to reg_base
809 * @polarity: Polarity configuration register offset to reg_base
811 struct irq_chip_regs {
812 unsigned long enable;
813 unsigned long disable;
818 unsigned long polarity;
822 * struct irq_chip_type - Generic interrupt chip instance for a flow type
823 * @chip: The real interrupt chip which provides the callbacks
824 * @regs: Register offsets for this chip
825 * @handler: Flow handler associated with this chip
826 * @type: Chip can handle these flow types
827 * @mask_cache_priv: Cached mask register private to the chip type
828 * @mask_cache: Pointer to cached mask register
830 * A irq_generic_chip can have several instances of irq_chip_type when
831 * it requires different functions and register offsets for different
834 struct irq_chip_type {
835 struct irq_chip chip;
836 struct irq_chip_regs regs;
837 irq_flow_handler_t handler;
844 * struct irq_chip_generic - Generic irq chip data structure
845 * @lock: Lock to protect register and cache data access
846 * @reg_base: Register base address (virtual)
847 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
848 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
849 * @suspend: Function called from core code on suspend once per
850 * chip; can be useful instead of irq_chip::suspend to
851 * handle chip details even when no interrupts are in use
852 * @resume: Function called from core code on resume once per chip;
853 * can be useful instead of irq_chip::suspend to handle
854 * chip details even when no interrupts are in use
855 * @irq_base: Interrupt base nr for this chip
856 * @irq_cnt: Number of interrupts handled by this chip
857 * @mask_cache: Cached mask register shared between all chip types
858 * @type_cache: Cached type register
859 * @polarity_cache: Cached polarity register
860 * @wake_enabled: Interrupt can wakeup from suspend
861 * @wake_active: Interrupt is marked as an wakeup from suspend source
862 * @num_ct: Number of available irq_chip_type instances (usually 1)
863 * @private: Private data for non generic chip callbacks
864 * @installed: bitfield to denote installed interrupts
865 * @unused: bitfield to denote unused interrupts
866 * @domain: irq domain pointer
867 * @list: List head for keeping track of instances
868 * @chip_types: Array of interrupt irq_chip_types
870 * Note, that irq_chip_generic can have multiple irq_chip_type
871 * implementations which can be associated to a particular irq line of
872 * an irq_chip_generic instance. That allows to share and protect
873 * state in an irq_chip_generic instance when we need to implement
874 * different flow mechanisms (level/edge) for it.
876 struct irq_chip_generic {
878 void __iomem *reg_base;
879 u32 (*reg_readl)(void __iomem *addr);
880 void (*reg_writel)(u32 val, void __iomem *addr);
881 void (*suspend)(struct irq_chip_generic *gc);
882 void (*resume)(struct irq_chip_generic *gc);
883 unsigned int irq_base;
884 unsigned int irq_cnt;
892 unsigned long installed;
893 unsigned long unused;
894 struct irq_domain *domain;
895 struct list_head list;
896 struct irq_chip_type chip_types[0];
900 * enum irq_gc_flags - Initialization flags for generic irq chips
901 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
902 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
903 * irq chips which need to call irq_set_wake() on
904 * the parent irq. Usually GPIO implementations
905 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
906 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
907 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
910 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
911 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
912 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
913 IRQ_GC_NO_MASK = 1 << 3,
914 IRQ_GC_BE_IO = 1 << 4,
918 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
919 * @irqs_per_chip: Number of interrupts per chip
920 * @num_chips: Number of chips
921 * @irq_flags_to_set: IRQ* flags to set on irq setup
922 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
923 * @gc_flags: Generic chip specific setup flags
924 * @gc: Array of pointers to generic interrupt chips
926 struct irq_domain_chip_generic {
927 unsigned int irqs_per_chip;
928 unsigned int num_chips;
929 unsigned int irq_flags_to_clear;
930 unsigned int irq_flags_to_set;
931 enum irq_gc_flags gc_flags;
932 struct irq_chip_generic *gc[0];
935 /* Generic chip callback functions */
936 void irq_gc_noop(struct irq_data *d);
937 void irq_gc_mask_disable_reg(struct irq_data *d);
938 void irq_gc_mask_set_bit(struct irq_data *d);
939 void irq_gc_mask_clr_bit(struct irq_data *d);
940 void irq_gc_unmask_enable_reg(struct irq_data *d);
941 void irq_gc_ack_set_bit(struct irq_data *d);
942 void irq_gc_ack_clr_bit(struct irq_data *d);
943 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
944 void irq_gc_eoi(struct irq_data *d);
945 int irq_gc_set_wake(struct irq_data *d, unsigned int on);
947 /* Setup functions for irq_chip_generic */
948 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
949 irq_hw_number_t hw_irq);
950 struct irq_chip_generic *
951 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
952 void __iomem *reg_base, irq_flow_handler_t handler);
953 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
954 enum irq_gc_flags flags, unsigned int clr,
956 int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
957 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
958 unsigned int clr, unsigned int set);
960 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
962 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
963 int num_ct, const char *name,
964 irq_flow_handler_t handler,
965 unsigned int clr, unsigned int set,
966 enum irq_gc_flags flags);
968 #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \
969 handler, clr, set, flags) \
971 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \
972 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\
973 handler, clr, set, flags); \
976 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
978 return container_of(d->chip, struct irq_chip_type, chip);
981 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
984 static inline void irq_gc_lock(struct irq_chip_generic *gc)
986 raw_spin_lock(&gc->lock);
989 static inline void irq_gc_unlock(struct irq_chip_generic *gc)
991 raw_spin_unlock(&gc->lock);
994 static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
995 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
999 * The irqsave variants are for usage in non interrupt code. Do not use
1000 * them in irq_chip callbacks. Use irq_gc_lock() instead.
1002 #define irq_gc_lock_irqsave(gc, flags) \
1003 raw_spin_lock_irqsave(&(gc)->lock, flags)
1005 #define irq_gc_unlock_irqrestore(gc, flags) \
1006 raw_spin_unlock_irqrestore(&(gc)->lock, flags)
1008 static inline void irq_reg_writel(struct irq_chip_generic *gc,
1009 u32 val, int reg_offset)
1012 gc->reg_writel(val, gc->reg_base + reg_offset);
1014 writel(val, gc->reg_base + reg_offset);
1017 static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
1021 return gc->reg_readl(gc->reg_base + reg_offset);
1023 return readl(gc->reg_base + reg_offset);
1026 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */
1027 #define INVALID_HWIRQ (~0UL)
1028 irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu);
1029 int __ipi_send_single(struct irq_desc *desc, unsigned int cpu);
1030 int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest);
1031 int ipi_send_single(unsigned int virq, unsigned int cpu);
1032 int ipi_send_mask(unsigned int virq, const struct cpumask *dest);
1034 #endif /* _LINUX_IRQ_H */