2 * twl4030.h - header for TWL4030 PM and audio CODEC device
4 * Copyright (C) 2005-2006 Texas Instruments, Inc.
6 * Based on tlv320aic23.c:
7 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/types.h>
29 #include <linux/input/matrix_keypad.h>
32 * Using the twl4030 core we address registers using a pair
33 * { module id, relative register offset }
34 * which that core then maps to the relevant
35 * { i2c slave, absolute register address }
37 * The module IDs are meaningful only to the twl4030 core code,
38 * which uses them as array indices to look up the first register
39 * address each module uses within a given i2c slave.
42 /* Slave 0 (i2c address 0x48) */
43 #define TWL4030_MODULE_USB 0x00
45 /* Slave 1 (i2c address 0x49) */
46 #define TWL4030_MODULE_AUDIO_VOICE 0x01
47 #define TWL4030_MODULE_GPIO 0x02
48 #define TWL4030_MODULE_INTBR 0x03
49 #define TWL4030_MODULE_PIH 0x04
50 #define TWL4030_MODULE_TEST 0x05
52 /* Slave 2 (i2c address 0x4a) */
53 #define TWL4030_MODULE_KEYPAD 0x06
54 #define TWL4030_MODULE_MADC 0x07
55 #define TWL4030_MODULE_INTERRUPTS 0x08
56 #define TWL4030_MODULE_LED 0x09
57 #define TWL4030_MODULE_MAIN_CHARGE 0x0A
58 #define TWL4030_MODULE_PRECHARGE 0x0B
59 #define TWL4030_MODULE_PWM0 0x0C
60 #define TWL4030_MODULE_PWM1 0x0D
61 #define TWL4030_MODULE_PWMA 0x0E
62 #define TWL4030_MODULE_PWMB 0x0F
64 #define TWL5031_MODULE_ACCESSORY 0x10
65 #define TWL5031_MODULE_INTERRUPTS 0x11
67 /* Slave 3 (i2c address 0x4b) */
68 #define TWL4030_MODULE_BACKUP 0x12
69 #define TWL4030_MODULE_INT 0x13
70 #define TWL4030_MODULE_PM_MASTER 0x14
71 #define TWL4030_MODULE_PM_RECEIVER 0x15
72 #define TWL4030_MODULE_RTC 0x16
73 #define TWL4030_MODULE_SECURED_REG 0x17
75 #define TWL_MODULE_USB TWL4030_MODULE_USB
76 #define TWL_MODULE_AUDIO_VOICE TWL4030_MODULE_AUDIO_VOICE
77 #define TWL_MODULE_PIH TWL4030_MODULE_PIH
78 #define TWL_MODULE_MADC TWL4030_MODULE_MADC
79 #define TWL_MODULE_MAIN_CHARGE TWL4030_MODULE_MAIN_CHARGE
80 #define TWL_MODULE_PM_MASTER TWL4030_MODULE_PM_MASTER
81 #define TWL_MODULE_PM_RECEIVER TWL4030_MODULE_PM_RECEIVER
82 #define TWL_MODULE_RTC TWL4030_MODULE_RTC
84 #define GPIO_INTR_OFFSET 0
85 #define KEYPAD_INTR_OFFSET 1
86 #define BCI_INTR_OFFSET 2
87 #define MADC_INTR_OFFSET 3
88 #define USB_INTR_OFFSET 4
89 #define BCI_PRES_INTR_OFFSET 9
90 #define USB_PRES_INTR_OFFSET 10
91 #define RTC_INTR_OFFSET 11
93 * Read and write single 8-bit registers
95 int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg);
96 int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg);
99 * Read and write several 8-bit registers at once.
101 * IMPORTANT: For twl_i2c_write(), allocate num_bytes + 1
102 * for the value, and populate your data starting at offset 1.
104 int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
105 int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
107 /*----------------------------------------------------------------------*/
110 * NOTE: at up to 1024 registers, this is a big chip.
112 * Avoid putting register declarations in this file, instead of into
113 * a driver-private file, unless some of the registers in a block
114 * need to be shared with other drivers. One example is blocks that
115 * have Secondary IRQ Handler (SIH) registers.
118 #define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0)
119 #define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1)
120 #define TWL4030_SIH_CTRL_COR_MASK BIT(2)
122 /*----------------------------------------------------------------------*/
125 * GPIO Block Register offsets (use TWL4030_MODULE_GPIO)
128 #define REG_GPIODATAIN1 0x0
129 #define REG_GPIODATAIN2 0x1
130 #define REG_GPIODATAIN3 0x2
131 #define REG_GPIODATADIR1 0x3
132 #define REG_GPIODATADIR2 0x4
133 #define REG_GPIODATADIR3 0x5
134 #define REG_GPIODATAOUT1 0x6
135 #define REG_GPIODATAOUT2 0x7
136 #define REG_GPIODATAOUT3 0x8
137 #define REG_CLEARGPIODATAOUT1 0x9
138 #define REG_CLEARGPIODATAOUT2 0xA
139 #define REG_CLEARGPIODATAOUT3 0xB
140 #define REG_SETGPIODATAOUT1 0xC
141 #define REG_SETGPIODATAOUT2 0xD
142 #define REG_SETGPIODATAOUT3 0xE
143 #define REG_GPIO_DEBEN1 0xF
144 #define REG_GPIO_DEBEN2 0x10
145 #define REG_GPIO_DEBEN3 0x11
146 #define REG_GPIO_CTRL 0x12
147 #define REG_GPIOPUPDCTR1 0x13
148 #define REG_GPIOPUPDCTR2 0x14
149 #define REG_GPIOPUPDCTR3 0x15
150 #define REG_GPIOPUPDCTR4 0x16
151 #define REG_GPIOPUPDCTR5 0x17
152 #define REG_GPIO_ISR1A 0x19
153 #define REG_GPIO_ISR2A 0x1A
154 #define REG_GPIO_ISR3A 0x1B
155 #define REG_GPIO_IMR1A 0x1C
156 #define REG_GPIO_IMR2A 0x1D
157 #define REG_GPIO_IMR3A 0x1E
158 #define REG_GPIO_ISR1B 0x1F
159 #define REG_GPIO_ISR2B 0x20
160 #define REG_GPIO_ISR3B 0x21
161 #define REG_GPIO_IMR1B 0x22
162 #define REG_GPIO_IMR2B 0x23
163 #define REG_GPIO_IMR3B 0x24
164 #define REG_GPIO_EDR1 0x28
165 #define REG_GPIO_EDR2 0x29
166 #define REG_GPIO_EDR3 0x2A
167 #define REG_GPIO_EDR4 0x2B
168 #define REG_GPIO_EDR5 0x2C
169 #define REG_GPIO_SIH_CTRL 0x2D
171 /* Up to 18 signals are available as GPIOs, when their
172 * pins are not assigned to another use (such as ULPI/USB).
174 #define TWL4030_GPIO_MAX 18
176 /*----------------------------------------------------------------------*/
179 * Keypad register offsets (use TWL4030_MODULE_KEYPAD)
180 * ... SIH/interrupt only
183 #define TWL4030_KEYPAD_KEYP_ISR1 0x11
184 #define TWL4030_KEYPAD_KEYP_IMR1 0x12
185 #define TWL4030_KEYPAD_KEYP_ISR2 0x13
186 #define TWL4030_KEYPAD_KEYP_IMR2 0x14
187 #define TWL4030_KEYPAD_KEYP_SIR 0x15 /* test register */
188 #define TWL4030_KEYPAD_KEYP_EDR 0x16
189 #define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17
191 /*----------------------------------------------------------------------*/
194 * Multichannel ADC register offsets (use TWL4030_MODULE_MADC)
195 * ... SIH/interrupt only
198 #define TWL4030_MADC_ISR1 0x61
199 #define TWL4030_MADC_IMR1 0x62
200 #define TWL4030_MADC_ISR2 0x63
201 #define TWL4030_MADC_IMR2 0x64
202 #define TWL4030_MADC_SIR 0x65 /* test register */
203 #define TWL4030_MADC_EDR 0x66
204 #define TWL4030_MADC_SIH_CTRL 0x67
206 /*----------------------------------------------------------------------*/
209 * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS)
212 #define TWL4030_INTERRUPTS_BCIISR1A 0x0
213 #define TWL4030_INTERRUPTS_BCIISR2A 0x1
214 #define TWL4030_INTERRUPTS_BCIIMR1A 0x2
215 #define TWL4030_INTERRUPTS_BCIIMR2A 0x3
216 #define TWL4030_INTERRUPTS_BCIISR1B 0x4
217 #define TWL4030_INTERRUPTS_BCIISR2B 0x5
218 #define TWL4030_INTERRUPTS_BCIIMR1B 0x6
219 #define TWL4030_INTERRUPTS_BCIIMR2B 0x7
220 #define TWL4030_INTERRUPTS_BCISIR1 0x8 /* test register */
221 #define TWL4030_INTERRUPTS_BCISIR2 0x9 /* test register */
222 #define TWL4030_INTERRUPTS_BCIEDR1 0xa
223 #define TWL4030_INTERRUPTS_BCIEDR2 0xb
224 #define TWL4030_INTERRUPTS_BCIEDR3 0xc
225 #define TWL4030_INTERRUPTS_BCISIHCTRL 0xd
227 /*----------------------------------------------------------------------*/
230 * Power Interrupt block register offsets (use TWL4030_MODULE_INT)
233 #define TWL4030_INT_PWR_ISR1 0x0
234 #define TWL4030_INT_PWR_IMR1 0x1
235 #define TWL4030_INT_PWR_ISR2 0x2
236 #define TWL4030_INT_PWR_IMR2 0x3
237 #define TWL4030_INT_PWR_SIR 0x4 /* test register */
238 #define TWL4030_INT_PWR_EDR1 0x5
239 #define TWL4030_INT_PWR_EDR2 0x6
240 #define TWL4030_INT_PWR_SIH_CTRL 0x7
242 /*----------------------------------------------------------------------*/
245 * Accessory Interrupts
247 #define TWL5031_ACIIMR_LSB 0x05
248 #define TWL5031_ACIIMR_MSB 0x06
249 #define TWL5031_ACIIDR_LSB 0x07
250 #define TWL5031_ACIIDR_MSB 0x08
251 #define TWL5031_ACCISR1 0x0F
252 #define TWL5031_ACCIMR1 0x10
253 #define TWL5031_ACCISR2 0x11
254 #define TWL5031_ACCIMR2 0x12
255 #define TWL5031_ACCSIR 0x13
256 #define TWL5031_ACCEDR1 0x14
257 #define TWL5031_ACCSIHCTRL 0x15
259 /*----------------------------------------------------------------------*/
262 * Battery Charger Controller
265 #define TWL5031_INTERRUPTS_BCIISR1 0x0
266 #define TWL5031_INTERRUPTS_BCIIMR1 0x1
267 #define TWL5031_INTERRUPTS_BCIISR2 0x2
268 #define TWL5031_INTERRUPTS_BCIIMR2 0x3
269 #define TWL5031_INTERRUPTS_BCISIR 0x4
270 #define TWL5031_INTERRUPTS_BCIEDR1 0x5
271 #define TWL5031_INTERRUPTS_BCIEDR2 0x6
272 #define TWL5031_INTERRUPTS_BCISIHCTRL 0x7
274 /*----------------------------------------------------------------------*/
276 /* Power bus message definitions */
278 /* The TWL4030/5030 splits its power-management resources (the various
279 * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
280 * P3. These groups can then be configured to transition between sleep, wait-on
281 * and active states by sending messages to the power bus. See Section 5.4.2
282 * Power Resources of TWL4030 TRM
285 /* Processor groups */
286 #define DEV_GRP_NULL 0x0
287 #define DEV_GRP_P1 0x1 /* P1: all OMAP devices */
288 #define DEV_GRP_P2 0x2 /* P2: all Modem devices */
289 #define DEV_GRP_P3 0x4 /* P3: all peripheral devices */
291 /* Resource groups */
292 #define RES_GRP_RES 0x0 /* Reserved */
293 #define RES_GRP_PP 0x1 /* Power providers */
294 #define RES_GRP_RC 0x2 /* Reset and control */
295 #define RES_GRP_PP_RC 0x3
296 #define RES_GRP_PR 0x4 /* Power references */
297 #define RES_GRP_PP_PR 0x5
298 #define RES_GRP_RC_PR 0x6
299 #define RES_GRP_ALL 0x7 /* All resource groups */
301 #define RES_TYPE2_R0 0x0
303 #define RES_TYPE_ALL 0x7
305 /* Resource states */
306 #define RES_STATE_WRST 0xF
307 #define RES_STATE_ACTIVE 0xE
308 #define RES_STATE_SLEEP 0x8
309 #define RES_STATE_OFF 0x0
311 /* Power resources */
313 /* Power providers */
324 #define RES_VINTANA1 11
325 #define RES_VINTANA2 12
326 #define RES_VINTDIG 13
330 #define RES_VUSB_1V5 17
331 #define RES_VUSB_1V8 18
332 #define RES_VUSB_3V1 19
333 #define RES_VUSBCP 20
335 /* Reset and control */
336 #define RES_NRES_PWRON 22
339 #define RES_HFCLKOUT 25
340 #define RES_32KCLKOUT 26
342 /* Power Reference */
343 #define RES_Main_Ref 28
345 #define TOTAL_RESOURCES 28
347 * Power Bus Message Format ... these can be sent individually by Linux,
348 * but are usually part of downloaded scripts that are run when various
349 * power events are triggered.
351 * Broadcast Message (16 Bits):
352 * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
355 * Singular Message (16 Bits):
356 * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
359 #define MSG_BROADCAST(devgrp, grp, type, type2, state) \
360 ( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
361 | (type) << 4 | (state))
363 #define MSG_SINGULAR(devgrp, id, state) \
364 ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
366 /*----------------------------------------------------------------------*/
368 struct twl4030_clock_init_data {
369 bool ck32k_lowpwr_enable;
372 struct twl4030_bci_platform_data {
373 int *battery_tmp_tbl;
374 unsigned int tblsize;
377 /* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */
378 struct twl4030_gpio_platform_data {
380 unsigned irq_base, irq_end;
382 /* package the two LED signals as output-only GPIOs? */
385 /* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */
388 /* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */
391 /* For gpio-N, bit (1 << N) in "pullups" is set if that pullup
392 * should be enabled. Else, if that bit is set in "pulldowns",
393 * that pulldown is enabled. Don't waste power by letting any
394 * digital inputs float...
399 int (*setup)(struct device *dev,
400 unsigned gpio, unsigned ngpio);
401 int (*teardown)(struct device *dev,
402 unsigned gpio, unsigned ngpio);
405 struct twl4030_madc_platform_data {
409 /* Boards have uniqe mappings of {row, col} --> keycode.
410 * Column and row are 8 bits each, but range only from 0..7.
411 * a PERSISTENT_KEY is "always on" and never reported.
413 #define PERSISTENT_KEY(r, c) KEY((r), (c), KEY_RESERVED)
415 struct twl4030_keypad_data {
416 const struct matrix_keymap_data *keymap_data;
422 enum twl4030_usb_mode {
423 T2_USB_MODE_ULPI = 1,
424 T2_USB_MODE_CEA2011_3PIN = 2,
427 struct twl4030_usb_data {
428 enum twl4030_usb_mode usb_mode;
436 struct twl4030_script {
437 struct twl4030_ins *script;
440 #define TWL4030_WRST_SCRIPT (1<<0)
441 #define TWL4030_WAKEUP12_SCRIPT (1<<1)
442 #define TWL4030_WAKEUP3_SCRIPT (1<<2)
443 #define TWL4030_SLEEP_SCRIPT (1<<3)
446 struct twl4030_resconfig {
448 u8 devgroup; /* Processor group that Power resource belongs to */
449 u8 type; /* Power resource addressed, 6 / broadcast message */
450 u8 type2; /* Power resource addressed, 3 / broadcast message */
451 u8 remap_off; /* off state remapping */
452 u8 remap_sleep; /* sleep state remapping */
455 struct twl4030_power_data {
456 struct twl4030_script **scripts;
458 struct twl4030_resconfig *resource_config;
459 #define TWL4030_RESCONFIG_UNDEF ((u8)-1)
462 extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
464 struct twl4030_codec_audio_data {
465 unsigned int audio_mclk;
466 unsigned int ramp_delay_value;
467 unsigned int hs_extmute:1;
468 void (*set_hs_extmute)(int mute);
471 struct twl4030_codec_vibra_data {
472 unsigned int audio_mclk;
473 unsigned int coexist;
476 struct twl4030_codec_data {
477 unsigned int audio_mclk;
478 struct twl4030_codec_audio_data *audio;
479 struct twl4030_codec_vibra_data *vibra;
482 struct twl4030_platform_data {
483 unsigned irq_base, irq_end;
484 struct twl4030_clock_init_data *clock;
485 struct twl4030_bci_platform_data *bci;
486 struct twl4030_gpio_platform_data *gpio;
487 struct twl4030_madc_platform_data *madc;
488 struct twl4030_keypad_data *keypad;
489 struct twl4030_usb_data *usb;
490 struct twl4030_power_data *power;
491 struct twl4030_codec_data *codec;
494 struct regulator_init_data *vdac;
495 struct regulator_init_data *vpll1;
496 struct regulator_init_data *vpll2;
497 struct regulator_init_data *vmmc1;
498 struct regulator_init_data *vmmc2;
499 struct regulator_init_data *vsim;
500 struct regulator_init_data *vaux1;
501 struct regulator_init_data *vaux2;
502 struct regulator_init_data *vaux3;
503 struct regulator_init_data *vaux4;
504 struct regulator_init_data *vio;
505 struct regulator_init_data *vdd1;
506 struct regulator_init_data *vdd2;
507 struct regulator_init_data *vintana1;
508 struct regulator_init_data *vintana2;
509 struct regulator_init_data *vintdig;
512 /*----------------------------------------------------------------------*/
514 int twl4030_sih_setup(int module);
516 /* Offsets to Power Registers */
517 #define TWL4030_VDAC_DEV_GRP 0x3B
518 #define TWL4030_VDAC_DEDICATED 0x3E
519 #define TWL4030_VAUX1_DEV_GRP 0x17
520 #define TWL4030_VAUX1_DEDICATED 0x1A
521 #define TWL4030_VAUX2_DEV_GRP 0x1B
522 #define TWL4030_VAUX2_DEDICATED 0x1E
523 #define TWL4030_VAUX3_DEV_GRP 0x1F
524 #define TWL4030_VAUX3_DEDICATED 0x22
526 #if defined(CONFIG_TWL4030_BCI_BATTERY) || \
527 defined(CONFIG_TWL4030_BCI_BATTERY_MODULE)
528 extern int twl4030charger_usb_en(int enable);
530 static inline int twl4030charger_usb_en(int enable) { return 0; }
533 /*----------------------------------------------------------------------*/
535 /* Linux-specific regulator identifiers ... for now, we only support
536 * the LDOs, and leave the three buck converters alone. VDD1 and VDD2
537 * need to tie into hardware based voltage scaling (cpufreq etc), while
538 * VIO is generally fixed.
541 /* EXTERNAL dc-to-dc buck converters */
542 #define TWL4030_REG_VDD1 0
543 #define TWL4030_REG_VDD2 1
544 #define TWL4030_REG_VIO 2
547 #define TWL4030_REG_VDAC 3
548 #define TWL4030_REG_VPLL1 4
549 #define TWL4030_REG_VPLL2 5 /* not on all chips */
550 #define TWL4030_REG_VMMC1 6
551 #define TWL4030_REG_VMMC2 7 /* not on all chips */
552 #define TWL4030_REG_VSIM 8 /* not on all chips */
553 #define TWL4030_REG_VAUX1 9 /* not on all chips */
554 #define TWL4030_REG_VAUX2_4030 10 /* (twl4030-specific) */
555 #define TWL4030_REG_VAUX2 11 /* (twl5030 and newer) */
556 #define TWL4030_REG_VAUX3 12 /* not on all chips */
557 #define TWL4030_REG_VAUX4 13 /* not on all chips */
560 #define TWL4030_REG_VINTANA1 14
561 #define TWL4030_REG_VINTANA2 15
562 #define TWL4030_REG_VINTDIG 16
563 #define TWL4030_REG_VUSB1V5 17
564 #define TWL4030_REG_VUSB1V8 18
565 #define TWL4030_REG_VUSB3V1 19
567 #endif /* End of __TWL4030_H */