1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2019 HiSilicon Limited. */
6 #include <linux/bitfield.h>
7 #include <linux/debugfs.h>
8 #include <linux/iopoll.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
12 #define QM_QNUM_V1 4096
13 #define QM_QNUM_V2 1024
14 #define QM_MAX_VFS_NUM_V2 63
17 #define QM_ARUSER_M_CFG_1 0x100088
18 #define AXUSER_SNOOP_ENABLE BIT(30)
19 #define AXUSER_CMD_TYPE GENMASK(14, 12)
20 #define AXUSER_CMD_SMMU_NORMAL 1
21 #define AXUSER_NS BIT(6)
22 #define AXUSER_NO BIT(5)
23 #define AXUSER_FP BIT(4)
24 #define AXUSER_SSV BIT(0)
25 #define AXUSER_BASE (AXUSER_SNOOP_ENABLE | \
26 FIELD_PREP(AXUSER_CMD_TYPE, \
27 AXUSER_CMD_SMMU_NORMAL) | \
28 AXUSER_NS | AXUSER_NO | AXUSER_FP)
29 #define QM_ARUSER_M_CFG_ENABLE 0x100090
30 #define ARUSER_M_CFG_ENABLE 0xfffffffe
31 #define QM_AWUSER_M_CFG_1 0x100098
32 #define QM_AWUSER_M_CFG_ENABLE 0x1000a0
33 #define AWUSER_M_CFG_ENABLE 0xfffffffe
34 #define QM_WUSER_M_CFG_ENABLE 0x1000a8
35 #define WUSER_M_CFG_ENABLE 0xffffffff
38 #define QM_MB_CMD_SQC 0x0
39 #define QM_MB_CMD_CQC 0x1
40 #define QM_MB_CMD_EQC 0x2
41 #define QM_MB_CMD_AEQC 0x3
42 #define QM_MB_CMD_SQC_BT 0x4
43 #define QM_MB_CMD_CQC_BT 0x5
44 #define QM_MB_CMD_SQC_VFT_V2 0x6
45 #define QM_MB_CMD_STOP_QP 0x8
46 #define QM_MB_CMD_SRC 0xc
47 #define QM_MB_CMD_DST 0xd
49 #define QM_MB_CMD_SEND_BASE 0x300
50 #define QM_MB_EVENT_SHIFT 8
51 #define QM_MB_BUSY_SHIFT 13
52 #define QM_MB_OP_SHIFT 14
53 #define QM_MB_CMD_DATA_ADDR_L 0x304
54 #define QM_MB_CMD_DATA_ADDR_H 0x308
55 #define QM_MB_MAX_WAIT_CNT 6000
58 #define QM_DOORBELL_CMD_SQ 0
59 #define QM_DOORBELL_CMD_CQ 1
60 #define QM_DOORBELL_CMD_EQ 2
61 #define QM_DOORBELL_CMD_AEQ 3
63 #define QM_DOORBELL_SQ_CQ_BASE_V2 0x1000
64 #define QM_DOORBELL_EQ_AEQ_BASE_V2 0x2000
65 #define QM_QP_MAX_NUM_SHIFT 11
66 #define QM_DB_CMD_SHIFT_V2 12
67 #define QM_DB_RAND_SHIFT_V2 16
68 #define QM_DB_INDEX_SHIFT_V2 32
69 #define QM_DB_PRIORITY_SHIFT_V2 48
70 #define QM_VF_STATE 0x60
73 #define QM_CACHE_CTL 0x100050
74 #define SQC_CACHE_ENABLE BIT(0)
75 #define CQC_CACHE_ENABLE BIT(1)
76 #define SQC_CACHE_WB_ENABLE BIT(4)
77 #define SQC_CACHE_WB_THRD GENMASK(10, 5)
78 #define CQC_CACHE_WB_ENABLE BIT(11)
79 #define CQC_CACHE_WB_THRD GENMASK(17, 12)
80 #define QM_AXI_M_CFG 0x1000ac
81 #define AXI_M_CFG 0xffff
82 #define QM_AXI_M_CFG_ENABLE 0x1000b0
83 #define AM_CFG_SINGLE_PORT_MAX_TRANS 0x300014
84 #define AXI_M_CFG_ENABLE 0xffffffff
85 #define QM_PEH_AXUSER_CFG 0x1000cc
86 #define QM_PEH_AXUSER_CFG_ENABLE 0x1000d0
87 #define PEH_AXUSER_CFG 0x401001
88 #define PEH_AXUSER_CFG_ENABLE 0xffffffff
90 #define QM_AXI_RRESP BIT(0)
91 #define QM_AXI_BRESP BIT(1)
92 #define QM_ECC_MBIT BIT(2)
93 #define QM_ECC_1BIT BIT(3)
94 #define QM_ACC_GET_TASK_TIMEOUT BIT(4)
95 #define QM_ACC_DO_TASK_TIMEOUT BIT(5)
96 #define QM_ACC_WB_NOT_READY_TIMEOUT BIT(6)
97 #define QM_SQ_CQ_VF_INVALID BIT(7)
98 #define QM_CQ_VF_INVALID BIT(8)
99 #define QM_SQ_VF_INVALID BIT(9)
100 #define QM_DB_TIMEOUT BIT(10)
101 #define QM_OF_FIFO_OF BIT(11)
102 #define QM_DB_RANDOM_INVALID BIT(12)
103 #define QM_MAILBOX_TIMEOUT BIT(13)
104 #define QM_FLR_TIMEOUT BIT(14)
106 #define QM_BASE_NFE (QM_AXI_RRESP | QM_AXI_BRESP | QM_ECC_MBIT | \
107 QM_ACC_GET_TASK_TIMEOUT | QM_DB_TIMEOUT | \
108 QM_OF_FIFO_OF | QM_DB_RANDOM_INVALID | \
109 QM_MAILBOX_TIMEOUT | QM_FLR_TIMEOUT)
110 #define QM_BASE_CE QM_ECC_1BIT
112 #define QM_Q_DEPTH 1024
113 #define QM_MIN_QNUM 2
114 #define HISI_ACC_SGL_SGE_NR_MAX 255
115 #define QM_SHAPER_CFG 0x100164
116 #define QM_SHAPER_ENABLE BIT(30)
117 #define QM_SHAPER_TYPE1_OFFSET 10
119 /* page number for queue file region */
120 #define QM_DOORBELL_PAGE_NR 1
122 /* uacce mode of the driver */
123 #define UACCE_MODE_NOUACCE 0 /* don't use uacce */
124 #define UACCE_MODE_SVA 1 /* use uacce sva mode */
125 #define UACCE_MODE_DESC "0(default) means only register to crypto, 1 means both register to crypto and uacce"
127 enum qm_stop_reason {
172 atomic64_t err_irq_cnt;
173 atomic64_t aeq_irq_cnt;
174 atomic64_t abnormal_irq_cnt;
175 atomic64_t create_qp_err_cnt;
176 atomic64_t mb_err_cnt;
179 struct debugfs_file {
180 enum qm_debug_file index;
182 struct qm_debug *debug;
190 struct dentry *debug_root;
192 struct debugfs_file files[DEBUG_FILE_NUM];
195 struct qm_shaper_factor {
209 struct hisi_qm_status {
220 struct hisi_qm_err_info {
230 struct hisi_qm_err_status {
235 struct hisi_qm_err_ini {
236 int (*hw_init)(struct hisi_qm *qm);
237 void (*hw_err_enable)(struct hisi_qm *qm);
238 void (*hw_err_disable)(struct hisi_qm *qm);
239 u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
240 void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts);
241 void (*open_axi_master_ooo)(struct hisi_qm *qm);
242 void (*close_axi_master_ooo)(struct hisi_qm *qm);
243 void (*open_sva_prefetch)(struct hisi_qm *qm);
244 void (*close_sva_prefetch)(struct hisi_qm *qm);
245 void (*log_dev_hw_err)(struct hisi_qm *qm, u32 err_sts);
246 void (*err_info_init)(struct hisi_qm *qm);
249 struct hisi_qm_list {
251 struct list_head list;
252 int (*register_to_crypto)(struct hisi_qm *qm);
253 void (*unregister_from_crypto)(struct hisi_qm *qm);
258 enum qm_fun_type fun_type;
259 const char *dev_name;
260 struct pci_dev *pdev;
261 void __iomem *io_base;
262 void __iomem *db_io_base;
271 struct list_head list;
272 struct hisi_qm_list *qm_list;
278 struct qm_aeqe *aeqe;
284 struct hisi_qm_status status;
285 const struct hisi_qm_err_ini *err_ini;
286 struct hisi_qm_err_info err_info;
287 struct hisi_qm_err_status err_status;
288 unsigned long misc_ctl; /* driver removing and reset sched */
290 struct rw_semaphore qps_lock;
292 struct hisi_qp *qp_array;
294 struct mutex mailbox_lock;
296 const struct hisi_qm_hw_ops *ops;
298 struct qm_debug debug;
302 struct workqueue_struct *wq;
303 struct work_struct work;
304 struct work_struct rst_work;
305 struct work_struct cmd_process;
311 /* doorbell isolation enable */
312 bool use_db_isolation;
313 resource_size_t phys_base;
314 resource_size_t db_phys_base;
315 struct uacce_device *uacce;
317 struct qm_shaper_factor *factor;
322 struct hisi_qp_status {
331 int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm);
345 struct hisi_qp_status qp_status;
346 struct hisi_qp_ops *hw_ops;
348 void (*req_cb)(struct hisi_qp *qp, void *data);
349 void (*event_cb)(struct hisi_qp *qp);
355 struct uacce_queue *uacce_q;
358 static inline int q_num_set(const char *val, const struct kernel_param *kp,
361 struct pci_dev *pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI,
370 q_num = min_t(u32, QM_QNUM_V1, QM_QNUM_V2);
371 pr_info("No device found currently, suppose queue number is %u\n",
374 if (pdev->revision == QM_HW_V1)
380 ret = kstrtou32(val, 10, &n);
381 if (ret || n < QM_MIN_QNUM || n > q_num)
384 return param_set_int(val, kp);
387 static inline int vfs_num_set(const char *val, const struct kernel_param *kp)
395 ret = kstrtou32(val, 10, &n);
399 if (n > QM_MAX_VFS_NUM_V2)
402 return param_set_int(val, kp);
405 static inline int mode_set(const char *val, const struct kernel_param *kp)
413 ret = kstrtou32(val, 10, &n);
414 if (ret != 0 || (n != UACCE_MODE_SVA &&
415 n != UACCE_MODE_NOUACCE))
418 return param_set_int(val, kp);
421 static inline int uacce_mode_set(const char *val, const struct kernel_param *kp)
423 return mode_set(val, kp);
426 static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
428 INIT_LIST_HEAD(&qm_list->list);
429 mutex_init(&qm_list->lock);
432 int hisi_qm_init(struct hisi_qm *qm);
433 void hisi_qm_uninit(struct hisi_qm *qm);
434 int hisi_qm_start(struct hisi_qm *qm);
435 int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r);
436 struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type);
437 int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
438 int hisi_qm_stop_qp(struct hisi_qp *qp);
439 void hisi_qm_release_qp(struct hisi_qp *qp);
440 int hisi_qp_send(struct hisi_qp *qp, const void *msg);
441 int hisi_qm_get_free_qp_num(struct hisi_qm *qm);
442 int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number);
443 void hisi_qm_debug_init(struct hisi_qm *qm);
444 enum qm_hw_ver hisi_qm_get_hw_version(struct pci_dev *pdev);
445 void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
446 int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs);
447 int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen);
448 int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs);
449 void hisi_qm_dev_err_init(struct hisi_qm *qm);
450 void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
451 pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
452 pci_channel_state_t state);
453 pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev);
454 void hisi_qm_reset_prepare(struct pci_dev *pdev);
455 void hisi_qm_reset_done(struct pci_dev *pdev);
457 int hisi_qm_wait_mb_ready(struct hisi_qm *qm);
458 int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
461 struct hisi_acc_sgl_pool;
462 struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
463 struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool,
464 u32 index, dma_addr_t *hw_sgl_dma);
465 void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
466 struct hisi_acc_hw_sgl *hw_sgl);
467 struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
468 u32 count, u32 sge_nr);
469 void hisi_acc_free_sgl_pool(struct device *dev,
470 struct hisi_acc_sgl_pool *pool);
471 int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
472 u8 alg_type, int node, struct hisi_qp **qps);
473 void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num);
474 void hisi_qm_dev_shutdown(struct pci_dev *pdev);
475 void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
476 int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
477 void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
478 int hisi_qm_resume(struct device *dev);
479 int hisi_qm_suspend(struct device *dev);
480 void hisi_qm_pm_uninit(struct hisi_qm *qm);
481 void hisi_qm_pm_init(struct hisi_qm *qm);
482 int hisi_qm_get_dfx_access(struct hisi_qm *qm);
483 void hisi_qm_put_dfx_access(struct hisi_qm *qm);
484 void hisi_qm_regs_dump(struct seq_file *s, struct debugfs_regset32 *regset);
486 /* Used by VFIO ACC live migration driver */
487 struct pci_driver *hisi_sec_get_pf_driver(void);
488 struct pci_driver *hisi_hpre_get_pf_driver(void);
489 struct pci_driver *hisi_zip_get_pf_driver(void);