1 #ifndef __LINUX_GPIO_DRIVER_H
2 #define __LINUX_GPIO_DRIVER_H
4 #include <linux/device.h>
5 #include <linux/types.h>
7 #include <linux/irqchip/chained_irq.h>
8 #include <linux/irqdomain.h>
9 #include <linux/lockdep.h>
10 #include <linux/pinctrl/pinctrl.h>
11 #include <linux/pinctrl/pinconf-generic.h>
14 struct of_phandle_args;
22 #ifdef CONFIG_GPIOLIB_IRQCHIP
24 * struct gpio_irq_chip - GPIO interrupt controller
26 struct gpio_irq_chip {
30 * GPIO IRQ chip implementation, provided by GPIO driver.
32 struct irq_chip *chip;
37 * Interrupt translation domain; responsible for mapping between GPIO
38 * hwirq number and Linux IRQ number.
40 struct irq_domain *domain;
45 * Table of interrupt domain operations for this IRQ chip.
47 const struct irq_domain_ops *domain_ops;
52 * The IRQ handler to use (often a predefined IRQ core function) for
53 * GPIO IRQs, provided by GPIO driver.
55 irq_flow_handler_t handler;
60 * Default IRQ triggering type applied during GPIO driver
61 * initialization, provided by GPIO driver.
63 unsigned int default_type;
68 * Per GPIO IRQ chip lockdep class.
70 struct lock_class_key *lock_key;
75 * The interrupt handler for the GPIO chip's parent interrupts, may be
76 * NULL if the parent interrupts are nested rather than cascaded.
78 irq_flow_handler_t parent_handler;
81 * @parent_handler_data:
83 * Data associated, and passed to, the handler for the parent
86 void *parent_handler_data;
91 * The number of interrupt parents of a GPIO chip.
93 unsigned int num_parents;
98 * A list of interrupt parents of a GPIO chip. This is owned by the
99 * driver, so the core will only reference this list, not modify it.
101 unsigned int *parents;
106 * True if set the interrupt handling is nested.
113 * If set core allocates @valid_mask with all bits set to one.
115 bool need_valid_mask;
120 * If not %NULL holds bitmask of GPIOs which are valid to be included
121 * in IRQ domain of the chip.
123 unsigned long *valid_mask;
126 static inline struct gpio_irq_chip *to_gpio_irq_chip(struct irq_chip *chip)
128 return container_of(chip, struct gpio_irq_chip, chip);
133 * struct gpio_chip - abstract a GPIO controller
134 * @label: a functional name for the GPIO device, such as a part
135 * number or the name of the SoC IP-block implementing it.
136 * @gpiodev: the internal state holder, opaque struct
137 * @parent: optional parent device providing the GPIOs
138 * @owner: helps prevent removal of modules exporting active GPIOs
139 * @request: optional hook for chip-specific activation, such as
140 * enabling module power and clock; may sleep
141 * @free: optional hook for chip-specific deactivation, such as
142 * disabling module power and clock; may sleep
143 * @get_direction: returns direction for signal "offset", 0=out, 1=in,
144 * (same as GPIOF_DIR_XXX), or negative error
145 * @direction_input: configures signal "offset" as input, or returns error
146 * @direction_output: configures signal "offset" as output, or returns error
147 * @get: returns value for signal "offset", 0=low, 1=high, or negative error
148 * @get_multiple: reads values for multiple signals defined by "mask" and
149 * stores them in "bits", returns 0 on success or negative error
150 * @set: assigns output value for signal "offset"
151 * @set_multiple: assigns output values for multiple signals defined by "mask"
152 * @set_config: optional hook for all kinds of settings. Uses the same
153 * packed config format as generic pinconf.
154 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
155 * implementation may not sleep
156 * @dbg_show: optional routine to show contents in debugfs; default code
157 * will be used when this is omitted, but custom code can show extra
158 * state (such as pullup/pulldown configuration).
159 * @base: identifies the first GPIO number handled by this chip;
160 * or, if negative during registration, requests dynamic ID allocation.
161 * DEPRECATION: providing anything non-negative and nailing the base
162 * offset of GPIO chips is deprecated. Please pass -1 as base to
163 * let gpiolib select the chip base in all possible cases. We want to
164 * get rid of the static GPIO number space in the long run.
165 * @ngpio: the number of GPIOs handled by this controller; the last GPIO
166 * handled is (base + ngpio - 1).
167 * @names: if set, must be an array of strings to use as alternative
168 * names for the GPIOs in this chip. Any entry in the array
169 * may be NULL if there is no alias for the GPIO, however the
170 * array must be @ngpio entries long. A name can include a single printk
171 * format specifier for an unsigned int. It is substituted by the actual
172 * number of the gpio.
173 * @can_sleep: flag must be set iff get()/set() methods sleep, as they
174 * must while accessing GPIO expander chips over I2C or SPI. This
175 * implies that if the chip supports IRQs, these IRQs need to be threaded
176 * as the chip access may sleep when e.g. reading out the IRQ status
178 * @read_reg: reader function for generic GPIO
179 * @write_reg: writer function for generic GPIO
180 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
181 * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
182 * generic GPIO core. It is for internal housekeeping only.
183 * @reg_dat: data (in) register for generic GPIO
184 * @reg_set: output set register (out=high) for generic GPIO
185 * @reg_clr: output clear register (out=low) for generic GPIO
186 * @reg_dir: direction setting register for generic GPIO
187 * @bgpio_bits: number of register bits used for a generic GPIO i.e.
188 * <register width> * 8
189 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
190 * shadowed and real data registers writes together.
191 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits
193 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
196 * A gpio_chip can help platforms abstract various sources of GPIOs so
197 * they can all be accessed through a common programing interface.
198 * Example sources would be SOC controllers, FPGAs, multifunction
199 * chips, dedicated GPIO expanders, and so on.
201 * Each chip controls a number of signals, identified in method calls
202 * by "offset" values in the range 0..(@ngpio - 1). When those signals
203 * are referenced through calls like gpio_get_value(gpio), the offset
204 * is calculated by subtracting @base from the gpio number.
208 struct gpio_device *gpiodev;
209 struct device *parent;
210 struct module *owner;
212 int (*request)(struct gpio_chip *chip,
214 void (*free)(struct gpio_chip *chip,
216 int (*get_direction)(struct gpio_chip *chip,
218 int (*direction_input)(struct gpio_chip *chip,
220 int (*direction_output)(struct gpio_chip *chip,
221 unsigned offset, int value);
222 int (*get)(struct gpio_chip *chip,
224 int (*get_multiple)(struct gpio_chip *chip,
226 unsigned long *bits);
227 void (*set)(struct gpio_chip *chip,
228 unsigned offset, int value);
229 void (*set_multiple)(struct gpio_chip *chip,
231 unsigned long *bits);
232 int (*set_config)(struct gpio_chip *chip,
234 unsigned long config);
235 int (*to_irq)(struct gpio_chip *chip,
238 void (*dbg_show)(struct seq_file *s,
239 struct gpio_chip *chip);
242 const char *const *names;
245 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
246 unsigned long (*read_reg)(void __iomem *reg);
247 void (*write_reg)(void __iomem *reg, unsigned long data);
249 void __iomem *reg_dat;
250 void __iomem *reg_set;
251 void __iomem *reg_clr;
252 void __iomem *reg_dir;
254 spinlock_t bgpio_lock;
255 unsigned long bgpio_data;
256 unsigned long bgpio_dir;
259 #ifdef CONFIG_GPIOLIB_IRQCHIP
261 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
262 * to handle IRQs for most practical cases.
268 * Integrates interrupt chip functionality with the GPIO chip. Can be
269 * used to handle IRQs for most practical cases.
271 struct gpio_irq_chip irq;
274 #if defined(CONFIG_OF_GPIO)
276 * If CONFIG_OF is enabled, then all GPIO controllers described in the
277 * device tree automatically may have an OF translation
283 * Pointer to a device tree node representing this GPIO controller.
285 struct device_node *of_node;
290 * Number of cells used to form the GPIO specifier.
292 unsigned int of_gpio_n_cells;
297 * Callback to translate a device tree GPIO specifier into a chip-
298 * relative GPIO number and flags.
300 int (*of_xlate)(struct gpio_chip *gc,
301 const struct of_phandle_args *gpiospec, u32 *flags);
305 extern const char *gpiochip_is_requested(struct gpio_chip *chip,
308 /* add/remove chips */
309 extern int gpiochip_add_data(struct gpio_chip *chip, void *data);
310 static inline int gpiochip_add(struct gpio_chip *chip)
312 return gpiochip_add_data(chip, NULL);
314 extern void gpiochip_remove(struct gpio_chip *chip);
315 extern int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip,
317 extern void devm_gpiochip_remove(struct device *dev, struct gpio_chip *chip);
319 extern struct gpio_chip *gpiochip_find(void *data,
320 int (*match)(struct gpio_chip *chip, void *data));
322 /* lock/unlock as IRQ */
323 int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
324 void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
325 bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset);
327 /* Line status inquiry for drivers */
328 bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset);
329 bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset);
331 /* Sleep persistence inquiry for drivers */
332 bool gpiochip_line_is_persistent(struct gpio_chip *chip, unsigned int offset);
334 /* get driver data */
335 void *gpiochip_get_data(struct gpio_chip *chip);
337 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
345 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
347 int bgpio_init(struct gpio_chip *gc, struct device *dev,
348 unsigned long sz, void __iomem *dat, void __iomem *set,
349 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
350 unsigned long flags);
352 #define BGPIOF_BIG_ENDIAN BIT(0)
353 #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
354 #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
355 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
356 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
357 #define BGPIOF_NO_OUTPUT BIT(5) /* only input */
361 #ifdef CONFIG_GPIOLIB_IRQCHIP
363 void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
364 struct irq_chip *irqchip,
365 unsigned int parent_irq,
366 irq_flow_handler_t parent_handler);
368 void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip,
369 struct irq_chip *irqchip,
370 unsigned int parent_irq);
372 int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip,
373 struct irq_chip *irqchip,
374 unsigned int first_irq,
375 irq_flow_handler_t handler,
378 struct lock_class_key *lock_key);
380 #ifdef CONFIG_LOCKDEP
383 * Lockdep requires that each irqchip instance be created with a
384 * unique key so as to avoid unnecessary warnings. This upfront
385 * boilerplate static inlines provides such a key for each
388 static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
389 struct irq_chip *irqchip,
390 unsigned int first_irq,
391 irq_flow_handler_t handler,
394 static struct lock_class_key key;
396 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
397 handler, type, false, &key);
400 static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
401 struct irq_chip *irqchip,
402 unsigned int first_irq,
403 irq_flow_handler_t handler,
407 static struct lock_class_key key;
409 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
410 handler, type, true, &key);
413 static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
414 struct irq_chip *irqchip,
415 unsigned int first_irq,
416 irq_flow_handler_t handler,
419 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
420 handler, type, false, NULL);
423 static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
424 struct irq_chip *irqchip,
425 unsigned int first_irq,
426 irq_flow_handler_t handler,
429 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
430 handler, type, true, NULL);
432 #endif /* CONFIG_LOCKDEP */
434 #endif /* CONFIG_GPIOLIB_IRQCHIP */
436 int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset);
437 void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset);
438 int gpiochip_generic_config(struct gpio_chip *chip, unsigned offset,
439 unsigned long config);
441 #ifdef CONFIG_PINCTRL
444 * struct gpio_pin_range - pin range controlled by a gpio chip
445 * @node: list for maintaining set of pin ranges, used internally
446 * @pctldev: pinctrl device which handles corresponding pins
447 * @range: actual range of pins controlled by a gpio controller
449 struct gpio_pin_range {
450 struct list_head node;
451 struct pinctrl_dev *pctldev;
452 struct pinctrl_gpio_range range;
455 int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
456 unsigned int gpio_offset, unsigned int pin_offset,
458 int gpiochip_add_pingroup_range(struct gpio_chip *chip,
459 struct pinctrl_dev *pctldev,
460 unsigned int gpio_offset, const char *pin_group);
461 void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
466 gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
467 unsigned int gpio_offset, unsigned int pin_offset,
473 gpiochip_add_pingroup_range(struct gpio_chip *chip,
474 struct pinctrl_dev *pctldev,
475 unsigned int gpio_offset, const char *pin_group)
481 gpiochip_remove_pin_ranges(struct gpio_chip *chip)
485 #endif /* CONFIG_PINCTRL */
487 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
489 void gpiochip_free_own_desc(struct gpio_desc *desc);
491 #else /* CONFIG_GPIOLIB */
493 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
495 /* GPIO can never have been requested */
497 return ERR_PTR(-ENODEV);
500 #endif /* CONFIG_GPIOLIB */