4 * Copyright (C) 2013-2015 Altera Corporation
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/mutex.h>
19 #include <linux/platform_device.h>
21 #ifndef _LINUX_FPGA_MGR_H
22 #define _LINUX_FPGA_MGR_H
28 * enum fpga_mgr_states - fpga framework states
29 * @FPGA_MGR_STATE_UNKNOWN: can't determine state
30 * @FPGA_MGR_STATE_POWER_OFF: FPGA power is off
31 * @FPGA_MGR_STATE_POWER_UP: FPGA reports power is up
32 * @FPGA_MGR_STATE_RESET: FPGA in reset state
33 * @FPGA_MGR_STATE_FIRMWARE_REQ: firmware request in progress
34 * @FPGA_MGR_STATE_FIRMWARE_REQ_ERR: firmware request failed
35 * @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming
36 * @FPGA_MGR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage
37 * @FPGA_MGR_STATE_WRITE: writing image to FPGA
38 * @FPGA_MGR_STATE_WRITE_ERR: Error while writing FPGA
39 * @FPGA_MGR_STATE_WRITE_COMPLETE: Doing post programming steps
40 * @FPGA_MGR_STATE_WRITE_COMPLETE_ERR: Error during WRITE_COMPLETE
41 * @FPGA_MGR_STATE_OPERATING: FPGA is programmed and operating
43 enum fpga_mgr_states {
44 /* default FPGA states */
45 FPGA_MGR_STATE_UNKNOWN,
46 FPGA_MGR_STATE_POWER_OFF,
47 FPGA_MGR_STATE_POWER_UP,
50 /* getting an image for loading */
51 FPGA_MGR_STATE_FIRMWARE_REQ,
52 FPGA_MGR_STATE_FIRMWARE_REQ_ERR,
54 /* write sequence: init, write, complete */
55 FPGA_MGR_STATE_WRITE_INIT,
56 FPGA_MGR_STATE_WRITE_INIT_ERR,
58 FPGA_MGR_STATE_WRITE_ERR,
59 FPGA_MGR_STATE_WRITE_COMPLETE,
60 FPGA_MGR_STATE_WRITE_COMPLETE_ERR,
62 /* fpga is programmed and operating */
63 FPGA_MGR_STATE_OPERATING,
68 * FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported
69 * FPGA_MGR_EXTERNAL_CONFIG: FPGA has been configured prior to Linux booting
70 * FPGA_MGR_BITSTREAM_LSB_FIRST: SPI bitstream bit order is LSB first
71 * FPGA_MGR_COMPRESSED_BITSTREAM: FPGA bitstream is compressed
73 #define FPGA_MGR_PARTIAL_RECONFIG BIT(0)
74 #define FPGA_MGR_EXTERNAL_CONFIG BIT(1)
75 #define FPGA_MGR_ENCRYPTED_BITSTREAM BIT(2)
76 #define FPGA_MGR_BITSTREAM_LSB_FIRST BIT(3)
77 #define FPGA_MGR_COMPRESSED_BITSTREAM BIT(4)
80 * struct fpga_image_info - information specific to a FPGA image
81 * @flags: boolean flags as defined above
82 * @enable_timeout_us: maximum time to enable traffic through bridge (uSec)
83 * @disable_timeout_us: maximum time to disable traffic through bridge (uSec)
84 * @config_complete_timeout_us: maximum time for FPGA to switch to operating
85 * status in the write_complete op.
87 struct fpga_image_info {
89 u32 enable_timeout_us;
90 u32 disable_timeout_us;
91 u32 config_complete_timeout_us;
95 * struct fpga_manager_ops - ops for low level fpga manager drivers
96 * @initial_header_size: Maximum number of bytes that should be passed into write_init
97 * @state: returns an enum value of the FPGA's state
98 * @write_init: prepare the FPGA to receive confuration data
99 * @write: write count bytes of configuration data to the FPGA
100 * @write_sg: write the scatter list of configuration data to the FPGA
101 * @write_complete: set FPGA to operating state after writing is done
102 * @fpga_remove: optional: Set FPGA into a specific state during driver remove
104 * fpga_manager_ops are the low level functions implemented by a specific
105 * fpga manager driver. The optional ones are tested for NULL before being
106 * called, so leaving them out is fine.
108 struct fpga_manager_ops {
109 size_t initial_header_size;
110 enum fpga_mgr_states (*state)(struct fpga_manager *mgr);
111 int (*write_init)(struct fpga_manager *mgr,
112 struct fpga_image_info *info,
113 const char *buf, size_t count);
114 int (*write)(struct fpga_manager *mgr, const char *buf, size_t count);
115 int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt);
116 int (*write_complete)(struct fpga_manager *mgr,
117 struct fpga_image_info *info);
118 void (*fpga_remove)(struct fpga_manager *mgr);
122 * struct fpga_manager - fpga manager structure
123 * @name: name of low level fpga manager
124 * @dev: fpga manager device
125 * @ref_mutex: only allows one reference to fpga manager
126 * @state: state of fpga manager
127 * @mops: pointer to struct of fpga manager ops
128 * @priv: low level driver private date
130 struct fpga_manager {
133 struct mutex ref_mutex;
134 enum fpga_mgr_states state;
135 const struct fpga_manager_ops *mops;
139 #define to_fpga_manager(d) container_of(d, struct fpga_manager, dev)
141 int fpga_mgr_buf_load(struct fpga_manager *mgr, struct fpga_image_info *info,
142 const char *buf, size_t count);
143 int fpga_mgr_buf_load_sg(struct fpga_manager *mgr, struct fpga_image_info *info,
144 struct sg_table *sgt);
146 int fpga_mgr_firmware_load(struct fpga_manager *mgr,
147 struct fpga_image_info *info,
148 const char *image_name);
150 struct fpga_manager *of_fpga_mgr_get(struct device_node *node);
152 struct fpga_manager *fpga_mgr_get(struct device *dev);
154 void fpga_mgr_put(struct fpga_manager *mgr);
156 int fpga_mgr_register(struct device *dev, const char *name,
157 const struct fpga_manager_ops *mops, void *priv);
159 void fpga_mgr_unregister(struct device *dev);
161 #endif /*_LINUX_FPGA_MGR_H */