include/linux/firmware/xlnx-zynqmp.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Xilinx Zynq MPSoC Firmware layer
   4  *
   5  *  Copyright (C) 2014-2021 Xilinx
   6  *
   7  *  Michal Simek <michal.simek@xilinx.com>
   8  *  Davorin Mista <davorin.mista@aggios.com>
   9  *  Jolly Shah <jollys@xilinx.com>
  10  *  Rajan Vaja <rajanv@xilinx.com>
  11  */
  12
  13 #ifndef __FIRMWARE_ZYNQMP_H__
  14 #define __FIRMWARE_ZYNQMP_H__
  15 #include <linux/types.h>
  16
  17 #include <linux/err.h>
  18
  19 #define ZYNQMP_PM_VERSION_MAJOR 1
  20 #define ZYNQMP_PM_VERSION_MINOR 0
  21
  22 #define ZYNQMP_PM_VERSION       ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
  23                                         ZYNQMP_PM_VERSION_MINOR)
  24
  25 #define ZYNQMP_TZ_VERSION_MAJOR 1
  26 #define ZYNQMP_TZ_VERSION_MINOR 0
  27
  28 #define ZYNQMP_TZ_VERSION       ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
  29                                         ZYNQMP_TZ_VERSION_MINOR)
  30
  31 /* SMC SIP service Call Function Identifier Prefix */
  32 #define PM_SIP_SVC                      0xC2000000
  33
  34 /* PM API versions */
  35 #define PM_API_VERSION_2        2
  36
  37 /* ATF only commands */
  38 #define TF_A_PM_REGISTER_SGI            0xa04
  39 #define PM_GET_TRUSTZONE_VERSION        0xa03
  40 #define PM_SET_SUSPEND_MODE             0xa02
  41 #define GET_CALLBACK_DATA               0xa01
  42
  43 /* Number of 32bits values in payload */
  44 #define PAYLOAD_ARG_CNT 4U
  45
  46 /* Number of arguments for a callback */
  47 #define CB_ARG_CNT     4
  48
  49 /* Payload size (consists of callback API ID + arguments) */
  50 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
  51
  52 #define ZYNQMP_PM_MAX_QOS               100U
  53
  54 #define GSS_NUM_REGS    (4)
  55
  56 /* Node capabilities */
  57 #define ZYNQMP_PM_CAPABILITY_ACCESS     0x1U
  58 #define ZYNQMP_PM_CAPABILITY_CONTEXT    0x2U
  59 #define ZYNQMP_PM_CAPABILITY_WAKEUP     0x4U
  60 #define ZYNQMP_PM_CAPABILITY_UNUSABLE   0x8U
  61
  62 /* Loader commands */
  63 #define PM_LOAD_PDI     0x701
  64 #define PDI_SRC_DDR     0xF
  65
  66 /*
  67  * Firmware FPGA Manager flags
  68  * XILINX_ZYNQMP_PM_FPGA_FULL:  FPGA full reconfiguration
  69  * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
  70  */
  71 #define XILINX_ZYNQMP_PM_FPGA_FULL      0x0U
  72 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL   BIT(0)
  73
  74 /*
  75  * Node IDs for the Error Events.
  76  */
  77 #define EVENT_ERROR_PMC_ERR1    (0x28100000U)
  78 #define EVENT_ERROR_PMC_ERR2    (0x28104000U)
  79 #define EVENT_ERROR_PSM_ERR1    (0x28108000U)
  80 #define EVENT_ERROR_PSM_ERR2    (0x2810C000U)
  81
  82 /* ZynqMP SD tap delay tuning */
  83 #define SD_ITAPDLY      0xFF180314
  84 #define SD_OTAPDLYSEL   0xFF180318
  85
  86 enum pm_api_cb_id {
  87         PM_INIT_SUSPEND_CB = 30,
  88         PM_ACKNOWLEDGE_CB = 31,
  89         PM_NOTIFY_CB = 32,
  90 };
  91
  92 enum pm_api_id {
  93         PM_GET_API_VERSION = 1,
  94         PM_REGISTER_NOTIFIER = 5,
  95         PM_FORCE_POWERDOWN = 8,
  96         PM_REQUEST_WAKEUP = 10,
  97         PM_SYSTEM_SHUTDOWN = 12,
  98         PM_REQUEST_NODE = 13,
  99         PM_RELEASE_NODE = 14,
 100         PM_SET_REQUIREMENT = 15,
 101         PM_RESET_ASSERT = 17,
 102         PM_RESET_GET_STATUS = 18,
 103         PM_MMIO_WRITE = 19,
 104         PM_MMIO_READ = 20,
 105         PM_PM_INIT_FINALIZE = 21,
 106         PM_FPGA_LOAD = 22,
 107         PM_FPGA_GET_STATUS = 23,
 108         PM_GET_CHIPID = 24,
 109         PM_SECURE_SHA = 26,
 110         PM_PINCTRL_REQUEST = 28,
 111         PM_PINCTRL_RELEASE = 29,
 112         PM_PINCTRL_GET_FUNCTION = 30,
 113         PM_PINCTRL_SET_FUNCTION = 31,
 114         PM_PINCTRL_CONFIG_PARAM_GET = 32,
 115         PM_PINCTRL_CONFIG_PARAM_SET = 33,
 116         PM_IOCTL = 34,
 117         PM_QUERY_DATA = 35,
 118         PM_CLOCK_ENABLE = 36,
 119         PM_CLOCK_DISABLE = 37,
 120         PM_CLOCK_GETSTATE = 38,
 121         PM_CLOCK_SETDIVIDER = 39,
 122         PM_CLOCK_GETDIVIDER = 40,
 123         PM_CLOCK_SETRATE = 41,
 124         PM_CLOCK_GETRATE = 42,
 125         PM_CLOCK_SETPARENT = 43,
 126         PM_CLOCK_GETPARENT = 44,
 127         PM_SECURE_AES = 47,
 128         PM_FEATURE_CHECK = 63,
 129 };
 130
 131 /* PMU-FW return status codes */
 132 enum pm_ret_status {
 133         XST_PM_SUCCESS = 0,
 134         XST_PM_NO_FEATURE = 19,
 135         XST_PM_INTERNAL = 2000,
 136         XST_PM_CONFLICT = 2001,
 137         XST_PM_NO_ACCESS = 2002,
 138         XST_PM_INVALID_NODE = 2003,
 139         XST_PM_DOUBLE_REQ = 2004,
 140         XST_PM_ABORT_SUSPEND = 2005,
 141         XST_PM_MULT_USER = 2008,
 142 };
 143
 144 enum pm_ioctl_id {
 145         IOCTL_GET_RPU_OPER_MODE = 0,
 146         IOCTL_SET_RPU_OPER_MODE = 1,
 147         IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
 148         IOCTL_TCM_COMB_CONFIG = 3,
 149         IOCTL_SET_TAPDELAY_BYPASS = 4,
 150         IOCTL_SD_DLL_RESET = 6,
 151         IOCTL_SET_SD_TAPDELAY = 7,
 152         IOCTL_SET_PLL_FRAC_MODE = 8,
 153         IOCTL_GET_PLL_FRAC_MODE = 9,
 154         IOCTL_SET_PLL_FRAC_DATA = 10,
 155         IOCTL_GET_PLL_FRAC_DATA = 11,
 156         IOCTL_WRITE_GGS = 12,
 157         IOCTL_READ_GGS = 13,
 158         IOCTL_WRITE_PGGS = 14,
 159         IOCTL_READ_PGGS = 15,
 160         /* Set healthy bit value */
 161         IOCTL_SET_BOOT_HEALTH_STATUS = 17,
 162         IOCTL_OSPI_MUX_SELECT = 21,
 163         /* Register SGI to ATF */
 164         IOCTL_REGISTER_SGI = 25,
 165         /* Runtime feature configuration */
 166         IOCTL_SET_FEATURE_CONFIG = 26,
 167         IOCTL_GET_FEATURE_CONFIG = 27,
 168         /* Dynamic SD/GEM configuration */
 169         IOCTL_SET_SD_CONFIG = 30,
 170         IOCTL_SET_GEM_CONFIG = 31,
 171 };
 172
 173 enum pm_query_id {
 174         PM_QID_INVALID = 0,
 175         PM_QID_CLOCK_GET_NAME = 1,
 176         PM_QID_CLOCK_GET_TOPOLOGY = 2,
 177         PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
 178         PM_QID_CLOCK_GET_PARENTS = 4,
 179         PM_QID_CLOCK_GET_ATTRIBUTES = 5,
 180         PM_QID_PINCTRL_GET_NUM_PINS = 6,
 181         PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
 182         PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
 183         PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
 184         PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
 185         PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
 186         PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
 187         PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
 188 };
 189
 190 enum rpu_oper_mode {
 191         PM_RPU_MODE_LOCKSTEP = 0,
 192         PM_RPU_MODE_SPLIT = 1,
 193 };
 194
 195 enum rpu_boot_mem {
 196         PM_RPU_BOOTMEM_LOVEC = 0,
 197         PM_RPU_BOOTMEM_HIVEC = 1,
 198 };
 199
 200 enum rpu_tcm_comb {
 201         PM_RPU_TCM_SPLIT = 0,
 202         PM_RPU_TCM_COMB = 1,
 203 };
 204
 205 enum zynqmp_pm_reset_action {
 206         PM_RESET_ACTION_RELEASE = 0,
 207         PM_RESET_ACTION_ASSERT = 1,
 208         PM_RESET_ACTION_PULSE = 2,
 209 };
 210
 211 enum zynqmp_pm_reset {
 212         ZYNQMP_PM_RESET_START = 1000,
 213         ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
 214         ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
 215         ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
 216         ZYNQMP_PM_RESET_DP = 1003,
 217         ZYNQMP_PM_RESET_SWDT_CRF = 1004,
 218         ZYNQMP_PM_RESET_AFI_FM5 = 1005,
 219         ZYNQMP_PM_RESET_AFI_FM4 = 1006,
 220         ZYNQMP_PM_RESET_AFI_FM3 = 1007,
 221         ZYNQMP_PM_RESET_AFI_FM2 = 1008,
 222         ZYNQMP_PM_RESET_AFI_FM1 = 1009,
 223         ZYNQMP_PM_RESET_AFI_FM0 = 1010,
 224         ZYNQMP_PM_RESET_GDMA = 1011,
 225         ZYNQMP_PM_RESET_GPU_PP1 = 1012,
 226         ZYNQMP_PM_RESET_GPU_PP0 = 1013,
 227         ZYNQMP_PM_RESET_GPU = 1014,
 228         ZYNQMP_PM_RESET_GT = 1015,
 229         ZYNQMP_PM_RESET_SATA = 1016,
 230         ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
 231         ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
 232         ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
 233         ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
 234         ZYNQMP_PM_RESET_APU_L2 = 1021,
 235         ZYNQMP_PM_RESET_ACPU3 = 1022,
 236         ZYNQMP_PM_RESET_ACPU2 = 1023,
 237         ZYNQMP_PM_RESET_ACPU1 = 1024,
 238         ZYNQMP_PM_RESET_ACPU0 = 1025,
 239         ZYNQMP_PM_RESET_DDR = 1026,
 240         ZYNQMP_PM_RESET_APM_FPD = 1027,
 241         ZYNQMP_PM_RESET_SOFT = 1028,
 242         ZYNQMP_PM_RESET_GEM0 = 1029,
 243         ZYNQMP_PM_RESET_GEM1 = 1030,
 244         ZYNQMP_PM_RESET_GEM2 = 1031,
 245         ZYNQMP_PM_RESET_GEM3 = 1032,
 246         ZYNQMP_PM_RESET_QSPI = 1033,
 247         ZYNQMP_PM_RESET_UART0 = 1034,
 248         ZYNQMP_PM_RESET_UART1 = 1035,
 249         ZYNQMP_PM_RESET_SPI0 = 1036,
 250         ZYNQMP_PM_RESET_SPI1 = 1037,
 251         ZYNQMP_PM_RESET_SDIO0 = 1038,
 252         ZYNQMP_PM_RESET_SDIO1 = 1039,
 253         ZYNQMP_PM_RESET_CAN0 = 1040,
 254         ZYNQMP_PM_RESET_CAN1 = 1041,
 255         ZYNQMP_PM_RESET_I2C0 = 1042,
 256         ZYNQMP_PM_RESET_I2C1 = 1043,
 257         ZYNQMP_PM_RESET_TTC0 = 1044,
 258         ZYNQMP_PM_RESET_TTC1 = 1045,
 259         ZYNQMP_PM_RESET_TTC2 = 1046,
 260         ZYNQMP_PM_RESET_TTC3 = 1047,
 261         ZYNQMP_PM_RESET_SWDT_CRL = 1048,
 262         ZYNQMP_PM_RESET_NAND = 1049,
 263         ZYNQMP_PM_RESET_ADMA = 1050,
 264         ZYNQMP_PM_RESET_GPIO = 1051,
 265         ZYNQMP_PM_RESET_IOU_CC = 1052,
 266         ZYNQMP_PM_RESET_TIMESTAMP = 1053,
 267         ZYNQMP_PM_RESET_RPU_R50 = 1054,
 268         ZYNQMP_PM_RESET_RPU_R51 = 1055,
 269         ZYNQMP_PM_RESET_RPU_AMBA = 1056,
 270         ZYNQMP_PM_RESET_OCM = 1057,
 271         ZYNQMP_PM_RESET_RPU_PGE = 1058,
 272         ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
 273         ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
 274         ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
 275         ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
 276         ZYNQMP_PM_RESET_USB0_APB = 1063,
 277         ZYNQMP_PM_RESET_USB1_APB = 1064,
 278         ZYNQMP_PM_RESET_IPI = 1065,
 279         ZYNQMP_PM_RESET_APM_LPD = 1066,
 280         ZYNQMP_PM_RESET_RTC = 1067,
 281         ZYNQMP_PM_RESET_SYSMON = 1068,
 282         ZYNQMP_PM_RESET_AFI_FM6 = 1069,
 283         ZYNQMP_PM_RESET_LPD_SWDT = 1070,
 284         ZYNQMP_PM_RESET_FPD = 1071,
 285         ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
 286         ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
 287         ZYNQMP_PM_RESET_DBG_LPD = 1074,
 288         ZYNQMP_PM_RESET_DBG_FPD = 1075,
 289         ZYNQMP_PM_RESET_APLL = 1076,
 290         ZYNQMP_PM_RESET_DPLL = 1077,
 291         ZYNQMP_PM_RESET_VPLL = 1078,
 292         ZYNQMP_PM_RESET_IOPLL = 1079,
 293         ZYNQMP_PM_RESET_RPLL = 1080,
 294         ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
 295         ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
 296         ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
 297         ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
 298         ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
 299         ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
 300         ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
 301         ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
 302         ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
 303         ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
 304         ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
 305         ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
 306         ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
 307         ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
 308         ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
 309         ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
 310         ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
 311         ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
 312         ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
 313         ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
 314         ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
 315         ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
 316         ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
 317         ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
 318         ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
 319         ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
 320         ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
 321         ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
 322         ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
 323         ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
 324         ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
 325         ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
 326         ZYNQMP_PM_RESET_RPU_LS = 1113,
 327         ZYNQMP_PM_RESET_PS_ONLY = 1114,
 328         ZYNQMP_PM_RESET_PL = 1115,
 329         ZYNQMP_PM_RESET_PS_PL0 = 1116,
 330         ZYNQMP_PM_RESET_PS_PL1 = 1117,
 331         ZYNQMP_PM_RESET_PS_PL2 = 1118,
 332         ZYNQMP_PM_RESET_PS_PL3 = 1119,
 333         ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
 334 };
 335
 336 enum zynqmp_pm_suspend_reason {
 337         SUSPEND_POWER_REQUEST = 201,
 338         SUSPEND_ALERT = 202,
 339         SUSPEND_SYSTEM_SHUTDOWN = 203,
 340 };
 341
 342 enum zynqmp_pm_request_ack {
 343         ZYNQMP_PM_REQUEST_ACK_NO = 1,
 344         ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
 345         ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
 346 };
 347
 348 enum pm_node_id {
 349         NODE_SD_0 = 39,
 350         NODE_SD_1 = 40,
 351 };
 352
 353 enum tap_delay_type {
 354         PM_TAPDELAY_INPUT = 0,
 355         PM_TAPDELAY_OUTPUT = 1,
 356 };
 357
 358 enum dll_reset_type {
 359         PM_DLL_RESET_ASSERT = 0,
 360         PM_DLL_RESET_RELEASE = 1,
 361         PM_DLL_RESET_PULSE = 2,
 362 };
 363
 364 enum pm_pinctrl_config_param {
 365         PM_PINCTRL_CONFIG_SLEW_RATE = 0,
 366         PM_PINCTRL_CONFIG_BIAS_STATUS = 1,
 367         PM_PINCTRL_CONFIG_PULL_CTRL = 2,
 368         PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3,
 369         PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4,
 370         PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5,
 371         PM_PINCTRL_CONFIG_TRI_STATE = 6,
 372         PM_PINCTRL_CONFIG_MAX = 7,
 373 };
 374
 375 enum pm_pinctrl_slew_rate {
 376         PM_PINCTRL_SLEW_RATE_FAST = 0,
 377         PM_PINCTRL_SLEW_RATE_SLOW = 1,
 378 };
 379
 380 enum pm_pinctrl_bias_status {
 381         PM_PINCTRL_BIAS_DISABLE = 0,
 382         PM_PINCTRL_BIAS_ENABLE = 1,
 383 };
 384
 385 enum pm_pinctrl_pull_ctrl {
 386         PM_PINCTRL_BIAS_PULL_DOWN = 0,
 387         PM_PINCTRL_BIAS_PULL_UP = 1,
 388 };
 389
 390 enum pm_pinctrl_schmitt_cmos {
 391         PM_PINCTRL_INPUT_TYPE_CMOS = 0,
 392         PM_PINCTRL_INPUT_TYPE_SCHMITT = 1,
 393 };
 394
 395 enum pm_pinctrl_drive_strength {
 396         PM_PINCTRL_DRIVE_STRENGTH_2MA = 0,
 397         PM_PINCTRL_DRIVE_STRENGTH_4MA = 1,
 398         PM_PINCTRL_DRIVE_STRENGTH_8MA = 2,
 399         PM_PINCTRL_DRIVE_STRENGTH_12MA = 3,
 400 };
 401
 402 enum pm_pinctrl_tri_state {
 403         PM_PINCTRL_TRI_STATE_DISABLE = 0,
 404         PM_PINCTRL_TRI_STATE_ENABLE = 1,
 405 };
 406
 407 enum zynqmp_pm_shutdown_type {
 408         ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0,
 409         ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1,
 410         ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2,
 411 };
 412
 413 enum zynqmp_pm_shutdown_subtype {
 414         ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0,
 415         ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1,
 416         ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
 417 };
 418
 419 enum tap_delay_signal_type {
 420         PM_TAPDELAY_NAND_DQS_IN = 0,
 421         PM_TAPDELAY_NAND_DQS_OUT = 1,
 422         PM_TAPDELAY_QSPI = 2,
 423         PM_TAPDELAY_MAX = 3,
 424 };
 425
 426 enum tap_delay_bypass_ctrl {
 427         PM_TAPDELAY_BYPASS_DISABLE = 0,
 428         PM_TAPDELAY_BYPASS_ENABLE = 1,
 429 };
 430
 431 enum ospi_mux_select_type {
 432         PM_OSPI_MUX_SEL_DMA = 0,
 433         PM_OSPI_MUX_SEL_LINEAR = 1,
 434 };
 435
 436 enum pm_feature_config_id {
 437         PM_FEATURE_INVALID = 0,
 438         PM_FEATURE_OVERTEMP_STATUS = 1,
 439         PM_FEATURE_OVERTEMP_VALUE = 2,
 440         PM_FEATURE_EXTWDT_STATUS = 3,
 441         PM_FEATURE_EXTWDT_VALUE = 4,
 442 };
 443
 444 /**
 445  * enum pm_sd_config_type - PM SD configuration.
 446  * @SD_CONFIG_EMMC_SEL: To set SD_EMMC_SEL in CTRL_REG_SD and SD_SLOTTYPE
 447  * @SD_CONFIG_BASECLK: To set SD_BASECLK in SD_CONFIG_REG1
 448  * @SD_CONFIG_8BIT: To set SD_8BIT in SD_CONFIG_REG2
 449  * @SD_CONFIG_FIXED: To set fixed config registers
 450  */
 451 enum pm_sd_config_type {
 452         SD_CONFIG_EMMC_SEL = 1,
 453         SD_CONFIG_BASECLK = 2,
 454         SD_CONFIG_8BIT = 3,
 455         SD_CONFIG_FIXED = 4,
 456 };
 457
 458 /**
 459  * enum pm_gem_config_type - PM GEM configuration.
 460  * @GEM_CONFIG_SGMII_MODE: To set GEM_SGMII_MODE in GEM_CLK_CTRL register
 461  * @GEM_CONFIG_FIXED: To set fixed config registers
 462  */
 463 enum pm_gem_config_type {
 464         GEM_CONFIG_SGMII_MODE = 1,
 465         GEM_CONFIG_FIXED = 2,
 466 };
 467
 468 /**
 469  * struct zynqmp_pm_query_data - PM query data
 470  * @qid:        query ID
 471  * @arg1:       Argument 1 of query data
 472  * @arg2:       Argument 2 of query data
 473  * @arg3:       Argument 3 of query data
 474  */
 475 struct zynqmp_pm_query_data {
 476         u32 qid;
 477         u32 arg1;
 478         u32 arg2;
 479         u32 arg3;
 480 };
 481
 482 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
 483                         u32 arg2, u32 arg3, u32 *ret_payload);
 484
 485 #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
 486 int zynqmp_pm_get_api_version(u32 *version);
 487 int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
 488 int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
 489 int zynqmp_pm_clock_enable(u32 clock_id);
 490 int zynqmp_pm_clock_disable(u32 clock_id);
 491 int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
 492 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
 493 int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
 494 int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate);
 495 int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate);
 496 int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id);
 497 int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id);
 498 int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode);
 499 int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode);
 500 int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
 501 int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
 502 int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
 503 int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
 504 int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select);
 505 int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
 506                            const enum zynqmp_pm_reset_action assert_flag);
 507 int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status);
 508 unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode);
 509 int zynqmp_pm_bootmode_write(u32 ps_mode);
 510 int zynqmp_pm_init_finalize(void);
 511 int zynqmp_pm_set_suspend_mode(u32 mode);
 512 int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
 513                            const u32 qos, const enum zynqmp_pm_request_ack ack);
 514 int zynqmp_pm_release_node(const u32 node);
 515 int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
 516                               const u32 qos,
 517                               const enum zynqmp_pm_request_ack ack);
 518 int zynqmp_pm_aes_engine(const u64 address, u32 *out);
 519 int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
 520 int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
 521 int zynqmp_pm_fpga_get_status(u32 *value);
 522 int zynqmp_pm_write_ggs(u32 index, u32 value);
 523 int zynqmp_pm_read_ggs(u32 index, u32 *value);
 524 int zynqmp_pm_write_pggs(u32 index, u32 value);
 525 int zynqmp_pm_read_pggs(u32 index, u32 *value);
 526 int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value);
 527 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
 528 int zynqmp_pm_set_boot_health_status(u32 value);
 529 int zynqmp_pm_pinctrl_request(const u32 pin);
 530 int zynqmp_pm_pinctrl_release(const u32 pin);
 531 int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id);
 532 int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id);
 533 int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
 534                                  u32 *value);
 535 int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
 536                                  u32 value);
 537 int zynqmp_pm_load_pdi(const u32 src, const u64 address);
 538 int zynqmp_pm_register_notifier(const u32 node, const u32 event,
 539                                 const u32 wake, const u32 enable);
 540 int zynqmp_pm_feature(const u32 api_id);
 541 int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
 542 int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value);
 543 int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload);
 544 int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset);
 545 int zynqmp_pm_force_pwrdwn(const u32 target,
 546                            const enum zynqmp_pm_request_ack ack);
 547 int zynqmp_pm_request_wake(const u32 node,
 548                            const bool set_addr,
 549                            const u64 address,
 550                            const enum zynqmp_pm_request_ack ack);
 551 int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode);
 552 int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode);
 553 int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode);
 554 int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
 555 int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
 556                              u32 value);
 557 #else
 558 static inline int zynqmp_pm_get_api_version(u32 *version)
 559 {
 560         return -ENODEV;
 561 }
 562
 563 static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
 564 {
 565         return -ENODEV;
 566 }
 567
 568 static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
 569                                        u32 *out)
 570 {
 571         return -ENODEV;
 572 }
 573
 574 static inline int zynqmp_pm_clock_enable(u32 clock_id)
 575 {
 576         return -ENODEV;
 577 }
 578
 579 static inline int zynqmp_pm_clock_disable(u32 clock_id)
 580 {
 581         return -ENODEV;
 582 }
 583
 584 static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
 585 {
 586         return -ENODEV;
 587 }
 588
 589 static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
 590 {
 591         return -ENODEV;
 592 }
 593
 594 static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
 595 {
 596         return -ENODEV;
 597 }
 598
 599 static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)
 600 {
 601         return -ENODEV;
 602 }
 603
 604 static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)
 605 {
 606         return -ENODEV;
 607 }
 608
 609 static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
 610 {
 611         return -ENODEV;
 612 }
 613
 614 static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
 615 {
 616         return -ENODEV;
 617 }
 618
 619 static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
 620 {
 621         return -ENODEV;
 622 }
 623
 624 static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
 625 {
 626         return -ENODEV;
 627 }
 628
 629 static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
 630 {
 631         return -ENODEV;
 632 }
 633
 634 static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
 635 {
 636         return -ENODEV;
 637 }
 638
 639 static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
 640 {
 641         return -ENODEV;
 642 }
 643
 644 static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
 645 {
 646         return -ENODEV;
 647 }
 648
 649 static inline int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select)
 650 {
 651         return -ENODEV;
 652 }
 653
 654 static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
 655                                          const enum zynqmp_pm_reset_action assert_flag)
 656 {
 657         return -ENODEV;
 658 }
 659
 660 static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
 661                                              u32 *status)
 662 {
 663         return -ENODEV;
 664 }
 665
 666 static inline unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode)
 667 {
 668         return -ENODEV;
 669 }
 670
 671 static inline int zynqmp_pm_bootmode_write(u32 ps_mode)
 672 {
 673         return -ENODEV;
 674 }
 675
 676 static inline int zynqmp_pm_init_finalize(void)
 677 {
 678         return -ENODEV;
 679 }
 680
 681 static inline int zynqmp_pm_set_suspend_mode(u32 mode)
 682 {
 683         return -ENODEV;
 684 }
 685
 686 static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
 687                                          const u32 qos,
 688                                          const enum zynqmp_pm_request_ack ack)
 689 {
 690         return -ENODEV;
 691 }
 692
 693 static inline int zynqmp_pm_release_node(const u32 node)
 694 {
 695         return -ENODEV;
 696 }
 697
 698 static inline int zynqmp_pm_set_requirement(const u32 node,
 699                                             const u32 capabilities,
 700                                             const u32 qos,
 701                                             const enum zynqmp_pm_request_ack ack)
 702 {
 703         return -ENODEV;
 704 }
 705
 706 static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
 707 {
 708         return -ENODEV;
 709 }
 710
 711 static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,
 712                                      const u32 flags)
 713 {
 714         return -ENODEV;
 715 }
 716
 717 static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
 718                                       const u32 flags)
 719 {
 720         return -ENODEV;
 721 }
 722
 723 static inline int zynqmp_pm_fpga_get_status(u32 *value)
 724 {
 725         return -ENODEV;
 726 }
 727
 728 static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
 729 {
 730         return -ENODEV;
 731 }
 732
 733 static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
 734 {
 735         return -ENODEV;
 736 }
 737
 738 static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
 739 {
 740         return -ENODEV;
 741 }
 742
 743 static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
 744 {
 745         return -ENODEV;
 746 }
 747
 748 static inline int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value)
 749 {
 750         return -ENODEV;
 751 }
 752
 753 static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
 754 {
 755         return -ENODEV;
 756 }
 757
 758 static inline int zynqmp_pm_set_boot_health_status(u32 value)
 759 {
 760         return -ENODEV;
 761 }
 762
 763 static inline int zynqmp_pm_pinctrl_request(const u32 pin)
 764 {
 765         return -ENODEV;
 766 }
 767
 768 static inline int zynqmp_pm_pinctrl_release(const u32 pin)
 769 {
 770         return -ENODEV;
 771 }
 772
 773 static inline int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id)
 774 {
 775         return -ENODEV;
 776 }
 777
 778 static inline int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
 779 {
 780         return -ENODEV;
 781 }
 782
 783 static inline int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id)
 784 {
 785         return -ENODEV;
 786 }
 787
 788 static inline int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
 789                                                u32 *value)
 790 {
 791         return -ENODEV;
 792 }
 793
 794 static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
 795                                                u32 value)
 796 {
 797         return -ENODEV;
 798 }
 799
 800 static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
 801 {
 802         return -ENODEV;
 803 }
 804
 805 static inline int zynqmp_pm_register_notifier(const u32 node, const u32 event,
 806                                               const u32 wake, const u32 enable)
 807 {
 808         return -ENODEV;
 809 }
 810
 811 static inline int zynqmp_pm_feature(const u32 api_id)
 812 {
 813         return -ENODEV;
 814 }
 815
 816 static inline int zynqmp_pm_set_feature_config(enum pm_feature_config_id id,
 817                                                u32 value)
 818 {
 819         return -ENODEV;
 820 }
 821
 822 static inline int zynqmp_pm_get_feature_config(enum pm_feature_config_id id,
 823                                                u32 *payload)
 824 {
 825         return -ENODEV;
 826 }
 827
 828 static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset)
 829 {
 830         return -ENODEV;
 831 }
 832
 833 static inline int zynqmp_pm_force_pwrdwn(const u32 target,
 834                                          const enum zynqmp_pm_request_ack ack)
 835 {
 836         return -ENODEV;
 837 }
 838
 839 static inline int zynqmp_pm_request_wake(const u32 node,
 840                                          const bool set_addr,
 841                                          const u64 address,
 842                                          const enum zynqmp_pm_request_ack ack)
 843 {
 844         return -ENODEV;
 845 }
 846
 847 static inline int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode)
 848 {
 849         return -ENODEV;
 850 }
 851
 852 static inline int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode)
 853 {
 854         return -ENODEV;
 855 }
 856
 857 static inline int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode)
 858 {
 859         return -ENODEV;
 860 }
 861
 862 static inline int zynqmp_pm_set_sd_config(u32 node,
 863                                           enum pm_sd_config_type config,
 864                                           u32 value)
 865 {
 866         return -ENODEV;
 867 }
 868
 869 static inline int zynqmp_pm_set_gem_config(u32 node,
 870                                            enum pm_gem_config_type config,
 871                                            u32 value)
 872 {
 873         return -ENODEV;
 874 }
 875
 876 #endif
 877
 878 #endif /* __FIRMWARE_ZYNQMP_H__ */