1 #ifndef __INCLUDE_ATMEL_SSC_H
2 #define __INCLUDE_ATMEL_SSC_H
4 #include <linux/platform_device.h>
5 #include <linux/list.h>
8 struct atmel_ssc_platform_data {
14 struct list_head list;
17 struct platform_device *pdev;
18 struct atmel_ssc_platform_data *pdata;
25 struct ssc_device * __must_check ssc_request(unsigned int ssc_num);
26 void ssc_free(struct ssc_device *ssc);
28 /* SSC register offsets */
30 /* SSC Control Register */
31 #define SSC_CR 0x00000000
32 #define SSC_CR_RXDIS_SIZE 1
33 #define SSC_CR_RXDIS_OFFSET 1
34 #define SSC_CR_RXEN_SIZE 1
35 #define SSC_CR_RXEN_OFFSET 0
36 #define SSC_CR_SWRST_SIZE 1
37 #define SSC_CR_SWRST_OFFSET 15
38 #define SSC_CR_TXDIS_SIZE 1
39 #define SSC_CR_TXDIS_OFFSET 9
40 #define SSC_CR_TXEN_SIZE 1
41 #define SSC_CR_TXEN_OFFSET 8
43 /* SSC Clock Mode Register */
44 #define SSC_CMR 0x00000004
45 #define SSC_CMR_DIV_SIZE 12
46 #define SSC_CMR_DIV_OFFSET 0
48 /* SSC Receive Clock Mode Register */
49 #define SSC_RCMR 0x00000010
50 #define SSC_RCMR_CKG_SIZE 2
51 #define SSC_RCMR_CKG_OFFSET 6
52 #define SSC_RCMR_CKI_SIZE 1
53 #define SSC_RCMR_CKI_OFFSET 5
54 #define SSC_RCMR_CKO_SIZE 3
55 #define SSC_RCMR_CKO_OFFSET 2
56 #define SSC_RCMR_CKS_SIZE 2
57 #define SSC_RCMR_CKS_OFFSET 0
58 #define SSC_RCMR_PERIOD_SIZE 8
59 #define SSC_RCMR_PERIOD_OFFSET 24
60 #define SSC_RCMR_START_SIZE 4
61 #define SSC_RCMR_START_OFFSET 8
62 #define SSC_RCMR_STOP_SIZE 1
63 #define SSC_RCMR_STOP_OFFSET 12
64 #define SSC_RCMR_STTDLY_SIZE 8
65 #define SSC_RCMR_STTDLY_OFFSET 16
67 /* SSC Receive Frame Mode Register */
68 #define SSC_RFMR 0x00000014
69 #define SSC_RFMR_DATLEN_SIZE 5
70 #define SSC_RFMR_DATLEN_OFFSET 0
71 #define SSC_RFMR_DATNB_SIZE 4
72 #define SSC_RFMR_DATNB_OFFSET 8
73 #define SSC_RFMR_FSEDGE_SIZE 1
74 #define SSC_RFMR_FSEDGE_OFFSET 24
75 #define SSC_RFMR_FSLEN_SIZE 4
76 #define SSC_RFMR_FSLEN_OFFSET 16
77 #define SSC_RFMR_FSOS_SIZE 4
78 #define SSC_RFMR_FSOS_OFFSET 20
79 #define SSC_RFMR_LOOP_SIZE 1
80 #define SSC_RFMR_LOOP_OFFSET 5
81 #define SSC_RFMR_MSBF_SIZE 1
82 #define SSC_RFMR_MSBF_OFFSET 7
84 /* SSC Transmit Clock Mode Register */
85 #define SSC_TCMR 0x00000018
86 #define SSC_TCMR_CKG_SIZE 2
87 #define SSC_TCMR_CKG_OFFSET 6
88 #define SSC_TCMR_CKI_SIZE 1
89 #define SSC_TCMR_CKI_OFFSET 5
90 #define SSC_TCMR_CKO_SIZE 3
91 #define SSC_TCMR_CKO_OFFSET 2
92 #define SSC_TCMR_CKS_SIZE 2
93 #define SSC_TCMR_CKS_OFFSET 0
94 #define SSC_TCMR_PERIOD_SIZE 8
95 #define SSC_TCMR_PERIOD_OFFSET 24
96 #define SSC_TCMR_START_SIZE 4
97 #define SSC_TCMR_START_OFFSET 8
98 #define SSC_TCMR_STTDLY_SIZE 8
99 #define SSC_TCMR_STTDLY_OFFSET 16
101 /* SSC Transmit Frame Mode Register */
102 #define SSC_TFMR 0x0000001c
103 #define SSC_TFMR_DATDEF_SIZE 1
104 #define SSC_TFMR_DATDEF_OFFSET 5
105 #define SSC_TFMR_DATLEN_SIZE 5
106 #define SSC_TFMR_DATLEN_OFFSET 0
107 #define SSC_TFMR_DATNB_SIZE 4
108 #define SSC_TFMR_DATNB_OFFSET 8
109 #define SSC_TFMR_FSDEN_SIZE 1
110 #define SSC_TFMR_FSDEN_OFFSET 23
111 #define SSC_TFMR_FSEDGE_SIZE 1
112 #define SSC_TFMR_FSEDGE_OFFSET 24
113 #define SSC_TFMR_FSLEN_SIZE 4
114 #define SSC_TFMR_FSLEN_OFFSET 16
115 #define SSC_TFMR_FSOS_SIZE 3
116 #define SSC_TFMR_FSOS_OFFSET 20
117 #define SSC_TFMR_MSBF_SIZE 1
118 #define SSC_TFMR_MSBF_OFFSET 7
120 /* SSC Receive Hold Register */
121 #define SSC_RHR 0x00000020
122 #define SSC_RHR_RDAT_SIZE 32
123 #define SSC_RHR_RDAT_OFFSET 0
125 /* SSC Transmit Hold Register */
126 #define SSC_THR 0x00000024
127 #define SSC_THR_TDAT_SIZE 32
128 #define SSC_THR_TDAT_OFFSET 0
130 /* SSC Receive Sync. Holding Register */
131 #define SSC_RSHR 0x00000030
132 #define SSC_RSHR_RSDAT_SIZE 16
133 #define SSC_RSHR_RSDAT_OFFSET 0
135 /* SSC Transmit Sync. Holding Register */
136 #define SSC_TSHR 0x00000034
137 #define SSC_TSHR_TSDAT_SIZE 16
138 #define SSC_TSHR_RSDAT_OFFSET 0
140 /* SSC Receive Compare 0 Register */
141 #define SSC_RC0R 0x00000038
142 #define SSC_RC0R_CP0_SIZE 16
143 #define SSC_RC0R_CP0_OFFSET 0
145 /* SSC Receive Compare 1 Register */
146 #define SSC_RC1R 0x0000003c
147 #define SSC_RC1R_CP1_SIZE 16
148 #define SSC_RC1R_CP1_OFFSET 0
150 /* SSC Status Register */
151 #define SSC_SR 0x00000040
152 #define SSC_SR_CP0_SIZE 1
153 #define SSC_SR_CP0_OFFSET 8
154 #define SSC_SR_CP1_SIZE 1
155 #define SSC_SR_CP1_OFFSET 9
156 #define SSC_SR_ENDRX_SIZE 1
157 #define SSC_SR_ENDRX_OFFSET 6
158 #define SSC_SR_ENDTX_SIZE 1
159 #define SSC_SR_ENDTX_OFFSET 2
160 #define SSC_SR_OVRUN_SIZE 1
161 #define SSC_SR_OVRUN_OFFSET 5
162 #define SSC_SR_RXBUFF_SIZE 1
163 #define SSC_SR_RXBUFF_OFFSET 7
164 #define SSC_SR_RXEN_SIZE 1
165 #define SSC_SR_RXEN_OFFSET 17
166 #define SSC_SR_RXRDY_SIZE 1
167 #define SSC_SR_RXRDY_OFFSET 4
168 #define SSC_SR_RXSYN_SIZE 1
169 #define SSC_SR_RXSYN_OFFSET 11
170 #define SSC_SR_TXBUFE_SIZE 1
171 #define SSC_SR_TXBUFE_OFFSET 3
172 #define SSC_SR_TXEMPTY_SIZE 1
173 #define SSC_SR_TXEMPTY_OFFSET 1
174 #define SSC_SR_TXEN_SIZE 1
175 #define SSC_SR_TXEN_OFFSET 16
176 #define SSC_SR_TXRDY_SIZE 1
177 #define SSC_SR_TXRDY_OFFSET 0
178 #define SSC_SR_TXSYN_SIZE 1
179 #define SSC_SR_TXSYN_OFFSET 10
181 /* SSC Interrupt Enable Register */
182 #define SSC_IER 0x00000044
183 #define SSC_IER_CP0_SIZE 1
184 #define SSC_IER_CP0_OFFSET 8
185 #define SSC_IER_CP1_SIZE 1
186 #define SSC_IER_CP1_OFFSET 9
187 #define SSC_IER_ENDRX_SIZE 1
188 #define SSC_IER_ENDRX_OFFSET 6
189 #define SSC_IER_ENDTX_SIZE 1
190 #define SSC_IER_ENDTX_OFFSET 2
191 #define SSC_IER_OVRUN_SIZE 1
192 #define SSC_IER_OVRUN_OFFSET 5
193 #define SSC_IER_RXBUFF_SIZE 1
194 #define SSC_IER_RXBUFF_OFFSET 7
195 #define SSC_IER_RXRDY_SIZE 1
196 #define SSC_IER_RXRDY_OFFSET 4
197 #define SSC_IER_RXSYN_SIZE 1
198 #define SSC_IER_RXSYN_OFFSET 11
199 #define SSC_IER_TXBUFE_SIZE 1
200 #define SSC_IER_TXBUFE_OFFSET 3
201 #define SSC_IER_TXEMPTY_SIZE 1
202 #define SSC_IER_TXEMPTY_OFFSET 1
203 #define SSC_IER_TXRDY_SIZE 1
204 #define SSC_IER_TXRDY_OFFSET 0
205 #define SSC_IER_TXSYN_SIZE 1
206 #define SSC_IER_TXSYN_OFFSET 10
208 /* SSC Interrupt Disable Register */
209 #define SSC_IDR 0x00000048
210 #define SSC_IDR_CP0_SIZE 1
211 #define SSC_IDR_CP0_OFFSET 8
212 #define SSC_IDR_CP1_SIZE 1
213 #define SSC_IDR_CP1_OFFSET 9
214 #define SSC_IDR_ENDRX_SIZE 1
215 #define SSC_IDR_ENDRX_OFFSET 6
216 #define SSC_IDR_ENDTX_SIZE 1
217 #define SSC_IDR_ENDTX_OFFSET 2
218 #define SSC_IDR_OVRUN_SIZE 1
219 #define SSC_IDR_OVRUN_OFFSET 5
220 #define SSC_IDR_RXBUFF_SIZE 1
221 #define SSC_IDR_RXBUFF_OFFSET 7
222 #define SSC_IDR_RXRDY_SIZE 1
223 #define SSC_IDR_RXRDY_OFFSET 4
224 #define SSC_IDR_RXSYN_SIZE 1
225 #define SSC_IDR_RXSYN_OFFSET 11
226 #define SSC_IDR_TXBUFE_SIZE 1
227 #define SSC_IDR_TXBUFE_OFFSET 3
228 #define SSC_IDR_TXEMPTY_SIZE 1
229 #define SSC_IDR_TXEMPTY_OFFSET 1
230 #define SSC_IDR_TXRDY_SIZE 1
231 #define SSC_IDR_TXRDY_OFFSET 0
232 #define SSC_IDR_TXSYN_SIZE 1
233 #define SSC_IDR_TXSYN_OFFSET 10
235 /* SSC Interrupt Mask Register */
236 #define SSC_IMR 0x0000004c
237 #define SSC_IMR_CP0_SIZE 1
238 #define SSC_IMR_CP0_OFFSET 8
239 #define SSC_IMR_CP1_SIZE 1
240 #define SSC_IMR_CP1_OFFSET 9
241 #define SSC_IMR_ENDRX_SIZE 1
242 #define SSC_IMR_ENDRX_OFFSET 6
243 #define SSC_IMR_ENDTX_SIZE 1
244 #define SSC_IMR_ENDTX_OFFSET 2
245 #define SSC_IMR_OVRUN_SIZE 1
246 #define SSC_IMR_OVRUN_OFFSET 5
247 #define SSC_IMR_RXBUFF_SIZE 1
248 #define SSC_IMR_RXBUFF_OFFSET 7
249 #define SSC_IMR_RXRDY_SIZE 1
250 #define SSC_IMR_RXRDY_OFFSET 4
251 #define SSC_IMR_RXSYN_SIZE 1
252 #define SSC_IMR_RXSYN_OFFSET 11
253 #define SSC_IMR_TXBUFE_SIZE 1
254 #define SSC_IMR_TXBUFE_OFFSET 3
255 #define SSC_IMR_TXEMPTY_SIZE 1
256 #define SSC_IMR_TXEMPTY_OFFSET 1
257 #define SSC_IMR_TXRDY_SIZE 1
258 #define SSC_IMR_TXRDY_OFFSET 0
259 #define SSC_IMR_TXSYN_SIZE 1
260 #define SSC_IMR_TXSYN_OFFSET 10
262 /* SSC PDC Receive Pointer Register */
263 #define SSC_PDC_RPR 0x00000100
265 /* SSC PDC Receive Counter Register */
266 #define SSC_PDC_RCR 0x00000104
268 /* SSC PDC Transmit Pointer Register */
269 #define SSC_PDC_TPR 0x00000108
271 /* SSC PDC Receive Next Pointer Register */
272 #define SSC_PDC_RNPR 0x00000110
274 /* SSC PDC Receive Next Counter Register */
275 #define SSC_PDC_RNCR 0x00000114
277 /* SSC PDC Transmit Counter Register */
278 #define SSC_PDC_TCR 0x0000010c
280 /* SSC PDC Transmit Next Pointer Register */
281 #define SSC_PDC_TNPR 0x00000118
283 /* SSC PDC Transmit Next Counter Register */
284 #define SSC_PDC_TNCR 0x0000011c
286 /* SSC PDC Transfer Control Register */
287 #define SSC_PDC_PTCR 0x00000120
288 #define SSC_PDC_PTCR_RXTDIS_SIZE 1
289 #define SSC_PDC_PTCR_RXTDIS_OFFSET 1
290 #define SSC_PDC_PTCR_RXTEN_SIZE 1
291 #define SSC_PDC_PTCR_RXTEN_OFFSET 0
292 #define SSC_PDC_PTCR_TXTDIS_SIZE 1
293 #define SSC_PDC_PTCR_TXTDIS_OFFSET 9
294 #define SSC_PDC_PTCR_TXTEN_SIZE 1
295 #define SSC_PDC_PTCR_TXTEN_OFFSET 8
297 /* SSC PDC Transfer Status Register */
298 #define SSC_PDC_PTSR 0x00000124
299 #define SSC_PDC_PTSR_RXTEN_SIZE 1
300 #define SSC_PDC_PTSR_RXTEN_OFFSET 0
301 #define SSC_PDC_PTSR_TXTEN_SIZE 1
302 #define SSC_PDC_PTSR_TXTEN_OFFSET 8
304 /* Bit manipulation macros */
305 #define SSC_BIT(name) \
306 (1 << SSC_##name##_OFFSET)
307 #define SSC_BF(name, value) \
308 (((value) & ((1 << SSC_##name##_SIZE) - 1)) \
309 << SSC_##name##_OFFSET)
310 #define SSC_BFEXT(name, value) \
311 (((value) >> SSC_##name##_OFFSET) \
312 & ((1 << SSC_##name##_SIZE) - 1))
313 #define SSC_BFINS(name, value, old) \
314 (((old) & ~(((1 << SSC_##name##_SIZE) - 1) \
315 << SSC_##name##_OFFSET)) | SSC_BF(name, value))
317 /* Register access macros */
318 #define ssc_readl(base, reg) __raw_readl(base + SSC_##reg)
319 #define ssc_writel(base, reg, value) __raw_writel((value), base + SSC_##reg)
321 #endif /* __INCLUDE_ATMEL_SSC_H */