2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #ifndef __ASM_ARM_KVM_VGIC_H
20 #define __ASM_ARM_KVM_VGIC_H
22 #include <linux/kernel.h>
23 #include <linux/kvm.h>
24 #include <linux/irqreturn.h>
25 #include <linux/spinlock.h>
26 #include <linux/types.h>
27 #include <linux/irqchip/arm-gic.h>
29 #define VGIC_NR_IRQS 256
30 #define VGIC_NR_SGIS 16
31 #define VGIC_NR_PPIS 16
32 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
33 #define VGIC_NR_SHARED_IRQS (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
34 #define VGIC_MAX_CPUS KVM_MAX_VCPUS
35 #define VGIC_MAX_LRS (1 << 6)
37 /* Sanity checks... */
38 #if (VGIC_MAX_CPUS > 8)
39 #error Invalid number of CPU interfaces
42 #if (VGIC_NR_IRQS & 31)
43 #error "VGIC_NR_IRQS must be a multiple of 32"
46 #if (VGIC_NR_IRQS > 1024)
47 #error "VGIC_NR_IRQS must be <= 1024"
51 * The GIC distributor registers describing interrupts have two parts:
52 * - 32 per-CPU interrupts (SGI + PPI)
53 * - a bunch of shared interrupts (SPI)
57 u32 reg[VGIC_NR_PRIVATE_IRQS / 32];
58 DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS);
59 } percpu[VGIC_MAX_CPUS];
61 u32 reg[VGIC_NR_SHARED_IRQS / 32];
62 DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS);
67 u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4];
68 u32 shared[VGIC_NR_SHARED_IRQS / 4];
73 #define LR_STATE_PENDING (1 << 0)
74 #define LR_STATE_ACTIVE (1 << 1)
75 #define LR_STATE_MASK (3 << 0)
76 #define LR_EOI_INT (1 << 2)
85 struct vgic_lr (*get_lr)(const struct kvm_vcpu *, int);
86 void (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
87 void (*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr);
88 u64 (*get_elrsr)(const struct kvm_vcpu *vcpu);
89 u64 (*get_eisr)(const struct kvm_vcpu *vcpu);
90 u32 (*get_interrupt_status)(const struct kvm_vcpu *vcpu);
91 void (*enable_underflow)(struct kvm_vcpu *vcpu);
92 void (*disable_underflow)(struct kvm_vcpu *vcpu);
96 #ifdef CONFIG_KVM_ARM_VGIC
100 /* Virtual control interface mapping */
101 void __iomem *vctrl_base;
103 /* Distributor and vcpu interface mapping in the guest */
104 phys_addr_t vgic_dist_base;
105 phys_addr_t vgic_cpu_base;
107 /* Distributor enabled */
110 /* Interrupt enabled (one bit per IRQ) */
111 struct vgic_bitmap irq_enabled;
113 /* Interrupt 'pin' level */
114 struct vgic_bitmap irq_state;
116 /* Level-triggered interrupt in progress */
117 struct vgic_bitmap irq_active;
119 /* Interrupt priority. Not used yet. */
120 struct vgic_bytemap irq_priority;
122 /* Level/edge triggered */
123 struct vgic_bitmap irq_cfg;
125 /* Source CPU per SGI and target CPU */
126 u8 irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS];
128 /* Target CPU for each IRQ */
129 u8 irq_spi_cpu[VGIC_NR_SHARED_IRQS];
130 struct vgic_bitmap irq_spi_target[VGIC_MAX_CPUS];
132 /* Bitmap indicating which CPU has something pending */
133 unsigned long irq_pending_on_cpu;
137 struct vgic_v2_cpu_if {
140 u32 vgic_misr; /* Saved only */
141 u32 vgic_eisr[2]; /* Saved only */
142 u32 vgic_elrsr[2]; /* Saved only */
144 u32 vgic_lr[VGIC_MAX_LRS];
148 #ifdef CONFIG_KVM_ARM_VGIC
149 /* per IRQ to LR mapping */
150 u8 vgic_irq_lr_map[VGIC_NR_IRQS];
152 /* Pending interrupts on this VCPU */
153 DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
154 DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS);
156 /* Bitmap of used/free list registers */
157 DECLARE_BITMAP( lr_used, VGIC_MAX_LRS);
159 /* Number of list registers on this CPU */
162 /* CPU vif control registers for world switch */
164 struct vgic_v2_cpu_if vgic_v2;
169 #define LR_EMPTY 0xff
171 #define INT_STATUS_EOI (1 << 0)
172 #define INT_STATUS_UNDERFLOW (1 << 1)
177 struct kvm_exit_mmio;
179 #ifdef CONFIG_KVM_ARM_VGIC
180 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
181 int kvm_vgic_hyp_init(void);
182 int kvm_vgic_init(struct kvm *kvm);
183 int kvm_vgic_create(struct kvm *kvm);
184 int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
185 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
186 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
187 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
189 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
190 bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
191 struct kvm_exit_mmio *mmio);
193 #define irqchip_in_kernel(k) (!!((k)->arch.vgic.vctrl_base))
194 #define vgic_initialized(k) ((k)->arch.vgic.ready)
197 static inline int kvm_vgic_hyp_init(void)
202 static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
207 static inline int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
212 static inline int kvm_vgic_init(struct kvm *kvm)
217 static inline int kvm_vgic_create(struct kvm *kvm)
222 static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
227 static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
228 static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}
230 static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
231 unsigned int irq_num, bool level)
236 static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
241 static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
242 struct kvm_exit_mmio *mmio)
247 static inline int irqchip_in_kernel(struct kvm *kvm)
252 static inline bool vgic_initialized(struct kvm *kvm)