2 * Copyright (C) 2015, 2016 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 #ifndef __KVM_ARM_VGIC_H
17 #define __KVM_ARM_VGIC_H
19 #include <linux/kernel.h>
20 #include <linux/kvm.h>
21 #include <linux/irqreturn.h>
22 #include <linux/spinlock.h>
23 #include <linux/static_key.h>
24 #include <linux/types.h>
25 #include <kvm/iodev.h>
26 #include <linux/list.h>
27 #include <linux/jump_label.h>
29 #include <linux/irqchip/arm-gic-v4.h>
31 #define VGIC_V3_MAX_CPUS 255
32 #define VGIC_V2_MAX_CPUS 8
33 #define VGIC_NR_IRQS_LEGACY 256
34 #define VGIC_NR_SGIS 16
35 #define VGIC_NR_PPIS 16
36 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
37 #define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1)
38 #define VGIC_MAX_SPI 1019
39 #define VGIC_MAX_RESERVED 1023
40 #define VGIC_MIN_LPI 8192
41 #define KVM_IRQCHIP_NUM_PINS (1020 - 32)
43 #define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS)
44 #define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \
45 (irq) <= VGIC_MAX_SPI)
48 VGIC_V2, /* Good ol' GICv2 */
49 VGIC_V3, /* New fancy GICv3 */
52 /* same for all guests, as depending only on the _host's_ GIC model */
54 /* type of the host GIC */
57 /* Physical address of vgic virtual cpu interface */
58 phys_addr_t vcpu_base;
60 /* GICV mapping, kernel VA */
61 void __iomem *vcpu_base_va;
62 /* GICV mapping, HYP VA */
63 void __iomem *vcpu_hyp_va;
65 /* virtual control interface mapping, kernel VA */
66 void __iomem *vctrl_base;
67 /* virtual control interface mapping, HYP VA */
68 void __iomem *vctrl_hyp;
70 /* Number of implemented list registers */
73 /* Maintenance IRQ number */
74 unsigned int maint_irq;
76 /* maximum number of VCPUs allowed (GICv2 limits us to 8) */
79 /* Only needed for the legacy KVM_CREATE_IRQCHIP */
80 bool can_emulate_gicv2;
82 /* Hardware has GICv4? */
85 /* GIC system register CPU interface */
86 struct static_key_false gicv3_cpuif;
91 extern struct vgic_global kvm_vgic_global_state;
93 #define VGIC_V2_MAX_LRS (1 << 6)
94 #define VGIC_V3_MAX_LRS 16
95 #define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
97 enum vgic_irq_config {
103 spinlock_t irq_lock; /* Protects the content of the struct */
104 struct list_head lpi_list; /* Used to link all LPIs together */
105 struct list_head ap_list;
107 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU
108 * SPIs and LPIs: The VCPU whose ap_list
112 struct kvm_vcpu *target_vcpu; /* The VCPU that this interrupt should
113 * be sent to, as a result of the
114 * targets reg (v2) or the
118 u32 intid; /* Guest visible INTID */
119 bool line_level; /* Level only */
120 bool pending_latch; /* The pending latch state used to calculate
121 * the pending state for both level
122 * and edge triggered IRQs. */
123 bool active; /* not used for LPIs */
125 bool hw; /* Tied to HW IRQ */
126 struct kref refcount; /* Used for LPIs */
127 u32 hwintid; /* HW INTID number */
128 unsigned int host_irq; /* linux irq corresponding to hwintid */
130 u8 targets; /* GICv2 target VCPUs mask */
131 u32 mpidr; /* GICv3 target VCPU */
133 u8 source; /* GICv2 SGIs only */
135 enum vgic_irq_config config; /* Level or edge */
138 * Callback function pointer to in-kernel devices that can tell us the
139 * state of the input level of mapped level-triggered IRQ faster than
140 * peaking into the physical GIC.
142 * Always called in non-preemptible section and the functions can use
143 * kvm_arm_get_running_vcpu() to get the vcpu pointer for private
146 bool (*get_input_level)(int vintid);
148 void *owner; /* Opaque pointer to reserve an interrupt
149 for in-kernel devices. */
152 struct vgic_register_region;
162 struct vgic_io_device {
165 struct kvm_vcpu *redist_vcpu;
166 struct vgic_its *its;
168 const struct vgic_register_region *regions;
169 enum iodev_type iodev_type;
171 struct kvm_io_device dev;
175 /* The base address of the ITS control register frame */
179 struct vgic_io_device iodev;
180 struct kvm_device *dev;
182 /* These registers correspond to GITS_BASER{0,1} */
183 u64 baser_device_table;
184 u64 baser_coll_table;
186 /* Protects the command queue */
187 struct mutex cmd_lock;
192 /* migration ABI revision in use */
195 /* Protects the device and collection lists */
196 struct mutex its_lock;
197 struct list_head device_list;
198 struct list_head collection_list;
201 struct vgic_state_iter;
208 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
211 /* Do injected MSIs require an additional device ID? */
212 bool msis_require_devid;
216 /* base addresses in guest physical address space: */
217 gpa_t vgic_dist_base; /* distributor */
219 /* either a GICv2 CPU interface */
221 /* or a number of GICv3 redistributor regions */
223 gpa_t vgic_redist_base;
224 gpa_t vgic_redist_free_offset;
228 /* distributor enabled */
231 struct vgic_irq *spis;
233 struct vgic_io_device dist_iodev;
238 * Contains the attributes and gpa of the LPI configuration table.
239 * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
240 * one address across all redistributors.
241 * GICv3 spec: 6.1.2 "LPI Configuration tables"
245 /* Protects the lpi_list and the count value below. */
246 spinlock_t lpi_list_lock;
247 struct list_head lpi_list_head;
250 /* used by vgic-debug */
251 struct vgic_state_iter *iter;
254 * GICv4 ITS per-VM data, containing the IRQ domain, the VPE
255 * array, the property table pointer as well as allocation
256 * data. This essentially ties the Linux IRQ core and ITS
257 * together, and avoids leaking KVM's data structures anywhere
260 struct its_vm its_vm;
263 struct vgic_v2_cpu_if {
267 u32 vgic_lr[VGIC_V2_MAX_LRS];
270 struct vgic_v3_cpu_if {
273 u32 vgic_sre; /* Restored only, change ignored */
276 u64 vgic_lr[VGIC_V3_MAX_LRS];
279 * GICv4 ITS per-VPE data, containing the doorbell IRQ, the
280 * pending table pointer, the its_vm pointer and a few other
281 * HW specific things. As for the its_vm structure, this is
282 * linking the Linux IRQ subsystem and the ITS together.
284 struct its_vpe its_vpe;
288 /* CPU vif control registers for world switch */
290 struct vgic_v2_cpu_if vgic_v2;
291 struct vgic_v3_cpu_if vgic_v3;
294 unsigned int used_lrs;
295 struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
297 spinlock_t ap_list_lock; /* Protects the ap_list */
300 * List of IRQs that this VCPU should consider because they are either
301 * Active or Pending (hence the name; AP list), or because they recently
302 * were one of the two and need to be migrated off this list to another
305 struct list_head ap_list_head;
308 * Members below are used with GICv3 emulation only and represent
309 * parts of the redistributor.
311 struct vgic_io_device rd_iodev;
312 struct vgic_io_device sgi_iodev;
314 /* Contains the attributes and gpa of the LPI pending tables. */
319 /* Cache guest priority bits */
322 /* Cache guest interrupt ID bits */
326 extern struct static_key_false vgic_v2_cpuif_trap;
327 extern struct static_key_false vgic_v3_cpuif_trap;
329 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
330 void kvm_vgic_early_init(struct kvm *kvm);
331 int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
332 int kvm_vgic_create(struct kvm *kvm, u32 type);
333 void kvm_vgic_destroy(struct kvm *kvm);
334 void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
335 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
336 int kvm_vgic_map_resources(struct kvm *kvm);
337 int kvm_vgic_hyp_init(void);
338 void kvm_vgic_init_cpu_hardware(void);
340 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
341 bool level, void *owner);
342 int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq,
343 u32 vintid, bool (*get_input_level)(int vindid));
344 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid);
345 bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid);
347 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
349 void kvm_vgic_load(struct kvm_vcpu *vcpu);
350 void kvm_vgic_put(struct kvm_vcpu *vcpu);
352 #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
353 #define vgic_initialized(k) ((k)->arch.vgic.initialized)
354 #define vgic_ready(k) ((k)->arch.vgic.ready)
355 #define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \
356 ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
358 bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
359 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
360 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
361 void kvm_vgic_reset_mapped_irq(struct kvm_vcpu *vcpu, u32 vintid);
363 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
366 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
368 * The host's GIC naturally limits the maximum amount of VCPUs a guest
371 static inline int kvm_vgic_get_max_vcpus(void)
373 return kvm_vgic_global_state.max_gic_vcpus;
376 int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi);
379 * kvm_vgic_setup_default_irq_routing:
380 * Setup a default flat gsi routing table mapping all SPIs
382 int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);
384 int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner);
386 struct kvm_kernel_irq_routing_entry;
388 int kvm_vgic_v4_set_forwarding(struct kvm *kvm, int irq,
389 struct kvm_kernel_irq_routing_entry *irq_entry);
391 int kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int irq,
392 struct kvm_kernel_irq_routing_entry *irq_entry);
394 void kvm_vgic_v4_enable_doorbell(struct kvm_vcpu *vcpu);
395 void kvm_vgic_v4_disable_doorbell(struct kvm_vcpu *vcpu);
397 #endif /* __KVM_ARM_VGIC_H */