include/dt-bindings/clock/dra7.h

   1 /*
   2  * Copyright 2017 Texas Instruments, Inc.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13 #ifndef __DT_BINDINGS_CLK_DRA7_H
  14 #define __DT_BINDINGS_CLK_DRA7_H
  15
  16 #define DRA7_CLKCTRL_OFFSET     0x20
  17 #define DRA7_CLKCTRL_INDEX(offset)      ((offset) - DRA7_CLKCTRL_OFFSET)
  18
  19 /* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
  20
  21 /* mpu clocks */
  22 #define DRA7_MPU_CLKCTRL        DRA7_CLKCTRL_INDEX(0x20)
  23
  24 /* ipu clocks */
  25 #define _DRA7_IPU_CLKCTRL_OFFSET        0x40
  26 #define _DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - _DRA7_IPU_CLKCTRL_OFFSET)
  27 #define DRA7_MCASP1_CLKCTRL     _DRA7_IPU_CLKCTRL_INDEX(0x50)
  28 #define DRA7_TIMER5_CLKCTRL     _DRA7_IPU_CLKCTRL_INDEX(0x58)
  29 #define DRA7_TIMER6_CLKCTRL     _DRA7_IPU_CLKCTRL_INDEX(0x60)
  30 #define DRA7_TIMER7_CLKCTRL     _DRA7_IPU_CLKCTRL_INDEX(0x68)
  31 #define DRA7_TIMER8_CLKCTRL     _DRA7_IPU_CLKCTRL_INDEX(0x70)
  32 #define DRA7_I2C5_CLKCTRL       _DRA7_IPU_CLKCTRL_INDEX(0x78)
  33 #define DRA7_UART6_CLKCTRL      _DRA7_IPU_CLKCTRL_INDEX(0x80)
  34
  35 /* rtc clocks */
  36 #define DRA7_RTC_CLKCTRL_OFFSET 0x40
  37 #define DRA7_RTC_CLKCTRL_INDEX(offset)  ((offset) - DRA7_RTC_CLKCTRL_OFFSET)
  38 #define DRA7_RTCSS_CLKCTRL      DRA7_RTC_CLKCTRL_INDEX(0x44)
  39
  40 /* coreaon clocks */
  41 #define DRA7_SMARTREFLEX_MPU_CLKCTRL    DRA7_CLKCTRL_INDEX(0x28)
  42 #define DRA7_SMARTREFLEX_CORE_CLKCTRL   DRA7_CLKCTRL_INDEX(0x38)
  43
  44 /* l3main1 clocks */
  45 #define DRA7_L3_MAIN_1_CLKCTRL  DRA7_CLKCTRL_INDEX(0x20)
  46 #define DRA7_GPMC_CLKCTRL       DRA7_CLKCTRL_INDEX(0x28)
  47 #define DRA7_TPCC_CLKCTRL       DRA7_CLKCTRL_INDEX(0x70)
  48 #define DRA7_TPTC0_CLKCTRL      DRA7_CLKCTRL_INDEX(0x78)
  49 #define DRA7_TPTC1_CLKCTRL      DRA7_CLKCTRL_INDEX(0x80)
  50 #define DRA7_VCP1_CLKCTRL       DRA7_CLKCTRL_INDEX(0x88)
  51 #define DRA7_VCP2_CLKCTRL       DRA7_CLKCTRL_INDEX(0x90)
  52
  53 /* dma clocks */
  54 #define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
  55
  56 /* emif clocks */
  57 #define DRA7_DMM_CLKCTRL        DRA7_CLKCTRL_INDEX(0x20)
  58
  59 /* atl clocks */
  60 #define DRA7_ATL_CLKCTRL_OFFSET 0x0
  61 #define DRA7_ATL_CLKCTRL_INDEX(offset)  ((offset) - DRA7_ATL_CLKCTRL_OFFSET)
  62 #define DRA7_ATL_CLKCTRL        DRA7_ATL_CLKCTRL_INDEX(0x0)
  63
  64 /* l4cfg clocks */
  65 #define DRA7_L4_CFG_CLKCTRL     DRA7_CLKCTRL_INDEX(0x20)
  66 #define DRA7_SPINLOCK_CLKCTRL   DRA7_CLKCTRL_INDEX(0x28)
  67 #define DRA7_MAILBOX1_CLKCTRL   DRA7_CLKCTRL_INDEX(0x30)
  68 #define DRA7_MAILBOX2_CLKCTRL   DRA7_CLKCTRL_INDEX(0x48)
  69 #define DRA7_MAILBOX3_CLKCTRL   DRA7_CLKCTRL_INDEX(0x50)
  70 #define DRA7_MAILBOX4_CLKCTRL   DRA7_CLKCTRL_INDEX(0x58)
  71 #define DRA7_MAILBOX5_CLKCTRL   DRA7_CLKCTRL_INDEX(0x60)
  72 #define DRA7_MAILBOX6_CLKCTRL   DRA7_CLKCTRL_INDEX(0x68)
  73 #define DRA7_MAILBOX7_CLKCTRL   DRA7_CLKCTRL_INDEX(0x70)
  74 #define DRA7_MAILBOX8_CLKCTRL   DRA7_CLKCTRL_INDEX(0x78)
  75 #define DRA7_MAILBOX9_CLKCTRL   DRA7_CLKCTRL_INDEX(0x80)
  76 #define DRA7_MAILBOX10_CLKCTRL  DRA7_CLKCTRL_INDEX(0x88)
  77 #define DRA7_MAILBOX11_CLKCTRL  DRA7_CLKCTRL_INDEX(0x90)
  78 #define DRA7_MAILBOX12_CLKCTRL  DRA7_CLKCTRL_INDEX(0x98)
  79 #define DRA7_MAILBOX13_CLKCTRL  DRA7_CLKCTRL_INDEX(0xa0)
  80
  81 /* l3instr clocks */
  82 #define DRA7_L3_MAIN_2_CLKCTRL  DRA7_CLKCTRL_INDEX(0x20)
  83 #define DRA7_L3_INSTR_CLKCTRL   DRA7_CLKCTRL_INDEX(0x28)
  84
  85 /* dss clocks */
  86 #define DRA7_DSS_CORE_CLKCTRL   DRA7_CLKCTRL_INDEX(0x20)
  87 #define DRA7_BB2D_CLKCTRL       DRA7_CLKCTRL_INDEX(0x30)
  88
  89 /* l3init clocks */
  90 #define DRA7_MMC1_CLKCTRL       DRA7_CLKCTRL_INDEX(0x28)
  91 #define DRA7_MMC2_CLKCTRL       DRA7_CLKCTRL_INDEX(0x30)
  92 #define DRA7_USB_OTG_SS2_CLKCTRL        DRA7_CLKCTRL_INDEX(0x40)
  93 #define DRA7_USB_OTG_SS3_CLKCTRL        DRA7_CLKCTRL_INDEX(0x48)
  94 #define DRA7_USB_OTG_SS4_CLKCTRL        DRA7_CLKCTRL_INDEX(0x50)
  95 #define DRA7_SATA_CLKCTRL       DRA7_CLKCTRL_INDEX(0x88)
  96 #define DRA7_PCIE1_CLKCTRL      DRA7_CLKCTRL_INDEX(0xb0)
  97 #define DRA7_PCIE2_CLKCTRL      DRA7_CLKCTRL_INDEX(0xb8)
  98 #define DRA7_GMAC_CLKCTRL       DRA7_CLKCTRL_INDEX(0xd0)
  99 #define DRA7_OCP2SCP1_CLKCTRL   DRA7_CLKCTRL_INDEX(0xe0)
 100 #define DRA7_OCP2SCP3_CLKCTRL   DRA7_CLKCTRL_INDEX(0xe8)
 101 #define DRA7_USB_OTG_SS1_CLKCTRL        DRA7_CLKCTRL_INDEX(0xf0)
 102
 103 /* l4per clocks */
 104 #define _DRA7_L4PER_CLKCTRL_OFFSET      0x0
 105 #define _DRA7_L4PER_CLKCTRL_INDEX(offset)       ((offset) - _DRA7_L4PER_CLKCTRL_OFFSET)
 106 #define DRA7_L4_PER2_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0xc)
 107 #define DRA7_L4_PER3_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0x14)
 108 #define DRA7_TIMER10_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0x28)
 109 #define DRA7_TIMER11_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0x30)
 110 #define DRA7_TIMER2_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x38)
 111 #define DRA7_TIMER3_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x40)
 112 #define DRA7_TIMER4_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x48)
 113 #define DRA7_TIMER9_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x50)
 114 #define DRA7_ELM_CLKCTRL        _DRA7_L4PER_CLKCTRL_INDEX(0x58)
 115 #define DRA7_GPIO2_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x60)
 116 #define DRA7_GPIO3_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x68)
 117 #define DRA7_GPIO4_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x70)
 118 #define DRA7_GPIO5_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x78)
 119 #define DRA7_GPIO6_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x80)
 120 #define DRA7_HDQ1W_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x88)
 121 #define DRA7_EPWMSS1_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0x90)
 122 #define DRA7_EPWMSS2_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0x98)
 123 #define DRA7_I2C1_CLKCTRL       _DRA7_L4PER_CLKCTRL_INDEX(0xa0)
 124 #define DRA7_I2C2_CLKCTRL       _DRA7_L4PER_CLKCTRL_INDEX(0xa8)
 125 #define DRA7_I2C3_CLKCTRL       _DRA7_L4PER_CLKCTRL_INDEX(0xb0)
 126 #define DRA7_I2C4_CLKCTRL       _DRA7_L4PER_CLKCTRL_INDEX(0xb8)
 127 #define DRA7_L4_PER1_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0xc0)
 128 #define DRA7_EPWMSS0_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0xc4)
 129 #define DRA7_TIMER13_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0xc8)
 130 #define DRA7_TIMER14_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0xd0)
 131 #define DRA7_TIMER15_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0xd8)
 132 #define DRA7_MCSPI1_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0xf0)
 133 #define DRA7_MCSPI2_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0xf8)
 134 #define DRA7_MCSPI3_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x100)
 135 #define DRA7_MCSPI4_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x108)
 136 #define DRA7_GPIO7_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x110)
 137 #define DRA7_GPIO8_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x118)
 138 #define DRA7_MMC3_CLKCTRL       _DRA7_L4PER_CLKCTRL_INDEX(0x120)
 139 #define DRA7_MMC4_CLKCTRL       _DRA7_L4PER_CLKCTRL_INDEX(0x128)
 140 #define DRA7_TIMER16_CLKCTRL    _DRA7_L4PER_CLKCTRL_INDEX(0x130)
 141 #define DRA7_QSPI_CLKCTRL       _DRA7_L4PER_CLKCTRL_INDEX(0x138)
 142 #define DRA7_UART1_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x140)
 143 #define DRA7_UART2_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x148)
 144 #define DRA7_UART3_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x150)
 145 #define DRA7_UART4_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x158)
 146 #define DRA7_MCASP2_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x160)
 147 #define DRA7_MCASP3_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x168)
 148 #define DRA7_UART5_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x170)
 149 #define DRA7_MCASP5_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x178)
 150 #define DRA7_MCASP8_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x190)
 151 #define DRA7_MCASP4_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x198)
 152 #define DRA7_AES1_CLKCTRL       _DRA7_L4PER_CLKCTRL_INDEX(0x1a0)
 153 #define DRA7_AES2_CLKCTRL       _DRA7_L4PER_CLKCTRL_INDEX(0x1a8)
 154 #define DRA7_DES_CLKCTRL        _DRA7_L4PER_CLKCTRL_INDEX(0x1b0)
 155 #define DRA7_RNG_CLKCTRL        _DRA7_L4PER_CLKCTRL_INDEX(0x1c0)
 156 #define DRA7_SHAM_CLKCTRL       _DRA7_L4PER_CLKCTRL_INDEX(0x1c8)
 157 #define DRA7_UART7_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x1d0)
 158 #define DRA7_UART8_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x1e0)
 159 #define DRA7_UART9_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x1e8)
 160 #define DRA7_DCAN2_CLKCTRL      _DRA7_L4PER_CLKCTRL_INDEX(0x1f0)
 161 #define DRA7_MCASP6_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x204)
 162 #define DRA7_MCASP7_CLKCTRL     _DRA7_L4PER_CLKCTRL_INDEX(0x208)
 163
 164 /* wkupaon clocks */
 165 #define DRA7_L4_WKUP_CLKCTRL    DRA7_CLKCTRL_INDEX(0x20)
 166 #define DRA7_WD_TIMER2_CLKCTRL  DRA7_CLKCTRL_INDEX(0x30)
 167 #define DRA7_GPIO1_CLKCTRL      DRA7_CLKCTRL_INDEX(0x38)
 168 #define DRA7_TIMER1_CLKCTRL     DRA7_CLKCTRL_INDEX(0x40)
 169 #define DRA7_TIMER12_CLKCTRL    DRA7_CLKCTRL_INDEX(0x48)
 170 #define DRA7_COUNTER_32K_CLKCTRL        DRA7_CLKCTRL_INDEX(0x50)
 171 #define DRA7_UART10_CLKCTRL     DRA7_CLKCTRL_INDEX(0x80)
 172 #define DRA7_DCAN1_CLKCTRL      DRA7_CLKCTRL_INDEX(0x88)
 173 #define DRA7_ADC_CLKCTRL        DRA7_CLKCTRL_INDEX(0xa0)
 174
 175 /* XXX: Compatibility part end. */
 176
 177 /* mpu clocks */
 178 #define DRA7_MPU_MPU_CLKCTRL    DRA7_CLKCTRL_INDEX(0x20)
 179
 180 /* dsp1 clocks */
 181 #define DRA7_DSP1_MMU0_DSP1_CLKCTRL     DRA7_CLKCTRL_INDEX(0x20)
 182
 183 /* ipu1 clocks */
 184 #define DRA7_IPU1_MMU_IPU1_CLKCTRL      DRA7_CLKCTRL_INDEX(0x20)
 185
 186 /* ipu clocks */
 187 #define DRA7_IPU_CLKCTRL_OFFSET 0x50
 188 #define DRA7_IPU_CLKCTRL_INDEX(offset)  ((offset) - DRA7_IPU_CLKCTRL_OFFSET)
 189 #define DRA7_IPU_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
 190 #define DRA7_IPU_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58)
 191 #define DRA7_IPU_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60)
 192 #define DRA7_IPU_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68)
 193 #define DRA7_IPU_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70)
 194 #define DRA7_IPU_I2C5_CLKCTRL   DRA7_IPU_CLKCTRL_INDEX(0x78)
 195 #define DRA7_IPU_UART6_CLKCTRL  DRA7_IPU_CLKCTRL_INDEX(0x80)
 196
 197 /* dsp2 clocks */
 198 #define DRA7_DSP2_MMU0_DSP2_CLKCTRL     DRA7_CLKCTRL_INDEX(0x20)
 199
 200 /* rtc clocks */
 201 #define DRA7_RTC_RTCSS_CLKCTRL  DRA7_CLKCTRL_INDEX(0x44)
 202
 203 /* coreaon clocks */
 204 #define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL    DRA7_CLKCTRL_INDEX(0x28)
 205 #define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL   DRA7_CLKCTRL_INDEX(0x38)
 206
 207 /* l3main1 clocks */
 208 #define DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL  DRA7_CLKCTRL_INDEX(0x20)
 209 #define DRA7_L3MAIN1_GPMC_CLKCTRL       DRA7_CLKCTRL_INDEX(0x28)
 210 #define DRA7_L3MAIN1_TPCC_CLKCTRL       DRA7_CLKCTRL_INDEX(0x70)
 211 #define DRA7_L3MAIN1_TPTC0_CLKCTRL      DRA7_CLKCTRL_INDEX(0x78)
 212 #define DRA7_L3MAIN1_TPTC1_CLKCTRL      DRA7_CLKCTRL_INDEX(0x80)
 213 #define DRA7_L3MAIN1_VCP1_CLKCTRL       DRA7_CLKCTRL_INDEX(0x88)
 214 #define DRA7_L3MAIN1_VCP2_CLKCTRL       DRA7_CLKCTRL_INDEX(0x90)
 215
 216 /* ipu2 clocks */
 217 #define DRA7_IPU2_MMU_IPU2_CLKCTRL      DRA7_CLKCTRL_INDEX(0x20)
 218
 219 /* dma clocks */
 220 #define DRA7_DMA_DMA_SYSTEM_CLKCTRL     DRA7_CLKCTRL_INDEX(0x20)
 221
 222 /* emif clocks */
 223 #define DRA7_EMIF_DMM_CLKCTRL   DRA7_CLKCTRL_INDEX(0x20)
 224
 225 /* atl clocks */
 226 #define DRA7_ATL_CLKCTRL_OFFSET 0x0
 227 #define DRA7_ATL_CLKCTRL_INDEX(offset)  ((offset) - DRA7_ATL_CLKCTRL_OFFSET)
 228 #define DRA7_ATL_ATL_CLKCTRL    DRA7_ATL_CLKCTRL_INDEX(0x0)
 229
 230 /* l4cfg clocks */
 231 #define DRA7_L4CFG_L4_CFG_CLKCTRL       DRA7_CLKCTRL_INDEX(0x20)
 232 #define DRA7_L4CFG_SPINLOCK_CLKCTRL     DRA7_CLKCTRL_INDEX(0x28)
 233 #define DRA7_L4CFG_MAILBOX1_CLKCTRL     DRA7_CLKCTRL_INDEX(0x30)
 234 #define DRA7_L4CFG_MAILBOX2_CLKCTRL     DRA7_CLKCTRL_INDEX(0x48)
 235 #define DRA7_L4CFG_MAILBOX3_CLKCTRL     DRA7_CLKCTRL_INDEX(0x50)
 236 #define DRA7_L4CFG_MAILBOX4_CLKCTRL     DRA7_CLKCTRL_INDEX(0x58)
 237 #define DRA7_L4CFG_MAILBOX5_CLKCTRL     DRA7_CLKCTRL_INDEX(0x60)
 238 #define DRA7_L4CFG_MAILBOX6_CLKCTRL     DRA7_CLKCTRL_INDEX(0x68)
 239 #define DRA7_L4CFG_MAILBOX7_CLKCTRL     DRA7_CLKCTRL_INDEX(0x70)
 240 #define DRA7_L4CFG_MAILBOX8_CLKCTRL     DRA7_CLKCTRL_INDEX(0x78)
 241 #define DRA7_L4CFG_MAILBOX9_CLKCTRL     DRA7_CLKCTRL_INDEX(0x80)
 242 #define DRA7_L4CFG_MAILBOX10_CLKCTRL    DRA7_CLKCTRL_INDEX(0x88)
 243 #define DRA7_L4CFG_MAILBOX11_CLKCTRL    DRA7_CLKCTRL_INDEX(0x90)
 244 #define DRA7_L4CFG_MAILBOX12_CLKCTRL    DRA7_CLKCTRL_INDEX(0x98)
 245 #define DRA7_L4CFG_MAILBOX13_CLKCTRL    DRA7_CLKCTRL_INDEX(0xa0)
 246
 247 /* l3instr clocks */
 248 #define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL  DRA7_CLKCTRL_INDEX(0x20)
 249 #define DRA7_L3INSTR_L3_INSTR_CLKCTRL   DRA7_CLKCTRL_INDEX(0x28)
 250
 251 /* dss clocks */
 252 #define DRA7_DSS_DSS_CORE_CLKCTRL       DRA7_CLKCTRL_INDEX(0x20)
 253 #define DRA7_DSS_BB2D_CLKCTRL   DRA7_CLKCTRL_INDEX(0x30)
 254
 255 /* l3init clocks */
 256 #define DRA7_L3INIT_MMC1_CLKCTRL        DRA7_CLKCTRL_INDEX(0x28)
 257 #define DRA7_L3INIT_MMC2_CLKCTRL        DRA7_CLKCTRL_INDEX(0x30)
 258 #define DRA7_L3INIT_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
 259 #define DRA7_L3INIT_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
 260 #define DRA7_L3INIT_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
 261 #define DRA7_L3INIT_SATA_CLKCTRL        DRA7_CLKCTRL_INDEX(0x88)
 262 #define DRA7_L3INIT_OCP2SCP1_CLKCTRL    DRA7_CLKCTRL_INDEX(0xe0)
 263 #define DRA7_L3INIT_OCP2SCP3_CLKCTRL    DRA7_CLKCTRL_INDEX(0xe8)
 264 #define DRA7_L3INIT_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
 265
 266 /* pcie clocks */
 267 #define DRA7_PCIE_CLKCTRL_OFFSET        0xb0
 268 #define DRA7_PCIE_CLKCTRL_INDEX(offset) ((offset) - DRA7_PCIE_CLKCTRL_OFFSET)
 269 #define DRA7_PCIE_PCIE1_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb0)
 270 #define DRA7_PCIE_PCIE2_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb8)
 271
 272 /* gmac clocks */
 273 #define DRA7_GMAC_CLKCTRL_OFFSET        0xd0
 274 #define DRA7_GMAC_CLKCTRL_INDEX(offset) ((offset) - DRA7_GMAC_CLKCTRL_OFFSET)
 275 #define DRA7_GMAC_GMAC_CLKCTRL  DRA7_GMAC_CLKCTRL_INDEX(0xd0)
 276
 277 /* l4per clocks */
 278 #define DRA7_L4PER_CLKCTRL_OFFSET       0x28
 279 #define DRA7_L4PER_CLKCTRL_INDEX(offset)        ((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
 280 #define DRA7_L4PER_TIMER10_CLKCTRL      DRA7_L4PER_CLKCTRL_INDEX(0x28)
 281 #define DRA7_L4PER_TIMER11_CLKCTRL      DRA7_L4PER_CLKCTRL_INDEX(0x30)
 282 #define DRA7_L4PER_TIMER2_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0x38)
 283 #define DRA7_L4PER_TIMER3_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0x40)
 284 #define DRA7_L4PER_TIMER4_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0x48)
 285 #define DRA7_L4PER_TIMER9_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0x50)
 286 #define DRA7_L4PER_ELM_CLKCTRL  DRA7_L4PER_CLKCTRL_INDEX(0x58)
 287 #define DRA7_L4PER_GPIO2_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x60)
 288 #define DRA7_L4PER_GPIO3_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x68)
 289 #define DRA7_L4PER_GPIO4_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x70)
 290 #define DRA7_L4PER_GPIO5_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x78)
 291 #define DRA7_L4PER_GPIO6_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x80)
 292 #define DRA7_L4PER_HDQ1W_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x88)
 293 #define DRA7_L4PER_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0)
 294 #define DRA7_L4PER_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8)
 295 #define DRA7_L4PER_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0)
 296 #define DRA7_L4PER_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8)
 297 #define DRA7_L4PER_L4_PER1_CLKCTRL      DRA7_L4PER_CLKCTRL_INDEX(0xc0)
 298 #define DRA7_L4PER_MCSPI1_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0xf0)
 299 #define DRA7_L4PER_MCSPI2_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0xf8)
 300 #define DRA7_L4PER_MCSPI3_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0x100)
 301 #define DRA7_L4PER_MCSPI4_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0x108)
 302 #define DRA7_L4PER_GPIO7_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x110)
 303 #define DRA7_L4PER_GPIO8_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x118)
 304 #define DRA7_L4PER_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120)
 305 #define DRA7_L4PER_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128)
 306 #define DRA7_L4PER_UART1_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x140)
 307 #define DRA7_L4PER_UART2_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x148)
 308 #define DRA7_L4PER_UART3_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x150)
 309 #define DRA7_L4PER_UART4_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x158)
 310 #define DRA7_L4PER_UART5_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x170)
 311
 312 /* l4sec clocks */
 313 #define DRA7_L4SEC_CLKCTRL_OFFSET       0x1a0
 314 #define DRA7_L4SEC_CLKCTRL_INDEX(offset)        ((offset) - DRA7_L4SEC_CLKCTRL_OFFSET)
 315 #define DRA7_L4SEC_AES1_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a0)
 316 #define DRA7_L4SEC_AES2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a8)
 317 #define DRA7_L4SEC_DES_CLKCTRL  DRA7_L4SEC_CLKCTRL_INDEX(0x1b0)
 318 #define DRA7_L4SEC_RNG_CLKCTRL  DRA7_L4SEC_CLKCTRL_INDEX(0x1c0)
 319 #define DRA7_L4SEC_SHAM_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c8)
 320
 321 /* l4per2 clocks */
 322 #define DRA7_L4PER2_CLKCTRL_OFFSET      0xc
 323 #define DRA7_L4PER2_CLKCTRL_INDEX(offset)       ((offset) - DRA7_L4PER2_CLKCTRL_OFFSET)
 324 #define DRA7_L4PER2_L4_PER2_CLKCTRL     DRA7_L4PER2_CLKCTRL_INDEX(0xc)
 325 #define DRA7_L4PER2_PRUSS1_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x18)
 326 #define DRA7_L4PER2_PRUSS2_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x20)
 327 #define DRA7_L4PER2_EPWMSS1_CLKCTRL     DRA7_L4PER2_CLKCTRL_INDEX(0x90)
 328 #define DRA7_L4PER2_EPWMSS2_CLKCTRL     DRA7_L4PER2_CLKCTRL_INDEX(0x98)
 329 #define DRA7_L4PER2_EPWMSS0_CLKCTRL     DRA7_L4PER2_CLKCTRL_INDEX(0xc4)
 330 #define DRA7_L4PER2_QSPI_CLKCTRL        DRA7_L4PER2_CLKCTRL_INDEX(0x138)
 331 #define DRA7_L4PER2_MCASP2_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x160)
 332 #define DRA7_L4PER2_MCASP3_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x168)
 333 #define DRA7_L4PER2_MCASP5_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x178)
 334 #define DRA7_L4PER2_MCASP8_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x190)
 335 #define DRA7_L4PER2_MCASP4_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x198)
 336 #define DRA7_L4PER2_UART7_CLKCTRL       DRA7_L4PER2_CLKCTRL_INDEX(0x1d0)
 337 #define DRA7_L4PER2_UART8_CLKCTRL       DRA7_L4PER2_CLKCTRL_INDEX(0x1e0)
 338 #define DRA7_L4PER2_UART9_CLKCTRL       DRA7_L4PER2_CLKCTRL_INDEX(0x1e8)
 339 #define DRA7_L4PER2_DCAN2_CLKCTRL       DRA7_L4PER2_CLKCTRL_INDEX(0x1f0)
 340 #define DRA7_L4PER2_MCASP6_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x204)
 341 #define DRA7_L4PER2_MCASP7_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x208)
 342
 343 /* l4per3 clocks */
 344 #define DRA7_L4PER3_CLKCTRL_OFFSET      0x14
 345 #define DRA7_L4PER3_CLKCTRL_INDEX(offset)       ((offset) - DRA7_L4PER3_CLKCTRL_OFFSET)
 346 #define DRA7_L4PER3_L4_PER3_CLKCTRL     DRA7_L4PER3_CLKCTRL_INDEX(0x14)
 347 #define DRA7_L4PER3_TIMER13_CLKCTRL     DRA7_L4PER3_CLKCTRL_INDEX(0xc8)
 348 #define DRA7_L4PER3_TIMER14_CLKCTRL     DRA7_L4PER3_CLKCTRL_INDEX(0xd0)
 349 #define DRA7_L4PER3_TIMER15_CLKCTRL     DRA7_L4PER3_CLKCTRL_INDEX(0xd8)
 350 #define DRA7_L4PER3_TIMER16_CLKCTRL     DRA7_L4PER3_CLKCTRL_INDEX(0x130)
 351
 352 /* wkupaon clocks */
 353 #define DRA7_WKUPAON_L4_WKUP_CLKCTRL    DRA7_CLKCTRL_INDEX(0x20)
 354 #define DRA7_WKUPAON_WD_TIMER2_CLKCTRL  DRA7_CLKCTRL_INDEX(0x30)
 355 #define DRA7_WKUPAON_GPIO1_CLKCTRL      DRA7_CLKCTRL_INDEX(0x38)
 356 #define DRA7_WKUPAON_TIMER1_CLKCTRL     DRA7_CLKCTRL_INDEX(0x40)
 357 #define DRA7_WKUPAON_TIMER12_CLKCTRL    DRA7_CLKCTRL_INDEX(0x48)
 358 #define DRA7_WKUPAON_COUNTER_32K_CLKCTRL        DRA7_CLKCTRL_INDEX(0x50)
 359 #define DRA7_WKUPAON_UART10_CLKCTRL     DRA7_CLKCTRL_INDEX(0x80)
 360 #define DRA7_WKUPAON_DCAN1_CLKCTRL      DRA7_CLKCTRL_INDEX(0x88)
 361 #define DRA7_WKUPAON_ADC_CLKCTRL        DRA7_CLKCTRL_INDEX(0xa0)
 362
 363 #endif