2 * Copyright © 2008 Keith Packard
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
23 #ifndef _DRM_DP_HELPER_H_
24 #define _DRM_DP_HELPER_H_
26 #include <linux/delay.h>
27 #include <linux/i2c.h>
28 #include <linux/types.h>
29 #include <drm/drm_connector.h>
36 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
37 * DP and DPCD versions are independent. Differences from 1.0 are not noted,
38 * 1.0 devices basically don't exist in the wild.
40 * Abbreviations, in chronological order:
42 * eDP: Embedded DisplayPort version 1
43 * DPI: DisplayPort Interoperability Guideline v1.1a
44 * 1.2: DisplayPort 1.2
45 * MST: Multistream Transport - part of DP 1.2a
47 * 1.2 formally includes both eDP and DPI definitions.
50 /* MSA (Main Stream Attribute) MISC bits (as MISC1<<8|MISC0) */
51 #define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
52 #define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN (1 << 8)
53 #define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
54 #define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE (1 << 9)
55 #define DP_MSA_MISC_STEREO_PROG_LEFT_EYE (3 << 9)
56 /* bits per component for non-RAW */
57 #define DP_MSA_MISC_6_BPC (0 << 5)
58 #define DP_MSA_MISC_8_BPC (1 << 5)
59 #define DP_MSA_MISC_10_BPC (2 << 5)
60 #define DP_MSA_MISC_12_BPC (3 << 5)
61 #define DP_MSA_MISC_16_BPC (4 << 5)
62 /* bits per component for RAW */
63 #define DP_MSA_MISC_RAW_6_BPC (1 << 5)
64 #define DP_MSA_MISC_RAW_7_BPC (2 << 5)
65 #define DP_MSA_MISC_RAW_8_BPC (3 << 5)
66 #define DP_MSA_MISC_RAW_10_BPC (4 << 5)
67 #define DP_MSA_MISC_RAW_12_BPC (5 << 5)
68 #define DP_MSA_MISC_RAW_14_BPC (6 << 5)
69 #define DP_MSA_MISC_RAW_16_BPC (7 << 5)
70 /* pixel encoding/colorimetry format */
71 #define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \
72 ((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1))
73 #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
74 #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
75 #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
76 #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
77 #define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
78 #define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
79 #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
80 #define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1)
81 #define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0)
82 #define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1)
83 #define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0)
84 #define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1)
85 #define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0)
86 #define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1)
87 #define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1)
88 #define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0)
89 #define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1)
90 #define DP_MSA_MISC_COLOR_VSC_SDP (1 << 14)
92 #define DP_AUX_MAX_PAYLOAD_BYTES 16
94 #define DP_AUX_I2C_WRITE 0x0
95 #define DP_AUX_I2C_READ 0x1
96 #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
97 #define DP_AUX_I2C_MOT 0x4
98 #define DP_AUX_NATIVE_WRITE 0x8
99 #define DP_AUX_NATIVE_READ 0x9
101 #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
102 #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
103 #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
104 #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
106 #define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
107 #define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
108 #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
109 #define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
111 /* DPCD Field Address Mapping */
113 /* Receiver Capability */
114 #define DP_DPCD_REV 0x000
115 # define DP_DPCD_REV_10 0x10
116 # define DP_DPCD_REV_11 0x11
117 # define DP_DPCD_REV_12 0x12
118 # define DP_DPCD_REV_13 0x13
119 # define DP_DPCD_REV_14 0x14
121 #define DP_MAX_LINK_RATE 0x001
123 #define DP_MAX_LANE_COUNT 0x002
124 # define DP_MAX_LANE_COUNT_MASK 0x1f
125 # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
126 # define DP_ENHANCED_FRAME_CAP (1 << 7)
128 #define DP_MAX_DOWNSPREAD 0x003
129 # define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
130 # define DP_STREAM_REGENERATION_STATUS_CAP (1 << 1) /* 2.0 */
131 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
132 # define DP_TPS4_SUPPORTED (1 << 7)
134 #define DP_NORP 0x004
136 #define DP_DOWNSTREAMPORT_PRESENT 0x005
137 # define DP_DWN_STRM_PORT_PRESENT (1 << 0)
138 # define DP_DWN_STRM_PORT_TYPE_MASK 0x06
139 # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
140 # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
141 # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
142 # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
143 # define DP_FORMAT_CONVERSION (1 << 3)
144 # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
146 #define DP_MAIN_LINK_CHANNEL_CODING 0x006
147 # define DP_CAP_ANSI_8B10B (1 << 0)
148 # define DP_CAP_ANSI_128B132B (1 << 1) /* 2.0 */
150 #define DP_DOWN_STREAM_PORT_COUNT 0x007
151 # define DP_PORT_COUNT_MASK 0x0f
152 # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
153 # define DP_OUI_SUPPORT (1 << 7)
155 #define DP_RECEIVE_PORT_0_CAP_0 0x008
156 # define DP_LOCAL_EDID_PRESENT (1 << 1)
157 # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
159 #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
161 #define DP_RECEIVE_PORT_1_CAP_0 0x00a
162 #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
164 #define DP_I2C_SPEED_CAP 0x00c /* DPI */
165 # define DP_I2C_SPEED_1K 0x01
166 # define DP_I2C_SPEED_5K 0x02
167 # define DP_I2C_SPEED_10K 0x04
168 # define DP_I2C_SPEED_100K 0x08
169 # define DP_I2C_SPEED_400K 0x10
170 # define DP_I2C_SPEED_1M 0x20
172 #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
173 # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
174 # define DP_FRAMING_CHANGE_CAP (1 << 1)
175 # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
177 #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
178 # define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */
179 # define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */
181 #define DP_ADAPTER_CAP 0x00f /* 1.2 */
182 # define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
183 # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
185 #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
186 # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
188 /* Multiple stream transport */
189 #define DP_FAUX_CAP 0x020 /* 1.2 */
190 # define DP_FAUX_CAP_1 (1 << 0)
192 #define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 /* 2.0 */
193 # define DP_FALLBACK_1024x768_60HZ_24BPP (1 << 0)
194 # define DP_FALLBACK_1280x720_60HZ_24BPP (1 << 1)
195 # define DP_FALLBACK_1920x1080_60HZ_24BPP (1 << 2)
197 #define DP_MSTM_CAP 0x021 /* 1.2 */
198 # define DP_MST_CAP (1 << 0)
199 # define DP_SINGLE_STREAM_SIDEBAND_MSG (1 << 1) /* 2.0 */
201 #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
203 /* AV_SYNC_DATA_BLOCK 1.2 */
204 #define DP_AV_GRANULARITY 0x023
205 # define DP_AG_FACTOR_MASK (0xf << 0)
206 # define DP_AG_FACTOR_3MS (0 << 0)
207 # define DP_AG_FACTOR_2MS (1 << 0)
208 # define DP_AG_FACTOR_1MS (2 << 0)
209 # define DP_AG_FACTOR_500US (3 << 0)
210 # define DP_AG_FACTOR_200US (4 << 0)
211 # define DP_AG_FACTOR_100US (5 << 0)
212 # define DP_AG_FACTOR_10US (6 << 0)
213 # define DP_AG_FACTOR_1US (7 << 0)
214 # define DP_VG_FACTOR_MASK (0xf << 4)
215 # define DP_VG_FACTOR_3MS (0 << 4)
216 # define DP_VG_FACTOR_2MS (1 << 4)
217 # define DP_VG_FACTOR_1MS (2 << 4)
218 # define DP_VG_FACTOR_500US (3 << 4)
219 # define DP_VG_FACTOR_200US (4 << 4)
220 # define DP_VG_FACTOR_100US (5 << 4)
222 #define DP_AUD_DEC_LAT0 0x024
223 #define DP_AUD_DEC_LAT1 0x025
225 #define DP_AUD_PP_LAT0 0x026
226 #define DP_AUD_PP_LAT1 0x027
228 #define DP_VID_INTER_LAT 0x028
230 #define DP_VID_PROG_LAT 0x029
232 #define DP_REP_LAT 0x02a
234 #define DP_AUD_DEL_INS0 0x02b
235 #define DP_AUD_DEL_INS1 0x02c
236 #define DP_AUD_DEL_INS2 0x02d
237 /* End of AV_SYNC_DATA_BLOCK */
239 #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
240 # define DP_ALPM_CAP (1 << 0)
242 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
243 # define DP_AUX_FRAME_SYNC_CAP (1 << 0)
245 #define DP_GUID 0x030 /* 1.2 */
247 #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
248 # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
250 #define DP_DSC_REV 0x061
251 # define DP_DSC_MAJOR_MASK (0xf << 0)
252 # define DP_DSC_MINOR_MASK (0xf << 4)
253 # define DP_DSC_MAJOR_SHIFT 0
254 # define DP_DSC_MINOR_SHIFT 4
256 #define DP_DSC_RC_BUF_BLK_SIZE 0x062
257 # define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
258 # define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
259 # define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
260 # define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
262 #define DP_DSC_RC_BUF_SIZE 0x063
264 #define DP_DSC_SLICE_CAP_1 0x064
265 # define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
266 # define DP_DSC_2_PER_DP_DSC_SINK (1 << 1)
267 # define DP_DSC_4_PER_DP_DSC_SINK (1 << 3)
268 # define DP_DSC_6_PER_DP_DSC_SINK (1 << 4)
269 # define DP_DSC_8_PER_DP_DSC_SINK (1 << 5)
270 # define DP_DSC_10_PER_DP_DSC_SINK (1 << 6)
271 # define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)
273 #define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
274 # define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
275 # define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
276 # define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
277 # define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
278 # define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
279 # define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
280 # define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
281 # define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
282 # define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
283 # define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
285 #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
286 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
288 #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
290 #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
291 # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0)
292 # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8
294 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
295 # define DP_DSC_RGB (1 << 0)
296 # define DP_DSC_YCbCr444 (1 << 1)
297 # define DP_DSC_YCbCr422_Simple (1 << 2)
298 # define DP_DSC_YCbCr422_Native (1 << 3)
299 # define DP_DSC_YCbCr420_Native (1 << 4)
301 #define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
302 # define DP_DSC_8_BPC (1 << 1)
303 # define DP_DSC_10_BPC (1 << 2)
304 # define DP_DSC_12_BPC (1 << 3)
306 #define DP_DSC_PEAK_THROUGHPUT 0x06B
307 # define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
308 # define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
309 # define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0
310 # define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
311 # define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
312 # define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
313 # define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
314 # define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
315 # define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
316 # define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
317 # define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
318 # define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
319 # define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
320 # define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
321 # define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
322 # define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
323 # define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
324 # define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */
325 # define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
326 # define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4
327 # define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED 0
328 # define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)
329 # define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)
330 # define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)
331 # define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4)
332 # define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4)
333 # define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4)
334 # define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)
335 # define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4)
336 # define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4)
337 # define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4)
338 # define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4)
339 # define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)
340 # define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)
341 # define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
342 # define DP_DSC_THROUGHPUT_MODE_1_170 (15 << 4)
344 #define DP_DSC_MAX_SLICE_WIDTH 0x06C
345 #define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560
346 #define DP_DSC_SLICE_WIDTH_MULTIPLIER 320
348 #define DP_DSC_SLICE_CAP_2 0x06D
349 # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
350 # define DP_DSC_20_PER_DP_DSC_SINK (1 << 1)
351 # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2)
353 #define DP_DSC_BITS_PER_PIXEL_INC 0x06F
354 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0
355 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1
356 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2
357 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3
358 # define DP_DSC_BITS_PER_PIXEL_1 0x4
360 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
361 # define DP_PSR_IS_SUPPORTED 1
362 # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
363 # define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */
364 # define DP_PSR2_WITH_Y_COORD_ET_SUPPORTED 4 /* eDP 1.5, adopted eDP 1.4b SCR */
366 #define DP_PSR_CAPS 0x071 /* XXX 1.2? */
367 # define DP_PSR_NO_TRAIN_ON_EXIT 1
368 # define DP_PSR_SETUP_TIME_330 (0 << 1)
369 # define DP_PSR_SETUP_TIME_275 (1 << 1)
370 # define DP_PSR_SETUP_TIME_220 (2 << 1)
371 # define DP_PSR_SETUP_TIME_165 (3 << 1)
372 # define DP_PSR_SETUP_TIME_110 (4 << 1)
373 # define DP_PSR_SETUP_TIME_55 (5 << 1)
374 # define DP_PSR_SETUP_TIME_0 (6 << 1)
375 # define DP_PSR_SETUP_TIME_MASK (7 << 1)
376 # define DP_PSR_SETUP_TIME_SHIFT 1
377 # define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */
378 # define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */
379 # define DP_PSR2_SU_AUX_FRAME_SYNC_NOT_NEEDED (1 << 6)/* eDP 1.5, adopted eDP 1.4b SCR */
381 #define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */
382 #define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */
385 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
386 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
387 * each port's descriptor is one byte wide. If it was set, each port's is
388 * four bytes wide, starting with the one byte from the base info. As of
389 * DP interop v1.1a only VGA defines additional detail.
393 #define DP_DOWNSTREAM_PORT_0 0x80
394 # define DP_DS_PORT_TYPE_MASK (7 << 0)
395 # define DP_DS_PORT_TYPE_DP 0
396 # define DP_DS_PORT_TYPE_VGA 1
397 # define DP_DS_PORT_TYPE_DVI 2
398 # define DP_DS_PORT_TYPE_HDMI 3
399 # define DP_DS_PORT_TYPE_NON_EDID 4
400 # define DP_DS_PORT_TYPE_DP_DUALMODE 5
401 # define DP_DS_PORT_TYPE_WIRELESS 6
402 # define DP_DS_PORT_HPD (1 << 3)
403 # define DP_DS_NON_EDID_MASK (0xf << 4)
404 # define DP_DS_NON_EDID_720x480i_60 (1 << 4)
405 # define DP_DS_NON_EDID_720x480i_50 (2 << 4)
406 # define DP_DS_NON_EDID_1920x1080i_60 (3 << 4)
407 # define DP_DS_NON_EDID_1920x1080i_50 (4 << 4)
408 # define DP_DS_NON_EDID_1280x720_60 (5 << 4)
409 # define DP_DS_NON_EDID_1280x720_50 (7 << 4)
410 /* offset 1 for VGA is maximum megapixels per second / 8 */
411 /* offset 1 for DVI/HDMI is maximum TMDS clock in Mbps / 2.5 */
412 /* offset 2 for VGA/DVI/HDMI */
413 # define DP_DS_MAX_BPC_MASK (3 << 0)
414 # define DP_DS_8BPC 0
415 # define DP_DS_10BPC 1
416 # define DP_DS_12BPC 2
417 # define DP_DS_16BPC 3
418 /* HDMI2.1 PCON FRL CONFIGURATION */
419 # define DP_PCON_MAX_FRL_BW (7 << 2)
420 # define DP_PCON_MAX_0GBPS (0 << 2)
421 # define DP_PCON_MAX_9GBPS (1 << 2)
422 # define DP_PCON_MAX_18GBPS (2 << 2)
423 # define DP_PCON_MAX_24GBPS (3 << 2)
424 # define DP_PCON_MAX_32GBPS (4 << 2)
425 # define DP_PCON_MAX_40GBPS (5 << 2)
426 # define DP_PCON_MAX_48GBPS (6 << 2)
427 # define DP_PCON_SOURCE_CTL_MODE (1 << 5)
429 /* offset 3 for DVI */
430 # define DP_DS_DVI_DUAL_LINK (1 << 1)
431 # define DP_DS_DVI_HIGH_COLOR_DEPTH (1 << 2)
432 /* offset 3 for HDMI */
433 # define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0)
434 # define DP_DS_HDMI_YCBCR422_PASS_THROUGH (1 << 1)
435 # define DP_DS_HDMI_YCBCR420_PASS_THROUGH (1 << 2)
436 # define DP_DS_HDMI_YCBCR444_TO_422_CONV (1 << 3)
437 # define DP_DS_HDMI_YCBCR444_TO_420_CONV (1 << 4)
440 * VESA DP-to-HDMI PCON Specification adds caps for colorspace
441 * conversion in DFP cap DPCD 83h. Sec6.1 Table-3.
442 * Based on the available support the source can enable
443 * color conversion by writing into PROTOCOL_COVERTER_CONTROL_2
446 # define DP_DS_HDMI_BT601_RGB_YCBCR_CONV (1 << 5)
447 # define DP_DS_HDMI_BT709_RGB_YCBCR_CONV (1 << 6)
448 # define DP_DS_HDMI_BT2020_RGB_YCBCR_CONV (1 << 7)
450 #define DP_MAX_DOWNSTREAM_PORTS 0x10
452 /* DP Forward error Correction Registers */
453 #define DP_FEC_CAPABILITY 0x090 /* 1.4 */
454 # define DP_FEC_CAPABLE (1 << 0)
455 # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
456 # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
457 # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
458 #define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */
460 /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
461 #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xD /* 0x92 through 0x9E */
462 #define DP_PCON_DSC_ENCODER 0x092
463 # define DP_PCON_DSC_ENCODER_SUPPORTED (1 << 0)
464 # define DP_PCON_DSC_PPS_ENC_OVERRIDE (1 << 1)
466 /* DP-HDMI2.1 PCON DSC Version */
467 #define DP_PCON_DSC_VERSION 0x093
468 # define DP_PCON_DSC_MAJOR_MASK (0xF << 0)
469 # define DP_PCON_DSC_MINOR_MASK (0xF << 4)
470 # define DP_PCON_DSC_MAJOR_SHIFT 0
471 # define DP_PCON_DSC_MINOR_SHIFT 4
473 /* DP-HDMI2.1 PCON DSC RC Buffer block size */
474 #define DP_PCON_DSC_RC_BUF_BLK_INFO 0x094
475 # define DP_PCON_DSC_RC_BUF_BLK_SIZE (0x3 << 0)
476 # define DP_PCON_DSC_RC_BUF_BLK_1KB 0
477 # define DP_PCON_DSC_RC_BUF_BLK_4KB 1
478 # define DP_PCON_DSC_RC_BUF_BLK_16KB 2
479 # define DP_PCON_DSC_RC_BUF_BLK_64KB 3
481 /* DP-HDMI2.1 PCON DSC RC Buffer size */
482 #define DP_PCON_DSC_RC_BUF_SIZE 0x095
484 /* DP-HDMI2.1 PCON DSC Slice capabilities-1 */
485 #define DP_PCON_DSC_SLICE_CAP_1 0x096
486 # define DP_PCON_DSC_1_PER_DSC_ENC (0x1 << 0)
487 # define DP_PCON_DSC_2_PER_DSC_ENC (0x1 << 1)
488 # define DP_PCON_DSC_4_PER_DSC_ENC (0x1 << 3)
489 # define DP_PCON_DSC_6_PER_DSC_ENC (0x1 << 4)
490 # define DP_PCON_DSC_8_PER_DSC_ENC (0x1 << 5)
491 # define DP_PCON_DSC_10_PER_DSC_ENC (0x1 << 6)
492 # define DP_PCON_DSC_12_PER_DSC_ENC (0x1 << 7)
494 #define DP_PCON_DSC_BUF_BIT_DEPTH 0x097
495 # define DP_PCON_DSC_BIT_DEPTH_MASK (0xF << 0)
496 # define DP_PCON_DSC_DEPTH_9_BITS 0
497 # define DP_PCON_DSC_DEPTH_10_BITS 1
498 # define DP_PCON_DSC_DEPTH_11_BITS 2
499 # define DP_PCON_DSC_DEPTH_12_BITS 3
500 # define DP_PCON_DSC_DEPTH_13_BITS 4
501 # define DP_PCON_DSC_DEPTH_14_BITS 5
502 # define DP_PCON_DSC_DEPTH_15_BITS 6
503 # define DP_PCON_DSC_DEPTH_16_BITS 7
504 # define DP_PCON_DSC_DEPTH_8_BITS 8
506 #define DP_PCON_DSC_BLOCK_PREDICTION 0x098
507 # define DP_PCON_DSC_BLOCK_PRED_SUPPORT (0x1 << 0)
509 #define DP_PCON_DSC_ENC_COLOR_FMT_CAP 0x099
510 # define DP_PCON_DSC_ENC_RGB (0x1 << 0)
511 # define DP_PCON_DSC_ENC_YUV444 (0x1 << 1)
512 # define DP_PCON_DSC_ENC_YUV422_S (0x1 << 2)
513 # define DP_PCON_DSC_ENC_YUV422_N (0x1 << 3)
514 # define DP_PCON_DSC_ENC_YUV420_N (0x1 << 4)
516 #define DP_PCON_DSC_ENC_COLOR_DEPTH_CAP 0x09A
517 # define DP_PCON_DSC_ENC_8BPC (0x1 << 1)
518 # define DP_PCON_DSC_ENC_10BPC (0x1 << 2)
519 # define DP_PCON_DSC_ENC_12BPC (0x1 << 3)
521 #define DP_PCON_DSC_MAX_SLICE_WIDTH 0x09B
523 /* DP-HDMI2.1 PCON DSC Slice capabilities-2 */
524 #define DP_PCON_DSC_SLICE_CAP_2 0x09C
525 # define DP_PCON_DSC_16_PER_DSC_ENC (0x1 << 0)
526 # define DP_PCON_DSC_20_PER_DSC_ENC (0x1 << 1)
527 # define DP_PCON_DSC_24_PER_DSC_ENC (0x1 << 2)
529 /* DP-HDMI2.1 PCON HDMI TX Encoder Bits/pixel increment */
530 #define DP_PCON_DSC_BPP_INCR 0x09E
531 # define DP_PCON_DSC_BPP_INCR_MASK (0x7 << 0)
532 # define DP_PCON_DSC_ONE_16TH_BPP 0
533 # define DP_PCON_DSC_ONE_8TH_BPP 1
534 # define DP_PCON_DSC_ONE_4TH_BPP 2
535 # define DP_PCON_DSC_ONE_HALF_BPP 3
536 # define DP_PCON_DSC_ONE_BPP 4
538 /* DP Extended DSC Capabilities */
539 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */
540 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
541 #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
543 /* DFP Capability Extension */
544 #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
546 /* Link Configuration */
547 #define DP_LINK_BW_SET 0x100
548 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
549 # define DP_LINK_BW_1_62 0x06
550 # define DP_LINK_BW_2_7 0x0a
551 # define DP_LINK_BW_5_4 0x14 /* 1.2 */
552 # define DP_LINK_BW_8_1 0x1e /* 1.4 */
553 # define DP_LINK_BW_10 0x01 /* 2.0 128b/132b Link Layer */
554 # define DP_LINK_BW_13_5 0x04 /* 2.0 128b/132b Link Layer */
555 # define DP_LINK_BW_20 0x02 /* 2.0 128b/132b Link Layer */
557 #define DP_LANE_COUNT_SET 0x101
558 # define DP_LANE_COUNT_MASK 0x0f
559 # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
561 #define DP_TRAINING_PATTERN_SET 0x102
562 # define DP_TRAINING_PATTERN_DISABLE 0
563 # define DP_TRAINING_PATTERN_1 1
564 # define DP_TRAINING_PATTERN_2 2
565 # define DP_TRAINING_PATTERN_2_CDS 3 /* 2.0 E11 */
566 # define DP_TRAINING_PATTERN_3 3 /* 1.2 */
567 # define DP_TRAINING_PATTERN_4 7 /* 1.4 */
568 # define DP_TRAINING_PATTERN_MASK 0x3
569 # define DP_TRAINING_PATTERN_MASK_1_4 0xf
571 /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
572 # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
573 # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
574 # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
575 # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
576 # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
578 # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
579 # define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
581 # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
582 # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
583 # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
584 # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
586 #define DP_TRAINING_LANE0_SET 0x103
587 #define DP_TRAINING_LANE1_SET 0x104
588 #define DP_TRAINING_LANE2_SET 0x105
589 #define DP_TRAINING_LANE3_SET 0x106
591 # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
592 # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
593 # define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
594 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
595 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
596 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
597 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
599 # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
600 # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
601 # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
602 # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
603 # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
605 # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
606 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
608 # define DP_TX_FFE_PRESET_VALUE_MASK (0xf << 0) /* 2.0 128b/132b Link Layer */
610 #define DP_DOWNSPREAD_CTRL 0x107
611 # define DP_SPREAD_AMP_0_5 (1 << 4)
612 # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
614 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
615 # define DP_SET_ANSI_8B10B (1 << 0)
616 # define DP_SET_ANSI_128B132B (1 << 1)
618 #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
619 /* bitmask as for DP_I2C_SPEED_CAP */
621 #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
622 # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
623 # define DP_FRAMING_CHANGE_ENABLE (1 << 1)
624 # define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
626 #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
627 #define DP_LINK_QUAL_LANE1_SET 0x10c
628 #define DP_LINK_QUAL_LANE2_SET 0x10d
629 #define DP_LINK_QUAL_LANE3_SET 0x10e
630 # define DP_LINK_QUAL_PATTERN_DISABLE 0
631 # define DP_LINK_QUAL_PATTERN_D10_2 1
632 # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
633 # define DP_LINK_QUAL_PATTERN_PRBS7 3
634 # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
635 # define DP_LINK_QUAL_PATTERN_CP2520_PAT_1 5
636 # define DP_LINK_QUAL_PATTERN_CP2520_PAT_2 6
637 # define DP_LINK_QUAL_PATTERN_CP2520_PAT_3 7
638 /* DP 2.0 UHBR10, UHBR13.5, UHBR20 */
639 # define DP_LINK_QUAL_PATTERN_128B132B_TPS1 0x08
640 # define DP_LINK_QUAL_PATTERN_128B132B_TPS2 0x10
641 # define DP_LINK_QUAL_PATTERN_PRSBS9 0x18
642 # define DP_LINK_QUAL_PATTERN_PRSBS11 0x20
643 # define DP_LINK_QUAL_PATTERN_PRSBS15 0x28
644 # define DP_LINK_QUAL_PATTERN_PRSBS23 0x30
645 # define DP_LINK_QUAL_PATTERN_PRSBS31 0x38
646 # define DP_LINK_QUAL_PATTERN_CUSTOM 0x40
647 # define DP_LINK_QUAL_PATTERN_SQUARE 0x48
649 #define DP_TRAINING_LANE0_1_SET2 0x10f
650 #define DP_TRAINING_LANE2_3_SET2 0x110
651 # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
652 # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
653 # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
654 # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
656 #define DP_MSTM_CTRL 0x111 /* 1.2 */
657 # define DP_MST_EN (1 << 0)
658 # define DP_UP_REQ_EN (1 << 1)
659 # define DP_UPSTREAM_IS_SRC (1 << 2)
661 #define DP_AUDIO_DELAY0 0x112 /* 1.2 */
662 #define DP_AUDIO_DELAY1 0x113
663 #define DP_AUDIO_DELAY2 0x114
665 #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
666 # define DP_LINK_RATE_SET_SHIFT 0
667 # define DP_LINK_RATE_SET_MASK (7 << 0)
669 #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
670 # define DP_ALPM_ENABLE (1 << 0)
671 # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
673 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
674 # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
675 # define DP_IRQ_HPD_ENABLE (1 << 1)
677 #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
678 # define DP_PWR_NOT_NEEDED (1 << 0)
680 #define DP_FEC_CONFIGURATION 0x120 /* 1.4 */
681 # define DP_FEC_READY (1 << 0)
682 # define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1)
683 # define DP_FEC_ERR_COUNT_DIS (0 << 1)
684 # define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1)
685 # define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1)
686 # define DP_FEC_BIT_ERROR_COUNT (3 << 1)
687 # define DP_FEC_LANE_SELECT_MASK (3 << 4)
688 # define DP_FEC_LANE_0_SELECT (0 << 4)
689 # define DP_FEC_LANE_1_SELECT (1 << 4)
690 # define DP_FEC_LANE_2_SELECT (2 << 4)
691 # define DP_FEC_LANE_3_SELECT (3 << 4)
693 #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
694 # define DP_AUX_FRAME_SYNC_VALID (1 << 0)
696 #define DP_DSC_ENABLE 0x160 /* DP 1.4 */
697 # define DP_DECOMPRESSION_EN (1 << 0)
698 #define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */
700 #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
701 # define DP_PSR_ENABLE BIT(0)
702 # define DP_PSR_MAIN_LINK_ACTIVE BIT(1)
703 # define DP_PSR_CRC_VERIFICATION BIT(2)
704 # define DP_PSR_FRAME_CAPTURE BIT(3)
705 # define DP_PSR_SU_REGION_SCANLINE_CAPTURE BIT(4) /* eDP 1.4a */
706 # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS BIT(5) /* eDP 1.4a */
707 # define DP_PSR_ENABLE_PSR2 BIT(6) /* eDP 1.4a */
709 #define DP_ADAPTER_CTRL 0x1a0
710 # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
712 #define DP_BRANCH_DEVICE_CTRL 0x1a1
713 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
715 #define DP_PAYLOAD_ALLOCATE_SET 0x1c0
716 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
717 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
719 /* Link/Sink Device Status */
720 #define DP_SINK_COUNT 0x200
721 /* prior to 1.2 bit 7 was reserved mbz */
722 # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
723 # define DP_SINK_CP_READY (1 << 6)
725 #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
726 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
727 # define DP_AUTOMATED_TEST_REQUEST (1 << 1)
728 # define DP_CP_IRQ (1 << 2)
729 # define DP_MCCS_IRQ (1 << 3)
730 # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */
731 # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */
732 # define DP_SINK_SPECIFIC_IRQ (1 << 6)
734 #define DP_LANE0_1_STATUS 0x202
735 #define DP_LANE2_3_STATUS 0x203
736 # define DP_LANE_CR_DONE (1 << 0)
737 # define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
738 # define DP_LANE_SYMBOL_LOCKED (1 << 2)
740 #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
741 DP_LANE_CHANNEL_EQ_DONE | \
742 DP_LANE_SYMBOL_LOCKED)
744 #define DP_LANE_ALIGN_STATUS_UPDATED 0x204
745 #define DP_INTERLANE_ALIGN_DONE (1 << 0)
746 #define DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE (1 << 2) /* 2.0 E11 */
747 #define DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE (1 << 3) /* 2.0 E11 */
748 #define DP_128B132B_LT_FAILED (1 << 4) /* 2.0 E11 */
749 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
750 #define DP_LINK_STATUS_UPDATED (1 << 7)
752 #define DP_SINK_STATUS 0x205
753 # define DP_RECEIVE_PORT_0_STATUS (1 << 0)
754 # define DP_RECEIVE_PORT_1_STATUS (1 << 1)
755 # define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */
756 # define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */
758 #define DP_ADJUST_REQUEST_LANE0_1 0x206
759 #define DP_ADJUST_REQUEST_LANE2_3 0x207
760 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
761 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
762 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
763 # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
764 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
765 # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
766 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
767 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
769 /* DP 2.0 128b/132b Link Layer */
770 # define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK (0xf << 0)
771 # define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 0
772 # define DP_ADJUST_TX_FFE_PRESET_LANE1_MASK (0xf << 4)
773 # define DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT 4
775 #define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c
776 # define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03
777 # define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0
778 # define DP_ADJUST_POST_CURSOR2_LANE1_MASK 0x0c
779 # define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT 2
780 # define DP_ADJUST_POST_CURSOR2_LANE2_MASK 0x30
781 # define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT 4
782 # define DP_ADJUST_POST_CURSOR2_LANE3_MASK 0xc0
783 # define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT 6
785 #define DP_TEST_REQUEST 0x218
786 # define DP_TEST_LINK_TRAINING (1 << 0)
787 # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
788 # define DP_TEST_LINK_EDID_READ (1 << 2)
789 # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
790 # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */
791 # define DP_TEST_LINK_AUDIO_PATTERN (1 << 5) /* DPCD >= 1.2 */
792 # define DP_TEST_LINK_AUDIO_DISABLED_VIDEO (1 << 6) /* DPCD >= 1.2 */
794 #define DP_TEST_LINK_RATE 0x219
795 # define DP_LINK_RATE_162 (0x6)
796 # define DP_LINK_RATE_27 (0xa)
798 #define DP_TEST_LANE_COUNT 0x220
800 #define DP_TEST_PATTERN 0x221
801 # define DP_NO_TEST_PATTERN 0x0
802 # define DP_COLOR_RAMP 0x1
803 # define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
804 # define DP_COLOR_SQUARE 0x3
806 #define DP_TEST_H_TOTAL_HI 0x222
807 #define DP_TEST_H_TOTAL_LO 0x223
809 #define DP_TEST_V_TOTAL_HI 0x224
810 #define DP_TEST_V_TOTAL_LO 0x225
812 #define DP_TEST_H_START_HI 0x226
813 #define DP_TEST_H_START_LO 0x227
815 #define DP_TEST_V_START_HI 0x228
816 #define DP_TEST_V_START_LO 0x229
818 #define DP_TEST_HSYNC_HI 0x22A
819 # define DP_TEST_HSYNC_POLARITY (1 << 7)
820 # define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
821 #define DP_TEST_HSYNC_WIDTH_LO 0x22B
823 #define DP_TEST_VSYNC_HI 0x22C
824 # define DP_TEST_VSYNC_POLARITY (1 << 7)
825 # define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
826 #define DP_TEST_VSYNC_WIDTH_LO 0x22D
828 #define DP_TEST_H_WIDTH_HI 0x22E
829 #define DP_TEST_H_WIDTH_LO 0x22F
831 #define DP_TEST_V_HEIGHT_HI 0x230
832 #define DP_TEST_V_HEIGHT_LO 0x231
834 #define DP_TEST_MISC0 0x232
835 # define DP_TEST_SYNC_CLOCK (1 << 0)
836 # define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
837 # define DP_TEST_COLOR_FORMAT_SHIFT 1
838 # define DP_COLOR_FORMAT_RGB (0 << 1)
839 # define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
840 # define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
841 # define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3)
842 # define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3)
843 # define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
844 # define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
845 # define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
846 # define DP_TEST_BIT_DEPTH_MASK (7 << 5)
847 # define DP_TEST_BIT_DEPTH_SHIFT 5
848 # define DP_TEST_BIT_DEPTH_6 (0 << 5)
849 # define DP_TEST_BIT_DEPTH_8 (1 << 5)
850 # define DP_TEST_BIT_DEPTH_10 (2 << 5)
851 # define DP_TEST_BIT_DEPTH_12 (3 << 5)
852 # define DP_TEST_BIT_DEPTH_16 (4 << 5)
854 #define DP_TEST_MISC1 0x233
855 # define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
856 # define DP_TEST_INTERLACED (1 << 1)
858 #define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
860 #define DP_TEST_MISC0 0x232
862 #define DP_TEST_CRC_R_CR 0x240
863 #define DP_TEST_CRC_G_Y 0x242
864 #define DP_TEST_CRC_B_CB 0x244
866 #define DP_TEST_SINK_MISC 0x246
867 # define DP_TEST_CRC_SUPPORTED (1 << 5)
868 # define DP_TEST_COUNT_MASK 0xf
870 #define DP_PHY_TEST_PATTERN 0x248
871 # define DP_PHY_TEST_PATTERN_SEL_MASK 0x7
872 # define DP_PHY_TEST_PATTERN_NONE 0x0
873 # define DP_PHY_TEST_PATTERN_D10_2 0x1
874 # define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2
875 # define DP_PHY_TEST_PATTERN_PRBS7 0x3
876 # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
877 # define DP_PHY_TEST_PATTERN_CP2520 0x5
879 #define DP_PHY_SQUARE_PATTERN 0x249
881 #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
882 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
883 #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
884 #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
885 #define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253
886 #define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254
887 #define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255
888 #define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256
889 #define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257
890 #define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258
891 #define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259
893 #define DP_TEST_RESPONSE 0x260
894 # define DP_TEST_ACK (1 << 0)
895 # define DP_TEST_NAK (1 << 1)
896 # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
898 #define DP_TEST_EDID_CHECKSUM 0x261
900 #define DP_TEST_SINK 0x270
901 # define DP_TEST_SINK_START (1 << 0)
902 #define DP_TEST_AUDIO_MODE 0x271
903 #define DP_TEST_AUDIO_PATTERN_TYPE 0x272
904 #define DP_TEST_AUDIO_PERIOD_CH1 0x273
905 #define DP_TEST_AUDIO_PERIOD_CH2 0x274
906 #define DP_TEST_AUDIO_PERIOD_CH3 0x275
907 #define DP_TEST_AUDIO_PERIOD_CH4 0x276
908 #define DP_TEST_AUDIO_PERIOD_CH5 0x277
909 #define DP_TEST_AUDIO_PERIOD_CH6 0x278
910 #define DP_TEST_AUDIO_PERIOD_CH7 0x279
911 #define DP_TEST_AUDIO_PERIOD_CH8 0x27A
913 #define DP_FEC_STATUS 0x280 /* 1.4 */
914 # define DP_FEC_DECODE_EN_DETECTED (1 << 0)
915 # define DP_FEC_DECODE_DIS_DETECTED (1 << 1)
917 #define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */
919 #define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */
920 # define DP_FEC_ERROR_COUNT_MASK 0x7F
921 # define DP_FEC_ERR_COUNT_VALID (1 << 7)
923 #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
924 # define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
925 # define DP_PAYLOAD_ACT_HANDLED (1 << 1)
927 #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
928 /* up to ID_SLOT_63 at 0x2ff */
930 /* Source Device-specific */
931 #define DP_SOURCE_OUI 0x300
933 /* Sink Device-specific */
934 #define DP_SINK_OUI 0x400
936 /* Branch Device-specific */
937 #define DP_BRANCH_OUI 0x500
938 #define DP_BRANCH_ID 0x503
939 #define DP_BRANCH_REVISION_START 0x509
940 #define DP_BRANCH_HW_REV 0x509
941 #define DP_BRANCH_SW_REV 0x50A
943 /* Link/Sink Device Power Control */
944 #define DP_SET_POWER 0x600
945 # define DP_SET_POWER_D0 0x1
946 # define DP_SET_POWER_D3 0x2
947 # define DP_SET_POWER_MASK 0x3
948 # define DP_SET_POWER_D3_AUX_ON 0x5
951 #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
952 # define DP_EDP_11 0x00
953 # define DP_EDP_12 0x01
954 # define DP_EDP_13 0x02
955 # define DP_EDP_14 0x03
956 # define DP_EDP_14a 0x04 /* eDP 1.4a */
957 # define DP_EDP_14b 0x05 /* eDP 1.4b */
959 #define DP_EDP_GENERAL_CAP_1 0x701
960 # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
961 # define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1)
962 # define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2)
963 # define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3)
964 # define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4)
965 # define DP_EDP_FRC_ENABLE_CAP (1 << 5)
966 # define DP_EDP_COLOR_ENGINE_CAP (1 << 6)
967 # define DP_EDP_SET_POWER_CAP (1 << 7)
969 #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
970 # define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)
971 # define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1)
972 # define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2)
973 # define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3)
974 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4)
975 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5)
976 # define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6)
977 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7)
979 #define DP_EDP_GENERAL_CAP_2 0x703
980 # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
982 #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
983 # define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
984 # define DP_EDP_X_REGION_CAP_SHIFT 0
985 # define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)
986 # define DP_EDP_Y_REGION_CAP_SHIFT 4
988 #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
989 # define DP_EDP_BACKLIGHT_ENABLE (1 << 0)
990 # define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1)
991 # define DP_EDP_FRC_ENABLE (1 << 2)
992 # define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3)
993 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7)
995 #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
996 # define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)
997 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)
998 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)
999 # define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)
1000 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)
1001 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2)
1002 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3)
1003 # define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4)
1004 # define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5)
1005 # define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */
1007 #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
1008 #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
1010 #define DP_EDP_PWMGEN_BIT_COUNT 0x724
1011 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
1012 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
1013 # define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0)
1015 #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
1017 #define DP_EDP_BACKLIGHT_FREQ_SET 0x728
1018 # define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000
1020 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
1021 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
1022 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
1024 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
1025 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
1026 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
1028 #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
1029 #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
1031 #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
1032 #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
1034 #define DP_EDP_MSO_LINK_CAPABILITIES 0x7a4 /* eDP 1.4 */
1035 # define DP_EDP_MSO_NUMBER_OF_LINKS_MASK (7 << 0)
1036 # define DP_EDP_MSO_NUMBER_OF_LINKS_SHIFT 0
1037 # define DP_EDP_MSO_INDEPENDENT_LINK_BIT (1 << 3)
1039 /* Sideband MSG Buffers */
1040 #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
1041 #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
1042 #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
1043 #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
1045 /* DPRX Event Status Indicator */
1046 #define DP_SINK_COUNT_ESI 0x2002 /* same as 0x200 */
1047 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* same as 0x201 */
1049 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
1050 # define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0)
1051 # define DP_LOCK_ACQUISITION_REQUEST (1 << 1)
1052 # define DP_CEC_IRQ (1 << 2)
1054 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
1055 # define RX_CAP_CHANGED (1 << 0)
1056 # define LINK_STATUS_CHANGED (1 << 1)
1057 # define STREAM_STATUS_CHANGED (1 << 2)
1058 # define HDMI_LINK_STATUS_CHANGED (1 << 3)
1059 # define CONNECTED_OFF_ENTRY_REQUESTED (1 << 4)
1061 #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
1062 # define DP_PSR_LINK_CRC_ERROR (1 << 0)
1063 # define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
1064 # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
1066 #define DP_PSR_ESI 0x2007 /* XXX 1.2? */
1067 # define DP_PSR_CAPS_CHANGE (1 << 0)
1069 #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
1070 # define DP_PSR_SINK_INACTIVE 0
1071 # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
1072 # define DP_PSR_SINK_ACTIVE_RFB 2
1073 # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
1074 # define DP_PSR_SINK_ACTIVE_RESYNC 4
1075 # define DP_PSR_SINK_INTERNAL_ERROR 7
1076 # define DP_PSR_SINK_STATE_MASK 0x07
1078 #define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */
1079 # define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0)
1080 # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0
1081 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)
1082 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4
1084 #define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */
1085 # define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */
1086 # define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */
1087 # define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */
1088 # define DP_SU_VALID (1 << 3) /* eDP 1.4 */
1089 # define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */
1090 # define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */
1091 # define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */
1093 #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
1094 # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
1096 #define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */
1097 #define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */
1098 #define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
1099 #define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
1101 /* Extended Receiver Capability: See DP_DPCD_REV for definitions */
1102 #define DP_DP13_DPCD_REV 0x2200
1104 #define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */
1105 # define DP_GTC_CAP (1 << 0) /* DP 1.3 */
1106 # define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */
1107 # define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */
1108 # define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */
1109 # define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */
1110 # define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */
1111 # define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */
1112 # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */
1114 #define DP_128B132B_SUPPORTED_LINK_RATES 0x2215 /* 2.0 */
1115 # define DP_UHBR10 (1 << 0)
1116 # define DP_UHBR20 (1 << 1)
1117 # define DP_UHBR13_5 (1 << 2)
1119 #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */
1120 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT (1 << 7)
1121 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
1122 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US 0x00
1123 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS 0x01
1124 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS 0x02
1125 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS 0x03
1126 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS 0x04
1127 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS 0x05
1128 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS 0x06
1130 #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230
1131 #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250
1133 /* DSC Extended Capability Branch Total DSC Resources */
1134 #define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */
1135 # define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
1136 # define DP_DSC_DECODER_COUNT_SHIFT 5
1137 #define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */
1138 # define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
1139 # define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
1140 # define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
1142 /* Protocol Converter Extension */
1143 /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
1144 #define DP_CEC_TUNNELING_CAPABILITY 0x3000
1145 # define DP_CEC_TUNNELING_CAPABLE (1 << 0)
1146 # define DP_CEC_SNOOPING_CAPABLE (1 << 1)
1147 # define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2)
1149 #define DP_CEC_TUNNELING_CONTROL 0x3001
1150 # define DP_CEC_TUNNELING_ENABLE (1 << 0)
1151 # define DP_CEC_SNOOPING_ENABLE (1 << 1)
1153 #define DP_CEC_RX_MESSAGE_INFO 0x3002
1154 # define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
1155 # define DP_CEC_RX_MESSAGE_LEN_SHIFT 0
1156 # define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4)
1157 # define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5)
1158 # define DP_CEC_RX_MESSAGE_ACKED (1 << 6)
1159 # define DP_CEC_RX_MESSAGE_ENDED (1 << 7)
1161 #define DP_CEC_TX_MESSAGE_INFO 0x3003
1162 # define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
1163 # define DP_CEC_TX_MESSAGE_LEN_SHIFT 0
1164 # define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
1165 # define DP_CEC_TX_RETRY_COUNT_SHIFT 4
1166 # define DP_CEC_TX_MESSAGE_SEND (1 << 7)
1168 #define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004
1169 # define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0)
1170 # define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1)
1171 # define DP_CEC_TX_MESSAGE_SENT (1 << 4)
1172 # define DP_CEC_TX_LINE_ERROR (1 << 5)
1173 # define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6)
1174 # define DP_CEC_TX_DATA_NACK_ERROR (1 << 7)
1176 #define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */
1177 # define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0)
1178 # define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1)
1179 # define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2)
1180 # define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3)
1181 # define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4)
1182 # define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5)
1183 # define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6)
1184 # define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7)
1185 #define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */
1186 # define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0)
1187 # define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1)
1188 # define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2)
1189 # define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3)
1190 # define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4)
1191 # define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5)
1192 # define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6)
1193 # define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7)
1195 #define DP_CEC_RX_MESSAGE_BUFFER 0x3010
1196 #define DP_CEC_TX_MESSAGE_BUFFER 0x3020
1197 #define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
1199 /* PCON CONFIGURE-1 FRL FOR HDMI SINK */
1200 #define DP_PCON_HDMI_LINK_CONFIG_1 0x305A
1201 # define DP_PCON_ENABLE_MAX_FRL_BW (7 << 0)
1202 # define DP_PCON_ENABLE_MAX_BW_0GBPS 0
1203 # define DP_PCON_ENABLE_MAX_BW_9GBPS 1
1204 # define DP_PCON_ENABLE_MAX_BW_18GBPS 2
1205 # define DP_PCON_ENABLE_MAX_BW_24GBPS 3
1206 # define DP_PCON_ENABLE_MAX_BW_32GBPS 4
1207 # define DP_PCON_ENABLE_MAX_BW_40GBPS 5
1208 # define DP_PCON_ENABLE_MAX_BW_48GBPS 6
1209 # define DP_PCON_ENABLE_SOURCE_CTL_MODE (1 << 3)
1210 # define DP_PCON_ENABLE_CONCURRENT_LINK (1 << 4)
1211 # define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4)
1212 # define DP_PCON_ENABLE_LINK_FRL_MODE (1 << 5)
1213 # define DP_PCON_ENABLE_HPD_READY (1 << 6)
1214 # define DP_PCON_ENABLE_HDMI_LINK (1 << 7)
1216 /* PCON CONFIGURE-2 FRL FOR HDMI SINK */
1217 #define DP_PCON_HDMI_LINK_CONFIG_2 0x305B
1218 # define DP_PCON_MAX_LINK_BW_MASK (0x3F << 0)
1219 # define DP_PCON_FRL_BW_MASK_9GBPS (1 << 0)
1220 # define DP_PCON_FRL_BW_MASK_18GBPS (1 << 1)
1221 # define DP_PCON_FRL_BW_MASK_24GBPS (1 << 2)
1222 # define DP_PCON_FRL_BW_MASK_32GBPS (1 << 3)
1223 # define DP_PCON_FRL_BW_MASK_40GBPS (1 << 4)
1224 # define DP_PCON_FRL_BW_MASK_48GBPS (1 << 5)
1225 # define DP_PCON_FRL_LINK_TRAIN_EXTENDED (1 << 6)
1226 # define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6)
1228 /* PCON HDMI LINK STATUS */
1229 #define DP_PCON_HDMI_TX_LINK_STATUS 0x303B
1230 # define DP_PCON_HDMI_TX_LINK_ACTIVE (1 << 0)
1231 # define DP_PCON_FRL_READY (1 << 1)
1233 /* PCON HDMI POST FRL STATUS */
1234 #define DP_PCON_HDMI_POST_FRL_STATUS 0x3036
1235 # define DP_PCON_HDMI_LINK_MODE (1 << 0)
1236 # define DP_PCON_HDMI_MODE_TMDS 0
1237 # define DP_PCON_HDMI_MODE_FRL 1
1238 # define DP_PCON_HDMI_FRL_TRAINED_BW (0x3F << 1)
1239 # define DP_PCON_FRL_TRAINED_BW_9GBPS (1 << 1)
1240 # define DP_PCON_FRL_TRAINED_BW_18GBPS (1 << 2)
1241 # define DP_PCON_FRL_TRAINED_BW_24GBPS (1 << 3)
1242 # define DP_PCON_FRL_TRAINED_BW_32GBPS (1 << 4)
1243 # define DP_PCON_FRL_TRAINED_BW_40GBPS (1 << 5)
1244 # define DP_PCON_FRL_TRAINED_BW_48GBPS (1 << 6)
1246 #define DP_PROTOCOL_CONVERTER_CONTROL_0 0x3050 /* DP 1.3 */
1247 # define DP_HDMI_DVI_OUTPUT_CONFIG (1 << 0) /* DP 1.3 */
1248 #define DP_PROTOCOL_CONVERTER_CONTROL_1 0x3051 /* DP 1.3 */
1249 # define DP_CONVERSION_TO_YCBCR420_ENABLE (1 << 0) /* DP 1.3 */
1250 # define DP_HDMI_EDID_PROCESSING_DISABLE (1 << 1) /* DP 1.4 */
1251 # define DP_HDMI_AUTONOMOUS_SCRAMBLING_DISABLE (1 << 2) /* DP 1.4 */
1252 # define DP_HDMI_FORCE_SCRAMBLING (1 << 3) /* DP 1.4 */
1253 #define DP_PROTOCOL_CONVERTER_CONTROL_2 0x3052 /* DP 1.3 */
1254 # define DP_CONVERSION_TO_YCBCR422_ENABLE (1 << 0) /* DP 1.3 */
1255 # define DP_PCON_ENABLE_DSC_ENCODER (1 << 1)
1256 # define DP_PCON_ENCODER_PPS_OVERRIDE_MASK (0x3 << 2)
1257 # define DP_PCON_ENC_PPS_OVERRIDE_DISABLED 0
1258 # define DP_PCON_ENC_PPS_OVERRIDE_EN_PARAMS 1
1259 # define DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER 2
1260 # define DP_CONVERSION_RGB_YCBCR_MASK (7 << 4)
1261 # define DP_CONVERSION_BT601_RGB_YCBCR_ENABLE (1 << 4)
1262 # define DP_CONVERSION_BT709_RGB_YCBCR_ENABLE (1 << 5)
1263 # define DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE (1 << 6)
1265 /* PCON Downstream HDMI ERROR Status per Lane */
1266 #define DP_PCON_HDMI_ERROR_STATUS_LN0 0x3037
1267 #define DP_PCON_HDMI_ERROR_STATUS_LN1 0x3038
1268 #define DP_PCON_HDMI_ERROR_STATUS_LN2 0x3039
1269 #define DP_PCON_HDMI_ERROR_STATUS_LN3 0x303A
1270 # define DP_PCON_HDMI_ERROR_COUNT_MASK (0x7 << 0)
1271 # define DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS (1 << 0)
1272 # define DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS (1 << 1)
1273 # define DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS (1 << 2)
1275 /* PCON HDMI CONFIG PPS Override Buffer
1276 * Valid Offsets to be added to Base : 0-127
1278 #define DP_PCON_HDMI_PPS_OVERRIDE_BASE 0x3100
1280 /* PCON HDMI CONFIG PPS Override Parameter: Slice height
1281 * Offset-0 8LSBs of the Slice height.
1282 * Offset-1 8MSBs of the Slice height.
1284 #define DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT 0x3180
1286 /* PCON HDMI CONFIG PPS Override Parameter: Slice width
1287 * Offset-0 8LSBs of the Slice width.
1288 * Offset-1 8MSBs of the Slice width.
1290 #define DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH 0x3182
1292 /* PCON HDMI CONFIG PPS Override Parameter: bits_per_pixel
1293 * Offset-0 8LSBs of the bits_per_pixel.
1294 * Offset-1 2MSBs of the bits_per_pixel.
1296 #define DP_PCON_HDMI_PPS_OVRD_BPP 0x3184
1298 /* HDCP 1.3 and HDCP 2.2 */
1299 #define DP_AUX_HDCP_BKSV 0x68000
1300 #define DP_AUX_HDCP_RI_PRIME 0x68005
1301 #define DP_AUX_HDCP_AKSV 0x68007
1302 #define DP_AUX_HDCP_AN 0x6800C
1303 #define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4)
1304 #define DP_AUX_HDCP_BCAPS 0x68028
1305 # define DP_BCAPS_REPEATER_PRESENT BIT(1)
1306 # define DP_BCAPS_HDCP_CAPABLE BIT(0)
1307 #define DP_AUX_HDCP_BSTATUS 0x68029
1308 # define DP_BSTATUS_REAUTH_REQ BIT(3)
1309 # define DP_BSTATUS_LINK_FAILURE BIT(2)
1310 # define DP_BSTATUS_R0_PRIME_READY BIT(1)
1311 # define DP_BSTATUS_READY BIT(0)
1312 #define DP_AUX_HDCP_BINFO 0x6802A
1313 #define DP_AUX_HDCP_KSV_FIFO 0x6802C
1314 #define DP_AUX_HDCP_AINFO 0x6803B
1316 /* DP HDCP2.2 parameter offsets in DPCD address space */
1317 #define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000
1318 #define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008
1319 #define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B
1320 #define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215
1321 #define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D
1322 #define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220
1323 #define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0
1324 #define DP_HDCP_2_2_REG_M_OFFSET 0x692B0
1325 #define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0
1326 #define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0
1327 #define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0
1328 #define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8
1329 #define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318
1330 #define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328
1331 #define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330
1332 #define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332
1333 #define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335
1334 #define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345
1335 #define DP_HDCP_2_2_REG_V_OFFSET 0x693E0
1336 #define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0
1337 #define DP_HDCP_2_2_REG_K_OFFSET 0x693F3
1338 #define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5
1339 #define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473
1340 #define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493
1341 #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
1342 #define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
1344 /* LTTPR: Link Training (LT)-tunable PHY Repeaters */
1345 #define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
1346 #define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */
1347 #define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */
1348 #define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */
1349 #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
1350 #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
1351 #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
1352 #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
1353 # define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0)
1354 /* See DP_128B132B_SUPPORTED_LINK_RATES for values */
1355 #define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */
1356 #define DP_PHY_REPEATER_EQ_DONE 0xf0008 /* 2.0 E11 */
1370 DP_MAX_LTTPR_COUNT = DP_PHY_LTTPR8,
1373 #define DP_PHY_LTTPR(i) (DP_PHY_LTTPR1 + (i))
1375 #define __DP_LTTPR1_BASE 0xf0010 /* 1.3 */
1376 #define __DP_LTTPR2_BASE 0xf0060 /* 1.3 */
1377 #define DP_LTTPR_BASE(dp_phy) \
1378 (__DP_LTTPR1_BASE + (__DP_LTTPR2_BASE - __DP_LTTPR1_BASE) * \
1379 ((dp_phy) - DP_PHY_LTTPR1))
1381 #define DP_LTTPR_REG(dp_phy, lttpr1_reg) \
1382 (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg))
1384 #define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */
1385 #define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \
1386 DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1)
1388 #define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */
1389 #define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \
1390 DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1)
1392 #define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */
1393 #define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */
1394 #define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */
1395 #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */
1396 #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \
1397 DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
1399 #define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */
1400 # define DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED BIT(0)
1401 # define DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED BIT(1)
1403 #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0022 /* 2.0 */
1404 #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \
1405 DP_LTTPR_REG(dp_phy, DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
1406 /* see DP_128B132B_TRAINING_AUX_RD_INTERVAL for values */
1408 #define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */
1409 #define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) \
1410 DP_LTTPR_REG(dp_phy, DP_LANE0_1_STATUS_PHY_REPEATER1)
1412 #define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */
1414 #define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */
1415 #define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */
1416 #define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */
1417 #define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */
1418 #define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */
1419 #define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */
1420 #define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */
1422 #define __DP_FEC1_BASE 0xf0290 /* 1.4 */
1423 #define __DP_FEC2_BASE 0xf0298 /* 1.4 */
1424 #define DP_FEC_BASE(dp_phy) \
1425 (__DP_FEC1_BASE + ((__DP_FEC2_BASE - __DP_FEC1_BASE) * \
1426 ((dp_phy) - DP_PHY_LTTPR1)))
1428 #define DP_FEC_REG(dp_phy, fec1_reg) \
1429 (DP_FEC_BASE(dp_phy) - DP_FEC_BASE(DP_PHY_LTTPR1) + fec1_reg)
1431 #define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */
1432 #define DP_FEC_STATUS_PHY_REPEATER(dp_phy) \
1433 DP_FEC_REG(dp_phy, DP_FEC_STATUS_PHY_REPEATER1)
1435 #define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291 /* 1.4 */
1436 #define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */
1438 #define DP_LTTPR_MAX_ADD 0xf02ff /* 1.4 */
1440 #define DP_DPCD_MAX_ADD 0xfffff /* 1.4 */
1442 /* Repeater modes */
1443 #define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */
1444 #define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */
1446 /* DP HDCP message start offsets in DPCD address space */
1447 #define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET
1448 #define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET
1449 #define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
1450 #define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET
1451 #define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET
1452 #define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \
1453 DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
1454 #define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET
1455 #define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET
1456 #define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
1457 #define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET
1458 #define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET
1459 #define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
1460 #define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET
1462 #define HDCP_2_2_DP_RXSTATUS_LEN 1
1463 #define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0))
1464 #define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1))
1465 #define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2))
1466 #define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
1467 #define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4))
1469 /* DP 1.2 Sideband message defines */
1470 /* peer device type - DP 1.2a Table 2-92 */
1471 #define DP_PEER_DEVICE_NONE 0x0
1472 #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
1473 #define DP_PEER_DEVICE_MST_BRANCHING 0x2
1474 #define DP_PEER_DEVICE_SST_SINK 0x3
1475 #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
1477 /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
1478 #define DP_GET_MSG_TRANSACTION_VERSION 0x00 /* DP 1.3 */
1479 #define DP_LINK_ADDRESS 0x01
1480 #define DP_CONNECTION_STATUS_NOTIFY 0x02
1481 #define DP_ENUM_PATH_RESOURCES 0x10
1482 #define DP_ALLOCATE_PAYLOAD 0x11
1483 #define DP_QUERY_PAYLOAD 0x12
1484 #define DP_RESOURCE_STATUS_NOTIFY 0x13
1485 #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
1486 #define DP_REMOTE_DPCD_READ 0x20
1487 #define DP_REMOTE_DPCD_WRITE 0x21
1488 #define DP_REMOTE_I2C_READ 0x22
1489 #define DP_REMOTE_I2C_WRITE 0x23
1490 #define DP_POWER_UP_PHY 0x24
1491 #define DP_POWER_DOWN_PHY 0x25
1492 #define DP_SINK_EVENT_NOTIFY 0x30
1493 #define DP_QUERY_STREAM_ENC_STATUS 0x38
1494 #define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 0
1495 #define DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE 1
1496 #define DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE 2
1498 /* DP 1.2 MST sideband reply types */
1499 #define DP_SIDEBAND_REPLY_ACK 0x00
1500 #define DP_SIDEBAND_REPLY_NAK 0x01
1502 /* DP 1.2 MST sideband nak reasons - table 2.84 */
1503 #define DP_NAK_WRITE_FAILURE 0x01
1504 #define DP_NAK_INVALID_READ 0x02
1505 #define DP_NAK_CRC_FAILURE 0x03
1506 #define DP_NAK_BAD_PARAM 0x04
1507 #define DP_NAK_DEFER 0x05
1508 #define DP_NAK_LINK_FAILURE 0x06
1509 #define DP_NAK_NO_RESOURCES 0x07
1510 #define DP_NAK_DPCD_FAIL 0x08
1511 #define DP_NAK_I2C_NAK 0x09
1512 #define DP_NAK_ALLOCATE_FAIL 0x0a
1514 #define MODE_I2C_START 1
1515 #define MODE_I2C_WRITE 2
1516 #define MODE_I2C_READ 4
1517 #define MODE_I2C_STOP 8
1519 /* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */
1520 #define DP_MST_PHYSICAL_PORT_0 0
1521 #define DP_MST_LOGICAL_PORT_0 8
1523 #define DP_LINK_CONSTANT_N_VALUE 0x8000
1524 #define DP_LINK_STATUS_SIZE 6
1525 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
1527 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
1529 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
1531 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
1533 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
1536 #define DP_BRANCH_OUI_HEADER_SIZE 0xc
1537 #define DP_RECEIVER_CAP_SIZE 0xf
1538 #define DP_DSC_RECEIVER_CAP_SIZE 0xf
1539 #define EDP_PSR_RECEIVER_CAP_SIZE 2
1540 #define EDP_DISPLAY_CTL_CAP_SIZE 3
1541 #define DP_LTTPR_COMMON_CAP_SIZE 8
1542 #define DP_LTTPR_PHY_CAP_SIZE 3
1544 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1545 enum drm_dp_phy dp_phy, bool uhbr);
1546 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1547 enum drm_dp_phy dp_phy, bool uhbr);
1549 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
1550 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1551 void drm_dp_lttpr_link_train_clock_recovery_delay(void);
1552 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
1553 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1554 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
1555 const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
1557 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux);
1558 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],
1560 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],
1562 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
1563 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
1564 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]);
1566 u8 drm_dp_link_rate_to_bw_code(int link_rate);
1567 int drm_dp_bw_code_to_link_rate(u8 link_bw);
1569 #define DP_SDP_AUDIO_TIMESTAMP 0x01
1570 #define DP_SDP_AUDIO_STREAM 0x02
1571 #define DP_SDP_EXTENSION 0x04 /* DP 1.1 */
1572 #define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */
1573 #define DP_SDP_ISRC 0x06 /* DP 1.2 */
1574 #define DP_SDP_VSC 0x07 /* DP 1.2 */
1575 #define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */
1576 #define DP_SDP_PPS 0x10 /* DP 1.4 */
1577 #define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */
1578 #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */
1579 /* 0x80+ CEA-861 infoframe types */
1582 * struct dp_sdp_header - DP secondary data packet header
1583 * @HB0: Secondary Data Packet ID
1584 * @HB1: Secondary Data Packet Type
1585 * @HB2: Secondary Data Packet Specific header, Byte 0
1586 * @HB3: Secondary Data packet Specific header, Byte 1
1588 struct dp_sdp_header {
1595 #define EDP_SDP_HEADER_REVISION_MASK 0x1F
1596 #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
1597 #define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
1600 * struct dp_sdp - DP secondary data packet
1601 * @sdp_header: DP secondary data packet header
1602 * @db: DP secondaray data packet data blocks
1603 * VSC SDP Payload for PSR
1604 * db[0]: Stereo Interface
1605 * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid
1606 * db[2]: CRC value bits 7:0 of the R or Cr component
1607 * db[3]: CRC value bits 15:8 of the R or Cr component
1608 * db[4]: CRC value bits 7:0 of the G or Y component
1609 * db[5]: CRC value bits 15:8 of the G or Y component
1610 * db[6]: CRC value bits 7:0 of the B or Cb component
1611 * db[7]: CRC value bits 15:8 of the B or Cb component
1612 * db[8] - db[31]: Reserved
1613 * VSC SDP Payload for Pixel Encoding/Colorimetry Format
1614 * db[0] - db[15]: Reserved
1615 * db[16]: Pixel Encoding and Colorimetry Formats
1616 * db[17]: Dynamic Range and Component Bit Depth
1617 * db[18]: Content Type
1618 * db[19] - db[31]: Reserved
1621 struct dp_sdp_header sdp_header;
1625 #define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
1626 #define EDP_VSC_PSR_UPDATE_RFB (1<<1)
1627 #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
1630 * enum dp_pixelformat - drm DP Pixel encoding formats
1632 * This enum is used to indicate DP VSC SDP Pixel encoding formats.
1633 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1636 * @DP_PIXELFORMAT_RGB: RGB pixel encoding format
1637 * @DP_PIXELFORMAT_YUV444: YCbCr 4:4:4 pixel encoding format
1638 * @DP_PIXELFORMAT_YUV422: YCbCr 4:2:2 pixel encoding format
1639 * @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format
1640 * @DP_PIXELFORMAT_Y_ONLY: Y Only pixel encoding format
1641 * @DP_PIXELFORMAT_RAW: RAW pixel encoding format
1642 * @DP_PIXELFORMAT_RESERVED: Reserved pixel encoding format
1644 enum dp_pixelformat {
1645 DP_PIXELFORMAT_RGB = 0,
1646 DP_PIXELFORMAT_YUV444 = 0x1,
1647 DP_PIXELFORMAT_YUV422 = 0x2,
1648 DP_PIXELFORMAT_YUV420 = 0x3,
1649 DP_PIXELFORMAT_Y_ONLY = 0x4,
1650 DP_PIXELFORMAT_RAW = 0x5,
1651 DP_PIXELFORMAT_RESERVED = 0x6,
1655 * enum dp_colorimetry - drm DP Colorimetry formats
1657 * This enum is used to indicate DP VSC SDP Colorimetry formats.
1658 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1659 * DB18] and a name of enum member follows DRM_MODE_COLORIMETRY definition.
1661 * @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or
1662 * ITU-R BT.601 colorimetry format
1663 * @DP_COLORIMETRY_RGB_WIDE_FIXED: RGB wide gamut fixed point colorimetry format
1664 * @DP_COLORIMETRY_BT709_YCC: ITU-R BT.709 colorimetry format
1665 * @DP_COLORIMETRY_RGB_WIDE_FLOAT: RGB wide gamut floating point
1666 * (scRGB (IEC 61966-2-2)) colorimetry format
1667 * @DP_COLORIMETRY_XVYCC_601: xvYCC601 colorimetry format
1668 * @DP_COLORIMETRY_OPRGB: OpRGB colorimetry format
1669 * @DP_COLORIMETRY_XVYCC_709: xvYCC709 colorimetry format
1670 * @DP_COLORIMETRY_DCI_P3_RGB: DCI-P3 (SMPTE RP 431-2) colorimetry format
1671 * @DP_COLORIMETRY_SYCC_601: sYCC601 colorimetry format
1672 * @DP_COLORIMETRY_RGB_CUSTOM: RGB Custom Color Profile colorimetry format
1673 * @DP_COLORIMETRY_OPYCC_601: opYCC601 colorimetry format
1674 * @DP_COLORIMETRY_BT2020_RGB: ITU-R BT.2020 R' G' B' colorimetry format
1675 * @DP_COLORIMETRY_BT2020_CYCC: ITU-R BT.2020 Y'c C'bc C'rc colorimetry format
1676 * @DP_COLORIMETRY_BT2020_YCC: ITU-R BT.2020 Y' C'b C'r colorimetry format
1678 enum dp_colorimetry {
1679 DP_COLORIMETRY_DEFAULT = 0,
1680 DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
1681 DP_COLORIMETRY_BT709_YCC = 0x1,
1682 DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
1683 DP_COLORIMETRY_XVYCC_601 = 0x2,
1684 DP_COLORIMETRY_OPRGB = 0x3,
1685 DP_COLORIMETRY_XVYCC_709 = 0x3,
1686 DP_COLORIMETRY_DCI_P3_RGB = 0x4,
1687 DP_COLORIMETRY_SYCC_601 = 0x4,
1688 DP_COLORIMETRY_RGB_CUSTOM = 0x5,
1689 DP_COLORIMETRY_OPYCC_601 = 0x5,
1690 DP_COLORIMETRY_BT2020_RGB = 0x6,
1691 DP_COLORIMETRY_BT2020_CYCC = 0x6,
1692 DP_COLORIMETRY_BT2020_YCC = 0x7,
1696 * enum dp_dynamic_range - drm DP Dynamic Range
1698 * This enum is used to indicate DP VSC SDP Dynamic Range.
1699 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1702 * @DP_DYNAMIC_RANGE_VESA: VESA range
1703 * @DP_DYNAMIC_RANGE_CTA: CTA range
1705 enum dp_dynamic_range {
1706 DP_DYNAMIC_RANGE_VESA = 0,
1707 DP_DYNAMIC_RANGE_CTA = 1,
1711 * enum dp_content_type - drm DP Content Type
1713 * This enum is used to indicate DP VSC SDP Content Types.
1714 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1716 * CTA-861-G defines content types and expected processing by a sink device
1718 * @DP_CONTENT_TYPE_NOT_DEFINED: Not defined type
1719 * @DP_CONTENT_TYPE_GRAPHICS: Graphics type
1720 * @DP_CONTENT_TYPE_PHOTO: Photo type
1721 * @DP_CONTENT_TYPE_VIDEO: Video type
1722 * @DP_CONTENT_TYPE_GAME: Game type
1724 enum dp_content_type {
1725 DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
1726 DP_CONTENT_TYPE_GRAPHICS = 0x01,
1727 DP_CONTENT_TYPE_PHOTO = 0x02,
1728 DP_CONTENT_TYPE_VIDEO = 0x03,
1729 DP_CONTENT_TYPE_GAME = 0x04,
1733 * struct drm_dp_vsc_sdp - drm DP VSC SDP
1735 * This structure represents a DP VSC SDP of drm
1736 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
1737 * [Table 2-117: VSC SDP Payload for DB16 through DB18]
1739 * @sdp_type: secondary-data packet type
1740 * @revision: revision number
1741 * @length: number of valid data bytes
1742 * @pixelformat: pixel encoding format
1743 * @colorimetry: colorimetry format
1744 * @bpc: bit per color
1745 * @dynamic_range: dynamic range information
1746 * @content_type: CTA-861-G defines content types and expected processing by a sink device
1748 struct drm_dp_vsc_sdp {
1749 unsigned char sdp_type;
1750 unsigned char revision;
1751 unsigned char length;
1752 enum dp_pixelformat pixelformat;
1753 enum dp_colorimetry colorimetry;
1755 enum dp_dynamic_range dynamic_range;
1756 enum dp_content_type content_type;
1759 void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
1760 const struct drm_dp_vsc_sdp *vsc);
1762 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
1765 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1767 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
1771 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1773 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
1777 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1779 return dpcd[DP_DPCD_REV] >= 0x11 &&
1780 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
1784 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1786 return dpcd[DP_DPCD_REV] >= 0x11 &&
1787 (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
1791 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1793 return dpcd[DP_DPCD_REV] >= 0x12 &&
1794 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
1798 drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1800 return dpcd[DP_DPCD_REV] >= 0x11 ||
1801 dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5;
1805 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1807 return dpcd[DP_DPCD_REV] >= 0x14 &&
1808 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
1812 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1814 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
1815 DP_TRAINING_PATTERN_MASK;
1819 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1821 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
1824 /* DP/eDP DSC support */
1825 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
1827 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
1828 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
1832 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1834 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
1835 DP_DSC_DECOMPRESSION_IS_SUPPORTED;
1839 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1841 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
1842 (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
1843 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK <<
1844 DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT);
1848 drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1850 /* Max Slicewidth = Number of Pixels * 320 */
1851 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
1852 DP_DSC_SLICE_WIDTH_MULTIPLIER;
1855 /* Forward Error Correction Support on DP 1.4 */
1857 drm_dp_sink_supports_fec(const u8 fec_capable)
1859 return fec_capable & DP_FEC_CAPABLE;
1863 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1865 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
1869 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1871 return dpcd[DP_EDP_CONFIGURATION_CAP] &
1872 DP_ALTERNATE_SCRAMBLER_RESET_CAP;
1875 /* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
1877 drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1879 return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
1880 DP_MSA_TIMING_PAR_IGNORED;
1884 * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support
1885 * @edp_dpcd: The DPCD to check
1887 * Note that currently this function will return %false for panels which support various DPCD
1888 * backlight features but which require the brightness be set through PWM, and don't support setting
1889 * the brightness level via the DPCD.
1891 * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
1895 drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
1897 return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP);
1901 * DisplayPort AUX channel
1905 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
1906 * @address: address of the (first) register to access
1907 * @request: contains the type of transaction (see DP_AUX_* macros)
1908 * @reply: upon completion, contains the reply type of the transaction
1909 * @buffer: pointer to a transmission or reception buffer
1910 * @size: size of @buffer
1912 struct drm_dp_aux_msg {
1913 unsigned int address;
1922 struct drm_connector;
1925 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
1926 * @lock: mutex protecting this struct
1927 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
1928 * @connector: the connector this CEC adapter is associated with
1929 * @unregister_work: unregister the CEC adapter
1931 struct drm_dp_aux_cec {
1933 struct cec_adapter *adap;
1934 struct drm_connector *connector;
1935 struct delayed_work unregister_work;
1939 * struct drm_dp_aux - DisplayPort AUX channel
1941 * An AUX channel can also be used to transport I2C messages to a sink. A
1942 * typical application of that is to access an EDID that's present in the sink
1943 * device. The @transfer() function can also be used to execute such
1944 * transactions. The drm_dp_aux_register() function registers an I2C adapter
1945 * that can be passed to drm_probe_ddc(). Upon removal, drivers should call
1946 * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long
1947 * transfers by default; if a partial response is received, the adapter will
1948 * drop down to the size given by the partial response for this transaction
1953 * @name: user-visible name of this AUX channel and the
1954 * I2C-over-AUX adapter.
1956 * It's also used to specify the name of the I2C adapter. If set
1957 * to %NULL, dev_name() of @dev will be used.
1962 * @ddc: I2C adapter that can be used for I2C-over-AUX
1965 struct i2c_adapter ddc;
1968 * @dev: pointer to struct device that is the parent for this
1974 * @drm_dev: pointer to the &drm_device that owns this AUX channel.
1975 * Beware, this may be %NULL before drm_dp_aux_register() has been
1978 * It should be set to the &drm_device that will be using this AUX
1979 * channel as early as possible. For many graphics drivers this should
1980 * happen before drm_dp_aux_init(), however it's perfectly fine to set
1981 * this field later so long as it's assigned before calling
1982 * drm_dp_aux_register().
1984 struct drm_device *drm_dev;
1987 * @crtc: backpointer to the crtc that is currently using this
1990 struct drm_crtc *crtc;
1993 * @hw_mutex: internal mutex used for locking transfers.
1995 * Note that if the underlying hardware is shared among multiple
1996 * channels, the driver needs to do additional locking to
1997 * prevent concurrent access.
1999 struct mutex hw_mutex;
2002 * @crc_work: worker that captures CRCs for each frame
2004 struct work_struct crc_work;
2007 * @crc_count: counter of captured frame CRCs
2012 * @transfer: transfers a message representing a single AUX
2015 * This is a hardware-specific implementation of how
2016 * transactions are executed that the drivers must provide.
2018 * A pointer to a &drm_dp_aux_msg structure describing the
2019 * transaction is passed into this function. Upon success, the
2020 * implementation should return the number of payload bytes that
2021 * were transferred, or a negative error-code on failure.
2023 * Helpers will propagate these errors, with the exception of
2024 * the %-EBUSY error, which causes a transaction to be retried.
2025 * On a short, helpers will return %-EPROTO to make it simpler
2026 * to check for failure.
2028 * The @transfer() function must only modify the reply field of
2029 * the &drm_dp_aux_msg structure. The retry logic and i2c
2030 * helpers assume this is the case.
2032 * Also note that this callback can be called no matter the
2033 * state @dev is in. Drivers that need that device to be powered
2034 * to perform this operation will first need to make sure it's
2035 * been properly enabled.
2037 ssize_t (*transfer)(struct drm_dp_aux *aux,
2038 struct drm_dp_aux_msg *msg);
2041 * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
2043 unsigned i2c_nack_count;
2045 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
2047 unsigned i2c_defer_count;
2049 * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
2051 struct drm_dp_aux_cec cec;
2053 * @is_remote: Is this AUX CH actually using sideband messaging.
2058 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset);
2059 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
2060 void *buffer, size_t size);
2061 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
2062 void *buffer, size_t size);
2065 * drm_dp_dpcd_readb() - read a single byte from the DPCD
2066 * @aux: DisplayPort AUX channel
2067 * @offset: address of the register to read
2068 * @valuep: location where the value of the register will be stored
2070 * Returns the number of bytes transferred (1) on success, or a negative
2071 * error code on failure.
2073 static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
2074 unsigned int offset, u8 *valuep)
2076 return drm_dp_dpcd_read(aux, offset, valuep, 1);
2080 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
2081 * @aux: DisplayPort AUX channel
2082 * @offset: address of the register to write
2083 * @value: value to write to the register
2085 * Returns the number of bytes transferred (1) on success, or a negative
2086 * error code on failure.
2088 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
2089 unsigned int offset, u8 value)
2091 return drm_dp_dpcd_write(aux, offset, &value, 1);
2094 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
2095 u8 dpcd[DP_RECEIVER_CAP_SIZE]);
2097 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
2098 u8 status[DP_LINK_STATUS_SIZE]);
2100 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
2101 enum drm_dp_phy dp_phy,
2102 u8 link_status[DP_LINK_STATUS_SIZE]);
2104 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
2105 u8 real_edid_checksum);
2107 int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
2108 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2109 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]);
2110 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2111 const u8 port_cap[4], u8 type);
2112 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2113 const u8 port_cap[4],
2114 const struct edid *edid);
2115 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2116 const u8 port_cap[4]);
2117 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2118 const u8 port_cap[4],
2119 const struct edid *edid);
2120 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2121 const u8 port_cap[4],
2122 const struct edid *edid);
2123 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2124 const u8 port_cap[4],
2125 const struct edid *edid);
2126 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2127 const u8 port_cap[4]);
2128 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2129 const u8 port_cap[4]);
2130 struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
2131 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2132 const u8 port_cap[4]);
2133 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
2134 void drm_dp_downstream_debug(struct seq_file *m,
2135 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2136 const u8 port_cap[4],
2137 const struct edid *edid,
2138 struct drm_dp_aux *aux);
2139 enum drm_mode_subconnector
2140 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2141 const u8 port_cap[4]);
2142 void drm_dp_set_subconnector_property(struct drm_connector *connector,
2143 enum drm_connector_status status,
2145 const u8 port_cap[4]);
2148 bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
2149 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2150 const struct drm_dp_desc *desc);
2151 int drm_dp_read_sink_count(struct drm_dp_aux *aux);
2153 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
2154 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2155 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
2156 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
2157 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2158 enum drm_dp_phy dp_phy,
2159 u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
2160 int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
2161 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
2162 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
2163 bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
2164 bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
2166 void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
2167 void drm_dp_aux_init(struct drm_dp_aux *aux);
2168 int drm_dp_aux_register(struct drm_dp_aux *aux);
2169 void drm_dp_aux_unregister(struct drm_dp_aux *aux);
2171 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
2172 int drm_dp_stop_crc(struct drm_dp_aux *aux);
2174 struct drm_dp_dpcd_ident {
2183 * struct drm_dp_desc - DP branch/sink device descriptor
2184 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
2185 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
2187 struct drm_dp_desc {
2188 struct drm_dp_dpcd_ident ident;
2192 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
2196 * enum drm_dp_quirk - Display Port sink/branch device specific quirks
2198 * Display Port sink and branch devices in the wild have a variety of bugs, try
2199 * to collect them here. The quirks are shared, but it's up to the drivers to
2200 * implement workarounds for them.
2204 * @DP_DPCD_QUIRK_CONSTANT_N:
2206 * The device requires main link attributes Mvid and Nvid to be limited
2207 * to 16 bits. So will give a constant value (0x8000) for compatability.
2209 DP_DPCD_QUIRK_CONSTANT_N,
2211 * @DP_DPCD_QUIRK_NO_PSR:
2213 * The device does not support PSR even if reports that it supports or
2214 * driver still need to implement proper handling for such device.
2216 DP_DPCD_QUIRK_NO_PSR,
2218 * @DP_DPCD_QUIRK_NO_SINK_COUNT:
2220 * The device does not set SINK_COUNT to a non-zero value.
2221 * The driver should ignore SINK_COUNT during detection. Note that
2222 * drm_dp_read_sink_count_cap() automatically checks for this quirk.
2224 DP_DPCD_QUIRK_NO_SINK_COUNT,
2226 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
2228 * The device supports MST DSC despite not supporting Virtual DPCD.
2229 * The DSC caps can be read from the physical aux instead.
2231 DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
2233 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS:
2235 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite
2236 * the DP_MAX_LINK_RATE register reporting a lower max multiplier.
2238 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS,
2242 * drm_dp_has_quirk() - does the DP device have a specific quirk
2243 * @desc: Device descriptor filled by drm_dp_read_desc()
2244 * @quirk: Quirk to query for
2246 * Return true if DP device identified by @desc has @quirk.
2249 drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
2251 return desc->quirks & BIT(quirk);
2255 * struct drm_edp_backlight_info - Probed eDP backlight info struct
2256 * @pwmgen_bit_count: The pwmgen bit count
2257 * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any
2258 * @max: The maximum backlight level that may be set
2259 * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register?
2260 * @aux_enable: Does the panel support the AUX enable cap?
2261 * @aux_set: Does the panel support setting the brightness through AUX?
2263 * This structure contains various data about an eDP backlight, which can be populated by using
2264 * drm_edp_backlight_init().
2266 struct drm_edp_backlight_info {
2267 u8 pwmgen_bit_count;
2268 u8 pwm_freq_pre_divider;
2271 bool lsb_reg_used : 1;
2272 bool aux_enable : 1;
2277 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
2278 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
2279 u16 *current_level, u8 *current_mode);
2280 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
2282 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
2284 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl);
2286 #if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \
2287 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE)))
2289 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux);
2293 static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel,
2294 struct drm_dp_aux *aux)
2301 #ifdef CONFIG_DRM_DP_CEC
2302 void drm_dp_cec_irq(struct drm_dp_aux *aux);
2303 void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
2304 struct drm_connector *connector);
2305 void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
2306 void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
2307 void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
2309 static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
2314 drm_dp_cec_register_connector(struct drm_dp_aux *aux,
2315 struct drm_connector *connector)
2319 static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
2323 static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
2324 const struct edid *edid)
2328 static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
2335 * struct drm_dp_phy_test_params - DP Phy Compliance parameters
2336 * @link_rate: Requested Link rate from DPCD 0x219
2337 * @num_lanes: Number of lanes requested by sing through DPCD 0x220
2338 * @phy_pattern: DP Phy test pattern from DPCD 0x248
2339 * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
2340 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259
2341 * @enhanced_frame_cap: flag for enhanced frame capability.
2343 struct drm_dp_phy_test_params {
2349 bool enhanced_frame_cap;
2352 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
2353 struct drm_dp_phy_test_params *data);
2354 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
2355 struct drm_dp_phy_test_params *data, u8 dp_rev);
2356 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2357 const u8 port_cap[4]);
2358 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
2359 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
2360 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
2362 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
2364 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
2365 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
2367 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);
2368 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);
2369 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
2370 struct drm_connector *connector);
2371 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
2372 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
2373 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
2374 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
2375 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux);
2376 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]);
2377 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]);
2378 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2379 const u8 port_cap[4], u8 color_spc);
2380 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
2382 #endif /* _DRM_DP_HELPER_H_ */