1 #ifndef __ASM_X86_PROCESSOR_H
2 #define __ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
17 #include <asm/system.h>
19 #include <asm/percpu.h>
21 #include <asm/desc_defs.h>
25 #include <linux/personality.h>
26 #include <linux/cpumask.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/init.h>
32 * Default implementation of macro that returns current
33 * instruction pointer ("program counter").
35 static inline void *current_text_addr(void)
39 asm volatile("mov $1f, %0; 1:":"=r" (pc));
44 #ifdef CONFIG_X86_VSMP
45 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
46 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
48 # define ARCH_MIN_TASKALIGN 16
49 # define ARCH_MIN_MMSTRUCT_ALIGN 0
53 * CPU type and hardware bug flags. Kept separately for each CPU.
54 * Members of this structure are referenced in head.S, so think twice
55 * before touching them. [mj]
59 __u8 x86; /* CPU family */
60 __u8 x86_vendor; /* CPU vendor */
64 char wp_works_ok; /* It doesn't on 386's */
66 /* Problems on some 486Dx4's and old 386's: */
75 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
79 /* CPUID returned core id bits: */
81 /* Max extended CPUID function supported: */
82 __u32 extended_cpuid_level;
84 /* Maximum supported CPUID level, -1=no CPUID: */
86 __u32 x86_capability[NCAPINTS];
87 char x86_vendor_id[16];
88 char x86_model_id[64];
89 /* in KB - valid for CPUS which support this call: */
91 int x86_cache_alignment; /* In bytes */
93 unsigned long loops_per_jiffy;
95 /* cpus sharing the last level cache: */
96 cpumask_t llc_shared_map;
98 /* cpuid returned max cores value: */
102 u16 x86_clflush_size;
104 /* number of cores as seen by the OS: */
106 /* Physical processor id: */
110 /* Index into per_cpu list: */
113 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
115 #define X86_VENDOR_INTEL 0
116 #define X86_VENDOR_CYRIX 1
117 #define X86_VENDOR_AMD 2
118 #define X86_VENDOR_UMC 3
119 #define X86_VENDOR_CENTAUR 5
120 #define X86_VENDOR_TRANSMETA 7
121 #define X86_VENDOR_NSC 8
122 #define X86_VENDOR_NUM 9
124 #define X86_VENDOR_UNKNOWN 0xff
127 * capabilities of CPUs
129 extern struct cpuinfo_x86 boot_cpu_data;
130 extern struct cpuinfo_x86 new_cpu_data;
132 extern struct tss_struct doublefault_tss;
133 extern __u32 cleared_cpu_caps[NCAPINTS];
136 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
137 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
138 #define current_cpu_data __get_cpu_var(cpu_info)
140 #define cpu_data(cpu) boot_cpu_data
141 #define current_cpu_data boot_cpu_data
144 static inline int hlt_works(int cpu)
147 return cpu_data(cpu).hlt_works_ok;
153 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
155 extern void cpu_detect(struct cpuinfo_x86 *c);
157 extern void early_cpu_init(void);
158 extern void identify_boot_cpu(void);
159 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
160 extern void print_cpu_info(struct cpuinfo_x86 *);
161 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
162 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
163 extern unsigned short num_cache_leaves;
165 #if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)
166 extern void detect_ht(struct cpuinfo_x86 *c);
168 static inline void detect_ht(struct cpuinfo_x86 *c) {}
171 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
172 unsigned int *ecx, unsigned int *edx)
174 /* ecx is often an input as well as an output. */
180 : "0" (*eax), "2" (*ecx));
183 static inline void load_cr3(pgd_t *pgdir)
185 write_cr3(__pa(pgdir));
189 /* This is the TSS defined by the hardware. */
191 unsigned short back_link, __blh;
193 unsigned short ss0, __ss0h;
195 /* ss1 caches MSR_IA32_SYSENTER_CS: */
196 unsigned short ss1, __ss1h;
198 unsigned short ss2, __ss2h;
210 unsigned short es, __esh;
211 unsigned short cs, __csh;
212 unsigned short ss, __ssh;
213 unsigned short ds, __dsh;
214 unsigned short fs, __fsh;
215 unsigned short gs, __gsh;
216 unsigned short ldt, __ldth;
217 unsigned short trace;
218 unsigned short io_bitmap_base;
220 } __attribute__((packed));
234 } __attribute__((packed)) ____cacheline_aligned;
240 #define IO_BITMAP_BITS 65536
241 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
242 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
243 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
244 #define INVALID_IO_BITMAP_OFFSET 0x8000
245 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
249 * The hardware state:
251 struct x86_hw_tss x86_tss;
254 * The extra 1 is there because the CPU will access an
255 * additional byte beyond the end of the IO permission
256 * bitmap. The extra byte must be all 1 bits, and must
257 * be within the limit.
259 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
261 * Cache the current maximum and the last task that used the bitmap:
263 unsigned long io_bitmap_max;
264 struct thread_struct *io_bitmap_owner;
267 * .. and then another 0x100 bytes for the emergency kernel stack:
269 unsigned long stack[64];
271 } ____cacheline_aligned;
273 DECLARE_PER_CPU(struct tss_struct, init_tss);
276 * Save the original ist values for checking stack pointers during debugging
279 unsigned long ist[7];
282 #define MXCSR_DEFAULT 0x1f80
284 struct i387_fsave_struct {
285 u32 cwd; /* FPU Control Word */
286 u32 swd; /* FPU Status Word */
287 u32 twd; /* FPU Tag Word */
288 u32 fip; /* FPU IP Offset */
289 u32 fcs; /* FPU IP Selector */
290 u32 foo; /* FPU Operand Pointer Offset */
291 u32 fos; /* FPU Operand Pointer Selector */
293 /* 8*10 bytes for each FP-reg = 80 bytes: */
296 /* Software status information [not touched by FSAVE ]: */
300 struct i387_fxsave_struct {
301 u16 cwd; /* Control Word */
302 u16 swd; /* Status Word */
303 u16 twd; /* Tag Word */
304 u16 fop; /* Last Instruction Opcode */
307 u64 rip; /* Instruction Pointer */
308 u64 rdp; /* Data Pointer */
311 u32 fip; /* FPU IP Offset */
312 u32 fcs; /* FPU IP Selector */
313 u32 foo; /* FPU Operand Offset */
314 u32 fos; /* FPU Operand Selector */
317 u32 mxcsr; /* MXCSR Register State */
318 u32 mxcsr_mask; /* MXCSR Mask */
320 /* 8*16 bytes for each FP-reg = 128 bytes: */
323 /* 16*16 bytes for each XMM-reg = 256 bytes: */
328 } __attribute__((aligned(16)));
330 struct i387_soft_struct {
338 /* 8*10 bytes for each FP-reg = 80 bytes: */
350 union thread_xstate {
351 struct i387_fsave_struct fsave;
352 struct i387_fxsave_struct fxsave;
353 struct i387_soft_struct soft;
357 DECLARE_PER_CPU(struct orig_ist, orig_ist);
360 extern void print_cpu_info(struct cpuinfo_x86 *);
361 extern unsigned int xstate_size;
362 extern void free_thread_xstate(struct task_struct *);
363 extern struct kmem_cache *task_xstate_cachep;
364 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
365 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
366 extern unsigned short num_cache_leaves;
368 struct thread_struct {
369 /* Cached TLS descriptors: */
370 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
374 unsigned long sysenter_cs;
376 unsigned long usersp; /* Copy from PDA */
379 unsigned short fsindex;
380 unsigned short gsindex;
385 /* Hardware debugging registers: */
386 unsigned long debugreg0;
387 unsigned long debugreg1;
388 unsigned long debugreg2;
389 unsigned long debugreg3;
390 unsigned long debugreg6;
391 unsigned long debugreg7;
394 unsigned long trap_no;
395 unsigned long error_code;
396 /* floating point and extended processor state */
397 union thread_xstate *xstate;
399 /* Virtual 86 mode info */
400 struct vm86_struct __user *vm86_info;
401 unsigned long screen_bitmap;
402 unsigned long v86flags;
403 unsigned long v86mask;
404 unsigned long saved_sp0;
405 unsigned int saved_fs;
406 unsigned int saved_gs;
408 /* IO permissions: */
409 unsigned long *io_bitmap_ptr;
411 /* Max allowed port in the bitmap, in bytes: */
412 unsigned io_bitmap_max;
413 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
414 unsigned long debugctlmsr;
416 /* Debug Store context; see include/asm-x86/ds.h; goes into MSR_IA32_DS_AREA */
417 struct ds_context *ds_ctx;
418 #endif /* CONFIG_X86_DS */
419 #ifdef CONFIG_X86_PTRACE_BTS
420 /* the signal to send on a bts buffer overflow */
421 unsigned int bts_ovfl_signal;
422 #endif /* CONFIG_X86_PTRACE_BTS */
425 static inline unsigned long native_get_debugreg(int regno)
427 unsigned long val = 0; /* Damn you, gcc! */
431 asm("mov %%db0, %0" :"=r" (val));
434 asm("mov %%db1, %0" :"=r" (val));
437 asm("mov %%db2, %0" :"=r" (val));
440 asm("mov %%db3, %0" :"=r" (val));
443 asm("mov %%db6, %0" :"=r" (val));
446 asm("mov %%db7, %0" :"=r" (val));
454 static inline void native_set_debugreg(int regno, unsigned long value)
458 asm("mov %0, %%db0" ::"r" (value));
461 asm("mov %0, %%db1" ::"r" (value));
464 asm("mov %0, %%db2" ::"r" (value));
467 asm("mov %0, %%db3" ::"r" (value));
470 asm("mov %0, %%db6" ::"r" (value));
473 asm("mov %0, %%db7" ::"r" (value));
481 * Set IOPL bits in EFLAGS from given mask
483 static inline void native_set_iopl_mask(unsigned mask)
488 asm volatile ("pushfl;"
495 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
500 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
502 tss->x86_tss.sp0 = thread->sp0;
504 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
505 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
506 tss->x86_tss.ss1 = thread->sysenter_cs;
507 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
512 static inline void native_swapgs(void)
515 asm volatile("swapgs" ::: "memory");
519 #ifdef CONFIG_PARAVIRT
520 #include <asm/paravirt.h>
522 #define __cpuid native_cpuid
523 #define paravirt_enabled() 0
526 * These special macros can be used to get or set a debugging register
528 #define get_debugreg(var, register) \
529 (var) = native_get_debugreg(register)
530 #define set_debugreg(value, register) \
531 native_set_debugreg(register, value)
533 static inline void load_sp0(struct tss_struct *tss,
534 struct thread_struct *thread)
536 native_load_sp0(tss, thread);
539 #define set_iopl_mask native_set_iopl_mask
540 #endif /* CONFIG_PARAVIRT */
543 * Save the cr4 feature set we're using (ie
544 * Pentium 4MB enable and PPro Global page
545 * enable), so that any CPU's that boot up
546 * after us can get the correct flags.
548 extern unsigned long mmu_cr4_features;
550 static inline void set_in_cr4(unsigned long mask)
554 mmu_cr4_features |= mask;
560 static inline void clear_in_cr4(unsigned long mask)
564 mmu_cr4_features &= ~mask;
570 struct microcode_header {
578 unsigned int datasize;
579 unsigned int totalsize;
580 unsigned int reserved[3];
584 struct microcode_header hdr;
585 unsigned int bits[0];
588 typedef struct microcode microcode_t;
589 typedef struct microcode_header microcode_header_t;
591 /* microcode format is extended from prescott processors */
592 struct extended_signature {
598 struct extended_sigtable {
601 unsigned int reserved[3];
602 struct extended_signature sigs[0];
611 * create a kernel thread without removing it from tasklists
613 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
615 /* Free all resources held by a thread. */
616 extern void release_thread(struct task_struct *);
618 /* Prepare to copy thread state - unlazy all lazy state */
619 extern void prepare_to_copy(struct task_struct *tsk);
621 unsigned long get_wchan(struct task_struct *p);
624 * Generic CPUID function
625 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
626 * resulting in stale register contents being returned.
628 static inline void cpuid(unsigned int op,
629 unsigned int *eax, unsigned int *ebx,
630 unsigned int *ecx, unsigned int *edx)
634 __cpuid(eax, ebx, ecx, edx);
637 /* Some CPUID calls want 'count' to be placed in ecx */
638 static inline void cpuid_count(unsigned int op, int count,
639 unsigned int *eax, unsigned int *ebx,
640 unsigned int *ecx, unsigned int *edx)
644 __cpuid(eax, ebx, ecx, edx);
648 * CPUID functions returning a single datum
650 static inline unsigned int cpuid_eax(unsigned int op)
652 unsigned int eax, ebx, ecx, edx;
654 cpuid(op, &eax, &ebx, &ecx, &edx);
659 static inline unsigned int cpuid_ebx(unsigned int op)
661 unsigned int eax, ebx, ecx, edx;
663 cpuid(op, &eax, &ebx, &ecx, &edx);
668 static inline unsigned int cpuid_ecx(unsigned int op)
670 unsigned int eax, ebx, ecx, edx;
672 cpuid(op, &eax, &ebx, &ecx, &edx);
677 static inline unsigned int cpuid_edx(unsigned int op)
679 unsigned int eax, ebx, ecx, edx;
681 cpuid(op, &eax, &ebx, &ecx, &edx);
686 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
687 static inline void rep_nop(void)
689 asm volatile("rep; nop" ::: "memory");
692 static inline void cpu_relax(void)
697 /* Stop speculative execution: */
698 static inline void sync_core(void)
702 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
703 : "ebx", "ecx", "edx", "memory");
706 static inline void __monitor(const void *eax, unsigned long ecx,
709 /* "monitor %eax, %ecx, %edx;" */
710 asm volatile(".byte 0x0f, 0x01, 0xc8;"
711 :: "a" (eax), "c" (ecx), "d"(edx));
714 static inline void __mwait(unsigned long eax, unsigned long ecx)
716 /* "mwait %eax, %ecx;" */
717 asm volatile(".byte 0x0f, 0x01, 0xc9;"
718 :: "a" (eax), "c" (ecx));
721 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
724 /* "mwait %eax, %ecx;" */
725 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
726 :: "a" (eax), "c" (ecx));
729 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
731 extern void select_idle_routine(const struct cpuinfo_x86 *c);
733 extern unsigned long boot_option_idle_override;
734 extern unsigned long idle_halt;
735 extern unsigned long idle_nomwait;
738 * on systems with caches, caches must be flashed as the absolute
739 * last instruction before going into a suspended halt. Otherwise,
740 * dirty data can linger in the cache and become stale on resume,
741 * leading to strange errors.
743 * perform a variety of operations to guarantee that the compiler
744 * will not reorder instructions. wbinvd itself is serializing
745 * so the processor will not reorder.
747 * Systems without cache can just go into halt.
749 static inline void wbinvd_halt(void)
752 /* check for clflush to determine if wbinvd is legal */
754 asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
760 extern void enable_sep_cpu(void);
761 extern int sysenter_setup(void);
763 /* Defined in head.S */
764 extern struct desc_ptr early_gdt_descr;
766 extern void cpu_set_gdt(int);
767 extern void switch_to_new_gdt(void);
768 extern void cpu_init(void);
769 extern void init_gdt(int cpu);
771 static inline void update_debugctlmsr(unsigned long debugctlmsr)
773 #ifndef CONFIG_X86_DEBUGCTLMSR
774 if (boot_cpu_data.x86 < 6)
777 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
781 * from system description table in BIOS. Mostly for MCA use, but
782 * others may find it useful:
784 extern unsigned int machine_id;
785 extern unsigned int machine_submodel_id;
786 extern unsigned int BIOS_revision;
788 /* Boot loader type from the setup header: */
789 extern int bootloader_type;
791 extern char ignore_fpu_irq;
793 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
794 #define ARCH_HAS_PREFETCHW
795 #define ARCH_HAS_SPINLOCK_PREFETCH
798 # define BASE_PREFETCH ASM_NOP4
799 # define ARCH_HAS_PREFETCH
801 # define BASE_PREFETCH "prefetcht0 (%1)"
805 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
807 * It's not worth to care about 3dnow prefetches for the K6
808 * because they are microcoded there and very slow.
810 static inline void prefetch(const void *x)
812 alternative_input(BASE_PREFETCH,
819 * 3dnow prefetch to get an exclusive cache line.
820 * Useful for spinlocks to avoid one state transition in the
821 * cache coherency protocol:
823 static inline void prefetchw(const void *x)
825 alternative_input(BASE_PREFETCH,
831 static inline void spin_lock_prefetch(const void *x)
838 * User space process size: 3GB (default).
840 #define TASK_SIZE PAGE_OFFSET
841 #define STACK_TOP TASK_SIZE
842 #define STACK_TOP_MAX STACK_TOP
844 #define INIT_THREAD { \
845 .sp0 = sizeof(init_stack) + (long)&init_stack, \
847 .sysenter_cs = __KERNEL_CS, \
848 .io_bitmap_ptr = NULL, \
849 .fs = __KERNEL_PERCPU, \
853 * Note that the .io_bitmap member must be extra-big. This is because
854 * the CPU will access an additional byte beyond the end of the IO
855 * permission bitmap. The extra byte must be all 1 bits, and must
856 * be within the limit.
860 .sp0 = sizeof(init_stack) + (long)&init_stack, \
861 .ss0 = __KERNEL_DS, \
862 .ss1 = __KERNEL_CS, \
863 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
865 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
868 extern unsigned long thread_saved_pc(struct task_struct *tsk);
870 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
871 #define KSTK_TOP(info) \
873 unsigned long *__ptr = (unsigned long *)(info); \
874 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
878 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
879 * This is necessary to guarantee that the entire "struct pt_regs"
880 * is accessable even if the CPU haven't stored the SS/ESP registers
881 * on the stack (interrupt gate does not save these registers
882 * when switching to the same priv ring).
883 * Therefore beware: accessing the ss/esp fields of the
884 * "struct pt_regs" is possible, but they may contain the
885 * completely wrong values.
887 #define task_pt_regs(task) \
889 struct pt_regs *__regs__; \
890 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
894 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
898 * User space process size. 47bits minus one guard page.
900 #define TASK_SIZE64 ((1UL << 47) - PAGE_SIZE)
902 /* This decides where the kernel will search for a free chunk of vm
903 * space during mmap's.
905 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
906 0xc0000000 : 0xFFFFe000)
908 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
909 IA32_PAGE_OFFSET : TASK_SIZE64)
910 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
911 IA32_PAGE_OFFSET : TASK_SIZE64)
913 #define STACK_TOP TASK_SIZE
914 #define STACK_TOP_MAX TASK_SIZE64
916 #define INIT_THREAD { \
917 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
921 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
925 * Return saved PC of a blocked thread.
926 * What is this good for? it will be always the scheduler or ret_from_fork.
928 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
930 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
931 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
932 #endif /* CONFIG_X86_64 */
934 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
935 unsigned long new_sp);
938 * This decides where the kernel will search for a free chunk of vm
939 * space during mmap's.
941 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
943 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
945 /* Get/set a process' ability to use the timestamp counter instruction */
946 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
947 #define SET_TSC_CTL(val) set_tsc_mode((val))
949 extern int get_tsc_mode(unsigned long adr);
950 extern int set_tsc_mode(unsigned int val);