1 #ifndef __ASM_SH_CPU_FEATURES_H
2 #define __ASM_SH_CPU_FEATURES_H
7 #define CPU_HAS_FPU 0x0001 /* Hardware FPU support */
8 #define CPU_HAS_P2_FLUSH_BUG 0x0002 /* Need to flush the cache in P2 area */
9 #define CPU_HAS_MMU_PAGE_ASSOC 0x0004 /* SH3: TLB way selection bit support */
10 #define CPU_HAS_DSP 0x0008 /* SH-DSP: DSP support */
11 #define CPU_HAS_PERF_COUNTER 0x0010 /* Hardware performance counters */
12 #define CPU_HAS_PTEA 0x0020 /* PTEA register */
13 #define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */
15 #endif /* __ASM_SH_CPU_FEATURES_H */