2 * Author: MontaVista Software, Inc.
5 * Copyright 2001-2006 MontaVista Software Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
15 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
17 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
18 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
19 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
20 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
21 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 #ifndef __ASM_TXX9_TX4927_H
28 #define __ASM_TXX9_TX4927_H
30 #include <linux/types.h>
32 #include <asm/txx9irq.h>
33 #include <asm/txx9/tx4927pcic.h>
35 #define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE
36 #define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1)
38 #define TX4927_IRQ_PIC_BEG TXX9_IRQ_BASE
39 #define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
42 #define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0)
43 #define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1)
44 #define TX4927_IRQ_NEST_PIC_ON_CP0 (TX4927_IRQ_CP0_BEG+2)
45 #define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7)
47 #define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3)
49 #define TX4927_SDRAMC_REG 0xff1f8000
50 #define TX4927_EBUSC_REG 0xff1f9000
51 #define TX4927_PCIC_REG 0xff1fd000
52 #define TX4927_CCFG_REG 0xff1fe000
53 #define TX4927_IRC_REG 0xff1ff600
54 #define TX4927_NR_TMR 3
55 #define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100)
57 #define TX4927_IR_PCIC 16
58 #define TX4927_IR_PCIERR 22
59 #define TX4927_NUM_IR 32
61 struct tx4927_sdramc_reg {
62 volatile unsigned long long cr[4];
63 volatile unsigned long long unused0[4];
64 volatile unsigned long long tr;
65 volatile unsigned long long unused1[2];
66 volatile unsigned long long cmd;
69 struct tx4927_ebusc_reg {
70 volatile unsigned long long cr[8];
73 struct tx4927_ccfg_reg {
89 /* CCFG : Chip Configuration */
90 #define TX4927_CCFG_WDRST 0x0000020000000000ULL
91 #define TX4927_CCFG_WDREXEN 0x0000010000000000ULL
92 #define TX4927_CCFG_BCFG_MASK 0x000000ff00000000ULL
93 #define TX4927_CCFG_TINTDIS 0x01000000
94 #define TX4927_CCFG_PCI66 0x00800000
95 #define TX4927_CCFG_PCIMODE 0x00400000
96 #define TX4927_CCFG_DIVMODE_MASK 0x000e0000
97 #define TX4927_CCFG_DIVMODE_8 (0x0 << 17)
98 #define TX4927_CCFG_DIVMODE_12 (0x1 << 17)
99 #define TX4927_CCFG_DIVMODE_16 (0x2 << 17)
100 #define TX4927_CCFG_DIVMODE_10 (0x3 << 17)
101 #define TX4927_CCFG_DIVMODE_2 (0x4 << 17)
102 #define TX4927_CCFG_DIVMODE_3 (0x5 << 17)
103 #define TX4927_CCFG_DIVMODE_4 (0x6 << 17)
104 #define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
105 #define TX4927_CCFG_BEOW 0x00010000
106 #define TX4927_CCFG_WR 0x00008000
107 #define TX4927_CCFG_TOE 0x00004000
108 #define TX4927_CCFG_PCIARB 0x00002000
109 #define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
110 #define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
111 #define TX4927_CCFG_PCIDIVMODE_3 0x00000800
112 #define TX4927_CCFG_PCIDIVMODE_5 0x00001000
113 #define TX4927_CCFG_PCIDIVMODE_6 0x00001800
114 #define TX4927_CCFG_SYSSP_MASK 0x000000c0
115 #define TX4927_CCFG_ENDIAN 0x00000004
116 #define TX4927_CCFG_HALT 0x00000002
117 #define TX4927_CCFG_ACEHOLD 0x00000001
118 #define TX4927_CCFG_W1CBITS (TX4927_CCFG_WDRST | TX4927_CCFG_BEOW)
120 /* PCFG : Pin Configuration */
121 #define TX4927_PCFG_SDCLKDLY_MASK 0x30000000
122 #define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)
123 #define TX4927_PCFG_SYSCLKEN 0x08000000
124 #define TX4927_PCFG_SDCLKEN_ALL 0x07800000
125 #define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
126 #define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
127 #define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
128 #define TX4927_PCFG_SEL2 0x00000200
129 #define TX4927_PCFG_SEL1 0x00000100
130 #define TX4927_PCFG_DMASEL_ALL 0x000000ff
131 #define TX4927_PCFG_DMASEL0_MASK 0x00000003
132 #define TX4927_PCFG_DMASEL1_MASK 0x0000000c
133 #define TX4927_PCFG_DMASEL2_MASK 0x00000030
134 #define TX4927_PCFG_DMASEL3_MASK 0x000000c0
135 #define TX4927_PCFG_DMASEL0_DRQ0 0x00000000
136 #define TX4927_PCFG_DMASEL0_SIO1 0x00000001
137 #define TX4927_PCFG_DMASEL0_ACL0 0x00000002
138 #define TX4927_PCFG_DMASEL0_ACL2 0x00000003
139 #define TX4927_PCFG_DMASEL1_DRQ1 0x00000000
140 #define TX4927_PCFG_DMASEL1_SIO1 0x00000004
141 #define TX4927_PCFG_DMASEL1_ACL1 0x00000008
142 #define TX4927_PCFG_DMASEL1_ACL3 0x0000000c
143 #define TX4927_PCFG_DMASEL2_DRQ2 0x00000000 /* SEL2=0 */
144 #define TX4927_PCFG_DMASEL2_SIO0 0x00000010 /* SEL2=0 */
145 #define TX4927_PCFG_DMASEL2_ACL1 0x00000000 /* SEL2=1 */
146 #define TX4927_PCFG_DMASEL2_ACL2 0x00000020 /* SEL2=1 */
147 #define TX4927_PCFG_DMASEL2_ACL0 0x00000030 /* SEL2=1 */
148 #define TX4927_PCFG_DMASEL3_DRQ3 0x00000000
149 #define TX4927_PCFG_DMASEL3_SIO0 0x00000040
150 #define TX4927_PCFG_DMASEL3_ACL3 0x00000080
151 #define TX4927_PCFG_DMASEL3_ACL1 0x000000c0
153 /* CLKCTR : Clock Control */
154 #define TX4927_CLKCTR_ACLCKD 0x02000000
155 #define TX4927_CLKCTR_PIOCKD 0x01000000
156 #define TX4927_CLKCTR_DMACKD 0x00800000
157 #define TX4927_CLKCTR_PCICKD 0x00400000
158 #define TX4927_CLKCTR_TM0CKD 0x00100000
159 #define TX4927_CLKCTR_TM1CKD 0x00080000
160 #define TX4927_CLKCTR_TM2CKD 0x00040000
161 #define TX4927_CLKCTR_SIO0CKD 0x00020000
162 #define TX4927_CLKCTR_SIO1CKD 0x00010000
163 #define TX4927_CLKCTR_ACLRST 0x00000200
164 #define TX4927_CLKCTR_PIORST 0x00000100
165 #define TX4927_CLKCTR_DMARST 0x00000080
166 #define TX4927_CLKCTR_PCIRST 0x00000040
167 #define TX4927_CLKCTR_TM0RST 0x00000010
168 #define TX4927_CLKCTR_TM1RST 0x00000008
169 #define TX4927_CLKCTR_TM2RST 0x00000004
170 #define TX4927_CLKCTR_SIO0RST 0x00000002
171 #define TX4927_CLKCTR_SIO1RST 0x00000001
173 #define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG)
174 #define tx4927_pcicptr \
175 ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG)
176 #define tx4927_ccfgptr \
177 ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
178 #define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
181 static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
185 local_irq_save(flags);
187 ____raw_writeq(____raw_readq(adr) & ~bits, adr);
189 local_irq_restore(flags);
192 static inline void txx9_set64(__u64 __iomem *adr, __u64 bits)
196 local_irq_save(flags);
198 ____raw_writeq(____raw_readq(adr) | bits, adr);
200 local_irq_restore(flags);
204 /* These functions are not interrupt safe. */
205 static inline void tx4927_ccfg_clear(__u64 bits)
207 ____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg)
208 & ~(TX4927_CCFG_W1CBITS | bits),
209 &tx4927_ccfgptr->ccfg);
211 static inline void tx4927_ccfg_set(__u64 bits)
213 ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
214 & ~TX4927_CCFG_W1CBITS) | bits,
215 &tx4927_ccfgptr->ccfg);
217 static inline void tx4927_ccfg_change(__u64 change, __u64 new)
219 ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
220 & ~(TX4927_CCFG_W1CBITS | change)) |
222 &tx4927_ccfgptr->ccfg);
225 int tx4927_report_pciclk(void);
226 int tx4927_pciclk66_setup(void);
228 #endif /* __ASM_TXX9_TX4927_H */