2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Inline assembly cache operations.
8 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
9 * Copyright (C) 1997 - 2002 Ralf Baechle (ralf@gnu.org)
10 * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org)
12 #ifndef _ASM_R4KCACHE_H
13 #define _ASM_R4KCACHE_H
16 #include <asm/cacheops.h>
19 * This macro return a properly sign-extended address suitable as base address
20 * for indexed cache operations. Two issues here:
22 * - The MIPS32 and MIPS64 specs permit an implementation to directly derive
23 * the index bits from the virtual address. This breaks with tradition
24 * set by the R4000. To keep unpleasant surprises from happening we pick
25 * an address in KSEG0 / CKSEG0.
26 * - We need a properly sign extended address for 64-bit code. To get away
27 * without ifdefs we let the compiler do it by a type cast.
29 #define INDEX_BASE CKSEG0
31 #define cache_op(op,addr) \
32 __asm__ __volatile__( \
34 " .set noreorder \n" \
35 " .set mips3\n\t \n" \
39 : "i" (op), "m" (*(unsigned char *)(addr)))
41 static inline void flush_icache_line_indexed(unsigned long addr)
43 cache_op(Index_Invalidate_I, addr);
46 static inline void flush_dcache_line_indexed(unsigned long addr)
48 cache_op(Index_Writeback_Inv_D, addr);
51 static inline void flush_scache_line_indexed(unsigned long addr)
53 cache_op(Index_Writeback_Inv_SD, addr);
56 static inline void flush_icache_line(unsigned long addr)
58 cache_op(Hit_Invalidate_I, addr);
61 static inline void flush_dcache_line(unsigned long addr)
63 cache_op(Hit_Writeback_Inv_D, addr);
66 static inline void invalidate_dcache_line(unsigned long addr)
68 cache_op(Hit_Invalidate_D, addr);
71 static inline void invalidate_scache_line(unsigned long addr)
73 cache_op(Hit_Invalidate_SD, addr);
76 static inline void flush_scache_line(unsigned long addr)
78 cache_op(Hit_Writeback_Inv_SD, addr);
82 * The next two are for badland addresses like signal trampolines.
84 static inline void protected_flush_icache_line(unsigned long addr)
90 "1: cache %0, (%1) \n"
92 " .section __ex_table,\"a\" \n"
93 " "STR(PTR)" 1b, 2b \n"
96 : "i" (Hit_Invalidate_I), "r" (addr));
100 * R10000 / R12000 hazard - these processors don't support the Hit_Writeback_D
101 * cacheop so we use Hit_Writeback_Inv_D which is supported by all R4000-style
102 * caches. We're talking about one cacheline unnecessarily getting invalidated
103 * here so the penalty isn't overly hard.
105 static inline void protected_writeback_dcache_line(unsigned long addr)
107 __asm__ __volatile__(
111 "1: cache %0, (%1) \n"
113 " .section __ex_table,\"a\" \n"
114 " "STR(PTR)" 1b, 2b \n"
117 : "i" (Hit_Writeback_Inv_D), "r" (addr));
120 static inline void protected_writeback_scache_line(unsigned long addr)
122 __asm__ __volatile__(
126 "1: cache %0, (%1) \n"
128 " .section __ex_table,\"a\" \n"
129 " "STR(PTR)" 1b, 2b \n"
132 : "i" (Hit_Writeback_Inv_SD), "r" (addr));
136 * This one is RM7000-specific
138 static inline void invalidate_tcache_page(unsigned long addr)
140 cache_op(Page_Invalidate_T, addr);
143 #define cache16_unroll32(base,op) \
144 __asm__ __volatile__( \
146 " .set noreorder \n" \
148 " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \
149 " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \
150 " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \
151 " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \
152 " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \
153 " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \
154 " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \
155 " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \
156 " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \
157 " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \
158 " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \
159 " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \
160 " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \
161 " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \
162 " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \
163 " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \
169 #define cache32_unroll32(base,op) \
170 __asm__ __volatile__( \
172 " .set noreorder \n" \
174 " cache %1, 0x000(%0); cache %1, 0x020(%0) \n" \
175 " cache %1, 0x040(%0); cache %1, 0x060(%0) \n" \
176 " cache %1, 0x080(%0); cache %1, 0x0a0(%0) \n" \
177 " cache %1, 0x0c0(%0); cache %1, 0x0e0(%0) \n" \
178 " cache %1, 0x100(%0); cache %1, 0x120(%0) \n" \
179 " cache %1, 0x140(%0); cache %1, 0x160(%0) \n" \
180 " cache %1, 0x180(%0); cache %1, 0x1a0(%0) \n" \
181 " cache %1, 0x1c0(%0); cache %1, 0x1e0(%0) \n" \
182 " cache %1, 0x200(%0); cache %1, 0x220(%0) \n" \
183 " cache %1, 0x240(%0); cache %1, 0x260(%0) \n" \
184 " cache %1, 0x280(%0); cache %1, 0x2a0(%0) \n" \
185 " cache %1, 0x2c0(%0); cache %1, 0x2e0(%0) \n" \
186 " cache %1, 0x300(%0); cache %1, 0x320(%0) \n" \
187 " cache %1, 0x340(%0); cache %1, 0x360(%0) \n" \
188 " cache %1, 0x380(%0); cache %1, 0x3a0(%0) \n" \
189 " cache %1, 0x3c0(%0); cache %1, 0x3e0(%0) \n" \
195 #define cache64_unroll32(base,op) \
196 __asm__ __volatile__( \
198 " .set noreorder \n" \
200 " cache %1, 0x000(%0); cache %1, 0x040(%0) \n" \
201 " cache %1, 0x080(%0); cache %1, 0x0c0(%0) \n" \
202 " cache %1, 0x100(%0); cache %1, 0x140(%0) \n" \
203 " cache %1, 0x180(%0); cache %1, 0x1c0(%0) \n" \
204 " cache %1, 0x200(%0); cache %1, 0x240(%0) \n" \
205 " cache %1, 0x280(%0); cache %1, 0x2c0(%0) \n" \
206 " cache %1, 0x300(%0); cache %1, 0x340(%0) \n" \
207 " cache %1, 0x380(%0); cache %1, 0x3c0(%0) \n" \
208 " cache %1, 0x400(%0); cache %1, 0x440(%0) \n" \
209 " cache %1, 0x480(%0); cache %1, 0x4c0(%0) \n" \
210 " cache %1, 0x500(%0); cache %1, 0x540(%0) \n" \
211 " cache %1, 0x580(%0); cache %1, 0x5c0(%0) \n" \
212 " cache %1, 0x600(%0); cache %1, 0x640(%0) \n" \
213 " cache %1, 0x680(%0); cache %1, 0x6c0(%0) \n" \
214 " cache %1, 0x700(%0); cache %1, 0x740(%0) \n" \
215 " cache %1, 0x780(%0); cache %1, 0x7c0(%0) \n" \
221 #define cache128_unroll32(base,op) \
222 __asm__ __volatile__( \
224 " .set noreorder \n" \
226 " cache %1, 0x000(%0); cache %1, 0x080(%0) \n" \
227 " cache %1, 0x100(%0); cache %1, 0x180(%0) \n" \
228 " cache %1, 0x200(%0); cache %1, 0x280(%0) \n" \
229 " cache %1, 0x300(%0); cache %1, 0x380(%0) \n" \
230 " cache %1, 0x400(%0); cache %1, 0x480(%0) \n" \
231 " cache %1, 0x500(%0); cache %1, 0x580(%0) \n" \
232 " cache %1, 0x600(%0); cache %1, 0x680(%0) \n" \
233 " cache %1, 0x700(%0); cache %1, 0x780(%0) \n" \
234 " cache %1, 0x800(%0); cache %1, 0x880(%0) \n" \
235 " cache %1, 0x900(%0); cache %1, 0x980(%0) \n" \
236 " cache %1, 0xa00(%0); cache %1, 0xa80(%0) \n" \
237 " cache %1, 0xb00(%0); cache %1, 0xb80(%0) \n" \
238 " cache %1, 0xc00(%0); cache %1, 0xc80(%0) \n" \
239 " cache %1, 0xd00(%0); cache %1, 0xd80(%0) \n" \
240 " cache %1, 0xe00(%0); cache %1, 0xe80(%0) \n" \
241 " cache %1, 0xf00(%0); cache %1, 0xf80(%0) \n" \
247 /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
248 #define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
249 static inline void blast_##pfx##cache##lsize(void) \
251 unsigned long start = INDEX_BASE; \
252 unsigned long end = start + current_cpu_data.desc.waysize; \
253 unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \
254 unsigned long ws_end = current_cpu_data.desc.ways << \
255 current_cpu_data.desc.waybit; \
256 unsigned long ws, addr; \
258 for (ws = 0; ws < ws_end; ws += ws_inc) \
259 for (addr = start; addr < end; addr += lsize * 32) \
260 cache##lsize##_unroll32(addr|ws,indexop); \
263 static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \
265 unsigned long start = page; \
266 unsigned long end = page + PAGE_SIZE; \
269 cache##lsize##_unroll32(start,hitop); \
270 start += lsize * 32; \
271 } while (start < end); \
274 static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
276 unsigned long start = page; \
277 unsigned long end = start + PAGE_SIZE; \
278 unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \
279 unsigned long ws_end = current_cpu_data.desc.ways << \
280 current_cpu_data.desc.waybit; \
281 unsigned long ws, addr; \
283 for (ws = 0; ws < ws_end; ws += ws_inc) \
284 for (addr = start; addr < end; addr += lsize * 32) \
285 cache##lsize##_unroll32(addr|ws,indexop); \
288 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
289 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
290 __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
291 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
292 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
293 __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
294 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
295 __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
296 __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
298 #endif /* _ASM_R4KCACHE_H */