2 * include/asm-mips/dec/kn05.h
4 * DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min
5 * or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or
6 * KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
9 * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
16 * WARNING! All this information is pure guesswork based on the
17 * ROM. It is provided here in hope it will give someone some
18 * food for thought. No documentation for the KN05 nor the KN04
19 * module has been located so far.
21 #ifndef __ASM_MIPS_DEC_KN05_H
22 #define __ASM_MIPS_DEC_KN05_H
24 #include <asm/addrspace.h>
25 #include <asm/dec/ioasic_addrs.h>
28 * The oncard MB (Memory Buffer) ASIC provides an additional address
29 * decoder. Certain address ranges within the "high" 16 slots are
30 * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA.
31 * Others are handled locally. "Low" slots are always passed.
33 #define KN4K_SLOT_BASE KSEG1ADDR(0x1fc00000)
35 #define KN4K_MB_ROM (0*IOASIC_SLOT_SIZE) /* KN05/KN04 card ROM */
36 #define KN4K_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */
37 #define KN4K_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */
38 #define KN4K_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */
39 #define KN4K_MB_INT (4*IOASIC_SLOT_SIZE) /* MB interrupt register */
40 #define KN4K_MB_EA (5*IOASIC_SLOT_SIZE) /* MB error address? */
41 #define KN4K_MB_EC (6*IOASIC_SLOT_SIZE) /* MB error ??? */
42 #define KN4K_MB_CSR (7*IOASIC_SLOT_SIZE) /* MB control & status */
43 #define KN4K_RES_08 (8*IOASIC_SLOT_SIZE) /* unused? */
44 #define KN4K_RES_09 (9*IOASIC_SLOT_SIZE) /* unused? */
45 #define KN4K_RES_10 (10*IOASIC_SLOT_SIZE) /* unused? */
46 #define KN4K_RES_11 (11*IOASIC_SLOT_SIZE) /* unused? */
47 #define KN4K_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */
48 #define KN4K_RES_13 (13*IOASIC_SLOT_SIZE) /* unused? */
49 #define KN4K_RES_14 (14*IOASIC_SLOT_SIZE) /* unused? */
50 #define KN4K_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */
53 * Bits for the MB interrupt register.
54 * The register appears read-only.
56 #define KN4K_MB_INT_TC (1<<0) /* TURBOchannel? */
57 #define KN4K_MB_INT_RTC (1<<1) /* RTC? */
58 #define KN4K_MB_INT_MT (1<<3) /* ??? */
61 * Bits for the MB control & status register.
62 * Set to 0x00bf8001 on my system by the ROM.
64 #define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */
65 #define KN4K_MB_CSR_F (1<<1) /* ??? */
66 #define KN4K_MB_CSR_ECC (0xff<<2) /* ??? */
67 #define KN4K_MB_CSR_OD (1<<10) /* ??? */
68 #define KN4K_MB_CSR_CP (1<<11) /* ??? */
69 #define KN4K_MB_CSR_UNC (1<<12) /* ??? */
70 #define KN4K_MB_CSR_IM (1<<13) /* ??? */
71 #define KN4K_MB_CSR_NC (1<<14) /* ??? */
72 #define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */
73 #define KN4K_MB_CSR_MSK (0x1f<<16) /* ??? */
74 #define KN4K_MB_CSR_FW (1<<21) /* ??? */
76 #endif /* __ASM_MIPS_DEC_KN05_H */