1 // SPDX-License-Identifier: GPL-2.0
3 * Starfive Watchdog driver
5 * Copyright (C) 2022 StarFive Technology Co., Ltd.
9 #include <linux/iopoll.h>
10 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/reset.h>
15 #include <linux/watchdog.h>
17 /* JH7100 Watchdog register define */
18 #define STARFIVE_WDT_JH7100_INTSTAUS 0x000
19 #define STARFIVE_WDT_JH7100_CONTROL 0x104
20 #define STARFIVE_WDT_JH7100_LOAD 0x108
21 #define STARFIVE_WDT_JH7100_EN 0x110
22 #define STARFIVE_WDT_JH7100_RELOAD 0x114 /* Write 0 or 1 to reload preset value */
23 #define STARFIVE_WDT_JH7100_VALUE 0x118
24 #define STARFIVE_WDT_JH7100_INTCLR 0x120 /*
25 * [0]: Write 1 to clear interrupt
26 * [1]: 1 mean clearing and 0 mean complete
29 #define STARFIVE_WDT_JH7100_LOCK 0x13c /* write 0x378f0765 to unlock */
31 /* JH7110 Watchdog register define */
32 #define STARFIVE_WDT_JH7110_LOAD 0x000
33 #define STARFIVE_WDT_JH7110_VALUE 0x004
34 #define STARFIVE_WDT_JH7110_CONTROL 0x008 /*
36 * [1]: interrupt enable && watchdog enable
39 #define STARFIVE_WDT_JH7110_INTCLR 0x00c /* clear intterupt and reload the counter */
40 #define STARFIVE_WDT_JH7110_IMS 0x014
41 #define STARFIVE_WDT_JH7110_LOCK 0xc00 /* write 0x1ACCE551 to unlock */
44 #define STARFIVE_WDT_ENABLE 0x1
45 #define STARFIVE_WDT_EN_SHIFT 0
46 #define STARFIVE_WDT_RESET_EN 0x1
47 #define STARFIVE_WDT_JH7100_RST_EN_SHIFT 0
48 #define STARFIVE_WDT_JH7110_RST_EN_SHIFT 1
51 #define STARFIVE_WDT_JH7100_UNLOCK_KEY 0x378f0765
52 #define STARFIVE_WDT_JH7110_UNLOCK_KEY 0x1acce551
55 #define STARFIVE_WDT_INTCLR 0x1
56 #define STARFIVE_WDT_JH7100_INTCLR_AVA_SHIFT 1 /* Watchdog can clear interrupt when 0 */
58 #define STARFIVE_WDT_MAXCNT 0xffffffff
59 #define STARFIVE_WDT_DEFAULT_TIME (15)
60 #define STARFIVE_WDT_DELAY_US 0
61 #define STARFIVE_WDT_TIMEOUT_US 10000
63 /* module parameter */
64 #define STARFIVE_WDT_EARLY_ENA 0
66 static bool nowayout = WATCHDOG_NOWAYOUT;
68 static bool early_enable = STARFIVE_WDT_EARLY_ENA;
70 module_param(heartbeat, int, 0);
71 module_param(early_enable, bool, 0);
72 module_param(nowayout, bool, 0);
74 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
75 __MODULE_STRING(STARFIVE_WDT_DEFAULT_TIME) ")");
76 MODULE_PARM_DESC(early_enable,
77 "Watchdog is started at boot time if set to 1, default="
78 __MODULE_STRING(STARFIVE_WDT_EARLY_ENA));
79 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
80 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
82 struct starfive_wdt_variant {
83 unsigned int control; /* Watchdog Control Resgister for reset enable */
84 unsigned int load; /* Watchdog Load register */
85 unsigned int reload; /* Watchdog Reload Control register */
86 unsigned int enable; /* Watchdog Enable Register */
87 unsigned int value; /* Watchdog Counter Value Register */
88 unsigned int int_clr; /* Watchdog Interrupt Clear Register */
89 unsigned int unlock; /* Watchdog Lock Register */
90 unsigned int int_status; /* Watchdog Interrupt Status Register */
95 bool intclr_check; /* whether need to check it before clearing interrupt */
96 char intclr_ava_shift;
97 bool double_timeout; /* The watchdog need twice timeout to reboot */
100 struct starfive_wdt {
101 struct watchdog_device wdd;
102 spinlock_t lock; /* spinlock for register handling */
104 struct clk *core_clk;
106 const struct starfive_wdt_variant *variant;
108 u32 count; /* count of timeout */
109 u32 reload; /* restore the count */
112 /* Register layout and configuration for the JH7100 */
113 static const struct starfive_wdt_variant starfive_wdt_jh7100_variant = {
114 .control = STARFIVE_WDT_JH7100_CONTROL,
115 .load = STARFIVE_WDT_JH7100_LOAD,
116 .reload = STARFIVE_WDT_JH7100_RELOAD,
117 .enable = STARFIVE_WDT_JH7100_EN,
118 .value = STARFIVE_WDT_JH7100_VALUE,
119 .int_clr = STARFIVE_WDT_JH7100_INTCLR,
120 .unlock = STARFIVE_WDT_JH7100_LOCK,
121 .unlock_key = STARFIVE_WDT_JH7100_UNLOCK_KEY,
122 .int_status = STARFIVE_WDT_JH7100_INTSTAUS,
123 .enrst_shift = STARFIVE_WDT_JH7100_RST_EN_SHIFT,
124 .en_shift = STARFIVE_WDT_EN_SHIFT,
125 .intclr_check = true,
126 .intclr_ava_shift = STARFIVE_WDT_JH7100_INTCLR_AVA_SHIFT,
127 .double_timeout = false,
130 /* Register layout and configuration for the JH7110 */
131 static const struct starfive_wdt_variant starfive_wdt_jh7110_variant = {
132 .control = STARFIVE_WDT_JH7110_CONTROL,
133 .load = STARFIVE_WDT_JH7110_LOAD,
134 .enable = STARFIVE_WDT_JH7110_CONTROL,
135 .value = STARFIVE_WDT_JH7110_VALUE,
136 .int_clr = STARFIVE_WDT_JH7110_INTCLR,
137 .unlock = STARFIVE_WDT_JH7110_LOCK,
138 .unlock_key = STARFIVE_WDT_JH7110_UNLOCK_KEY,
139 .int_status = STARFIVE_WDT_JH7110_IMS,
140 .enrst_shift = STARFIVE_WDT_JH7110_RST_EN_SHIFT,
141 .en_shift = STARFIVE_WDT_EN_SHIFT,
142 .intclr_check = false,
143 .double_timeout = true,
146 static int starfive_wdt_enable_clock(struct starfive_wdt *wdt)
150 ret = clk_prepare_enable(wdt->apb_clk);
152 return dev_err_probe(wdt->wdd.parent, ret, "failed to enable apb clock\n");
154 ret = clk_prepare_enable(wdt->core_clk);
156 return dev_err_probe(wdt->wdd.parent, ret, "failed to enable core clock\n");
161 static void starfive_wdt_disable_clock(struct starfive_wdt *wdt)
163 clk_disable_unprepare(wdt->core_clk);
164 clk_disable_unprepare(wdt->apb_clk);
167 static inline int starfive_wdt_get_clock(struct starfive_wdt *wdt)
169 struct device *dev = wdt->wdd.parent;
171 wdt->apb_clk = devm_clk_get(dev, "apb");
172 if (IS_ERR(wdt->apb_clk))
173 return dev_err_probe(dev, PTR_ERR(wdt->apb_clk), "failed to get apb clock\n");
175 wdt->core_clk = devm_clk_get(dev, "core");
176 if (IS_ERR(wdt->core_clk))
177 return dev_err_probe(dev, PTR_ERR(wdt->core_clk), "failed to get core clock\n");
182 static inline int starfive_wdt_reset_init(struct device *dev)
184 struct reset_control *rsts;
187 rsts = devm_reset_control_array_get_exclusive(dev);
189 return dev_err_probe(dev, PTR_ERR(rsts), "failed to get resets\n");
191 ret = reset_control_deassert(rsts);
193 return dev_err_probe(dev, ret, "failed to deassert resets\n");
198 static u32 starfive_wdt_ticks_to_sec(struct starfive_wdt *wdt, u32 ticks)
200 return DIV_ROUND_CLOSEST(ticks, wdt->freq);
203 /* Write unlock-key to unlock. Write other value to lock. */
204 static void starfive_wdt_unlock(struct starfive_wdt *wdt)
205 __acquires(&wdt->lock)
207 spin_lock(&wdt->lock);
208 writel(wdt->variant->unlock_key, wdt->base + wdt->variant->unlock);
211 static void starfive_wdt_lock(struct starfive_wdt *wdt)
212 __releases(&wdt->lock)
214 writel(~wdt->variant->unlock_key, wdt->base + wdt->variant->unlock);
215 spin_unlock(&wdt->lock);
218 /* enable watchdog interrupt to reset/reboot */
219 static void starfive_wdt_enable_reset(struct starfive_wdt *wdt)
223 val = readl(wdt->base + wdt->variant->control);
224 val |= STARFIVE_WDT_RESET_EN << wdt->variant->enrst_shift;
225 writel(val, wdt->base + wdt->variant->control);
228 /* interrupt status whether has been raised from the counter */
229 static bool starfive_wdt_raise_irq_status(struct starfive_wdt *wdt)
231 return !!readl(wdt->base + wdt->variant->int_status);
234 /* waiting interrupt can be free to clear */
235 static int starfive_wdt_wait_int_free(struct starfive_wdt *wdt)
239 return readl_poll_timeout_atomic(wdt->base + wdt->variant->int_clr, value,
240 !(value & BIT(wdt->variant->intclr_ava_shift)),
241 STARFIVE_WDT_DELAY_US, STARFIVE_WDT_TIMEOUT_US);
244 /* clear interrupt signal before initialization or reload */
245 static int starfive_wdt_int_clr(struct starfive_wdt *wdt)
249 if (wdt->variant->intclr_check) {
250 ret = starfive_wdt_wait_int_free(wdt);
252 return dev_err_probe(wdt->wdd.parent, ret,
253 "watchdog is not ready to clear interrupt.\n");
255 writel(STARFIVE_WDT_INTCLR, wdt->base + wdt->variant->int_clr);
260 static inline void starfive_wdt_set_count(struct starfive_wdt *wdt, u32 val)
262 writel(val, wdt->base + wdt->variant->load);
265 static inline u32 starfive_wdt_get_count(struct starfive_wdt *wdt)
267 return readl(wdt->base + wdt->variant->value);
270 /* enable watchdog */
271 static inline void starfive_wdt_enable(struct starfive_wdt *wdt)
275 val = readl(wdt->base + wdt->variant->enable);
276 val |= STARFIVE_WDT_ENABLE << wdt->variant->en_shift;
277 writel(val, wdt->base + wdt->variant->enable);
280 /* disable watchdog */
281 static inline void starfive_wdt_disable(struct starfive_wdt *wdt)
285 val = readl(wdt->base + wdt->variant->enable);
286 val &= ~(STARFIVE_WDT_ENABLE << wdt->variant->en_shift);
287 writel(val, wdt->base + wdt->variant->enable);
290 static inline void starfive_wdt_set_reload_count(struct starfive_wdt *wdt, u32 count)
292 starfive_wdt_set_count(wdt, count);
294 /* 7100 need set any value to reload register and could reload value to counter */
295 if (wdt->variant->reload)
296 writel(0x1, wdt->base + wdt->variant->reload);
299 static unsigned int starfive_wdt_max_timeout(struct starfive_wdt *wdt)
301 if (wdt->variant->double_timeout)
302 return DIV_ROUND_UP(STARFIVE_WDT_MAXCNT, (wdt->freq / 2)) - 1;
304 return DIV_ROUND_UP(STARFIVE_WDT_MAXCNT, wdt->freq) - 1;
307 static unsigned int starfive_wdt_get_timeleft(struct watchdog_device *wdd)
309 struct starfive_wdt *wdt = watchdog_get_drvdata(wdd);
313 * If the watchdog takes twice timeout and set half count value,
314 * timeleft value should add the count value before first timeout.
316 count = starfive_wdt_get_count(wdt);
317 if (wdt->variant->double_timeout && !starfive_wdt_raise_irq_status(wdt))
320 return starfive_wdt_ticks_to_sec(wdt, count);
323 static int starfive_wdt_keepalive(struct watchdog_device *wdd)
325 struct starfive_wdt *wdt = watchdog_get_drvdata(wdd);
328 starfive_wdt_unlock(wdt);
329 ret = starfive_wdt_int_clr(wdt);
333 starfive_wdt_set_reload_count(wdt, wdt->count);
336 /* exit with releasing spinlock and locking registers */
337 starfive_wdt_lock(wdt);
341 static int starfive_wdt_start(struct starfive_wdt *wdt)
345 starfive_wdt_unlock(wdt);
346 /* disable watchdog, to be safe */
347 starfive_wdt_disable(wdt);
349 starfive_wdt_enable_reset(wdt);
350 ret = starfive_wdt_int_clr(wdt);
354 starfive_wdt_set_count(wdt, wdt->count);
355 starfive_wdt_enable(wdt);
358 starfive_wdt_lock(wdt);
362 static void starfive_wdt_stop(struct starfive_wdt *wdt)
364 starfive_wdt_unlock(wdt);
365 starfive_wdt_disable(wdt);
366 starfive_wdt_lock(wdt);
369 static int starfive_wdt_pm_start(struct watchdog_device *wdd)
371 struct starfive_wdt *wdt = watchdog_get_drvdata(wdd);
372 int ret = pm_runtime_get_sync(wdd->parent);
377 return starfive_wdt_start(wdt);
380 static int starfive_wdt_pm_stop(struct watchdog_device *wdd)
382 struct starfive_wdt *wdt = watchdog_get_drvdata(wdd);
384 starfive_wdt_stop(wdt);
385 return pm_runtime_put_sync(wdd->parent);
388 static int starfive_wdt_set_timeout(struct watchdog_device *wdd,
389 unsigned int timeout)
391 struct starfive_wdt *wdt = watchdog_get_drvdata(wdd);
392 unsigned long count = timeout * wdt->freq;
394 /* some watchdogs take two timeouts to reset */
395 if (wdt->variant->double_timeout)
399 wdd->timeout = timeout;
401 starfive_wdt_unlock(wdt);
402 starfive_wdt_disable(wdt);
403 starfive_wdt_set_reload_count(wdt, wdt->count);
404 starfive_wdt_enable(wdt);
405 starfive_wdt_lock(wdt);
410 #define STARFIVE_WDT_OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
412 static const struct watchdog_info starfive_wdt_info = {
413 .options = STARFIVE_WDT_OPTIONS,
414 .identity = "StarFive Watchdog",
417 static const struct watchdog_ops starfive_wdt_ops = {
418 .owner = THIS_MODULE,
419 .start = starfive_wdt_pm_start,
420 .stop = starfive_wdt_pm_stop,
421 .ping = starfive_wdt_keepalive,
422 .set_timeout = starfive_wdt_set_timeout,
423 .get_timeleft = starfive_wdt_get_timeleft,
426 static int starfive_wdt_probe(struct platform_device *pdev)
428 struct starfive_wdt *wdt;
431 wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
435 wdt->base = devm_platform_ioremap_resource(pdev, 0);
436 if (IS_ERR(wdt->base))
437 return dev_err_probe(&pdev->dev, PTR_ERR(wdt->base), "error mapping registers\n");
439 wdt->wdd.parent = &pdev->dev;
440 ret = starfive_wdt_get_clock(wdt);
444 platform_set_drvdata(pdev, wdt);
445 pm_runtime_enable(&pdev->dev);
446 if (pm_runtime_enabled(&pdev->dev)) {
447 ret = pm_runtime_get_sync(&pdev->dev);
451 /* runtime PM is disabled but clocks need to be enabled */
452 ret = starfive_wdt_enable_clock(wdt);
457 ret = starfive_wdt_reset_init(&pdev->dev);
461 watchdog_set_drvdata(&wdt->wdd, wdt);
462 wdt->wdd.info = &starfive_wdt_info;
463 wdt->wdd.ops = &starfive_wdt_ops;
464 wdt->variant = of_device_get_match_data(&pdev->dev);
465 spin_lock_init(&wdt->lock);
467 wdt->freq = clk_get_rate(wdt->core_clk);
469 dev_err(&pdev->dev, "get clock rate failed.\n");
474 wdt->wdd.min_timeout = 1;
475 wdt->wdd.max_timeout = starfive_wdt_max_timeout(wdt);
476 wdt->wdd.timeout = STARFIVE_WDT_DEFAULT_TIME;
477 watchdog_init_timeout(&wdt->wdd, heartbeat, &pdev->dev);
478 starfive_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout);
480 watchdog_set_nowayout(&wdt->wdd, nowayout);
481 watchdog_stop_on_reboot(&wdt->wdd);
482 watchdog_stop_on_unregister(&wdt->wdd);
485 ret = starfive_wdt_start(wdt);
488 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
490 starfive_wdt_stop(wdt);
493 ret = watchdog_register_device(&wdt->wdd);
498 pm_runtime_put_sync(&pdev->dev);
503 starfive_wdt_disable_clock(wdt);
504 pm_runtime_disable(&pdev->dev);
509 static void starfive_wdt_remove(struct platform_device *pdev)
511 struct starfive_wdt *wdt = platform_get_drvdata(pdev);
513 starfive_wdt_stop(wdt);
514 watchdog_unregister_device(&wdt->wdd);
516 if (pm_runtime_enabled(&pdev->dev))
517 pm_runtime_disable(&pdev->dev);
519 /* disable clock without PM */
520 starfive_wdt_disable_clock(wdt);
523 static void starfive_wdt_shutdown(struct platform_device *pdev)
525 struct starfive_wdt *wdt = platform_get_drvdata(pdev);
527 starfive_wdt_pm_stop(&wdt->wdd);
530 static int starfive_wdt_suspend(struct device *dev)
532 struct starfive_wdt *wdt = dev_get_drvdata(dev);
534 /* Save watchdog state, and turn it off. */
535 wdt->reload = starfive_wdt_get_count(wdt);
537 /* Note that WTCNT doesn't need to be saved. */
538 starfive_wdt_stop(wdt);
540 return pm_runtime_force_suspend(dev);
543 static int starfive_wdt_resume(struct device *dev)
545 struct starfive_wdt *wdt = dev_get_drvdata(dev);
548 ret = pm_runtime_force_resume(dev);
552 starfive_wdt_unlock(wdt);
553 /* Restore watchdog state. */
554 starfive_wdt_set_reload_count(wdt, wdt->reload);
555 starfive_wdt_lock(wdt);
557 return starfive_wdt_start(wdt);
560 static int starfive_wdt_runtime_suspend(struct device *dev)
562 struct starfive_wdt *wdt = dev_get_drvdata(dev);
564 starfive_wdt_disable_clock(wdt);
569 static int starfive_wdt_runtime_resume(struct device *dev)
571 struct starfive_wdt *wdt = dev_get_drvdata(dev);
573 return starfive_wdt_enable_clock(wdt);
576 static const struct dev_pm_ops starfive_wdt_pm_ops = {
577 RUNTIME_PM_OPS(starfive_wdt_runtime_suspend, starfive_wdt_runtime_resume, NULL)
578 SYSTEM_SLEEP_PM_OPS(starfive_wdt_suspend, starfive_wdt_resume)
581 static const struct of_device_id starfive_wdt_match[] = {
582 { .compatible = "starfive,jh7100-wdt", .data = &starfive_wdt_jh7100_variant },
583 { .compatible = "starfive,jh7110-wdt", .data = &starfive_wdt_jh7110_variant },
586 MODULE_DEVICE_TABLE(of, starfive_wdt_match);
588 static struct platform_driver starfive_wdt_driver = {
589 .probe = starfive_wdt_probe,
590 .remove_new = starfive_wdt_remove,
591 .shutdown = starfive_wdt_shutdown,
593 .name = "starfive-wdt",
594 .pm = pm_ptr(&starfive_wdt_pm_ops),
595 .of_match_table = starfive_wdt_match,
598 module_platform_driver(starfive_wdt_driver);
600 MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
601 MODULE_AUTHOR("Samin Guo <samin.guo@starfivetech.com>");
602 MODULE_DESCRIPTION("StarFive Watchdog Device Driver");
603 MODULE_LICENSE("GPL");