drivers/watchdog/rzg2l_wdt.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Renesas RZ/G2L WDT Watchdog Driver
   4  *
   5  * Copyright (C) 2021 Renesas Electronics Corporation
   6  */
   7 #include <linux/bitops.h>
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/io.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/reset.h>
  17 #include <linux/units.h>
  18 #include <linux/watchdog.h>
  19
  20 #define WDTCNT          0x00
  21 #define WDTSET          0x04
  22 #define WDTTIM          0x08
  23 #define WDTINT          0x0C
  24 #define WDTCNT_WDTEN    BIT(0)
  25 #define WDTINT_INTDISP  BIT(0)
  26
  27 #define WDT_DEFAULT_TIMEOUT             60U
  28
  29 /* Setting period time register only 12 bit set in WDTSET[31:20] */
  30 #define WDTSET_COUNTER_MASK             (0xFFF00000)
  31 #define WDTSET_COUNTER_VAL(f)           ((f) << 20)
  32
  33 #define F2CYCLE_NSEC(f)                 (1000000000 / (f))
  34
  35 static bool nowayout = WATCHDOG_NOWAYOUT;
  36 module_param(nowayout, bool, 0);
  37 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  38                                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  39
  40 struct rzg2l_wdt_priv {
  41         void __iomem *base;
  42         struct watchdog_device wdev;
  43         struct reset_control *rstc;
  44         unsigned long osc_clk_rate;
  45         unsigned long delay;
  46 };
  47
  48 static void rzg2l_wdt_wait_delay(struct rzg2l_wdt_priv *priv)
  49 {
  50         /* delay timer when change the setting register */
  51         ndelay(priv->delay);
  52 }
  53
  54 static u32 rzg2l_wdt_get_cycle_usec(unsigned long cycle, u32 wdttime)
  55 {
  56         u64 timer_cycle_us = 1024 * 1024 * (wdttime + 1) * MICRO;
  57
  58         return div64_ul(timer_cycle_us, cycle);
  59 }
  60
  61 static void rzg2l_wdt_write(struct rzg2l_wdt_priv *priv, u32 val, unsigned int reg)
  62 {
  63         if (reg == WDTSET)
  64                 val &= WDTSET_COUNTER_MASK;
  65
  66         writel_relaxed(val, priv->base + reg);
  67         /* Registers other than the WDTINT is always synchronized with WDT_CLK */
  68         if (reg != WDTINT)
  69                 rzg2l_wdt_wait_delay(priv);
  70 }
  71
  72 static void rzg2l_wdt_init_timeout(struct watchdog_device *wdev)
  73 {
  74         struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
  75         u32 time_out;
  76
  77         /* Clear Lapsed Time Register and clear Interrupt */
  78         rzg2l_wdt_write(priv, WDTINT_INTDISP, WDTINT);
  79         /* 2 consecutive overflow cycle needed to trigger reset */
  80         time_out = (wdev->timeout * (MICRO / 2)) /
  81                    rzg2l_wdt_get_cycle_usec(priv->osc_clk_rate, 0);
  82         rzg2l_wdt_write(priv, WDTSET_COUNTER_VAL(time_out), WDTSET);
  83 }
  84
  85 static int rzg2l_wdt_start(struct watchdog_device *wdev)
  86 {
  87         struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
  88
  89         reset_control_deassert(priv->rstc);
  90         pm_runtime_get_sync(wdev->parent);
  91
  92         /* Initialize time out */
  93         rzg2l_wdt_init_timeout(wdev);
  94
  95         /* Initialize watchdog counter register */
  96         rzg2l_wdt_write(priv, 0, WDTTIM);
  97
  98         /* Enable watchdog timer*/
  99         rzg2l_wdt_write(priv, WDTCNT_WDTEN, WDTCNT);
 100
 101         return 0;
 102 }
 103
 104 static int rzg2l_wdt_stop(struct watchdog_device *wdev)
 105 {
 106         struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
 107
 108         pm_runtime_put(wdev->parent);
 109         reset_control_assert(priv->rstc);
 110
 111         return 0;
 112 }
 113
 114 static int rzg2l_wdt_restart(struct watchdog_device *wdev,
 115                              unsigned long action, void *data)
 116 {
 117         struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
 118
 119         /* Reset the module before we modify any register */
 120         reset_control_reset(priv->rstc);
 121         pm_runtime_get_sync(wdev->parent);
 122
 123         /* smallest counter value to reboot soon */
 124         rzg2l_wdt_write(priv, WDTSET_COUNTER_VAL(1), WDTSET);
 125
 126         /* Enable watchdog timer*/
 127         rzg2l_wdt_write(priv, WDTCNT_WDTEN, WDTCNT);
 128
 129         return 0;
 130 }
 131
 132 static const struct watchdog_info rzg2l_wdt_ident = {
 133         .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
 134         .identity = "Renesas RZ/G2L WDT Watchdog",
 135 };
 136
 137 static int rzg2l_wdt_ping(struct watchdog_device *wdev)
 138 {
 139         struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
 140
 141         rzg2l_wdt_write(priv, WDTINT_INTDISP, WDTINT);
 142
 143         return 0;
 144 }
 145
 146 static const struct watchdog_ops rzg2l_wdt_ops = {
 147         .owner = THIS_MODULE,
 148         .start = rzg2l_wdt_start,
 149         .stop = rzg2l_wdt_stop,
 150         .ping = rzg2l_wdt_ping,
 151         .restart = rzg2l_wdt_restart,
 152 };
 153
 154 static void rzg2l_wdt_reset_assert_pm_disable_put(void *data)
 155 {
 156         struct watchdog_device *wdev = data;
 157         struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
 158
 159         pm_runtime_put(wdev->parent);
 160         pm_runtime_disable(wdev->parent);
 161         reset_control_assert(priv->rstc);
 162 }
 163
 164 static int rzg2l_wdt_probe(struct platform_device *pdev)
 165 {
 166         struct device *dev = &pdev->dev;
 167         struct rzg2l_wdt_priv *priv;
 168         unsigned long pclk_rate;
 169         struct clk *wdt_clk;
 170         int ret;
 171
 172         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 173         if (!priv)
 174                 return -ENOMEM;
 175
 176         priv->base = devm_platform_ioremap_resource(pdev, 0);
 177         if (IS_ERR(priv->base))
 178                 return PTR_ERR(priv->base);
 179
 180         /* Get watchdog main clock */
 181         wdt_clk = clk_get(&pdev->dev, "oscclk");
 182         if (IS_ERR(wdt_clk))
 183                 return dev_err_probe(&pdev->dev, PTR_ERR(wdt_clk), "no oscclk");
 184
 185         priv->osc_clk_rate = clk_get_rate(wdt_clk);
 186         clk_put(wdt_clk);
 187         if (!priv->osc_clk_rate)
 188                 return dev_err_probe(&pdev->dev, -EINVAL, "oscclk rate is 0");
 189
 190         /* Get Peripheral clock */
 191         wdt_clk = clk_get(&pdev->dev, "pclk");
 192         if (IS_ERR(wdt_clk))
 193                 return dev_err_probe(&pdev->dev, PTR_ERR(wdt_clk), "no pclk");
 194
 195         pclk_rate = clk_get_rate(wdt_clk);
 196         clk_put(wdt_clk);
 197         if (!pclk_rate)
 198                 return dev_err_probe(&pdev->dev, -EINVAL, "pclk rate is 0");
 199
 200         priv->delay = F2CYCLE_NSEC(priv->osc_clk_rate) * 6 + F2CYCLE_NSEC(pclk_rate) * 9;
 201
 202         priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
 203         if (IS_ERR(priv->rstc))
 204                 return dev_err_probe(&pdev->dev, PTR_ERR(priv->rstc),
 205                                      "failed to get cpg reset");
 206
 207         reset_control_deassert(priv->rstc);
 208         pm_runtime_enable(&pdev->dev);
 209         ret = pm_runtime_resume_and_get(&pdev->dev);
 210         if (ret < 0) {
 211                 dev_err(dev, "pm_runtime_resume_and_get failed ret=%pe", ERR_PTR(ret));
 212                 goto out_pm_get;
 213         }
 214
 215         priv->wdev.info = &rzg2l_wdt_ident;
 216         priv->wdev.ops = &rzg2l_wdt_ops;
 217         priv->wdev.parent = dev;
 218         priv->wdev.min_timeout = 1;
 219         priv->wdev.max_timeout = rzg2l_wdt_get_cycle_usec(priv->osc_clk_rate, 0xfff) /
 220                                  USEC_PER_SEC;
 221         priv->wdev.timeout = WDT_DEFAULT_TIMEOUT;
 222
 223         watchdog_set_drvdata(&priv->wdev, priv);
 224         ret = devm_add_action_or_reset(&pdev->dev,
 225                                        rzg2l_wdt_reset_assert_pm_disable_put,
 226                                        &priv->wdev);
 227         if (ret < 0)
 228                 return ret;
 229
 230         watchdog_set_nowayout(&priv->wdev, nowayout);
 231         watchdog_stop_on_unregister(&priv->wdev);
 232
 233         ret = watchdog_init_timeout(&priv->wdev, 0, dev);
 234         if (ret)
 235                 dev_warn(dev, "Specified timeout invalid, using default");
 236
 237         return devm_watchdog_register_device(&pdev->dev, &priv->wdev);
 238
 239 out_pm_get:
 240         pm_runtime_disable(dev);
 241         reset_control_assert(priv->rstc);
 242
 243         return ret;
 244 }
 245
 246 static const struct of_device_id rzg2l_wdt_ids[] = {
 247         { .compatible = "renesas,rzg2l-wdt", },
 248         { /* sentinel */ }
 249 };
 250 MODULE_DEVICE_TABLE(of, rzg2l_wdt_ids);
 251
 252 static struct platform_driver rzg2l_wdt_driver = {
 253         .driver = {
 254                 .name = "rzg2l_wdt",
 255                 .of_match_table = rzg2l_wdt_ids,
 256         },
 257         .probe = rzg2l_wdt_probe,
 258 };
 259 module_platform_driver(rzg2l_wdt_driver);
 260
 261 MODULE_DESCRIPTION("Renesas RZ/G2L WDT Watchdog Driver");
 262 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
 263 MODULE_LICENSE("GPL v2");