drivers/watchdog/renesas_wdt.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Watchdog driver for Renesas WDT watchdog
   4  *
   5  * Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
   6  * Copyright (C) 2015-17 Renesas Electronics Corporation
   7  */
   8 #include <linux/bitops.h>
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/io.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/smp.h>
  19 #include <linux/sys_soc.h>
  20 #include <linux/watchdog.h>
  21
  22 #define RWTCNT          0
  23 #define RWTCSRA         4
  24 #define RWTCSRA_WOVF    BIT(4)
  25 #define RWTCSRA_WRFLG   BIT(5)
  26 #define RWTCSRA_TME     BIT(7)
  27 #define RWTCSRB         8
  28
  29 #define RWDT_DEFAULT_TIMEOUT 60U
  30
  31 /*
  32  * In probe, clk_rate is checked to be not more than 16 bit * biggest clock
  33  * divider (12 bits). d is only a factor to fully utilize the WDT counter and
  34  * will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits.
  35  */
  36 #define MUL_BY_CLKS_PER_SEC(p, d) \
  37         DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
  38
  39 /* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
  40 #define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
  41
  42 static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024, 4096 };
  43
  44 static bool nowayout = WATCHDOG_NOWAYOUT;
  45 module_param(nowayout, bool, 0);
  46 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  47                                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  48
  49 struct rwdt_priv {
  50         void __iomem *base;
  51         struct watchdog_device wdev;
  52         unsigned long clk_rate;
  53         u8 cks;
  54         struct clk *clk;
  55 };
  56
  57 static void rwdt_write(struct rwdt_priv *priv, u32 val, unsigned int reg)
  58 {
  59         if (reg == RWTCNT)
  60                 val |= 0x5a5a0000;
  61         else
  62                 val |= 0xa5a5a500;
  63
  64         writel_relaxed(val, priv->base + reg);
  65 }
  66
  67 static int rwdt_init_timeout(struct watchdog_device *wdev)
  68 {
  69         struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
  70
  71         rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT);
  72
  73         return 0;
  74 }
  75
  76 static void rwdt_wait_cycles(struct rwdt_priv *priv, unsigned int cycles)
  77 {
  78         unsigned int delay;
  79
  80         delay = DIV_ROUND_UP(cycles * 1000000, priv->clk_rate);
  81
  82         usleep_range(delay, 2 * delay);
  83 }
  84
  85 static int rwdt_start(struct watchdog_device *wdev)
  86 {
  87         struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
  88         u8 val;
  89
  90         pm_runtime_get_sync(wdev->parent);
  91
  92         /* Stop the timer before we modify any register */
  93         val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
  94         rwdt_write(priv, val, RWTCSRA);
  95         /* Delay 2 cycles before setting watchdog counter */
  96         rwdt_wait_cycles(priv, 2);
  97
  98         rwdt_init_timeout(wdev);
  99         rwdt_write(priv, priv->cks, RWTCSRA);
 100         rwdt_write(priv, 0, RWTCSRB);
 101
 102         while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG)
 103                 cpu_relax();
 104
 105         rwdt_write(priv, priv->cks | RWTCSRA_TME, RWTCSRA);
 106
 107         return 0;
 108 }
 109
 110 static int rwdt_stop(struct watchdog_device *wdev)
 111 {
 112         struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
 113
 114         rwdt_write(priv, priv->cks, RWTCSRA);
 115         /* Delay 3 cycles before disabling module clock */
 116         rwdt_wait_cycles(priv, 3);
 117         pm_runtime_put(wdev->parent);
 118
 119         return 0;
 120 }
 121
 122 static unsigned int rwdt_get_timeleft(struct watchdog_device *wdev)
 123 {
 124         struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
 125         u16 val = readw_relaxed(priv->base + RWTCNT);
 126
 127         return DIV_BY_CLKS_PER_SEC(priv, 65536 - val);
 128 }
 129
 130 /* needs to be atomic - no RPM, no usleep_range, no scheduling! */
 131 static int rwdt_restart(struct watchdog_device *wdev, unsigned long action,
 132                         void *data)
 133 {
 134         struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
 135         u8 val;
 136
 137         clk_prepare_enable(priv->clk);
 138
 139         /* Stop the timer before we modify any register */
 140         val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
 141         rwdt_write(priv, val, RWTCSRA);
 142         /* Delay 2 cycles before setting watchdog counter */
 143         udelay(DIV_ROUND_UP(2 * 1000000, priv->clk_rate));
 144
 145         rwdt_write(priv, 0xffff, RWTCNT);
 146         /* smallest divider to reboot soon */
 147         rwdt_write(priv, 0, RWTCSRA);
 148
 149         readb_poll_timeout_atomic(priv->base + RWTCSRA, val,
 150                                   !(val & RWTCSRA_WRFLG), 1, 100);
 151
 152         rwdt_write(priv, RWTCSRA_TME, RWTCSRA);
 153
 154         return 0;
 155 }
 156
 157 static const struct watchdog_info rwdt_ident = {
 158         .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
 159                 WDIOF_CARDRESET,
 160         .identity = "Renesas WDT Watchdog",
 161 };
 162
 163 static const struct watchdog_ops rwdt_ops = {
 164         .owner = THIS_MODULE,
 165         .start = rwdt_start,
 166         .stop = rwdt_stop,
 167         .ping = rwdt_init_timeout,
 168         .get_timeleft = rwdt_get_timeleft,
 169         .restart = rwdt_restart,
 170 };
 171
 172 #if defined(CONFIG_ARCH_RCAR_GEN2) && defined(CONFIG_SMP)
 173 /*
 174  * Watchdog-reset integration is broken on early revisions of R-Car Gen2 SoCs
 175  */
 176 static const struct soc_device_attribute rwdt_quirks_match[] = {
 177         {
 178                 .soc_id = "r8a7790",
 179                 .revision = "ES1.*",
 180                 .data = (void *)1,      /* needs single CPU */
 181         }, {
 182                 .soc_id = "r8a7791",
 183                 .revision = "ES1.*",
 184                 .data = (void *)1,      /* needs single CPU */
 185         }, {
 186                 .soc_id = "r8a7792",
 187                 .data = (void *)0,      /* needs SMP disabled */
 188         },
 189         { /* sentinel */ }
 190 };
 191
 192 static bool rwdt_blacklisted(struct device *dev)
 193 {
 194         const struct soc_device_attribute *attr;
 195
 196         attr = soc_device_match(rwdt_quirks_match);
 197         if (attr && setup_max_cpus > (uintptr_t)attr->data) {
 198                 dev_info(dev, "Watchdog blacklisted on %s %s\n", attr->soc_id,
 199                          attr->revision);
 200                 return true;
 201         }
 202
 203         return false;
 204 }
 205 #else /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */
 206 static inline bool rwdt_blacklisted(struct device *dev) { return false; }
 207 #endif /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */
 208
 209 static int rwdt_probe(struct platform_device *pdev)
 210 {
 211         struct device *dev = &pdev->dev;
 212         struct rwdt_priv *priv;
 213         unsigned long clks_per_sec;
 214         int ret, i;
 215         u8 csra;
 216
 217         if (rwdt_blacklisted(dev))
 218                 return -ENODEV;
 219
 220         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 221         if (!priv)
 222                 return -ENOMEM;
 223
 224         priv->base = devm_platform_ioremap_resource(pdev, 0);
 225         if (IS_ERR(priv->base))
 226                 return PTR_ERR(priv->base);
 227
 228         priv->clk = devm_clk_get(dev, NULL);
 229         if (IS_ERR(priv->clk))
 230                 return PTR_ERR(priv->clk);
 231
 232         pm_runtime_enable(dev);
 233         pm_runtime_get_sync(dev);
 234         priv->clk_rate = clk_get_rate(priv->clk);
 235         csra = readb_relaxed(priv->base + RWTCSRA);
 236         priv->wdev.bootstatus = csra & RWTCSRA_WOVF ? WDIOF_CARDRESET : 0;
 237         pm_runtime_put(dev);
 238
 239         if (!priv->clk_rate) {
 240                 ret = -ENOENT;
 241                 goto out_pm_disable;
 242         }
 243
 244         for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) {
 245                 clks_per_sec = priv->clk_rate / clk_divs[i];
 246                 if (clks_per_sec && clks_per_sec < 65536) {
 247                         priv->cks = i;
 248                         break;
 249                 }
 250         }
 251
 252         if (i < 0) {
 253                 dev_err(dev, "Can't find suitable clock divider\n");
 254                 ret = -ERANGE;
 255                 goto out_pm_disable;
 256         }
 257
 258         priv->wdev.info = &rwdt_ident;
 259         priv->wdev.ops = &rwdt_ops;
 260         priv->wdev.parent = dev;
 261         priv->wdev.min_timeout = 1;
 262         priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536);
 263         priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT);
 264
 265         platform_set_drvdata(pdev, priv);
 266         watchdog_set_drvdata(&priv->wdev, priv);
 267         watchdog_set_nowayout(&priv->wdev, nowayout);
 268         watchdog_set_restart_priority(&priv->wdev, 0);
 269         watchdog_stop_on_unregister(&priv->wdev);
 270
 271         /* This overrides the default timeout only if DT configuration was found */
 272         watchdog_init_timeout(&priv->wdev, 0, dev);
 273
 274         /* Check if FW enabled the watchdog */
 275         if (csra & RWTCSRA_TME) {
 276                 /* Ensure properly initialized dividers */
 277                 rwdt_start(&priv->wdev);
 278                 set_bit(WDOG_HW_RUNNING, &priv->wdev.status);
 279         }
 280
 281         ret = watchdog_register_device(&priv->wdev);
 282         if (ret < 0)
 283                 goto out_pm_disable;
 284
 285         return 0;
 286
 287  out_pm_disable:
 288         pm_runtime_disable(dev);
 289         return ret;
 290 }
 291
 292 static int rwdt_remove(struct platform_device *pdev)
 293 {
 294         struct rwdt_priv *priv = platform_get_drvdata(pdev);
 295
 296         watchdog_unregister_device(&priv->wdev);
 297         pm_runtime_disable(&pdev->dev);
 298
 299         return 0;
 300 }
 301
 302 static int __maybe_unused rwdt_suspend(struct device *dev)
 303 {
 304         struct rwdt_priv *priv = dev_get_drvdata(dev);
 305
 306         if (watchdog_active(&priv->wdev))
 307                 rwdt_stop(&priv->wdev);
 308
 309         return 0;
 310 }
 311
 312 static int __maybe_unused rwdt_resume(struct device *dev)
 313 {
 314         struct rwdt_priv *priv = dev_get_drvdata(dev);
 315
 316         if (watchdog_active(&priv->wdev))
 317                 rwdt_start(&priv->wdev);
 318
 319         return 0;
 320 }
 321
 322 static SIMPLE_DEV_PM_OPS(rwdt_pm_ops, rwdt_suspend, rwdt_resume);
 323
 324 static const struct of_device_id rwdt_ids[] = {
 325         { .compatible = "renesas,rcar-gen2-wdt", },
 326         { .compatible = "renesas,rcar-gen3-wdt", },
 327         { /* sentinel */ }
 328 };
 329 MODULE_DEVICE_TABLE(of, rwdt_ids);
 330
 331 static struct platform_driver rwdt_driver = {
 332         .driver = {
 333                 .name = "renesas_wdt",
 334                 .of_match_table = rwdt_ids,
 335                 .pm = &rwdt_pm_ops,
 336         },
 337         .probe = rwdt_probe,
 338         .remove = rwdt_remove,
 339 };
 340 module_platform_driver(rwdt_driver);
 341
 342 MODULE_DESCRIPTION("Renesas WDT Watchdog Driver");
 343 MODULE_LICENSE("GPL v2");
 344 MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");