2 * drivers/char/watchdog/davinci_wdt.c
4 * Watchdog driver for DaVinci DM644x/DM646x processors
6 * Copyright (C) 2006-2013 Texas Instruments.
8 * 2007 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/watchdog.h>
20 #include <linux/platform_device.h>
22 #include <linux/device.h>
23 #include <linux/clk.h>
24 #include <linux/err.h>
26 #define MODULE_NAME "DAVINCI-WDT: "
28 #define DEFAULT_HEARTBEAT 60
29 #define MAX_HEARTBEAT 600 /* really the max margin is 264/27MHz*/
31 /* Timer register set definition */
42 /* TCR bit definitions */
43 #define ENAMODE12_DISABLED (0 << 6)
44 #define ENAMODE12_ONESHOT (1 << 6)
45 #define ENAMODE12_PERIODIC (2 << 6)
47 /* TGCR bit definitions */
48 #define TIM12RS_UNRESET (1 << 0)
49 #define TIM34RS_UNRESET (1 << 1)
50 #define TIMMODE_64BIT_WDOG (2 << 2)
52 /* WDTCR bit definitions */
53 #define WDEN (1 << 14)
54 #define WDFLAG (1 << 15)
55 #define WDKEY_SEQ0 (0xa5c6 << 16)
56 #define WDKEY_SEQ1 (0xda7e << 16)
61 * struct to hold data for each WDT device
62 * @base - base io address of WD device
63 * @clk - source clock of WDT
64 * @wdd - hold watchdog device as is in WDT core
66 struct davinci_wdt_device {
69 struct watchdog_device wdd;
72 static int davinci_wdt_start(struct watchdog_device *wdd)
76 unsigned long wdt_freq;
77 struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
79 wdt_freq = clk_get_rate(davinci_wdt->clk);
81 /* disable, internal clock source */
82 iowrite32(0, davinci_wdt->base + TCR);
83 /* reset timer, set mode to 64-bit watchdog, and unreset */
84 iowrite32(0, davinci_wdt->base + TGCR);
85 tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
86 iowrite32(tgcr, davinci_wdt->base + TGCR);
87 /* clear counter regs */
88 iowrite32(0, davinci_wdt->base + TIM12);
89 iowrite32(0, davinci_wdt->base + TIM34);
90 /* set timeout period */
91 timer_margin = (((u64)wdd->timeout * wdt_freq) & 0xffffffff);
92 iowrite32(timer_margin, davinci_wdt->base + PRD12);
93 timer_margin = (((u64)wdd->timeout * wdt_freq) >> 32);
94 iowrite32(timer_margin, davinci_wdt->base + PRD34);
95 /* enable run continuously */
96 iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR);
97 /* Once the WDT is in pre-active state write to
98 * TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
99 * write protected (except for the WDKEY field)
101 /* put watchdog in pre-active state */
102 iowrite32(WDKEY_SEQ0 | WDEN, davinci_wdt->base + WDTCR);
103 /* put watchdog in active state */
104 iowrite32(WDKEY_SEQ1 | WDEN, davinci_wdt->base + WDTCR);
108 static int davinci_wdt_ping(struct watchdog_device *wdd)
110 struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
112 /* put watchdog in service state */
113 iowrite32(WDKEY_SEQ0, davinci_wdt->base + WDTCR);
114 /* put watchdog in active state */
115 iowrite32(WDKEY_SEQ1, davinci_wdt->base + WDTCR);
119 static unsigned int davinci_wdt_get_timeleft(struct watchdog_device *wdd)
124 struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
126 /* if timeout has occured then return 0 */
127 val = ioread32(davinci_wdt->base + WDTCR);
131 freq = clk_get_rate(davinci_wdt->clk);
136 timer_counter = ioread32(davinci_wdt->base + TIM12);
137 timer_counter |= ((u64)ioread32(davinci_wdt->base + TIM34) << 32);
139 do_div(timer_counter, freq);
141 return wdd->timeout - timer_counter;
144 static int davinci_wdt_restart(struct watchdog_device *wdd,
145 unsigned long action, void *data)
147 struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
150 /* disable, internal clock source */
151 iowrite32(0, davinci_wdt->base + TCR);
153 /* reset timer, set mode to 64-bit watchdog, and unreset */
155 iowrite32(tgcr, davinci_wdt->base + TGCR);
156 tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
157 iowrite32(tgcr, davinci_wdt->base + TGCR);
159 /* clear counter and period regs */
160 iowrite32(0, davinci_wdt->base + TIM12);
161 iowrite32(0, davinci_wdt->base + TIM34);
162 iowrite32(0, davinci_wdt->base + PRD12);
163 iowrite32(0, davinci_wdt->base + PRD34);
165 /* put watchdog in pre-active state */
166 wdtcr = WDKEY_SEQ0 | WDEN;
167 iowrite32(wdtcr, davinci_wdt->base + WDTCR);
169 /* put watchdog in active state */
170 wdtcr = WDKEY_SEQ1 | WDEN;
171 iowrite32(wdtcr, davinci_wdt->base + WDTCR);
173 /* write an invalid value to the WDKEY field to trigger a restart */
175 iowrite32(wdtcr, davinci_wdt->base + WDTCR);
180 static const struct watchdog_info davinci_wdt_info = {
181 .options = WDIOF_KEEPALIVEPING,
182 .identity = "DaVinci/Keystone Watchdog",
185 static const struct watchdog_ops davinci_wdt_ops = {
186 .owner = THIS_MODULE,
187 .start = davinci_wdt_start,
188 .stop = davinci_wdt_ping,
189 .ping = davinci_wdt_ping,
190 .get_timeleft = davinci_wdt_get_timeleft,
191 .restart = davinci_wdt_restart,
194 static int davinci_wdt_probe(struct platform_device *pdev)
197 struct device *dev = &pdev->dev;
198 struct watchdog_device *wdd;
199 struct davinci_wdt_device *davinci_wdt;
201 davinci_wdt = devm_kzalloc(dev, sizeof(*davinci_wdt), GFP_KERNEL);
205 davinci_wdt->clk = devm_clk_get(dev, NULL);
207 if (IS_ERR(davinci_wdt->clk)) {
208 if (PTR_ERR(davinci_wdt->clk) != -EPROBE_DEFER)
209 dev_err(&pdev->dev, "failed to get clock node\n");
210 return PTR_ERR(davinci_wdt->clk);
213 ret = clk_prepare_enable(davinci_wdt->clk);
215 dev_err(&pdev->dev, "failed to prepare clock\n");
219 platform_set_drvdata(pdev, davinci_wdt);
221 wdd = &davinci_wdt->wdd;
222 wdd->info = &davinci_wdt_info;
223 wdd->ops = &davinci_wdt_ops;
224 wdd->min_timeout = 1;
225 wdd->max_timeout = MAX_HEARTBEAT;
226 wdd->timeout = DEFAULT_HEARTBEAT;
227 wdd->parent = &pdev->dev;
229 watchdog_init_timeout(wdd, heartbeat, dev);
231 dev_info(dev, "heartbeat %d sec\n", wdd->timeout);
233 watchdog_set_drvdata(wdd, davinci_wdt);
234 watchdog_set_nowayout(wdd, 1);
235 watchdog_set_restart_priority(wdd, 128);
237 davinci_wdt->base = devm_platform_ioremap_resource(pdev, 0);
238 if (IS_ERR(davinci_wdt->base)) {
239 ret = PTR_ERR(davinci_wdt->base);
240 goto err_clk_disable;
243 ret = watchdog_register_device(wdd);
245 dev_err(dev, "cannot register watchdog device\n");
246 goto err_clk_disable;
252 clk_disable_unprepare(davinci_wdt->clk);
257 static int davinci_wdt_remove(struct platform_device *pdev)
259 struct davinci_wdt_device *davinci_wdt = platform_get_drvdata(pdev);
261 watchdog_unregister_device(&davinci_wdt->wdd);
262 clk_disable_unprepare(davinci_wdt->clk);
267 static const struct of_device_id davinci_wdt_of_match[] = {
268 { .compatible = "ti,davinci-wdt", },
271 MODULE_DEVICE_TABLE(of, davinci_wdt_of_match);
273 static struct platform_driver platform_wdt_driver = {
275 .name = "davinci-wdt",
276 .of_match_table = davinci_wdt_of_match,
278 .probe = davinci_wdt_probe,
279 .remove = davinci_wdt_remove,
282 module_platform_driver(platform_wdt_driver);
284 MODULE_AUTHOR("Texas Instruments");
285 MODULE_DESCRIPTION("DaVinci Watchdog Driver");
287 module_param(heartbeat, int, 0);
288 MODULE_PARM_DESC(heartbeat,
289 "Watchdog heartbeat period in seconds from 1 to "
290 __MODULE_STRING(MAX_HEARTBEAT) ", default "
291 __MODULE_STRING(DEFAULT_HEARTBEAT));
293 MODULE_LICENSE("GPL");
294 MODULE_ALIAS("platform:davinci-wdt");