2 * drivers/w1/masters/omap_hdq.c
4 * Copyright (C) 2007 Texas Instruments, Inc.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/interrupt.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
21 #include <mach/hardware.h>
24 #include "../w1_int.h"
26 #define MOD_NAME "OMAP_HDQ:"
28 #define OMAP_HDQ_REVISION 0x00
29 #define OMAP_HDQ_TX_DATA 0x04
30 #define OMAP_HDQ_RX_DATA 0x08
31 #define OMAP_HDQ_CTRL_STATUS 0x0c
32 #define OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK (1<<6)
33 #define OMAP_HDQ_CTRL_STATUS_CLOCKENABLE (1<<5)
34 #define OMAP_HDQ_CTRL_STATUS_GO (1<<4)
35 #define OMAP_HDQ_CTRL_STATUS_INITIALIZATION (1<<2)
36 #define OMAP_HDQ_CTRL_STATUS_DIR (1<<1)
37 #define OMAP_HDQ_CTRL_STATUS_MODE (1<<0)
38 #define OMAP_HDQ_INT_STATUS 0x10
39 #define OMAP_HDQ_INT_STATUS_TXCOMPLETE (1<<2)
40 #define OMAP_HDQ_INT_STATUS_RXCOMPLETE (1<<1)
41 #define OMAP_HDQ_INT_STATUS_TIMEOUT (1<<0)
42 #define OMAP_HDQ_SYSCONFIG 0x14
43 #define OMAP_HDQ_SYSCONFIG_SOFTRESET (1<<1)
44 #define OMAP_HDQ_SYSCONFIG_AUTOIDLE (1<<0)
45 #define OMAP_HDQ_SYSSTATUS 0x18
46 #define OMAP_HDQ_SYSSTATUS_RESETDONE (1<<0)
48 #define OMAP_HDQ_FLAG_CLEAR 0
49 #define OMAP_HDQ_FLAG_SET 1
50 #define OMAP_HDQ_TIMEOUT (HZ/5)
52 #define OMAP_HDQ_MAX_USER 4
54 static DECLARE_WAIT_QUEUE_HEAD(hdq_wait_queue);
59 void __iomem *hdq_base;
60 /* lock status update */
61 struct mutex hdq_mutex;
67 spinlock_t hdq_spinlock;
69 * Used to control the call to omap_hdq_get and omap_hdq_put.
70 * HDQ Protocol: Write the CMD|REG_address first, followed by
71 * the data wrire or read.
76 static int __devinit omap_hdq_probe(struct platform_device *pdev);
77 static int omap_hdq_remove(struct platform_device *pdev);
79 static struct platform_driver omap_hdq_driver = {
80 .probe = omap_hdq_probe,
81 .remove = omap_hdq_remove,
87 static u8 omap_w1_read_byte(void *_hdq);
88 static void omap_w1_write_byte(void *_hdq, u8 byte);
89 static u8 omap_w1_reset_bus(void *_hdq);
90 static void omap_w1_search_bus(void *_hdq, struct w1_master *master_dev,
91 u8 search_type, w1_slave_found_callback slave_found);
94 static struct w1_bus_master omap_w1_master = {
95 .read_byte = omap_w1_read_byte,
96 .write_byte = omap_w1_write_byte,
97 .reset_bus = omap_w1_reset_bus,
98 .search = omap_w1_search_bus,
101 /* HDQ register I/O routines */
102 static inline u8 hdq_reg_in(struct hdq_data *hdq_data, u32 offset)
104 return __raw_readb(hdq_data->hdq_base + offset);
107 static inline void hdq_reg_out(struct hdq_data *hdq_data, u32 offset, u8 val)
109 __raw_writeb(val, hdq_data->hdq_base + offset);
112 static inline u8 hdq_reg_merge(struct hdq_data *hdq_data, u32 offset,
115 u8 new_val = (__raw_readb(hdq_data->hdq_base + offset) & ~mask)
117 __raw_writeb(new_val, hdq_data->hdq_base + offset);
123 * Wait for one or more bits in flag change.
124 * HDQ_FLAG_SET: wait until any bit in the flag is set.
125 * HDQ_FLAG_CLEAR: wait until all bits in the flag are cleared.
126 * return 0 on success and -ETIMEDOUT in the case of timeout.
128 static int hdq_wait_for_flag(struct hdq_data *hdq_data, u32 offset,
129 u8 flag, u8 flag_set, u8 *status)
132 unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
134 if (flag_set == OMAP_HDQ_FLAG_CLEAR) {
135 /* wait for the flag clear */
136 while (((*status = hdq_reg_in(hdq_data, offset)) & flag)
137 && time_before(jiffies, timeout)) {
138 schedule_timeout_uninterruptible(1);
142 } else if (flag_set == OMAP_HDQ_FLAG_SET) {
143 /* wait for the flag set */
144 while (!((*status = hdq_reg_in(hdq_data, offset)) & flag)
145 && time_before(jiffies, timeout)) {
146 schedule_timeout_uninterruptible(1);
148 if (!(*status & flag))
156 /* write out a byte and fill *status with HDQ_INT_STATUS */
157 static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status)
161 unsigned long irqflags;
165 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
166 /* clear interrupt flags via a dummy read */
167 hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
168 /* ISR loads it with new INT_STATUS */
169 hdq_data->hdq_irqstatus = 0;
170 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
172 hdq_reg_out(hdq_data, OMAP_HDQ_TX_DATA, val);
175 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_GO,
176 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
177 /* wait for the TXCOMPLETE bit */
178 ret = wait_event_timeout(hdq_wait_queue,
179 hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
181 dev_dbg(hdq_data->dev, "TX wait elapsed\n");
185 *status = hdq_data->hdq_irqstatus;
186 /* check irqstatus */
187 if (!(*status & OMAP_HDQ_INT_STATUS_TXCOMPLETE)) {
188 dev_dbg(hdq_data->dev, "timeout waiting for"
189 "TXCOMPLETE/RXCOMPLETE, %x", *status);
194 /* wait for the GO bit return to zero */
195 ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
196 OMAP_HDQ_CTRL_STATUS_GO,
197 OMAP_HDQ_FLAG_CLEAR, &tmp_status);
199 dev_dbg(hdq_data->dev, "timeout waiting GO bit"
200 "return to zero, %x", tmp_status);
207 /* HDQ Interrupt service routine */
208 static irqreturn_t hdq_isr(int irq, void *_hdq)
210 struct hdq_data *hdq_data = _hdq;
211 unsigned long irqflags;
213 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
214 hdq_data->hdq_irqstatus = hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
215 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
216 dev_dbg(hdq_data->dev, "hdq_isr: %x", hdq_data->hdq_irqstatus);
218 if (hdq_data->hdq_irqstatus &
219 (OMAP_HDQ_INT_STATUS_TXCOMPLETE | OMAP_HDQ_INT_STATUS_RXCOMPLETE
220 | OMAP_HDQ_INT_STATUS_TIMEOUT)) {
221 /* wake up sleeping process */
222 wake_up(&hdq_wait_queue);
228 /* HDQ Mode: always return success */
229 static u8 omap_w1_reset_bus(void *_hdq)
234 /* W1 search callback function */
235 static void omap_w1_search_bus(void *_hdq, struct w1_master *master_dev,
236 u8 search_type, w1_slave_found_callback slave_found)
238 u64 module_id, rn_le, cs, id;
245 rn_le = cpu_to_le64(module_id);
247 * HDQ might not obey truly the 1-wire spec.
248 * So calculate CRC based on module parameter.
250 cs = w1_calc_crc8((u8 *)&rn_le, 7);
251 id = (cs << 56) | module_id;
253 slave_found(master_dev, id);
256 static int _omap_hdq_reset(struct hdq_data *hdq_data)
261 hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG, OMAP_HDQ_SYSCONFIG_SOFTRESET);
263 * Select HDQ mode & enable clocks.
264 * It is observed that INT flags can't be cleared via a read and GO/INIT
265 * won't return to zero if interrupt is disabled. So we always enable
268 hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
269 OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
270 OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
272 /* wait for reset to complete */
273 ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_SYSSTATUS,
274 OMAP_HDQ_SYSSTATUS_RESETDONE, OMAP_HDQ_FLAG_SET, &tmp_status);
276 dev_dbg(hdq_data->dev, "timeout waiting HDQ reset, %x",
279 hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
280 OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
281 OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
282 hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
283 OMAP_HDQ_SYSCONFIG_AUTOIDLE);
289 /* Issue break pulse to the device */
290 static int omap_hdq_break(struct hdq_data *hdq_data)
294 unsigned long irqflags;
296 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
298 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
303 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
304 /* clear interrupt flags via a dummy read */
305 hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
306 /* ISR loads it with new INT_STATUS */
307 hdq_data->hdq_irqstatus = 0;
308 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
310 /* set the INIT and GO bit */
311 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
312 OMAP_HDQ_CTRL_STATUS_INITIALIZATION | OMAP_HDQ_CTRL_STATUS_GO,
313 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
314 OMAP_HDQ_CTRL_STATUS_GO);
316 /* wait for the TIMEOUT bit */
317 ret = wait_event_timeout(hdq_wait_queue,
318 hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
320 dev_dbg(hdq_data->dev, "break wait elapsed\n");
325 tmp_status = hdq_data->hdq_irqstatus;
326 /* check irqstatus */
327 if (!(tmp_status & OMAP_HDQ_INT_STATUS_TIMEOUT)) {
328 dev_dbg(hdq_data->dev, "timeout waiting for TIMEOUT, %x",
334 * wait for both INIT and GO bits rerurn to zero.
335 * zero wait time expected for interrupt mode.
337 ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
338 OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
339 OMAP_HDQ_CTRL_STATUS_GO, OMAP_HDQ_FLAG_CLEAR,
342 dev_dbg(hdq_data->dev, "timeout waiting INIT&GO bits"
343 "return to zero, %x", tmp_status);
346 mutex_unlock(&hdq_data->hdq_mutex);
351 static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val)
355 unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
357 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
363 if (!hdq_data->hdq_usecount) {
368 if (!(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
369 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
370 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO,
371 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
373 * The RX comes immediately after TX. It
374 * triggers another interrupt before we
375 * sleep. So we have to wait for RXCOMPLETE bit.
377 while (!(hdq_data->hdq_irqstatus
378 & OMAP_HDQ_INT_STATUS_RXCOMPLETE)
379 && time_before(jiffies, timeout)) {
380 schedule_timeout_uninterruptible(1);
382 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0,
383 OMAP_HDQ_CTRL_STATUS_DIR);
384 status = hdq_data->hdq_irqstatus;
385 /* check irqstatus */
386 if (!(status & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
387 dev_dbg(hdq_data->dev, "timeout waiting for"
388 "RXCOMPLETE, %x", status);
393 /* the data is ready. Read it in! */
394 *val = hdq_reg_in(hdq_data, OMAP_HDQ_RX_DATA);
396 mutex_unlock(&hdq_data->hdq_mutex);
402 /* Enable clocks and set the controller to HDQ mode */
403 static int omap_hdq_get(struct hdq_data *hdq_data)
407 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
413 if (OMAP_HDQ_MAX_USER == hdq_data->hdq_usecount) {
414 dev_dbg(hdq_data->dev, "attempt to exceed the max use count");
418 hdq_data->hdq_usecount++;
419 try_module_get(THIS_MODULE);
420 if (1 == hdq_data->hdq_usecount) {
421 if (clk_enable(hdq_data->hdq_ick)) {
422 dev_dbg(hdq_data->dev, "Can not enable ick\n");
426 if (clk_enable(hdq_data->hdq_fck)) {
427 dev_dbg(hdq_data->dev, "Can not enable fck\n");
428 clk_disable(hdq_data->hdq_ick);
433 /* make sure HDQ is out of reset */
434 if (!(hdq_reg_in(hdq_data, OMAP_HDQ_SYSSTATUS) &
435 OMAP_HDQ_SYSSTATUS_RESETDONE)) {
436 ret = _omap_hdq_reset(hdq_data);
438 /* back up the count */
439 hdq_data->hdq_usecount--;
441 /* select HDQ mode & enable clocks */
442 hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
443 OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
444 OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
445 hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
446 OMAP_HDQ_SYSCONFIG_AUTOIDLE);
447 hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
453 clk_put(hdq_data->hdq_ick);
454 clk_put(hdq_data->hdq_fck);
456 mutex_unlock(&hdq_data->hdq_mutex);
461 /* Disable clocks to the module */
462 static int omap_hdq_put(struct hdq_data *hdq_data)
466 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
470 if (0 == hdq_data->hdq_usecount) {
471 dev_dbg(hdq_data->dev, "attempt to decrement use count"
475 hdq_data->hdq_usecount--;
476 module_put(THIS_MODULE);
477 if (0 == hdq_data->hdq_usecount) {
478 clk_disable(hdq_data->hdq_ick);
479 clk_disable(hdq_data->hdq_fck);
482 mutex_unlock(&hdq_data->hdq_mutex);
487 /* Read a byte of data from the device */
488 static u8 omap_w1_read_byte(void *_hdq)
490 struct hdq_data *hdq_data = _hdq;
494 ret = hdq_read_byte(hdq_data, &val);
496 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
498 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
501 hdq_data->init_trans = 0;
502 mutex_unlock(&hdq_data->hdq_mutex);
503 omap_hdq_put(hdq_data);
507 /* Write followed by a read, release the module */
508 if (hdq_data->init_trans) {
509 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
511 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
514 hdq_data->init_trans = 0;
515 mutex_unlock(&hdq_data->hdq_mutex);
516 omap_hdq_put(hdq_data);
522 /* Write a byte of data to the device */
523 static void omap_w1_write_byte(void *_hdq, u8 byte)
525 struct hdq_data *hdq_data = _hdq;
529 /* First write to initialize the transfer */
530 if (hdq_data->init_trans == 0)
531 omap_hdq_get(hdq_data);
533 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
535 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
538 hdq_data->init_trans++;
539 mutex_unlock(&hdq_data->hdq_mutex);
541 ret = hdq_write_byte(hdq_data, byte, &status);
543 dev_dbg(hdq_data->dev, "TX failure:Ctrl status %x\n", status);
547 /* Second write, data transfered. Release the module */
548 if (hdq_data->init_trans > 1) {
549 omap_hdq_put(hdq_data);
550 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
552 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
555 hdq_data->init_trans = 0;
556 mutex_unlock(&hdq_data->hdq_mutex);
562 static int __devinit omap_hdq_probe(struct platform_device *pdev)
564 struct hdq_data *hdq_data;
565 struct resource *res;
569 hdq_data = kmalloc(sizeof(*hdq_data), GFP_KERNEL);
571 dev_dbg(&pdev->dev, "unable to allocate memory\n");
576 hdq_data->dev = &pdev->dev;
577 platform_set_drvdata(pdev, hdq_data);
579 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
581 dev_dbg(&pdev->dev, "unable to get resource\n");
586 hdq_data->hdq_base = ioremap(res->start, SZ_4K);
587 if (!hdq_data->hdq_base) {
588 dev_dbg(&pdev->dev, "ioremap failed\n");
593 /* get interface & functional clock objects */
594 hdq_data->hdq_ick = clk_get(&pdev->dev, "ick");
595 hdq_data->hdq_fck = clk_get(&pdev->dev, "fck");
597 if (IS_ERR(hdq_data->hdq_ick) || IS_ERR(hdq_data->hdq_fck)) {
598 dev_dbg(&pdev->dev, "Can't get HDQ clock objects\n");
599 if (IS_ERR(hdq_data->hdq_ick)) {
600 ret = PTR_ERR(hdq_data->hdq_ick);
603 if (IS_ERR(hdq_data->hdq_fck)) {
604 ret = PTR_ERR(hdq_data->hdq_fck);
605 clk_put(hdq_data->hdq_ick);
610 hdq_data->hdq_usecount = 0;
611 mutex_init(&hdq_data->hdq_mutex);
613 if (clk_enable(hdq_data->hdq_ick)) {
614 dev_dbg(&pdev->dev, "Can not enable ick\n");
619 if (clk_enable(hdq_data->hdq_fck)) {
620 dev_dbg(&pdev->dev, "Can not enable fck\n");
625 rev = hdq_reg_in(hdq_data, OMAP_HDQ_REVISION);
626 dev_info(&pdev->dev, "OMAP HDQ Hardware Rev %c.%c. Driver in %s mode\n",
627 (rev >> 4) + '0', (rev & 0x0f) + '0', "Interrupt");
629 spin_lock_init(&hdq_data->hdq_spinlock);
631 irq = platform_get_irq(pdev, 0);
637 ret = request_irq(irq, hdq_isr, IRQF_DISABLED, "omap_hdq", hdq_data);
639 dev_dbg(&pdev->dev, "could not request irq\n");
643 omap_hdq_break(hdq_data);
645 /* don't clock the HDQ until it is needed */
646 clk_disable(hdq_data->hdq_ick);
647 clk_disable(hdq_data->hdq_fck);
649 omap_w1_master.data = hdq_data;
651 ret = w1_add_master_device(&omap_w1_master);
653 dev_dbg(&pdev->dev, "Failure in registering w1 master\n");
661 clk_disable(hdq_data->hdq_fck);
664 clk_disable(hdq_data->hdq_ick);
667 clk_put(hdq_data->hdq_ick);
668 clk_put(hdq_data->hdq_fck);
671 iounmap(hdq_data->hdq_base);
675 platform_set_drvdata(pdev, NULL);
683 static int omap_hdq_remove(struct platform_device *pdev)
685 struct hdq_data *hdq_data = platform_get_drvdata(pdev);
687 mutex_lock(&hdq_data->hdq_mutex);
689 if (hdq_data->hdq_usecount) {
690 dev_dbg(&pdev->dev, "removed when use count is not zero\n");
691 mutex_unlock(&hdq_data->hdq_mutex);
695 mutex_unlock(&hdq_data->hdq_mutex);
697 /* remove module dependency */
698 clk_put(hdq_data->hdq_ick);
699 clk_put(hdq_data->hdq_fck);
700 free_irq(INT_24XX_HDQ_IRQ, hdq_data);
701 platform_set_drvdata(pdev, NULL);
702 iounmap(hdq_data->hdq_base);
711 return platform_driver_register(&omap_hdq_driver);
713 module_init(omap_hdq_init);
718 platform_driver_unregister(&omap_hdq_driver);
720 module_exit(omap_hdq_exit);
722 module_param(w1_id, int, S_IRUSR);
723 MODULE_PARM_DESC(w1_id, "1-wire id for the slave detection");
725 MODULE_AUTHOR("Texas Instruments");
726 MODULE_DESCRIPTION("HDQ driver Library");
727 MODULE_LICENSE("GPL");