2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
4 * Copyright (C) 1995 Jay Estabrook
5 * Copyright (C) 1997 Geert Uytterhoeven
6 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
7 * Copyright (C) 2002 Richard Henderson
8 * Copyright (C) 2006, 2007 Maciej W. Rozycki
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive for
15 #include <linux/bitrev.h>
16 #include <linux/compiler.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/selection.h>
28 #include <linux/string.h>
33 #include <video/tgafb.h>
36 #define TGA_BUS_TC(dev) (dev->bus == &tc_bus_type)
38 #define TGA_BUS_TC(dev) 0
45 static int tgafb_check_var(struct fb_var_screeninfo *, struct fb_info *);
46 static int tgafb_set_par(struct fb_info *);
47 static void tgafb_set_pll(struct tga_par *, int);
48 static int tgafb_setcolreg(unsigned, unsigned, unsigned, unsigned,
49 unsigned, struct fb_info *);
50 static int tgafb_blank(int, struct fb_info *);
51 static void tgafb_init_fix(struct fb_info *);
53 static void tgafb_imageblit(struct fb_info *, const struct fb_image *);
54 static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *);
55 static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *);
56 static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
58 static int tgafb_register(struct device *dev);
59 static void tgafb_unregister(struct device *dev);
61 static const char *mode_option;
62 static const char *mode_option_pci = "640x480@60";
63 static const char *mode_option_tc = "1280x1024@72";
66 static struct pci_driver tgafb_pci_driver;
67 static struct tc_driver tgafb_tc_driver;
70 * Frame buffer operations
73 static struct fb_ops tgafb_ops = {
75 .fb_check_var = tgafb_check_var,
76 .fb_set_par = tgafb_set_par,
77 .fb_setcolreg = tgafb_setcolreg,
78 .fb_blank = tgafb_blank,
79 .fb_pan_display = tgafb_pan_display,
80 .fb_fillrect = tgafb_fillrect,
81 .fb_copyarea = tgafb_copyarea,
82 .fb_imageblit = tgafb_imageblit,
88 * PCI registration operations
90 static int tgafb_pci_register(struct pci_dev *, const struct pci_device_id *);
91 static void tgafb_pci_unregister(struct pci_dev *);
93 static struct pci_device_id const tgafb_pci_table[] = {
94 { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA) },
97 MODULE_DEVICE_TABLE(pci, tgafb_pci_table);
99 static struct pci_driver tgafb_pci_driver = {
101 .id_table = tgafb_pci_table,
102 .probe = tgafb_pci_register,
103 .remove = tgafb_pci_unregister,
106 static int tgafb_pci_register(struct pci_dev *pdev,
107 const struct pci_device_id *ent)
109 return tgafb_register(&pdev->dev);
112 static void tgafb_pci_unregister(struct pci_dev *pdev)
114 tgafb_unregister(&pdev->dev);
116 #endif /* CONFIG_PCI */
120 * TC registration operations
122 static int tgafb_tc_register(struct device *);
123 static int tgafb_tc_unregister(struct device *);
125 static struct tc_device_id const tgafb_tc_table[] = {
126 { "DEC ", "PMAGD-AA" },
127 { "DEC ", "PMAGD " },
130 MODULE_DEVICE_TABLE(tc, tgafb_tc_table);
132 static struct tc_driver tgafb_tc_driver = {
133 .id_table = tgafb_tc_table,
137 .probe = tgafb_tc_register,
138 .remove = tgafb_tc_unregister,
142 static int tgafb_tc_register(struct device *dev)
144 int status = tgafb_register(dev);
150 static int tgafb_tc_unregister(struct device *dev)
153 tgafb_unregister(dev);
156 #endif /* CONFIG_TC */
160 * tgafb_check_var - Optional function. Validates a var passed in.
161 * @var: frame buffer variable screen structure
162 * @info: frame buffer structure that represents a single frame buffer
165 tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
167 struct tga_par *par = (struct tga_par *)info->par;
169 if (par->tga_type == TGA_TYPE_8PLANE) {
170 if (var->bits_per_pixel != 8)
173 if (var->bits_per_pixel != 32)
176 var->red.length = var->green.length = var->blue.length = 8;
177 if (var->bits_per_pixel == 32) {
178 var->red.offset = 16;
179 var->green.offset = 8;
180 var->blue.offset = 0;
183 if (var->xres_virtual != var->xres || var->yres_virtual != var->yres)
185 if (var->xres * var->yres * (var->bits_per_pixel >> 3) > info->fix.smem_len)
189 if (1000000000 / var->pixclock > TGA_PLL_MAX_FREQ)
191 if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
194 /* Some of the acceleration routines assume the line width is
195 a multiple of 64 bytes. */
196 if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 64)
203 * tgafb_set_par - Optional function. Alters the hardware state.
204 * @info: frame buffer structure that represents a single frame buffer
207 tgafb_set_par(struct fb_info *info)
209 static unsigned int const deep_presets[4] = {
215 static unsigned int const rasterop_presets[4] = {
221 static unsigned int const mode_presets[4] = {
227 static unsigned int const base_addr_presets[4] = {
234 struct tga_par *par = (struct tga_par *) info->par;
235 int tga_bus_pci = dev_is_pci(par->dev);
236 int tga_bus_tc = TGA_BUS_TC(par->dev);
237 u32 htimings, vtimings, pll_freq;
241 /* Encode video timings. */
242 htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
243 | (((info->var.xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB));
244 vtimings = (info->var.yres & TGA_VERT_ACTIVE);
245 htimings |= ((info->var.right_margin/4) << 9) & TGA_HORIZ_FP;
246 vtimings |= (info->var.lower_margin << 11) & TGA_VERT_FP;
247 htimings |= ((info->var.hsync_len/4) << 14) & TGA_HORIZ_SYNC;
248 vtimings |= (info->var.vsync_len << 16) & TGA_VERT_SYNC;
249 htimings |= ((info->var.left_margin/4) << 21) & TGA_HORIZ_BP;
250 vtimings |= (info->var.upper_margin << 22) & TGA_VERT_BP;
252 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
253 htimings |= TGA_HORIZ_POLARITY;
254 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
255 vtimings |= TGA_VERT_POLARITY;
257 par->htimings = htimings;
258 par->vtimings = vtimings;
260 par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN);
262 /* Store other useful values in par. */
263 par->xres = info->var.xres;
264 par->yres = info->var.yres;
265 par->pll_freq = pll_freq = 1000000000 / info->var.pixclock;
266 par->bits_per_pixel = info->var.bits_per_pixel;
267 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
269 tga_type = par->tga_type;
271 /* First, disable video. */
272 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
274 /* Write the DEEP register. */
275 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
278 TGA_WRITE_REG(par, deep_presets[tga_type] |
279 (par->sync_on_green ? 0x0 : 0x00010000),
281 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
285 /* Write some more registers. */
286 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
287 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
288 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
290 /* Calculate & write the PLL. */
291 tgafb_set_pll(par, pll_freq);
293 /* Write some more registers. */
294 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
295 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
297 /* Init video timing regs. */
298 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
299 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
301 /* Initialise RAMDAC. */
302 if (tga_type == TGA_TYPE_8PLANE && tga_bus_pci) {
304 /* Init BT485 RAMDAC registers. */
305 BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0),
307 BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE);
308 BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */
309 BT485_WRITE(par, 0x40, BT485_CMD_1);
310 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
311 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
313 /* Fill palette registers. */
314 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
315 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
317 for (i = 0; i < 256 * 3; i += 4) {
318 TGA_WRITE_REG(par, 0x55 | (BT485_DATA_PAL << 8),
320 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
322 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
324 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
328 } else if (tga_type == TGA_TYPE_8PLANE && tga_bus_tc) {
330 /* Init BT459 RAMDAC registers. */
331 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_0, 0x40);
332 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_1, 0x00);
333 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_2,
334 (par->sync_on_green ? 0xc0 : 0x40));
336 BT459_WRITE(par, BT459_REG_ACC, BT459_CUR_CMD_REG, 0x00);
338 /* Fill the palette. */
339 BT459_LOAD_ADDR(par, 0x0000);
340 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
342 for (i = 0; i < 256 * 3; i += 4) {
343 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
344 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
345 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
346 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
349 } else { /* 24-plane or 24plusZ */
351 /* Init BT463 RAMDAC registers. */
352 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
353 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
354 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
355 (par->sync_on_green ? 0xc0 : 0x40));
357 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
358 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
359 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
360 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);
362 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
363 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
364 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
365 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
367 /* Fill the palette. */
368 BT463_LOAD_ADDR(par, 0x0000);
369 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
371 #ifdef CONFIG_HW_CONSOLE
372 for (i = 0; i < 16; i++) {
373 int j = color_table[i];
375 TGA_WRITE_REG(par, default_red[j], TGA_RAMDAC_REG);
376 TGA_WRITE_REG(par, default_grn[j], TGA_RAMDAC_REG);
377 TGA_WRITE_REG(par, default_blu[j], TGA_RAMDAC_REG);
379 for (i = 0; i < 512 * 3; i += 4) {
381 for (i = 0; i < 528 * 3; i += 4) {
383 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
384 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
385 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
386 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
389 /* Fill window type table after start of vertical retrace. */
390 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
392 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
394 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
396 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
398 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
399 TGA_WRITE_REG(par, BT463_REG_ACC << 2, TGA_RAMDAC_SETUP_REG);
401 for (i = 0; i < 16; i++) {
402 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
403 TGA_WRITE_REG(par, 0x01, TGA_RAMDAC_REG);
404 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
409 /* Finally, enable video scan (and pray for the monitor... :-) */
410 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
415 #define DIFFCHECK(X) \
418 int delta = f - (TGA_PLL_BASE_FREQ * (X)) / (r << shift); \
421 if (delta < min_diff) \
422 min_diff = delta, vm = m, va = a, vr = r; \
427 tgafb_set_pll(struct tga_par *par, int f)
429 int n, shift, base, min_diff, target;
430 int r,a,m,vm = 34, va = 1, vr = 30;
432 for (r = 0 ; r < 12 ; r++)
433 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
435 if (f > TGA_PLL_MAX_FREQ)
436 f = TGA_PLL_MAX_FREQ;
438 if (f >= TGA_PLL_MAX_FREQ / 2)
440 else if (f >= TGA_PLL_MAX_FREQ / 4)
445 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
446 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
448 for (r = 0 ; r < 10 ; r++)
449 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
452 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
453 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
455 else if (f <= 200000) {
456 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
457 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
460 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
461 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
464 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
465 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
466 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
467 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
468 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
469 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
471 target = (f << shift) / TGA_PLL_BASE_FREQ;
472 min_diff = TGA_PLL_MAX_FREQ;
479 for (n = base < 7 ? 7 : base; n < base + target && n < 449; n++) {
480 m = ((n + 3) / 7) - 1;
482 DIFFCHECK((m + 1) * 7);
484 DIFFCHECK((m + 1) * 7);
495 for (r = 0; r < 8; r++)
496 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
497 for (r = 0; r < 8 ; r++)
498 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
499 for (r = 0; r < 7 ; r++)
500 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
501 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
506 * tgafb_setcolreg - Optional function. Sets a color register.
507 * @regno: boolean, 0 copy local, 1 get_user() function
508 * @red: frame buffer colormap structure
509 * @green: The green value which can be up to 16 bits wide
510 * @blue: The blue value which can be up to 16 bits wide.
511 * @transp: If supported the alpha value which can be up to 16 bits wide.
512 * @info: frame buffer info structure
515 tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
516 unsigned transp, struct fb_info *info)
518 struct tga_par *par = (struct tga_par *) info->par;
519 int tga_bus_pci = dev_is_pci(par->dev);
520 int tga_bus_tc = TGA_BUS_TC(par->dev);
528 if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_pci) {
529 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE);
530 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
531 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
532 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
533 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
534 } else if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_tc) {
535 BT459_LOAD_ADDR(par, regno);
536 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
537 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
538 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
539 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
542 u32 value = (regno << 16) | (regno << 8) | regno;
543 ((u32 *)info->pseudo_palette)[regno] = value;
545 BT463_LOAD_ADDR(par, regno);
546 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
547 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
548 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
549 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
557 * tgafb_blank - Optional function. Blanks the display.
558 * @blank_mode: the blank mode we want.
559 * @info: frame buffer structure that represents a single frame buffer
562 tgafb_blank(int blank, struct fb_info *info)
564 struct tga_par *par = (struct tga_par *) info->par;
565 u32 vhcr, vvcr, vvvr;
568 local_irq_save(flags);
570 vhcr = TGA_READ_REG(par, TGA_HORIZ_REG);
571 vvcr = TGA_READ_REG(par, TGA_VERT_REG);
572 vvvr = TGA_READ_REG(par, TGA_VALID_REG);
573 vvvr &= ~(TGA_VALID_VIDEO | TGA_VALID_BLANK);
576 case FB_BLANK_UNBLANK: /* Unblanking */
577 if (par->vesa_blanked) {
578 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
579 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
580 par->vesa_blanked = 0;
582 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
585 case FB_BLANK_NORMAL: /* Normal blanking */
586 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
590 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
591 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
592 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
593 par->vesa_blanked = 1;
596 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
597 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
598 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
599 par->vesa_blanked = 1;
602 case FB_BLANK_POWERDOWN: /* Poweroff */
603 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
604 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
605 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
606 par->vesa_blanked = 1;
610 local_irq_restore(flags);
620 tgafb_mono_imageblit(struct fb_info *info, const struct fb_image *image)
622 struct tga_par *par = (struct tga_par *) info->par;
623 u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask;
624 unsigned long rincr, line_length, shift, pos, is8bpp;
626 const unsigned char *data;
627 void __iomem *regs_base;
628 void __iomem *fb_base;
630 is8bpp = info->var.bits_per_pixel == 8;
634 width = image->width;
635 height = image->height;
636 vxres = info->var.xres_virtual;
637 vyres = info->var.yres_virtual;
638 line_length = info->fix.line_length;
639 rincr = (width + 7) / 8;
641 /* A shift below cannot cope with. */
642 if (unlikely(width == 0))
644 /* Crop the image to the screen. */
645 if (dx > vxres || dy > vyres)
647 if (dx + width > vxres)
649 if (dy + height > vyres)
652 regs_base = par->tga_regs_base;
653 fb_base = par->tga_fb_base;
655 /* Expand the color values to fill 32-bits. */
656 /* ??? Would be nice to notice colour changes elsewhere, so
657 that we can do this only when necessary. */
658 fgcolor = image->fg_color;
659 bgcolor = image->bg_color;
661 fgcolor |= fgcolor << 8;
662 fgcolor |= fgcolor << 16;
663 bgcolor |= bgcolor << 8;
664 bgcolor |= bgcolor << 16;
667 fgcolor = ((u32 *)info->pseudo_palette)[fgcolor];
669 bgcolor = ((u32 *)info->pseudo_palette)[bgcolor];
671 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG);
672 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG);
674 /* Acquire proper alignment; set up the PIXELMASK register
675 so that we only write the proper character cell. */
676 pos = dy * line_length;
683 shift = (pos & 7) >> 2;
687 data = (const unsigned char *) image->data;
689 /* Enable opaque stipple mode. */
691 ? TGA_MODE_SBM_8BPP | TGA_MODE_OPAQUE_STIPPLE
692 : TGA_MODE_SBM_24BPP | TGA_MODE_OPAQUE_STIPPLE),
693 regs_base + TGA_MODE_REG);
695 if (width + shift <= 32) {
696 unsigned long bwidth;
698 /* Handle common case of imaging a single character, in
699 a font less than or 32 pixels wide. */
701 /* Avoid a shift by 32; width > 0 implied. */
702 pixelmask = (2ul << (width - 1)) - 1;
704 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
707 bwidth = (width + 7) / 8;
709 for (i = 0; i < height; ++i) {
712 /* The image data is bit big endian; we need
714 for (j = 0; j < bwidth; ++j)
715 mask |= bitrev8(data[j]) << (j * 8);
717 __raw_writel(mask << shift, fb_base + pos);
723 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
724 } else if (shift == 0) {
725 unsigned long pos0 = pos;
726 const unsigned char *data0 = data;
727 unsigned long bincr = (is8bpp ? 8 : 8*4);
728 unsigned long bwidth;
730 /* Handle another common case in which accel_putcs
731 generates a large bitmap, which happens to be aligned.
732 Allow the tail to be misaligned. This case is
733 interesting because we've not got to hold partial
734 bytes across the words being written. */
738 bwidth = (width / 8) & -4;
739 for (i = 0; i < height; ++i) {
740 for (j = 0; j < bwidth; j += 4) {
742 mask |= bitrev8(data[j+0]) << (0 * 8);
743 mask |= bitrev8(data[j+1]) << (1 * 8);
744 mask |= bitrev8(data[j+2]) << (2 * 8);
745 mask |= bitrev8(data[j+3]) << (3 * 8);
746 __raw_writel(mask, fb_base + pos + j*bincr);
753 pixelmask = (1ul << (width & 31)) - 1;
755 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
758 pos = pos0 + bwidth*bincr;
759 data = data0 + bwidth;
760 bwidth = ((width & 31) + 7) / 8;
762 for (i = 0; i < height; ++i) {
764 for (j = 0; j < bwidth; ++j)
765 mask |= bitrev8(data[j]) << (j * 8);
766 __raw_writel(mask, fb_base + pos);
771 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
774 unsigned long pos0 = pos;
775 const unsigned char *data0 = data;
776 unsigned long bincr = (is8bpp ? 8 : 8*4);
777 unsigned long bwidth;
779 /* Finally, handle the generic case of misaligned start.
780 Here we split the write into 16-bit spans. This allows
781 us to use only one pixel mask, instead of four as would
782 be required by writing 24-bit spans. */
784 pixelmask = 0xffff << shift;
785 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
788 bwidth = (width / 8) & -2;
789 for (i = 0; i < height; ++i) {
790 for (j = 0; j < bwidth; j += 2) {
792 mask |= bitrev8(data[j+0]) << (0 * 8);
793 mask |= bitrev8(data[j+1]) << (1 * 8);
795 __raw_writel(mask, fb_base + pos + j*bincr);
802 pixelmask = ((1ul << (width & 15)) - 1) << shift;
804 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
807 pos = pos0 + bwidth*bincr;
808 data = data0 + bwidth;
809 bwidth = (width & 15) > 8;
811 for (i = 0; i < height; ++i) {
812 u32 mask = bitrev8(data[0]);
814 mask |= bitrev8(data[1]) << 8;
816 __raw_writel(mask, fb_base + pos);
822 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
825 /* Disable opaque stipple mode. */
827 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
828 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
829 regs_base + TGA_MODE_REG);
833 tgafb_clut_imageblit(struct fb_info *info, const struct fb_image *image)
835 struct tga_par *par = (struct tga_par *) info->par;
836 u32 color, dx, dy, width, height, vxres, vyres;
837 u32 *palette = ((u32 *)info->pseudo_palette);
838 unsigned long pos, line_length, i, j;
839 const unsigned char *data;
840 void __iomem *regs_base, *fb_base;
844 width = image->width;
845 height = image->height;
846 vxres = info->var.xres_virtual;
847 vyres = info->var.yres_virtual;
848 line_length = info->fix.line_length;
850 /* Crop the image to the screen. */
851 if (dx > vxres || dy > vyres)
853 if (dx + width > vxres)
855 if (dy + height > vyres)
858 regs_base = par->tga_regs_base;
859 fb_base = par->tga_fb_base;
861 pos = dy * line_length + (dx * 4);
864 /* Now copy the image, color_expanding via the palette. */
865 for (i = 0; i < height; i++) {
866 for (j = 0; j < width; j++) {
867 color = palette[*data++];
868 __raw_writel(color, fb_base + pos + j*4);
875 * tgafb_imageblit - REQUIRED function. Can use generic routines if
876 * non acclerated hardware and packed pixel based.
877 * Copies a image from system memory to the screen.
879 * @info: frame buffer structure that represents a single frame buffer
880 * @image: structure defining the image.
883 tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
885 unsigned int is8bpp = info->var.bits_per_pixel == 8;
887 /* If a mono image, regardless of FB depth, go do it. */
888 if (image->depth == 1) {
889 tgafb_mono_imageblit(info, image);
893 /* For copies that aren't pixel expansion, there's little we
894 can do better than the generic code. */
895 /* ??? There is a DMA write mode; I wonder if that could be
896 made to pull the data from the image buffer... */
897 if (image->depth == info->var.bits_per_pixel) {
898 cfb_imageblit(info, image);
902 /* If 24-plane FB and the image is 8-plane with CLUT, we can do it. */
903 if (!is8bpp && image->depth == 8) {
904 tgafb_clut_imageblit(info, image);
908 /* Silently return... */
912 * tgafb_fillrect - REQUIRED function. Can use generic routines if
913 * non acclerated hardware and packed pixel based.
914 * Draws a rectangle on the screen.
916 * @info: frame buffer structure that represents a single frame buffer
917 * @rect: structure defining the rectagle and operation.
920 tgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
922 struct tga_par *par = (struct tga_par *) info->par;
923 int is8bpp = info->var.bits_per_pixel == 8;
924 u32 dx, dy, width, height, vxres, vyres, color;
925 unsigned long pos, align, line_length, i, j;
926 void __iomem *regs_base;
927 void __iomem *fb_base;
932 height = rect->height;
933 vxres = info->var.xres_virtual;
934 vyres = info->var.yres_virtual;
935 line_length = info->fix.line_length;
936 regs_base = par->tga_regs_base;
937 fb_base = par->tga_fb_base;
939 /* Crop the rectangle to the screen. */
940 if (dx > vxres || dy > vyres || !width || !height)
942 if (dx + width > vxres)
944 if (dy + height > vyres)
947 pos = dy * line_length + dx * (is8bpp ? 1 : 4);
949 /* ??? We could implement ROP_XOR with opaque fill mode
950 and a RasterOp setting of GXxor, but as far as I can
951 tell, this mode is not actually used in the kernel.
952 Thus I am ignoring it for now. */
953 if (rect->rop != ROP_COPY) {
954 cfb_fillrect(info, rect);
958 /* Expand the color value to fill 8 pixels. */
962 color |= color << 16;
963 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
964 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
967 color = ((u32 *)info->pseudo_palette)[color];
968 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
969 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
970 __raw_writel(color, regs_base + TGA_BLOCK_COLOR2_REG);
971 __raw_writel(color, regs_base + TGA_BLOCK_COLOR3_REG);
972 __raw_writel(color, regs_base + TGA_BLOCK_COLOR4_REG);
973 __raw_writel(color, regs_base + TGA_BLOCK_COLOR5_REG);
974 __raw_writel(color, regs_base + TGA_BLOCK_COLOR6_REG);
975 __raw_writel(color, regs_base + TGA_BLOCK_COLOR7_REG);
978 /* The DATA register holds the fill mask for block fill mode.
979 Since we're not stippling, this is all ones. */
980 __raw_writel(0xffffffff, regs_base + TGA_DATA_REG);
982 /* Enable block fill mode. */
984 ? TGA_MODE_SBM_8BPP | TGA_MODE_BLOCK_FILL
985 : TGA_MODE_SBM_24BPP | TGA_MODE_BLOCK_FILL),
986 regs_base + TGA_MODE_REG);
989 /* We can fill 2k pixels per operation. Notice blocks that fit
990 the width of the screen so that we can take advantage of this
991 and fill more than one line per write. */
992 if (width == line_length)
993 width *= height, height = 1;
995 /* The write into the frame buffer must be aligned to 4 bytes,
996 but we are allowed to encode the offset within the word in
997 the data word written. */
998 align = (pos & 3) << 16;
1001 if (width <= 2048) {
1004 data = (width - 1) | align;
1006 for (i = 0; i < height; ++i) {
1007 __raw_writel(data, fb_base + pos);
1011 unsigned long Bpp = (is8bpp ? 1 : 4);
1012 unsigned long nwidth = width & -2048;
1015 fdata = (2048 - 1) | align;
1016 ldata = ((width & 2047) - 1) | align;
1018 for (i = 0; i < height; ++i) {
1019 for (j = 0; j < nwidth; j += 2048)
1020 __raw_writel(fdata, fb_base + pos + j*Bpp);
1022 __raw_writel(ldata, fb_base + pos + j*Bpp);
1028 /* Disable block fill mode. */
1029 __raw_writel((is8bpp
1030 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
1031 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
1032 regs_base + TGA_MODE_REG);
1036 * tgafb_copyarea - REQUIRED function. Can use generic routines if
1037 * non acclerated hardware and packed pixel based.
1038 * Copies on area of the screen to another area.
1040 * @info: frame buffer structure that represents a single frame buffer
1041 * @area: structure defining the source and destination.
1044 /* Handle the special case of copying entire lines, e.g. during scrolling.
1045 We can avoid a lot of needless computation in this case. In the 8bpp
1046 case we need to use the COPY64 registers instead of mask writes into
1047 the frame buffer to achieve maximum performance. */
1050 copyarea_line_8bpp(struct fb_info *info, u32 dy, u32 sy,
1051 u32 height, u32 width)
1053 struct tga_par *par = (struct tga_par *) info->par;
1054 void __iomem *tga_regs = par->tga_regs_base;
1055 unsigned long dpos, spos, i, n64;
1057 /* Set up the MODE and PIXELSHIFT registers. */
1058 __raw_writel(TGA_MODE_SBM_8BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1059 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1062 n64 = (height * width) / 64;
1065 spos = (sy + height) * width;
1066 dpos = (dy + height) * width;
1068 for (i = 0; i < n64; ++i) {
1071 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
1073 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
1080 for (i = 0; i < n64; ++i) {
1081 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
1083 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
1090 /* Reset the MODE register to normal. */
1091 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1095 copyarea_line_32bpp(struct fb_info *info, u32 dy, u32 sy,
1096 u32 height, u32 width)
1098 struct tga_par *par = (struct tga_par *) info->par;
1099 void __iomem *tga_regs = par->tga_regs_base;
1100 void __iomem *tga_fb = par->tga_fb_base;
1103 unsigned long i, n16;
1105 /* Set up the MODE and PIXELSHIFT registers. */
1106 __raw_writel(TGA_MODE_SBM_24BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1107 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1110 n16 = (height * width) / 16;
1113 src = tga_fb + (sy + height) * width * 4;
1114 dst = tga_fb + (dy + height) * width * 4;
1116 for (i = 0; i < n16; ++i) {
1119 __raw_writel(0xffff, src);
1121 __raw_writel(0xffff, dst);
1125 src = tga_fb + sy * width * 4;
1126 dst = tga_fb + dy * width * 4;
1128 for (i = 0; i < n16; ++i) {
1129 __raw_writel(0xffff, src);
1131 __raw_writel(0xffff, dst);
1138 /* Reset the MODE register to normal. */
1139 __raw_writel(TGA_MODE_SBM_24BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1142 /* The general case of forward copy in 8bpp mode. */
1144 copyarea_foreward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1145 u32 height, u32 width, u32 line_length)
1147 struct tga_par *par = (struct tga_par *) info->par;
1148 unsigned long i, copied, left;
1149 unsigned long dpos, spos, dalign, salign, yincr;
1150 u32 smask_first, dmask_first, dmask_last;
1151 int pixel_shift, need_prime, need_second;
1152 unsigned long n64, n32, xincr_first;
1153 void __iomem *tga_regs;
1154 void __iomem *tga_fb;
1156 yincr = line_length;
1163 /* Compute the offsets and alignments in the frame buffer.
1164 More than anything else, these control how we do copies. */
1165 dpos = dy * line_length + dx;
1166 spos = sy * line_length + sx;
1172 /* Compute the value for the PIXELSHIFT register. This controls
1173 both non-co-aligned source and destination and copy direction. */
1174 if (dalign >= salign)
1175 pixel_shift = dalign - salign;
1177 pixel_shift = 8 - (salign - dalign);
1179 /* Figure out if we need an additional priming step for the
1180 residue register. */
1181 need_prime = (salign > dalign);
1185 /* Begin by copying the leading unaligned destination. Copy enough
1186 to make the next destination address 32-byte aligned. */
1187 copied = 32 - (dalign + (dpos & 31));
1190 xincr_first = (copied + 7) & -8;
1191 smask_first = dmask_first = (1ul << copied) - 1;
1192 smask_first <<= salign;
1193 dmask_first <<= dalign + need_prime*8;
1194 if (need_prime && copied > 24)
1196 left = width - copied;
1198 /* Care for small copies. */
1199 if (copied > width) {
1201 t = (1ul << width) - 1;
1202 t <<= dalign + need_prime*8;
1207 /* Attempt to use 64-byte copies. This is only possible if the
1208 source and destination are co-aligned at 64 bytes. */
1209 n64 = need_second = 0;
1210 if ((dpos & 63) == (spos & 63)
1211 && (height == 1 || line_length % 64 == 0)) {
1212 /* We may need a 32-byte copy to ensure 64 byte alignment. */
1213 need_second = (dpos + xincr_first) & 63;
1214 if ((need_second & 32) != need_second)
1215 printk(KERN_ERR "tgafb: need_second wrong\n");
1216 if (left >= need_second + 64) {
1217 left -= need_second;
1224 /* Copy trailing full 32-byte sections. This will be the main
1225 loop if the 64 byte loop can't be used. */
1229 /* Copy the trailing unaligned destination. */
1230 dmask_last = (1ul << left) - 1;
1232 tga_regs = par->tga_regs_base;
1233 tga_fb = par->tga_fb_base;
1235 /* Set up the MODE and PIXELSHIFT registers. */
1236 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1237 __raw_writel(pixel_shift, tga_regs+TGA_PIXELSHIFT_REG);
1240 for (i = 0; i < height; ++i) {
1245 sfb = tga_fb + spos;
1246 dfb = tga_fb + dpos;
1248 __raw_writel(smask_first, sfb);
1250 __raw_writel(dmask_first, dfb);
1257 __raw_writel(0xffffffff, sfb);
1259 __raw_writel(0xffffffff, dfb);
1265 if (n64 && (((unsigned long)sfb | (unsigned long)dfb) & 63))
1267 "tgafb: misaligned copy64 (s:%p, d:%p)\n",
1270 for (j = 0; j < n64; ++j) {
1271 __raw_writel(sfb - tga_fb, tga_regs+TGA_COPY64_SRC);
1273 __raw_writel(dfb - tga_fb, tga_regs+TGA_COPY64_DST);
1279 for (j = 0; j < n32; ++j) {
1280 __raw_writel(0xffffffff, sfb);
1282 __raw_writel(0xffffffff, dfb);
1289 __raw_writel(0xffffffff, sfb);
1291 __raw_writel(dmask_last, dfb);
1299 /* Reset the MODE register to normal. */
1300 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1303 /* The (almost) general case of backward copy in 8bpp mode. */
1305 copyarea_backward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1306 u32 height, u32 width, u32 line_length,
1307 const struct fb_copyarea *area)
1309 struct tga_par *par = (struct tga_par *) info->par;
1310 unsigned long i, left, yincr;
1311 unsigned long depos, sepos, dealign, sealign;
1312 u32 mask_first, mask_last;
1314 void __iomem *tga_regs;
1315 void __iomem *tga_fb;
1317 yincr = line_length;
1324 /* Compute the offsets and alignments in the frame buffer.
1325 More than anything else, these control how we do copies. */
1326 depos = dy * line_length + dx + width;
1327 sepos = sy * line_length + sx + width;
1328 dealign = depos & 7;
1329 sealign = sepos & 7;
1331 /* ??? The documentation appears to be incorrect (or very
1332 misleading) wrt how pixel shifting works in backward copy
1333 mode, i.e. when PIXELSHIFT is negative. I give up for now.
1334 Do handle the common case of co-aligned backward copies,
1335 but frob everything else back on generic code. */
1336 if (dealign != sealign) {
1337 cfb_copyarea(info, area);
1341 /* We begin the copy with the trailing pixels of the
1342 unaligned destination. */
1343 mask_first = (1ul << dealign) - 1;
1344 left = width - dealign;
1346 /* Care for small copies. */
1347 if (dealign > width) {
1348 mask_first ^= (1ul << (dealign - width)) - 1;
1352 /* Next copy full words at a time. */
1356 /* Finally copy the unaligned head of the span. */
1357 mask_last = -1 << (32 - left);
1359 tga_regs = par->tga_regs_base;
1360 tga_fb = par->tga_fb_base;
1362 /* Set up the MODE and PIXELSHIFT registers. */
1363 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1364 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1367 for (i = 0; i < height; ++i) {
1372 sfb = tga_fb + sepos;
1373 dfb = tga_fb + depos;
1375 __raw_writel(mask_first, sfb);
1377 __raw_writel(mask_first, dfb);
1381 for (j = 0; j < n32; ++j) {
1384 __raw_writel(0xffffffff, sfb);
1386 __raw_writel(0xffffffff, dfb);
1393 __raw_writel(mask_last, sfb);
1395 __raw_writel(mask_last, dfb);
1403 /* Reset the MODE register to normal. */
1404 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1408 tgafb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1410 unsigned long dx, dy, width, height, sx, sy, vxres, vyres;
1411 unsigned long line_length, bpp;
1415 width = area->width;
1416 height = area->height;
1419 vxres = info->var.xres_virtual;
1420 vyres = info->var.yres_virtual;
1421 line_length = info->fix.line_length;
1423 /* The top left corners must be in the virtual screen. */
1424 if (dx > vxres || sx > vxres || dy > vyres || sy > vyres)
1427 /* Clip the destination. */
1428 if (dx + width > vxres)
1430 if (dy + height > vyres)
1431 height = vyres - dy;
1433 /* The source must be completely inside the virtual screen. */
1434 if (sx + width > vxres || sy + height > vyres)
1437 bpp = info->var.bits_per_pixel;
1439 /* Detect copies of the entire line. */
1440 if (width * (bpp >> 3) == line_length) {
1442 copyarea_line_8bpp(info, dy, sy, height, width);
1444 copyarea_line_32bpp(info, dy, sy, height, width);
1447 /* ??? The documentation is unclear to me exactly how the pixelshift
1448 register works in 32bpp mode. Since I don't have hardware to test,
1449 give up for now and fall back on the generic routines. */
1451 cfb_copyarea(info, area);
1453 /* Detect overlapping source and destination that requires
1455 else if (dy == sy && dx > sx && dx < sx + width)
1456 copyarea_backward_8bpp(info, dx, dy, sx, sy, height,
1457 width, line_length, area);
1459 copyarea_foreward_8bpp(info, dx, dy, sx, sy, height,
1460 width, line_length);
1469 tgafb_init_fix(struct fb_info *info)
1471 struct tga_par *par = (struct tga_par *)info->par;
1472 int tga_bus_pci = dev_is_pci(par->dev);
1473 int tga_bus_tc = TGA_BUS_TC(par->dev);
1474 u8 tga_type = par->tga_type;
1475 const char *tga_type_name = NULL;
1476 unsigned memory_size;
1479 case TGA_TYPE_8PLANE:
1481 tga_type_name = "Digital ZLXp-E1";
1483 tga_type_name = "Digital ZLX-E1";
1484 memory_size = 2097152;
1486 case TGA_TYPE_24PLANE:
1488 tga_type_name = "Digital ZLXp-E2";
1490 tga_type_name = "Digital ZLX-E2";
1491 memory_size = 8388608;
1493 case TGA_TYPE_24PLUSZ:
1495 tga_type_name = "Digital ZLXp-E3";
1497 tga_type_name = "Digital ZLX-E3";
1498 memory_size = 16777216;
1501 if (!tga_type_name) {
1502 tga_type_name = "Unknown";
1503 memory_size = 16777216;
1506 strlcpy(info->fix.id, tga_type_name, sizeof(info->fix.id));
1508 info->fix.type = FB_TYPE_PACKED_PIXELS;
1509 info->fix.type_aux = 0;
1510 info->fix.visual = (tga_type == TGA_TYPE_8PLANE
1511 ? FB_VISUAL_PSEUDOCOLOR
1512 : FB_VISUAL_DIRECTCOLOR);
1514 info->fix.smem_start = (size_t) par->tga_fb_base;
1515 info->fix.smem_len = memory_size;
1516 info->fix.mmio_start = (size_t) par->tga_regs_base;
1517 info->fix.mmio_len = 512;
1519 info->fix.xpanstep = 0;
1520 info->fix.ypanstep = 0;
1521 info->fix.ywrapstep = 0;
1523 info->fix.accel = FB_ACCEL_DEC_TGA;
1526 * These are needed by fb_set_logo_truepalette(), so we
1527 * set them here for 24-plane cards.
1529 if (tga_type != TGA_TYPE_8PLANE) {
1530 info->var.red.length = 8;
1531 info->var.green.length = 8;
1532 info->var.blue.length = 8;
1533 info->var.red.offset = 16;
1534 info->var.green.offset = 8;
1535 info->var.blue.offset = 0;
1539 static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1541 /* We just use this to catch switches out of graphics mode. */
1542 tgafb_set_par(info); /* A bit of overkill for BASE_ADDR reset. */
1546 static int tgafb_register(struct device *dev)
1548 static const struct fb_videomode modedb_tc = {
1549 /* 1280x1024 @ 72 Hz, 76.8 kHz hsync */
1550 "1280x1024@72", 0, 1280, 1024, 7645, 224, 28, 33, 3, 160, 3,
1551 FB_SYNC_ON_GREEN, FB_VMODE_NONINTERLACED
1554 static unsigned int const fb_offset_presets[4] = {
1555 TGA_8PLANE_FB_OFFSET,
1556 TGA_24PLANE_FB_OFFSET,
1558 TGA_24PLUSZ_FB_OFFSET
1561 const struct fb_videomode *modedb_tga = NULL;
1562 resource_size_t bar0_start = 0, bar0_len = 0;
1563 const char *mode_option_tga = NULL;
1564 int tga_bus_pci = dev_is_pci(dev);
1565 int tga_bus_tc = TGA_BUS_TC(dev);
1566 unsigned int modedbsize_tga = 0;
1567 void __iomem *mem_base;
1568 struct fb_info *info;
1569 struct tga_par *par;
1573 /* Enable device in PCI config. */
1574 if (tga_bus_pci && pci_enable_device(to_pci_dev(dev))) {
1575 printk(KERN_ERR "tgafb: Cannot enable PCI device\n");
1579 /* Allocate the fb and par structures. */
1580 info = framebuffer_alloc(sizeof(struct tga_par), dev);
1582 printk(KERN_ERR "tgafb: Cannot allocate memory\n");
1587 dev_set_drvdata(dev, info);
1589 /* Request the mem regions. */
1592 bar0_start = pci_resource_start(to_pci_dev(dev), 0);
1593 bar0_len = pci_resource_len(to_pci_dev(dev), 0);
1596 bar0_start = to_tc_dev(dev)->resource.start;
1597 bar0_len = to_tc_dev(dev)->resource.end - bar0_start + 1;
1599 if (!request_mem_region (bar0_start, bar0_len, "tgafb")) {
1600 printk(KERN_ERR "tgafb: cannot reserve FB region\n");
1604 /* Map the framebuffer. */
1605 mem_base = ioremap_nocache(bar0_start, bar0_len);
1607 printk(KERN_ERR "tgafb: Cannot map MMIO\n");
1611 /* Grab info about the card. */
1612 tga_type = (readl(mem_base) >> 12) & 0x0f;
1614 par->tga_mem_base = mem_base;
1615 par->tga_fb_base = mem_base + fb_offset_presets[tga_type];
1616 par->tga_regs_base = mem_base + TGA_REGS_OFFSET;
1617 par->tga_type = tga_type;
1619 par->tga_chip_rev = (to_pci_dev(dev))->revision;
1621 par->tga_chip_rev = TGA_READ_REG(par, TGA_START_REG) & 0xff;
1623 /* Setup framebuffer. */
1624 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
1625 FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT;
1626 info->fbops = &tgafb_ops;
1627 info->screen_base = par->tga_fb_base;
1628 info->pseudo_palette = par->palette;
1630 /* This should give a reasonable default video mode. */
1632 mode_option_tga = mode_option_pci;
1635 mode_option_tga = mode_option_tc;
1636 modedb_tga = &modedb_tc;
1640 tgafb_init_fix(info);
1642 ret = fb_find_mode(&info->var, info,
1643 mode_option ? mode_option : mode_option_tga,
1644 modedb_tga, modedbsize_tga, NULL,
1645 tga_type == TGA_TYPE_8PLANE ? 8 : 32);
1646 if (ret == 0 || ret == 4) {
1647 printk(KERN_ERR "tgafb: Could not find valid video mode\n");
1652 if (fb_alloc_cmap(&info->cmap, 256, 0)) {
1653 printk(KERN_ERR "tgafb: Could not allocate color map\n");
1658 tgafb_set_par(info);
1660 if (register_framebuffer(info) < 0) {
1661 printk(KERN_ERR "tgafb: Could not register framebuffer\n");
1667 pr_info("tgafb: DC21030 [TGA] detected, rev=0x%02x\n",
1669 pr_info("tgafb: at PCI bus %d, device %d, function %d\n",
1670 to_pci_dev(dev)->bus->number,
1671 PCI_SLOT(to_pci_dev(dev)->devfn),
1672 PCI_FUNC(to_pci_dev(dev)->devfn));
1675 pr_info("tgafb: SFB+ detected, rev=0x%02x\n",
1677 fb_info(info, "%s frame buffer device at 0x%lx\n",
1678 info->fix.id, (long)bar0_start);
1683 fb_dealloc_cmap(&info->cmap);
1687 release_mem_region(bar0_start, bar0_len);
1689 framebuffer_release(info);
1693 static void tgafb_unregister(struct device *dev)
1695 resource_size_t bar0_start = 0, bar0_len = 0;
1696 int tga_bus_pci = dev_is_pci(dev);
1697 int tga_bus_tc = TGA_BUS_TC(dev);
1698 struct fb_info *info = NULL;
1699 struct tga_par *par;
1701 info = dev_get_drvdata(dev);
1706 unregister_framebuffer(info);
1707 fb_dealloc_cmap(&info->cmap);
1708 iounmap(par->tga_mem_base);
1710 bar0_start = pci_resource_start(to_pci_dev(dev), 0);
1711 bar0_len = pci_resource_len(to_pci_dev(dev), 0);
1714 bar0_start = to_tc_dev(dev)->resource.start;
1715 bar0_len = to_tc_dev(dev)->resource.end - bar0_start + 1;
1717 release_mem_region(bar0_start, bar0_len);
1718 framebuffer_release(info);
1721 static void tgafb_exit(void)
1723 tc_unregister_driver(&tgafb_tc_driver);
1724 pci_unregister_driver(&tgafb_pci_driver);
1728 static int tgafb_setup(char *arg)
1733 while ((this_opt = strsep(&arg, ","))) {
1736 if (!strncmp(this_opt, "mode:", 5))
1737 mode_option = this_opt+5;
1740 "tgafb: unknown parameter %s\n",
1747 #endif /* !MODULE */
1749 static int tgafb_init(void)
1753 char *option = NULL;
1755 if (fb_get_options("tgafb", &option))
1757 tgafb_setup(option);
1759 status = pci_register_driver(&tgafb_pci_driver);
1761 status = tc_register_driver(&tgafb_tc_driver);
1769 module_init(tgafb_init);
1770 module_exit(tgafb_exit);
1772 MODULE_DESCRIPTION("Framebuffer driver for TGA/SFB+ chipset");
1773 MODULE_LICENSE("GPL");