2 * SuperH Mobile LCDC Framebuffer
4 * Copyright (c) 2008 Magnus Damm
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/delay.h>
16 #include <linux/clk.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/interrupt.h>
21 #include <linux/vmalloc.h>
22 #include <video/sh_mobile_lcdc.h>
23 #include <asm/atomic.h>
26 #define SIDE_B_OFFSET 0x1000
27 #define MIRROR_OFFSET 0x2000
29 /* shared registers */
31 #define _LDDCKSTPR 0x414
34 #define _LDCNT1R 0x470
35 #define _LDCNT2R 0x474
36 #define _LDRCNTR 0x478
38 #define _LDDWD0R 0x800
43 /* shared registers and their order for context save/restore */
44 static int lcdc_shared_regs[] = {
52 #define NR_SHARED_REGS ARRAY_SIZE(lcdc_shared_regs)
54 /* per-channel registers */
55 enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
56 LDSM2R, LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR,
59 static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
77 static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
95 #define START_LCDC 0x00000001
96 #define LCDC_RESET 0x00000100
97 #define DISPLAY_BEU 0x00000008
98 #define LCDC_ENABLE 0x00000001
99 #define LDINTR_FE 0x00000400
100 #define LDINTR_VSE 0x00000200
101 #define LDINTR_VEE 0x00000100
102 #define LDINTR_FS 0x00000004
103 #define LDINTR_VSS 0x00000002
104 #define LDINTR_VES 0x00000001
105 #define LDRCNTR_SRS 0x00020000
106 #define LDRCNTR_SRC 0x00010000
107 #define LDRCNTR_MRS 0x00000002
108 #define LDRCNTR_MRC 0x00000001
110 struct sh_mobile_lcdc_priv;
111 struct sh_mobile_lcdc_chan {
112 struct sh_mobile_lcdc_priv *lcdc;
113 unsigned long *reg_offs;
114 unsigned long ldmt1r_value;
115 unsigned long enabled; /* ME and SE in LDCNT2R */
116 struct sh_mobile_lcdc_chan_cfg cfg;
117 u32 pseudo_palette[PALETTE_NR];
118 unsigned long saved_ch_regs[NR_CH_REGS];
119 struct fb_info *info;
120 dma_addr_t dma_handle;
121 struct fb_deferred_io defio;
122 struct scatterlist *sglist;
123 unsigned long frame_end;
124 unsigned long pan_offset;
125 unsigned long new_pan_offset;
126 wait_queue_head_t frame_end_wait;
129 struct sh_mobile_lcdc_priv {
135 unsigned long lddckr;
136 struct sh_mobile_lcdc_chan ch[2];
137 unsigned long saved_shared_regs[NR_SHARED_REGS];
141 static bool banked(int reg_nr)
160 static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
161 int reg_nr, unsigned long data)
163 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
165 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
169 static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
170 int reg_nr, unsigned long data)
172 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
176 static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
179 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
182 static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
183 unsigned long reg_offs, unsigned long data)
185 iowrite32(data, priv->base + reg_offs);
188 static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
189 unsigned long reg_offs)
191 return ioread32(priv->base + reg_offs);
194 static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
195 unsigned long reg_offs,
196 unsigned long mask, unsigned long until)
198 while ((lcdc_read(priv, reg_offs) & mask) != until)
202 static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
204 return chan->cfg.chan == LCDC_CHAN_SUBLCD;
207 static void lcdc_sys_write_index(void *handle, unsigned long data)
209 struct sh_mobile_lcdc_chan *ch = handle;
211 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000);
212 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
213 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
214 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
217 static void lcdc_sys_write_data(void *handle, unsigned long data)
219 struct sh_mobile_lcdc_chan *ch = handle;
221 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000);
222 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
223 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
224 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
227 static unsigned long lcdc_sys_read_data(void *handle)
229 struct sh_mobile_lcdc_chan *ch = handle;
231 lcdc_write(ch->lcdc, _LDDRDR, 0x01000000);
232 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
233 lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
235 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
237 return lcdc_read(ch->lcdc, _LDDRDR) & 0x3ffff;
240 struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
241 lcdc_sys_write_index,
246 static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
248 if (atomic_inc_and_test(&priv->hw_usecnt)) {
249 pm_runtime_get_sync(priv->dev);
251 clk_enable(priv->dot_clk);
255 static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
257 if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
259 clk_disable(priv->dot_clk);
260 pm_runtime_put(priv->dev);
264 static int sh_mobile_lcdc_sginit(struct fb_info *info,
265 struct list_head *pagelist)
267 struct sh_mobile_lcdc_chan *ch = info->par;
268 unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT;
272 sg_init_table(ch->sglist, nr_pages_max);
274 list_for_each_entry(page, pagelist, lru)
275 sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0);
280 static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
281 struct list_head *pagelist)
283 struct sh_mobile_lcdc_chan *ch = info->par;
285 /* enable clocks before accessing hardware */
286 sh_mobile_lcdc_clk_on(ch->lcdc);
289 * It's possible to get here without anything on the pagelist via
290 * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync()
291 * invocation. In the former case, the acceleration routines are
292 * stepped in to when using the framebuffer console causing the
293 * workqueue to be scheduled without any dirty pages on the list.
295 * Despite this, a panel update is still needed given that the
296 * acceleration routines have their own methods for writing in
297 * that still need to be updated.
299 * The fsync() and empty pagelist case could be optimized for,
300 * but we don't bother, as any application exhibiting such
301 * behaviour is fundamentally broken anyways.
303 if (!list_empty(pagelist)) {
304 unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist);
306 /* trigger panel update */
307 dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
308 lcdc_write_chan(ch, LDSM2R, 1);
309 dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
311 lcdc_write_chan(ch, LDSM2R, 1);
314 static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
316 struct fb_deferred_io *fbdefio = info->fbdefio;
319 schedule_delayed_work(&info->deferred_work, fbdefio->delay);
322 static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
324 struct sh_mobile_lcdc_priv *priv = data;
325 struct sh_mobile_lcdc_chan *ch;
327 unsigned long ldintr;
331 /* acknowledge interrupt */
332 ldintr = tmp = lcdc_read(priv, _LDINTR);
334 * disable further VSYNC End IRQs, preserve all other enabled IRQs,
335 * write 0 to bits 0-6 to ack all triggered IRQs.
337 tmp &= 0xffffff00 & ~LDINTR_VEE;
338 lcdc_write(priv, _LDINTR, tmp);
340 /* figure out if this interrupt is for main or sub lcd */
341 is_sub = (lcdc_read(priv, _LDSR) & (1 << 10)) ? 1 : 0;
343 /* wake up channel and disable clocks */
344 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
351 if (ldintr & LDINTR_FS) {
352 if (is_sub == lcdc_chan_is_sublcd(ch)) {
354 wake_up(&ch->frame_end_wait);
356 sh_mobile_lcdc_clk_off(priv);
361 if (ldintr & LDINTR_VES) {
362 unsigned long ldrcntr = lcdc_read(priv, _LDRCNTR);
363 /* Set the source address for the next refresh */
364 lcdc_write_chan_mirror(ch, LDSA1R, ch->dma_handle +
366 if (lcdc_chan_is_sublcd(ch))
367 lcdc_write(ch->lcdc, _LDRCNTR,
368 ldrcntr ^ LDRCNTR_SRS);
370 lcdc_write(ch->lcdc, _LDRCNTR,
371 ldrcntr ^ LDRCNTR_MRS);
372 ch->pan_offset = ch->new_pan_offset;
379 static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
382 unsigned long tmp = lcdc_read(priv, _LDCNT2R);
385 /* start or stop the lcdc */
387 lcdc_write(priv, _LDCNT2R, tmp | START_LCDC);
389 lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC);
391 /* wait until power is applied/stopped on all channels */
392 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
393 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
395 tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3;
396 if (start && tmp == 3)
398 if (!start && tmp == 0)
404 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
407 static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
409 struct sh_mobile_lcdc_chan *ch;
410 struct fb_videomode *lcd_cfg;
411 struct sh_mobile_lcdc_board_cfg *board_cfg;
416 /* enable clocks before accessing the hardware */
417 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
418 if (priv->ch[k].enabled)
419 sh_mobile_lcdc_clk_on(priv);
422 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET);
423 lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0);
425 /* enable LCDC channels */
426 tmp = lcdc_read(priv, _LDCNT2R);
427 tmp |= priv->ch[0].enabled;
428 tmp |= priv->ch[1].enabled;
429 lcdc_write(priv, _LDCNT2R, tmp);
431 /* read data from external memory, avoid using the BEU for now */
432 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU);
434 /* stop the lcdc first */
435 sh_mobile_lcdc_start_stop(priv, 0);
437 /* configure clocks */
439 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
442 if (!priv->ch[k].enabled)
445 m = ch->cfg.clock_divider;
451 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
453 lcdc_write_chan(ch, LDDCKPAT1R, 0x00000000);
454 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
457 lcdc_write(priv, _LDDCKR, tmp);
459 /* start dotclock again */
460 lcdc_write(priv, _LDDCKSTPR, 0);
461 lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
463 /* interrupts are disabled to begin with */
464 lcdc_write(priv, _LDINTR, 0);
466 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
468 lcd_cfg = &ch->cfg.lcd_cfg;
473 tmp = ch->ldmt1r_value;
474 tmp |= (lcd_cfg->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
475 tmp |= (lcd_cfg->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
476 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? 1 << 26 : 0;
477 tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? 1 << 25 : 0;
478 tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? 1 << 24 : 0;
479 tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? 1 << 17 : 0;
480 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? 1 << 16 : 0;
481 lcdc_write_chan(ch, LDMT1R, tmp);
484 lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
485 lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
487 /* horizontal configuration */
488 tmp = lcd_cfg->xres + lcd_cfg->hsync_len;
489 tmp += lcd_cfg->left_margin;
490 tmp += lcd_cfg->right_margin;
492 tmp |= (lcd_cfg->xres / 8) << 16; /* HDCN */
493 lcdc_write_chan(ch, LDHCNR, tmp);
496 tmp += lcd_cfg->right_margin;
497 tmp /= 8; /* HSYNP */
498 tmp |= (lcd_cfg->hsync_len / 8) << 16; /* HSYNW */
499 lcdc_write_chan(ch, LDHSYNR, tmp);
502 lcdc_write_chan(ch, LDPMR, 0);
504 /* vertical configuration */
505 tmp = lcd_cfg->yres + lcd_cfg->vsync_len;
506 tmp += lcd_cfg->upper_margin;
507 tmp += lcd_cfg->lower_margin; /* VTLN */
508 tmp |= lcd_cfg->yres << 16; /* VDLN */
509 lcdc_write_chan(ch, LDVLNR, tmp);
512 tmp += lcd_cfg->lower_margin; /* VSYNP */
513 tmp |= lcd_cfg->vsync_len << 16; /* VSYNW */
514 lcdc_write_chan(ch, LDVSYNR, tmp);
516 board_cfg = &ch->cfg.board_cfg;
517 if (board_cfg->setup_sys)
518 ret = board_cfg->setup_sys(board_cfg->board_data, ch,
519 &sh_mobile_lcdc_sys_bus_ops);
524 /* word and long word swap */
525 lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6);
527 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
530 if (!priv->ch[k].enabled)
533 /* set bpp format in PKF[4:0] */
534 tmp = lcdc_read_chan(ch, LDDFR);
535 tmp &= ~(0x0001001f);
536 tmp |= (ch->info->var.bits_per_pixel == 16) ? 3 : 0;
537 lcdc_write_chan(ch, LDDFR, tmp);
539 /* point out our frame buffer */
540 lcdc_write_chan(ch, LDSA1R, ch->info->fix.smem_start);
543 lcdc_write_chan(ch, LDMLSR, ch->info->fix.line_length);
545 /* setup deferred io if SYS bus */
546 tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
547 if (ch->ldmt1r_value & (1 << 12) && tmp) {
548 ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
549 ch->defio.delay = msecs_to_jiffies(tmp);
550 ch->info->fbdefio = &ch->defio;
551 fb_deferred_io_init(ch->info);
554 lcdc_write_chan(ch, LDSM1R, 1);
556 /* enable "Frame End Interrupt Enable" bit */
557 lcdc_write(priv, _LDINTR, LDINTR_FE);
560 /* continuous read mode */
561 lcdc_write_chan(ch, LDSM1R, 0);
566 lcdc_write(priv, _LDCNT1R, LCDC_ENABLE);
569 sh_mobile_lcdc_start_stop(priv, 1);
572 /* tell the board code to enable the panel */
573 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
578 board_cfg = &ch->cfg.board_cfg;
579 if (board_cfg->display_on)
580 board_cfg->display_on(board_cfg->board_data);
586 static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
588 struct sh_mobile_lcdc_chan *ch;
589 struct sh_mobile_lcdc_board_cfg *board_cfg;
592 /* clean up deferred io and ask board code to disable panel */
593 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
599 * flush frame, and wait for frame end interrupt
600 * clean up deferred io and enable clock
602 if (ch->info->fbdefio) {
604 schedule_delayed_work(&ch->info->deferred_work, 0);
605 wait_event(ch->frame_end_wait, ch->frame_end);
606 fb_deferred_io_cleanup(ch->info);
607 ch->info->fbdefio = NULL;
608 sh_mobile_lcdc_clk_on(priv);
611 board_cfg = &ch->cfg.board_cfg;
612 if (board_cfg->display_off)
613 board_cfg->display_off(board_cfg->board_data);
618 sh_mobile_lcdc_start_stop(priv, 0);
623 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
624 if (priv->ch[k].enabled)
625 sh_mobile_lcdc_clk_off(priv);
628 static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
632 switch (ch->cfg.interface_type) {
633 case RGB8: ifm = 0; miftyp = 0; break;
634 case RGB9: ifm = 0; miftyp = 4; break;
635 case RGB12A: ifm = 0; miftyp = 5; break;
636 case RGB12B: ifm = 0; miftyp = 6; break;
637 case RGB16: ifm = 0; miftyp = 7; break;
638 case RGB18: ifm = 0; miftyp = 10; break;
639 case RGB24: ifm = 0; miftyp = 11; break;
640 case SYS8A: ifm = 1; miftyp = 0; break;
641 case SYS8B: ifm = 1; miftyp = 1; break;
642 case SYS8C: ifm = 1; miftyp = 2; break;
643 case SYS8D: ifm = 1; miftyp = 3; break;
644 case SYS9: ifm = 1; miftyp = 4; break;
645 case SYS12: ifm = 1; miftyp = 5; break;
646 case SYS16A: ifm = 1; miftyp = 7; break;
647 case SYS16B: ifm = 1; miftyp = 8; break;
648 case SYS16C: ifm = 1; miftyp = 9; break;
649 case SYS18: ifm = 1; miftyp = 10; break;
650 case SYS24: ifm = 1; miftyp = 11; break;
654 /* SUBLCD only supports SYS interface */
655 if (lcdc_chan_is_sublcd(ch)) {
662 ch->ldmt1r_value = (ifm << 12) | miftyp;
668 static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
670 struct sh_mobile_lcdc_priv *priv)
675 switch (clock_source) {
676 case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break;
677 case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break;
678 case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break;
683 priv->lddckr = icksel << 16;
686 priv->dot_clk = clk_get(&pdev->dev, str);
687 if (IS_ERR(priv->dot_clk)) {
688 dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
689 return PTR_ERR(priv->dot_clk);
692 atomic_set(&priv->hw_usecnt, -1);
694 /* Runtime PM support involves two step for this driver:
695 * 1) Enable Runtime PM
696 * 2) Force Runtime PM Resume since hardware is accessed from probe()
698 pm_runtime_enable(priv->dev);
699 pm_runtime_resume(priv->dev);
703 static int sh_mobile_lcdc_setcolreg(u_int regno,
704 u_int red, u_int green, u_int blue,
705 u_int transp, struct fb_info *info)
707 u32 *palette = info->pseudo_palette;
709 if (regno >= PALETTE_NR)
712 /* only FB_VISUAL_TRUECOLOR supported */
714 red >>= 16 - info->var.red.length;
715 green >>= 16 - info->var.green.length;
716 blue >>= 16 - info->var.blue.length;
717 transp >>= 16 - info->var.transp.length;
719 palette[regno] = (red << info->var.red.offset) |
720 (green << info->var.green.offset) |
721 (blue << info->var.blue.offset) |
722 (transp << info->var.transp.offset);
727 static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
728 .id = "SH Mobile LCDC",
729 .type = FB_TYPE_PACKED_PIXELS,
730 .visual = FB_VISUAL_TRUECOLOR,
731 .accel = FB_ACCEL_NONE,
737 static void sh_mobile_lcdc_fillrect(struct fb_info *info,
738 const struct fb_fillrect *rect)
740 sys_fillrect(info, rect);
741 sh_mobile_lcdc_deferred_io_touch(info);
744 static void sh_mobile_lcdc_copyarea(struct fb_info *info,
745 const struct fb_copyarea *area)
747 sys_copyarea(info, area);
748 sh_mobile_lcdc_deferred_io_touch(info);
751 static void sh_mobile_lcdc_imageblit(struct fb_info *info,
752 const struct fb_image *image)
754 sys_imageblit(info, image);
755 sh_mobile_lcdc_deferred_io_touch(info);
758 static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
759 struct fb_info *info)
761 struct sh_mobile_lcdc_chan *ch = info->par;
763 if (info->var.xoffset == var->xoffset &&
764 info->var.yoffset == var->yoffset)
765 return 0; /* No change, do nothing */
767 ch->new_pan_offset = (var->yoffset * info->fix.line_length) +
768 (var->xoffset * (info->var.bits_per_pixel / 8));
770 if (ch->new_pan_offset != ch->pan_offset) {
771 unsigned long ldintr;
772 ldintr = lcdc_read(ch->lcdc, _LDINTR);
773 ldintr |= LDINTR_VEE;
774 lcdc_write(ch->lcdc, _LDINTR, ldintr);
775 sh_mobile_lcdc_deferred_io_touch(info);
781 static struct fb_ops sh_mobile_lcdc_ops = {
782 .owner = THIS_MODULE,
783 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
784 .fb_read = fb_sys_read,
785 .fb_write = fb_sys_write,
786 .fb_fillrect = sh_mobile_lcdc_fillrect,
787 .fb_copyarea = sh_mobile_lcdc_copyarea,
788 .fb_imageblit = sh_mobile_lcdc_imageblit,
789 .fb_pan_display = sh_mobile_fb_pan_display,
792 static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
795 case 16: /* PKF[4:0] = 00011 - RGB 565 */
796 var->red.offset = 11;
798 var->green.offset = 5;
799 var->green.length = 6;
800 var->blue.offset = 0;
801 var->blue.length = 5;
802 var->transp.offset = 0;
803 var->transp.length = 0;
806 case 32: /* PKF[4:0] = 00000 - RGB 888
807 * sh7722 pdf says 00RRGGBB but reality is GGBB00RR
808 * this may be because LDDDSR has word swap enabled..
812 var->green.offset = 24;
813 var->green.length = 8;
814 var->blue.offset = 16;
815 var->blue.length = 8;
816 var->transp.offset = 0;
817 var->transp.length = 0;
822 var->bits_per_pixel = bpp;
823 var->red.msb_right = 0;
824 var->green.msb_right = 0;
825 var->blue.msb_right = 0;
826 var->transp.msb_right = 0;
830 static int sh_mobile_lcdc_suspend(struct device *dev)
832 struct platform_device *pdev = to_platform_device(dev);
834 sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
838 static int sh_mobile_lcdc_resume(struct device *dev)
840 struct platform_device *pdev = to_platform_device(dev);
842 return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
845 static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
847 struct platform_device *pdev = to_platform_device(dev);
848 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
849 struct sh_mobile_lcdc_chan *ch;
852 /* save per-channel registers */
853 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
857 for (n = 0; n < NR_CH_REGS; n++)
858 ch->saved_ch_regs[n] = lcdc_read_chan(ch, n);
861 /* save shared registers */
862 for (n = 0; n < NR_SHARED_REGS; n++)
863 p->saved_shared_regs[n] = lcdc_read(p, lcdc_shared_regs[n]);
865 /* turn off LCDC hardware */
866 lcdc_write(p, _LDCNT1R, 0);
870 static int sh_mobile_lcdc_runtime_resume(struct device *dev)
872 struct platform_device *pdev = to_platform_device(dev);
873 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
874 struct sh_mobile_lcdc_chan *ch;
877 /* restore per-channel registers */
878 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
882 for (n = 0; n < NR_CH_REGS; n++)
883 lcdc_write_chan(ch, n, ch->saved_ch_regs[n]);
886 /* restore shared registers */
887 for (n = 0; n < NR_SHARED_REGS; n++)
888 lcdc_write(p, lcdc_shared_regs[n], p->saved_shared_regs[n]);
893 static struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
894 .suspend = sh_mobile_lcdc_suspend,
895 .resume = sh_mobile_lcdc_resume,
896 .runtime_suspend = sh_mobile_lcdc_runtime_suspend,
897 .runtime_resume = sh_mobile_lcdc_runtime_resume,
900 static int sh_mobile_lcdc_remove(struct platform_device *pdev);
902 static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
904 struct fb_info *info;
905 struct sh_mobile_lcdc_priv *priv;
906 struct sh_mobile_lcdc_info *pdata;
907 struct sh_mobile_lcdc_chan_cfg *cfg;
908 struct resource *res;
913 if (!pdev->dev.platform_data) {
914 dev_err(&pdev->dev, "no platform data defined\n");
919 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
920 i = platform_get_irq(pdev, 0);
922 dev_err(&pdev->dev, "cannot get platform resources\n");
927 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
929 dev_err(&pdev->dev, "cannot allocate device data\n");
934 error = request_irq(i, sh_mobile_lcdc_irq, IRQF_DISABLED,
935 dev_name(&pdev->dev), priv);
937 dev_err(&pdev->dev, "unable to request irq\n");
942 priv->dev = &pdev->dev;
943 platform_set_drvdata(pdev, priv);
944 pdata = pdev->dev.platform_data;
947 for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
948 priv->ch[j].lcdc = priv;
949 memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
951 error = sh_mobile_lcdc_check_interface(&priv->ch[i]);
953 dev_err(&pdev->dev, "unsupported interface type\n");
956 init_waitqueue_head(&priv->ch[i].frame_end_wait);
957 priv->ch[j].pan_offset = 0;
958 priv->ch[j].new_pan_offset = 0;
960 switch (pdata->ch[i].chan) {
961 case LCDC_CHAN_MAINLCD:
962 priv->ch[j].enabled = 1 << 1;
963 priv->ch[j].reg_offs = lcdc_offs_mainlcd;
966 case LCDC_CHAN_SUBLCD:
967 priv->ch[j].enabled = 1 << 2;
968 priv->ch[j].reg_offs = lcdc_offs_sublcd;
975 dev_err(&pdev->dev, "no channels defined\n");
980 error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
982 dev_err(&pdev->dev, "unable to setup clocks\n");
986 priv->base = ioremap_nocache(res->start, (res->end - res->start) + 1);
988 for (i = 0; i < j; i++) {
989 cfg = &priv->ch[i].cfg;
991 priv->ch[i].info = framebuffer_alloc(0, &pdev->dev);
992 if (!priv->ch[i].info) {
993 dev_err(&pdev->dev, "unable to allocate fb_info\n");
998 info = priv->ch[i].info;
999 info->fbops = &sh_mobile_lcdc_ops;
1000 info->var.xres = info->var.xres_virtual = cfg->lcd_cfg.xres;
1001 info->var.yres = cfg->lcd_cfg.yres;
1002 /* Default Y virtual resolution is 2x panel size */
1003 info->var.yres_virtual = info->var.yres * 2;
1004 info->var.width = cfg->lcd_size_cfg.width;
1005 info->var.height = cfg->lcd_size_cfg.height;
1006 info->var.activate = FB_ACTIVATE_NOW;
1007 error = sh_mobile_lcdc_set_bpp(&info->var, cfg->bpp);
1011 info->fix = sh_mobile_lcdc_fix;
1012 info->fix.line_length = cfg->lcd_cfg.xres * (cfg->bpp / 8);
1013 info->fix.smem_len = info->fix.line_length *
1014 info->var.yres_virtual;
1016 buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
1017 &priv->ch[i].dma_handle, GFP_KERNEL);
1019 dev_err(&pdev->dev, "unable to allocate buffer\n");
1024 info->pseudo_palette = &priv->ch[i].pseudo_palette;
1025 info->flags = FBINFO_FLAG_DEFAULT;
1027 error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
1029 dev_err(&pdev->dev, "unable to allocate cmap\n");
1030 dma_free_coherent(&pdev->dev, info->fix.smem_len,
1031 buf, priv->ch[i].dma_handle);
1035 memset(buf, 0, info->fix.smem_len);
1036 info->fix.smem_start = priv->ch[i].dma_handle;
1037 info->screen_base = buf;
1038 info->device = &pdev->dev;
1039 info->par = &priv->ch[i];
1045 error = sh_mobile_lcdc_start(priv);
1047 dev_err(&pdev->dev, "unable to start hardware\n");
1051 for (i = 0; i < j; i++) {
1052 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
1056 if (info->fbdefio) {
1057 priv->ch->sglist = vmalloc(sizeof(struct scatterlist) *
1058 info->fix.smem_len >> PAGE_SHIFT);
1059 if (!priv->ch->sglist) {
1060 dev_err(&pdev->dev, "cannot allocate sglist\n");
1065 error = register_framebuffer(info);
1070 "registered %s/%s as %dx%d %dbpp.\n",
1072 (ch->cfg.chan == LCDC_CHAN_MAINLCD) ?
1073 "mainlcd" : "sublcd",
1074 (int) ch->cfg.lcd_cfg.xres,
1075 (int) ch->cfg.lcd_cfg.yres,
1078 /* deferred io mode: disable clock to save power */
1080 sh_mobile_lcdc_clk_off(priv);
1085 sh_mobile_lcdc_remove(pdev);
1090 static int sh_mobile_lcdc_remove(struct platform_device *pdev)
1092 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
1093 struct fb_info *info;
1096 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
1097 if (priv->ch[i].info->dev)
1098 unregister_framebuffer(priv->ch[i].info);
1100 sh_mobile_lcdc_stop(priv);
1102 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
1103 info = priv->ch[i].info;
1105 if (!info || !info->device)
1108 if (priv->ch[i].sglist)
1109 vfree(priv->ch[i].sglist);
1111 dma_free_coherent(&pdev->dev, info->fix.smem_len,
1112 info->screen_base, priv->ch[i].dma_handle);
1113 fb_dealloc_cmap(&info->cmap);
1114 framebuffer_release(info);
1118 clk_put(priv->dot_clk);
1120 pm_runtime_disable(priv->dev);
1123 iounmap(priv->base);
1126 free_irq(priv->irq, priv);
1131 static struct platform_driver sh_mobile_lcdc_driver = {
1133 .name = "sh_mobile_lcdc_fb",
1134 .owner = THIS_MODULE,
1135 .pm = &sh_mobile_lcdc_dev_pm_ops,
1137 .probe = sh_mobile_lcdc_probe,
1138 .remove = sh_mobile_lcdc_remove,
1141 static int __init sh_mobile_lcdc_init(void)
1143 return platform_driver_register(&sh_mobile_lcdc_driver);
1146 static void __exit sh_mobile_lcdc_exit(void)
1148 platform_driver_unregister(&sh_mobile_lcdc_driver);
1151 module_init(sh_mobile_lcdc_init);
1152 module_exit(sh_mobile_lcdc_exit);
1154 MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
1155 MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
1156 MODULE_LICENSE("GPL v2");