3 * Logic for the below structure :
4 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
5 * There is a correspondence between CEA/VESA timing and code, please
6 * refer to section 6.3 in HDMI 1.3 specification for timing code.
8 * In the below structure, cea_vesa_timings corresponds to all OMAP4
9 * supported CEA and VESA timing values.code_cea corresponds to the CEA
10 * code, It is used to get the timing from cea_vesa_timing array.Similarly
11 * with code_vesa. Code_index is used for back mapping, that is once EDID
12 * is read from the TV, EDID is parsed to find the timing values and then
13 * map it to corresponding CEA or VESA index.
16 #define DSS_SUBSYS_NAME "HDMI"
18 #include <linux/kernel.h>
19 #include <linux/err.h>
20 #include <video/omapdss.h>
24 static const struct hdmi_config cea_timings[] = {
26 { 640, 480, 25200000, 96, 16, 48, 2, 10, 33,
27 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
32 { 720, 480, 27027000, 62, 16, 60, 6, 9, 30,
33 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
38 { 1280, 720, 74250000, 40, 110, 220, 5, 5, 20,
39 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
44 { 1920, 540, 74250000, 44, 88, 148, 5, 2, 15,
45 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
50 { 1440, 240, 27027000, 124, 38, 114, 3, 4, 15,
51 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
56 { 1920, 1080, 148500000, 44, 88, 148, 5, 4, 36,
57 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
62 { 720, 576, 27000000, 64, 12, 68, 5, 5, 39,
63 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
68 { 1280, 720, 74250000, 40, 440, 220, 5, 5, 20,
69 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
74 { 1920, 540, 74250000, 44, 528, 148, 5, 2, 15,
75 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
80 { 1440, 288, 27000000, 126, 24, 138, 3, 2, 19,
81 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
86 { 1440, 576, 54000000, 128, 24, 136, 5, 5, 39,
87 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
92 { 1920, 1080, 148500000, 44, 528, 148, 5, 4, 36,
93 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
98 { 1920, 1080, 74250000, 44, 638, 148, 5, 4, 36,
99 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
104 { 2880, 480, 108108000, 248, 64, 240, 6, 9, 30,
105 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
110 { 2880, 576, 108000000, 256, 48, 272, 5, 5, 39,
111 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
117 static const struct hdmi_config vesa_timings[] = {
120 { 640, 480, 25175000, 96, 16, 48, 2, 11, 31,
121 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
126 { 800, 600, 40000000, 128, 40, 88, 4, 1, 23,
127 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
132 { 848, 480, 33750000, 112, 16, 112, 8, 6, 23,
133 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
138 { 1280, 768, 79500000, 128, 64, 192, 7, 3, 20,
139 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
144 { 1280, 800, 83500000, 128, 72, 200, 6, 3, 22,
145 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
150 { 1360, 768, 85500000, 112, 64, 256, 6, 3, 18,
151 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
156 { 1280, 960, 108000000, 112, 96, 312, 3, 1, 36,
157 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
162 { 1280, 1024, 108000000, 112, 48, 248, 3, 1, 38,
163 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
168 { 1024, 768, 65000000, 136, 24, 160, 6, 3, 29,
169 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
174 { 1400, 1050, 121750000, 144, 88, 232, 4, 3, 32,
175 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
180 { 1440, 900, 106500000, 152, 80, 232, 6, 3, 25,
181 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
186 { 1680, 1050, 146250000, 176 , 104, 280, 6, 3, 30,
187 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
192 { 1366, 768, 85500000, 143, 70, 213, 3, 3, 24,
193 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
198 { 1920, 1080, 148500000, 44, 148, 80, 5, 4, 36,
199 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
204 { 1280, 768, 68250000, 32, 48, 80, 7, 3, 12,
205 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
210 { 1400, 1050, 101000000, 32, 48, 80, 4, 3, 23,
211 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
216 { 1680, 1050, 119000000, 32, 48, 80, 6, 3, 21,
217 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
222 { 1280, 800, 79500000, 32, 48, 80, 6, 3, 14,
223 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
228 { 1280, 720, 74250000, 40, 110, 220, 5, 5, 20,
229 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
234 { 1920, 1200, 154000000, 32, 48, 80, 6, 3, 26,
235 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
241 const struct hdmi_config *hdmi_default_timing(void)
243 return &vesa_timings[0];
246 static const struct hdmi_config *hdmi_find_timing(int code,
247 const struct hdmi_config *timings_arr, int len)
251 for (i = 0; i < len; i++) {
252 if (timings_arr[i].cm.code == code)
253 return &timings_arr[i];
259 const struct hdmi_config *hdmi_get_timings(int mode, int code)
261 const struct hdmi_config *arr;
264 if (mode == HDMI_DVI) {
266 len = ARRAY_SIZE(vesa_timings);
269 len = ARRAY_SIZE(cea_timings);
272 return hdmi_find_timing(code, arr, len);
275 static bool hdmi_timings_compare(struct omap_video_timings *timing1,
276 const struct omap_video_timings *timing2)
278 int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
280 if ((DIV_ROUND_CLOSEST(timing2->pixelclock, 1000000) ==
281 DIV_ROUND_CLOSEST(timing1->pixelclock, 1000000)) &&
282 (timing2->x_res == timing1->x_res) &&
283 (timing2->y_res == timing1->y_res)) {
285 timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
286 timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
287 timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
288 timing1_vsync = timing1->vfp + timing1->vsw + timing1->vbp;
290 DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
291 "timing2_hsync = %d timing2_vsync = %d\n",
292 timing1_hsync, timing1_vsync,
293 timing2_hsync, timing2_vsync);
295 if ((timing1_hsync == timing2_hsync) &&
296 (timing1_vsync == timing2_vsync)) {
303 struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
306 struct hdmi_cm cm = {-1};
307 DSSDBG("hdmi_get_code\n");
309 for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
310 if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
311 cm = cea_timings[i].cm;
315 for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
316 if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
317 cm = vesa_timings[i].cm;
326 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
327 int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts)
330 bool deep_color_correct = false;
332 if (n == NULL || cts == NULL)
335 /* TODO: When implemented, query deep color mode here. */
339 * When using deep color, the default N value (as in the HDMI
340 * specification) yields to an non-integer CTS. Hence, we
341 * modify it while keeping the restrictions described in
342 * section 7.2.1 of the HDMI 1.4a specification.
344 switch (sample_freq) {
349 if (deep_color == 125)
350 if (pclk == 27027 || pclk == 74250)
351 deep_color_correct = true;
352 if (deep_color == 150)
354 deep_color_correct = true;
359 if (deep_color == 125)
361 deep_color_correct = true;
367 if (deep_color_correct) {
368 switch (sample_freq) {
394 switch (sample_freq) {
420 /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
421 *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);