2 * linux/drivers/video/omap2/dss/dpi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DPI"
25 #include <linux/kernel.h>
26 #include <linux/delay.h>
27 #include <linux/export.h>
28 #include <linux/err.h>
29 #include <linux/errno.h>
30 #include <linux/platform_device.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/string.h>
34 #include <video/omapdss.h>
37 #include "dss_features.h"
40 struct platform_device *pdev;
42 struct regulator *vdds_dsi_reg;
43 struct platform_device *dsidev;
47 struct omap_video_timings timings;
48 struct dss_lcd_mgr_config mgr_config;
51 struct omap_dss_device output;
54 static struct platform_device *dpi_get_dsidev(enum omap_channel channel)
57 * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL
58 * would also be used for DISPC fclk. Meaning, when the DPI output is
59 * disabled, DISPC clock will be disabled, and TV out will stop.
61 switch (omapdss_get_version()) {
62 case OMAPDSS_VER_OMAP24xx:
63 case OMAPDSS_VER_OMAP34xx_ES1:
64 case OMAPDSS_VER_OMAP34xx_ES3:
65 case OMAPDSS_VER_OMAP3630:
66 case OMAPDSS_VER_AM35xx:
69 case OMAPDSS_VER_OMAP4430_ES1:
70 case OMAPDSS_VER_OMAP4430_ES2:
71 case OMAPDSS_VER_OMAP4:
73 case OMAP_DSS_CHANNEL_LCD:
74 return dsi_get_dsidev_from_id(0);
75 case OMAP_DSS_CHANNEL_LCD2:
76 return dsi_get_dsidev_from_id(1);
81 case OMAPDSS_VER_OMAP5:
83 case OMAP_DSS_CHANNEL_LCD:
84 return dsi_get_dsidev_from_id(0);
85 case OMAP_DSS_CHANNEL_LCD3:
86 return dsi_get_dsidev_from_id(1);
96 static enum omap_dss_clk_source dpi_get_alt_clk_src(enum omap_channel channel)
99 case OMAP_DSS_CHANNEL_LCD:
100 return OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC;
101 case OMAP_DSS_CHANNEL_LCD2:
102 return OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC;
104 /* this shouldn't happen */
106 return OMAP_DSS_CLK_SRC_FCK;
110 struct dpi_clk_calc_ctx {
111 struct platform_device *dsidev;
115 unsigned long pck_min, pck_max;
119 struct dsi_clock_info dsi_cinfo;
121 struct dispc_clock_info dispc_cinfo;
124 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
125 unsigned long pck, void *data)
127 struct dpi_clk_calc_ctx *ctx = data;
130 * Odd dividers give us uneven duty cycle, causing problem when level
131 * shifted. So skip all odd dividers when the pixel clock is on the
134 if (ctx->pck_min >= 100000000) {
135 if (lckd > 1 && lckd % 2 != 0)
138 if (pckd > 1 && pckd % 2 != 0)
142 ctx->dispc_cinfo.lck_div = lckd;
143 ctx->dispc_cinfo.pck_div = pckd;
144 ctx->dispc_cinfo.lck = lck;
145 ctx->dispc_cinfo.pck = pck;
151 static bool dpi_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
154 struct dpi_clk_calc_ctx *ctx = data;
157 * Odd dividers give us uneven duty cycle, causing problem when level
158 * shifted. So skip all odd dividers when the pixel clock is on the
161 if (regm_dispc > 1 && regm_dispc % 2 != 0 && ctx->pck_min >= 100000000)
164 ctx->dsi_cinfo.regm_dispc = regm_dispc;
165 ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc;
167 return dispc_div_calc(dispc, ctx->pck_min, ctx->pck_max,
168 dpi_calc_dispc_cb, ctx);
172 static bool dpi_calc_pll_cb(int regn, int regm, unsigned long fint,
176 struct dpi_clk_calc_ctx *ctx = data;
178 ctx->dsi_cinfo.regn = regn;
179 ctx->dsi_cinfo.regm = regm;
180 ctx->dsi_cinfo.fint = fint;
181 ctx->dsi_cinfo.clkin4ddr = pll;
183 return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->pck_min,
184 dpi_calc_hsdiv_cb, ctx);
187 static bool dpi_calc_dss_cb(unsigned long fck, void *data)
189 struct dpi_clk_calc_ctx *ctx = data;
193 return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
194 dpi_calc_dispc_cb, ctx);
197 static bool dpi_dsi_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx)
200 unsigned long pll_min, pll_max;
202 clkin = dsi_get_pll_clkin(dpi.dsidev);
204 memset(ctx, 0, sizeof(*ctx));
205 ctx->dsidev = dpi.dsidev;
206 ctx->pck_min = pck - 1000;
207 ctx->pck_max = pck + 1000;
208 ctx->dsi_cinfo.clkin = clkin;
213 return dsi_pll_calc(dpi.dsidev, clkin,
215 dpi_calc_pll_cb, ctx);
218 static bool dpi_dss_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx)
223 * DSS fck gives us very few possibilities, so finding a good pixel
224 * clock may not be possible. We try multiple times to find the clock,
225 * each time widening the pixel clock range we look for, up to
229 for (i = 0; i < 25; ++i) {
232 memset(ctx, 0, sizeof(*ctx));
233 if (pck > 1000 * i * i * i)
234 ctx->pck_min = max(pck - 1000 * i * i * i, 0lu);
237 ctx->pck_max = pck + 1000 * i * i * i;
239 ok = dss_div_calc(pck, ctx->pck_min, dpi_calc_dss_cb, ctx);
249 static int dpi_set_dsi_clk(enum omap_channel channel,
250 unsigned long pck_req, unsigned long *fck, int *lck_div,
253 struct dpi_clk_calc_ctx ctx;
257 ok = dpi_dsi_clk_calc(pck_req, &ctx);
261 r = dsi_pll_set_clock_div(dpi.dsidev, &ctx.dsi_cinfo);
265 dss_select_lcd_clk_source(channel,
266 dpi_get_alt_clk_src(channel));
268 dpi.mgr_config.clock_info = ctx.dispc_cinfo;
270 *fck = ctx.dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
271 *lck_div = ctx.dispc_cinfo.lck_div;
272 *pck_div = ctx.dispc_cinfo.pck_div;
277 static int dpi_set_dispc_clk(unsigned long pck_req, unsigned long *fck,
278 int *lck_div, int *pck_div)
280 struct dpi_clk_calc_ctx ctx;
284 ok = dpi_dss_clk_calc(pck_req, &ctx);
288 r = dss_set_fck_rate(ctx.fck);
292 dpi.mgr_config.clock_info = ctx.dispc_cinfo;
295 *lck_div = ctx.dispc_cinfo.lck_div;
296 *pck_div = ctx.dispc_cinfo.pck_div;
301 static int dpi_set_mode(struct omap_overlay_manager *mgr)
303 struct omap_video_timings *t = &dpi.timings;
304 int lck_div = 0, pck_div = 0;
305 unsigned long fck = 0;
310 r = dpi_set_dsi_clk(mgr->id, t->pixelclock, &fck,
313 r = dpi_set_dispc_clk(t->pixelclock, &fck,
318 pck = fck / lck_div / pck_div;
320 if (pck != t->pixelclock) {
321 DSSWARN("Could not find exact pixel clock. Requested %d Hz, got %lu Hz\n",
327 dss_mgr_set_timings(mgr, t);
332 static void dpi_config_lcd_manager(struct omap_overlay_manager *mgr)
334 dpi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
336 dpi.mgr_config.stallmode = false;
337 dpi.mgr_config.fifohandcheck = false;
339 dpi.mgr_config.video_port_width = dpi.data_lines;
341 dpi.mgr_config.lcden_sig_polarity = 0;
343 dss_mgr_set_lcd_config(mgr, &dpi.mgr_config);
346 static int dpi_display_enable(struct omap_dss_device *dssdev)
348 struct omap_dss_device *out = &dpi.output;
351 mutex_lock(&dpi.lock);
353 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI) && !dpi.vdds_dsi_reg) {
354 DSSERR("no VDSS_DSI regulator\n");
359 if (out == NULL || out->manager == NULL) {
360 DSSERR("failed to enable display: no output/manager\n");
365 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI)) {
366 r = regulator_enable(dpi.vdds_dsi_reg);
371 r = dispc_runtime_get();
375 r = dss_dpi_select_source(out->manager->id);
380 r = dsi_runtime_get(dpi.dsidev);
384 r = dsi_pll_init(dpi.dsidev, 0, 1);
386 goto err_dsi_pll_init;
389 r = dpi_set_mode(out->manager);
393 dpi_config_lcd_manager(out->manager);
397 r = dss_mgr_enable(out->manager);
401 mutex_unlock(&dpi.lock);
408 dsi_pll_uninit(dpi.dsidev, true);
411 dsi_runtime_put(dpi.dsidev);
416 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
417 regulator_disable(dpi.vdds_dsi_reg);
421 mutex_unlock(&dpi.lock);
425 static void dpi_display_disable(struct omap_dss_device *dssdev)
427 struct omap_overlay_manager *mgr = dpi.output.manager;
429 mutex_lock(&dpi.lock);
431 dss_mgr_disable(mgr);
434 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
435 dsi_pll_uninit(dpi.dsidev, true);
436 dsi_runtime_put(dpi.dsidev);
441 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
442 regulator_disable(dpi.vdds_dsi_reg);
444 mutex_unlock(&dpi.lock);
447 static void dpi_set_timings(struct omap_dss_device *dssdev,
448 struct omap_video_timings *timings)
450 DSSDBG("dpi_set_timings\n");
452 mutex_lock(&dpi.lock);
454 dpi.timings = *timings;
456 mutex_unlock(&dpi.lock);
459 static void dpi_get_timings(struct omap_dss_device *dssdev,
460 struct omap_video_timings *timings)
462 mutex_lock(&dpi.lock);
464 *timings = dpi.timings;
466 mutex_unlock(&dpi.lock);
469 static int dpi_check_timings(struct omap_dss_device *dssdev,
470 struct omap_video_timings *timings)
472 struct omap_overlay_manager *mgr = dpi.output.manager;
473 int lck_div, pck_div;
476 struct dpi_clk_calc_ctx ctx;
479 if (mgr && !dispc_mgr_timings_ok(mgr->id, timings))
482 if (timings->pixelclock == 0)
486 ok = dpi_dsi_clk_calc(timings->pixelclock, &ctx);
490 fck = ctx.dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
492 ok = dpi_dss_clk_calc(timings->pixelclock, &ctx);
499 lck_div = ctx.dispc_cinfo.lck_div;
500 pck_div = ctx.dispc_cinfo.pck_div;
502 pck = fck / lck_div / pck_div;
504 timings->pixelclock = pck;
509 static void dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines)
511 mutex_lock(&dpi.lock);
513 dpi.data_lines = data_lines;
515 mutex_unlock(&dpi.lock);
518 static int dpi_verify_dsi_pll(struct platform_device *dsidev)
522 /* do initial setup with the PLL to see if it is operational */
524 r = dsi_runtime_get(dsidev);
528 r = dsi_pll_init(dsidev, 0, 1);
530 dsi_runtime_put(dsidev);
534 dsi_pll_uninit(dsidev, true);
535 dsi_runtime_put(dsidev);
540 static int dpi_init_regulator(void)
542 struct regulator *vdds_dsi;
544 if (!dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
547 if (dpi.vdds_dsi_reg)
550 vdds_dsi = devm_regulator_get(&dpi.pdev->dev, "vdds_dsi");
551 if (IS_ERR(vdds_dsi)) {
552 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
553 DSSERR("can't get VDDS_DSI regulator\n");
554 return PTR_ERR(vdds_dsi);
557 dpi.vdds_dsi_reg = vdds_dsi;
562 static void dpi_init_pll(void)
564 struct platform_device *dsidev;
569 dsidev = dpi_get_dsidev(dpi.output.dispc_channel);
573 if (dpi_verify_dsi_pll(dsidev)) {
574 DSSWARN("DSI PLL not operational\n");
582 * Return a hardcoded channel for the DPI output. This should work for
583 * current use cases, but this can be later expanded to either resolve
584 * the channel in some more dynamic manner, or get the channel as a user
587 static enum omap_channel dpi_get_channel(void)
589 switch (omapdss_get_version()) {
590 case OMAPDSS_VER_OMAP24xx:
591 case OMAPDSS_VER_OMAP34xx_ES1:
592 case OMAPDSS_VER_OMAP34xx_ES3:
593 case OMAPDSS_VER_OMAP3630:
594 case OMAPDSS_VER_AM35xx:
595 return OMAP_DSS_CHANNEL_LCD;
597 case OMAPDSS_VER_OMAP4430_ES1:
598 case OMAPDSS_VER_OMAP4430_ES2:
599 case OMAPDSS_VER_OMAP4:
600 return OMAP_DSS_CHANNEL_LCD2;
602 case OMAPDSS_VER_OMAP5:
603 return OMAP_DSS_CHANNEL_LCD3;
606 DSSWARN("unsupported DSS version\n");
607 return OMAP_DSS_CHANNEL_LCD;
611 static int dpi_connect(struct omap_dss_device *dssdev,
612 struct omap_dss_device *dst)
614 struct omap_overlay_manager *mgr;
617 r = dpi_init_regulator();
623 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
627 r = dss_mgr_connect(mgr, dssdev);
631 r = omapdss_output_set_device(dssdev, dst);
633 DSSERR("failed to connect output to new device: %s\n",
635 dss_mgr_disconnect(mgr, dssdev);
642 static void dpi_disconnect(struct omap_dss_device *dssdev,
643 struct omap_dss_device *dst)
645 WARN_ON(dst != dssdev->dst);
647 if (dst != dssdev->dst)
650 omapdss_output_unset_device(dssdev);
653 dss_mgr_disconnect(dssdev->manager, dssdev);
656 static const struct omapdss_dpi_ops dpi_ops = {
657 .connect = dpi_connect,
658 .disconnect = dpi_disconnect,
660 .enable = dpi_display_enable,
661 .disable = dpi_display_disable,
663 .check_timings = dpi_check_timings,
664 .set_timings = dpi_set_timings,
665 .get_timings = dpi_get_timings,
667 .set_data_lines = dpi_set_data_lines,
670 static void dpi_init_output(struct platform_device *pdev)
672 struct omap_dss_device *out = &dpi.output;
674 out->dev = &pdev->dev;
675 out->id = OMAP_DSS_OUTPUT_DPI;
676 out->output_type = OMAP_DISPLAY_TYPE_DPI;
678 out->dispc_channel = dpi_get_channel();
679 out->ops.dpi = &dpi_ops;
680 out->owner = THIS_MODULE;
682 omapdss_register_output(out);
685 static void __exit dpi_uninit_output(struct platform_device *pdev)
687 struct omap_dss_device *out = &dpi.output;
689 omapdss_unregister_output(out);
692 static int omap_dpi_probe(struct platform_device *pdev)
696 mutex_init(&dpi.lock);
698 dpi_init_output(pdev);
703 static int __exit omap_dpi_remove(struct platform_device *pdev)
705 dpi_uninit_output(pdev);
710 static struct platform_driver omap_dpi_driver = {
711 .probe = omap_dpi_probe,
712 .remove = __exit_p(omap_dpi_remove),
714 .name = "omapdss_dpi",
715 .owner = THIS_MODULE,
719 int __init dpi_init_platform_driver(void)
721 return platform_driver_register(&omap_dpi_driver);
724 void __exit dpi_uninit_platform_driver(void)
726 platform_driver_unregister(&omap_dpi_driver);