2 * linux/drivers/video/omap2/dss/dispc.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DISPC"
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/clk.h>
30 #include <linux/jiffies.h>
31 #include <linux/seq_file.h>
32 #include <linux/delay.h>
33 #include <linux/workqueue.h>
34 #include <linux/hardirq.h>
35 #include <linux/interrupt.h>
37 #include <plat/sram.h>
38 #include <plat/clock.h>
40 #include <plat/display.h>
43 #include "dss_features.h"
46 #define DISPC_SZ_REGS SZ_4K
48 struct dispc_reg { u16 idx; };
50 #define DISPC_REG(idx) ((const struct dispc_reg) { idx })
53 * DISPC common registers and
54 * DISPC channel registers , ch = 0 for LCD, ch = 1 for
55 * DIGIT, and ch = 2 for LCD2
57 #define DISPC_REVISION DISPC_REG(0x0000)
58 #define DISPC_SYSCONFIG DISPC_REG(0x0010)
59 #define DISPC_SYSSTATUS DISPC_REG(0x0014)
60 #define DISPC_IRQSTATUS DISPC_REG(0x0018)
61 #define DISPC_IRQENABLE DISPC_REG(0x001C)
62 #define DISPC_CONTROL DISPC_REG(0x0040)
63 #define DISPC_CONTROL2 DISPC_REG(0x0238)
64 #define DISPC_CONFIG DISPC_REG(0x0044)
65 #define DISPC_CONFIG2 DISPC_REG(0x0620)
66 #define DISPC_CAPABLE DISPC_REG(0x0048)
67 #define DISPC_DEFAULT_COLOR(ch) DISPC_REG(ch == 0 ? 0x004C : \
68 (ch == 1 ? 0x0050 : 0x03AC))
69 #define DISPC_TRANS_COLOR(ch) DISPC_REG(ch == 0 ? 0x0054 : \
70 (ch == 1 ? 0x0058 : 0x03B0))
71 #define DISPC_LINE_STATUS DISPC_REG(0x005C)
72 #define DISPC_LINE_NUMBER DISPC_REG(0x0060)
73 #define DISPC_TIMING_H(ch) DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
74 #define DISPC_TIMING_V(ch) DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
75 #define DISPC_POL_FREQ(ch) DISPC_REG(ch != 2 ? 0x006C : 0x0408)
76 #define DISPC_DIVISOR(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
77 #define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
78 #define DISPC_SIZE_DIG DISPC_REG(0x0078)
79 #define DISPC_SIZE_LCD(ch) DISPC_REG(ch != 2 ? 0x007C : 0x03CC)
82 #define DISPC_GFX_BA0 DISPC_REG(0x0080)
83 #define DISPC_GFX_BA1 DISPC_REG(0x0084)
84 #define DISPC_GFX_POSITION DISPC_REG(0x0088)
85 #define DISPC_GFX_SIZE DISPC_REG(0x008C)
86 #define DISPC_GFX_ATTRIBUTES DISPC_REG(0x00A0)
87 #define DISPC_GFX_FIFO_THRESHOLD DISPC_REG(0x00A4)
88 #define DISPC_GFX_FIFO_SIZE_STATUS DISPC_REG(0x00A8)
89 #define DISPC_GFX_ROW_INC DISPC_REG(0x00AC)
90 #define DISPC_GFX_PIXEL_INC DISPC_REG(0x00B0)
91 #define DISPC_GFX_WINDOW_SKIP DISPC_REG(0x00B4)
92 #define DISPC_GFX_TABLE_BA DISPC_REG(0x00B8)
94 #define DISPC_DATA_CYCLE1(ch) DISPC_REG(ch != 2 ? 0x01D4 : 0x03C0)
95 #define DISPC_DATA_CYCLE2(ch) DISPC_REG(ch != 2 ? 0x01D8 : 0x03C4)
96 #define DISPC_DATA_CYCLE3(ch) DISPC_REG(ch != 2 ? 0x01DC : 0x03C8)
97 #define DISPC_CPR_COEF_R(ch) DISPC_REG(ch != 2 ? 0x0220 : 0x03BC)
98 #define DISPC_CPR_COEF_G(ch) DISPC_REG(ch != 2 ? 0x0224 : 0x03B8)
99 #define DISPC_CPR_COEF_B(ch) DISPC_REG(ch != 2 ? 0x0228 : 0x03B4)
101 #define DISPC_GFX_PRELOAD DISPC_REG(0x022C)
103 /* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
104 #define DISPC_VID_REG(n, idx) DISPC_REG(0x00BC + (n)*0x90 + idx)
106 #define DISPC_VID_BA0(n) DISPC_VID_REG(n, 0x0000)
107 #define DISPC_VID_BA1(n) DISPC_VID_REG(n, 0x0004)
108 #define DISPC_VID_POSITION(n) DISPC_VID_REG(n, 0x0008)
109 #define DISPC_VID_SIZE(n) DISPC_VID_REG(n, 0x000C)
110 #define DISPC_VID_ATTRIBUTES(n) DISPC_VID_REG(n, 0x0010)
111 #define DISPC_VID_FIFO_THRESHOLD(n) DISPC_VID_REG(n, 0x0014)
112 #define DISPC_VID_FIFO_SIZE_STATUS(n) DISPC_VID_REG(n, 0x0018)
113 #define DISPC_VID_ROW_INC(n) DISPC_VID_REG(n, 0x001C)
114 #define DISPC_VID_PIXEL_INC(n) DISPC_VID_REG(n, 0x0020)
115 #define DISPC_VID_FIR(n) DISPC_VID_REG(n, 0x0024)
116 #define DISPC_VID_PICTURE_SIZE(n) DISPC_VID_REG(n, 0x0028)
117 #define DISPC_VID_ACCU0(n) DISPC_VID_REG(n, 0x002C)
118 #define DISPC_VID_ACCU1(n) DISPC_VID_REG(n, 0x0030)
120 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
121 #define DISPC_VID_FIR_COEF_H(n, i) DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
122 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
123 #define DISPC_VID_FIR_COEF_HV(n, i) DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
124 /* coef index i = {0, 1, 2, 3, 4} */
125 #define DISPC_VID_CONV_COEF(n, i) DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
126 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
127 #define DISPC_VID_FIR_COEF_V(n, i) DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
129 #define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04)
132 #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
133 DISPC_IRQ_OCP_ERR | \
134 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
135 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
136 DISPC_IRQ_SYNC_LOST | \
137 DISPC_IRQ_SYNC_LOST_DIGIT)
139 #define DISPC_MAX_NR_ISRS 8
141 struct omap_dispc_isr_data {
142 omap_dispc_isr_t isr;
147 struct dispc_h_coef {
155 struct dispc_v_coef {
163 #define REG_GET(idx, start, end) \
164 FLD_GET(dispc_read_reg(idx), start, end)
166 #define REG_FLD_MOD(idx, val, start, end) \
167 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
169 static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
170 DISPC_VID_ATTRIBUTES(0),
171 DISPC_VID_ATTRIBUTES(1) };
173 struct dispc_irq_stats {
174 unsigned long last_reset;
180 struct platform_device *pdev;
188 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
190 struct work_struct error_work;
192 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
194 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
195 spinlock_t irq_stats_lock;
196 struct dispc_irq_stats irq_stats;
200 static void _omap_dispc_set_irqs(void);
202 static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
204 __raw_writel(val, dispc.base + idx.idx);
207 static inline u32 dispc_read_reg(const struct dispc_reg idx)
209 return __raw_readl(dispc.base + idx.idx);
213 dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
215 dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
217 void dispc_save_context(void)
219 if (cpu_is_omap24xx())
226 SR(DEFAULT_COLOR(0));
227 SR(DEFAULT_COLOR(1));
238 if (dss_has_feature(FEAT_MGR_LCD2)) {
240 SR(DEFAULT_COLOR(2));
255 SR(GFX_FIFO_THRESHOLD);
268 if (dss_has_feature(FEAT_MGR_LCD2)) {
285 SR(VID_ATTRIBUTES(0));
286 SR(VID_FIFO_THRESHOLD(0));
288 SR(VID_PIXEL_INC(0));
290 SR(VID_PICTURE_SIZE(0));
294 SR(VID_FIR_COEF_H(0, 0));
295 SR(VID_FIR_COEF_H(0, 1));
296 SR(VID_FIR_COEF_H(0, 2));
297 SR(VID_FIR_COEF_H(0, 3));
298 SR(VID_FIR_COEF_H(0, 4));
299 SR(VID_FIR_COEF_H(0, 5));
300 SR(VID_FIR_COEF_H(0, 6));
301 SR(VID_FIR_COEF_H(0, 7));
303 SR(VID_FIR_COEF_HV(0, 0));
304 SR(VID_FIR_COEF_HV(0, 1));
305 SR(VID_FIR_COEF_HV(0, 2));
306 SR(VID_FIR_COEF_HV(0, 3));
307 SR(VID_FIR_COEF_HV(0, 4));
308 SR(VID_FIR_COEF_HV(0, 5));
309 SR(VID_FIR_COEF_HV(0, 6));
310 SR(VID_FIR_COEF_HV(0, 7));
312 SR(VID_CONV_COEF(0, 0));
313 SR(VID_CONV_COEF(0, 1));
314 SR(VID_CONV_COEF(0, 2));
315 SR(VID_CONV_COEF(0, 3));
316 SR(VID_CONV_COEF(0, 4));
318 SR(VID_FIR_COEF_V(0, 0));
319 SR(VID_FIR_COEF_V(0, 1));
320 SR(VID_FIR_COEF_V(0, 2));
321 SR(VID_FIR_COEF_V(0, 3));
322 SR(VID_FIR_COEF_V(0, 4));
323 SR(VID_FIR_COEF_V(0, 5));
324 SR(VID_FIR_COEF_V(0, 6));
325 SR(VID_FIR_COEF_V(0, 7));
334 SR(VID_ATTRIBUTES(1));
335 SR(VID_FIFO_THRESHOLD(1));
337 SR(VID_PIXEL_INC(1));
339 SR(VID_PICTURE_SIZE(1));
343 SR(VID_FIR_COEF_H(1, 0));
344 SR(VID_FIR_COEF_H(1, 1));
345 SR(VID_FIR_COEF_H(1, 2));
346 SR(VID_FIR_COEF_H(1, 3));
347 SR(VID_FIR_COEF_H(1, 4));
348 SR(VID_FIR_COEF_H(1, 5));
349 SR(VID_FIR_COEF_H(1, 6));
350 SR(VID_FIR_COEF_H(1, 7));
352 SR(VID_FIR_COEF_HV(1, 0));
353 SR(VID_FIR_COEF_HV(1, 1));
354 SR(VID_FIR_COEF_HV(1, 2));
355 SR(VID_FIR_COEF_HV(1, 3));
356 SR(VID_FIR_COEF_HV(1, 4));
357 SR(VID_FIR_COEF_HV(1, 5));
358 SR(VID_FIR_COEF_HV(1, 6));
359 SR(VID_FIR_COEF_HV(1, 7));
361 SR(VID_CONV_COEF(1, 0));
362 SR(VID_CONV_COEF(1, 1));
363 SR(VID_CONV_COEF(1, 2));
364 SR(VID_CONV_COEF(1, 3));
365 SR(VID_CONV_COEF(1, 4));
367 SR(VID_FIR_COEF_V(1, 0));
368 SR(VID_FIR_COEF_V(1, 1));
369 SR(VID_FIR_COEF_V(1, 2));
370 SR(VID_FIR_COEF_V(1, 3));
371 SR(VID_FIR_COEF_V(1, 4));
372 SR(VID_FIR_COEF_V(1, 5));
373 SR(VID_FIR_COEF_V(1, 6));
374 SR(VID_FIR_COEF_V(1, 7));
379 void dispc_restore_context(void)
385 RR(DEFAULT_COLOR(0));
386 RR(DEFAULT_COLOR(1));
397 if (dss_has_feature(FEAT_MGR_LCD2)) {
398 RR(DEFAULT_COLOR(2));
413 RR(GFX_FIFO_THRESHOLD);
426 if (dss_has_feature(FEAT_MGR_LCD2)) {
443 RR(VID_ATTRIBUTES(0));
444 RR(VID_FIFO_THRESHOLD(0));
446 RR(VID_PIXEL_INC(0));
448 RR(VID_PICTURE_SIZE(0));
452 RR(VID_FIR_COEF_H(0, 0));
453 RR(VID_FIR_COEF_H(0, 1));
454 RR(VID_FIR_COEF_H(0, 2));
455 RR(VID_FIR_COEF_H(0, 3));
456 RR(VID_FIR_COEF_H(0, 4));
457 RR(VID_FIR_COEF_H(0, 5));
458 RR(VID_FIR_COEF_H(0, 6));
459 RR(VID_FIR_COEF_H(0, 7));
461 RR(VID_FIR_COEF_HV(0, 0));
462 RR(VID_FIR_COEF_HV(0, 1));
463 RR(VID_FIR_COEF_HV(0, 2));
464 RR(VID_FIR_COEF_HV(0, 3));
465 RR(VID_FIR_COEF_HV(0, 4));
466 RR(VID_FIR_COEF_HV(0, 5));
467 RR(VID_FIR_COEF_HV(0, 6));
468 RR(VID_FIR_COEF_HV(0, 7));
470 RR(VID_CONV_COEF(0, 0));
471 RR(VID_CONV_COEF(0, 1));
472 RR(VID_CONV_COEF(0, 2));
473 RR(VID_CONV_COEF(0, 3));
474 RR(VID_CONV_COEF(0, 4));
476 RR(VID_FIR_COEF_V(0, 0));
477 RR(VID_FIR_COEF_V(0, 1));
478 RR(VID_FIR_COEF_V(0, 2));
479 RR(VID_FIR_COEF_V(0, 3));
480 RR(VID_FIR_COEF_V(0, 4));
481 RR(VID_FIR_COEF_V(0, 5));
482 RR(VID_FIR_COEF_V(0, 6));
483 RR(VID_FIR_COEF_V(0, 7));
492 RR(VID_ATTRIBUTES(1));
493 RR(VID_FIFO_THRESHOLD(1));
495 RR(VID_PIXEL_INC(1));
497 RR(VID_PICTURE_SIZE(1));
501 RR(VID_FIR_COEF_H(1, 0));
502 RR(VID_FIR_COEF_H(1, 1));
503 RR(VID_FIR_COEF_H(1, 2));
504 RR(VID_FIR_COEF_H(1, 3));
505 RR(VID_FIR_COEF_H(1, 4));
506 RR(VID_FIR_COEF_H(1, 5));
507 RR(VID_FIR_COEF_H(1, 6));
508 RR(VID_FIR_COEF_H(1, 7));
510 RR(VID_FIR_COEF_HV(1, 0));
511 RR(VID_FIR_COEF_HV(1, 1));
512 RR(VID_FIR_COEF_HV(1, 2));
513 RR(VID_FIR_COEF_HV(1, 3));
514 RR(VID_FIR_COEF_HV(1, 4));
515 RR(VID_FIR_COEF_HV(1, 5));
516 RR(VID_FIR_COEF_HV(1, 6));
517 RR(VID_FIR_COEF_HV(1, 7));
519 RR(VID_CONV_COEF(1, 0));
520 RR(VID_CONV_COEF(1, 1));
521 RR(VID_CONV_COEF(1, 2));
522 RR(VID_CONV_COEF(1, 3));
523 RR(VID_CONV_COEF(1, 4));
525 RR(VID_FIR_COEF_V(1, 0));
526 RR(VID_FIR_COEF_V(1, 1));
527 RR(VID_FIR_COEF_V(1, 2));
528 RR(VID_FIR_COEF_V(1, 3));
529 RR(VID_FIR_COEF_V(1, 4));
530 RR(VID_FIR_COEF_V(1, 5));
531 RR(VID_FIR_COEF_V(1, 6));
532 RR(VID_FIR_COEF_V(1, 7));
536 /* enable last, because LCD & DIGIT enable are here */
538 if (dss_has_feature(FEAT_MGR_LCD2))
540 /* clear spurious SYNC_LOST_DIGIT interrupts */
541 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
544 * enable last so IRQs won't trigger before
545 * the context is fully restored
553 static inline void enable_clocks(bool enable)
556 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
558 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
561 bool dispc_go_busy(enum omap_channel channel)
565 if (channel == OMAP_DSS_CHANNEL_LCD ||
566 channel == OMAP_DSS_CHANNEL_LCD2)
569 bit = 6; /* GODIGIT */
571 if (channel == OMAP_DSS_CHANNEL_LCD2)
572 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
574 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
577 void dispc_go(enum omap_channel channel)
580 bool enable_bit, go_bit;
584 if (channel == OMAP_DSS_CHANNEL_LCD ||
585 channel == OMAP_DSS_CHANNEL_LCD2)
586 bit = 0; /* LCDENABLE */
588 bit = 1; /* DIGITALENABLE */
590 /* if the channel is not enabled, we don't need GO */
591 if (channel == OMAP_DSS_CHANNEL_LCD2)
592 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
594 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
599 if (channel == OMAP_DSS_CHANNEL_LCD ||
600 channel == OMAP_DSS_CHANNEL_LCD2)
603 bit = 6; /* GODIGIT */
605 if (channel == OMAP_DSS_CHANNEL_LCD2)
606 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
608 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
611 DSSERR("GO bit not down for channel %d\n", channel);
615 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
616 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
618 if (channel == OMAP_DSS_CHANNEL_LCD2)
619 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
621 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
626 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
628 BUG_ON(plane == OMAP_DSS_GFX);
630 dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
633 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
635 BUG_ON(plane == OMAP_DSS_GFX);
637 dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
640 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
642 BUG_ON(plane == OMAP_DSS_GFX);
644 dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
647 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
648 int vscaleup, int five_taps)
650 /* Coefficients for horizontal up-sampling */
651 static const struct dispc_h_coef coef_hup[8] = {
653 { -1, 13, 124, -8, 0 },
654 { -2, 30, 112, -11, -1 },
655 { -5, 51, 95, -11, -2 },
656 { 0, -9, 73, 73, -9 },
657 { -2, -11, 95, 51, -5 },
658 { -1, -11, 112, 30, -2 },
659 { 0, -8, 124, 13, -1 },
662 /* Coefficients for vertical up-sampling */
663 static const struct dispc_v_coef coef_vup_3tap[8] = {
666 { 0, 12, 111, 5, 0 },
670 { 0, 5, 111, 12, 0 },
674 static const struct dispc_v_coef coef_vup_5tap[8] = {
676 { -1, 13, 124, -8, 0 },
677 { -2, 30, 112, -11, -1 },
678 { -5, 51, 95, -11, -2 },
679 { 0, -9, 73, 73, -9 },
680 { -2, -11, 95, 51, -5 },
681 { -1, -11, 112, 30, -2 },
682 { 0, -8, 124, 13, -1 },
685 /* Coefficients for horizontal down-sampling */
686 static const struct dispc_h_coef coef_hdown[8] = {
687 { 0, 36, 56, 36, 0 },
688 { 4, 40, 55, 31, -2 },
689 { 8, 44, 54, 27, -5 },
690 { 12, 48, 53, 22, -7 },
691 { -9, 17, 52, 51, 17 },
692 { -7, 22, 53, 48, 12 },
693 { -5, 27, 54, 44, 8 },
694 { -2, 31, 55, 40, 4 },
697 /* Coefficients for vertical down-sampling */
698 static const struct dispc_v_coef coef_vdown_3tap[8] = {
699 { 0, 36, 56, 36, 0 },
700 { 0, 40, 57, 31, 0 },
701 { 0, 45, 56, 27, 0 },
702 { 0, 50, 55, 23, 0 },
703 { 0, 18, 55, 55, 0 },
704 { 0, 23, 55, 50, 0 },
705 { 0, 27, 56, 45, 0 },
706 { 0, 31, 57, 40, 0 },
709 static const struct dispc_v_coef coef_vdown_5tap[8] = {
710 { 0, 36, 56, 36, 0 },
711 { 4, 40, 55, 31, -2 },
712 { 8, 44, 54, 27, -5 },
713 { 12, 48, 53, 22, -7 },
714 { -9, 17, 52, 51, 17 },
715 { -7, 22, 53, 48, 12 },
716 { -5, 27, 54, 44, 8 },
717 { -2, 31, 55, 40, 4 },
720 const struct dispc_h_coef *h_coef;
721 const struct dispc_v_coef *v_coef;
730 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
732 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
734 for (i = 0; i < 8; i++) {
737 h = FLD_VAL(h_coef[i].hc0, 7, 0)
738 | FLD_VAL(h_coef[i].hc1, 15, 8)
739 | FLD_VAL(h_coef[i].hc2, 23, 16)
740 | FLD_VAL(h_coef[i].hc3, 31, 24);
741 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
742 | FLD_VAL(v_coef[i].vc0, 15, 8)
743 | FLD_VAL(v_coef[i].vc1, 23, 16)
744 | FLD_VAL(v_coef[i].vc2, 31, 24);
746 _dispc_write_firh_reg(plane, i, h);
747 _dispc_write_firhv_reg(plane, i, hv);
751 for (i = 0; i < 8; i++) {
753 v = FLD_VAL(v_coef[i].vc00, 7, 0)
754 | FLD_VAL(v_coef[i].vc22, 15, 8);
755 _dispc_write_firv_reg(plane, i, v);
760 static void _dispc_setup_color_conv_coef(void)
762 const struct color_conv_coef {
763 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
766 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
769 const struct color_conv_coef *ct;
771 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
775 dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
776 dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy, ct->rcb));
777 dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
778 dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
779 dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0, ct->bcb));
781 dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
782 dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy, ct->rcb));
783 dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
784 dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
785 dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0, ct->bcb));
789 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
790 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
794 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
796 const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
800 dispc_write_reg(ba0_reg[plane], paddr);
803 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
805 const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
809 dispc_write_reg(ba1_reg[plane], paddr);
812 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
814 const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
815 DISPC_VID_POSITION(0),
816 DISPC_VID_POSITION(1) };
818 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
819 dispc_write_reg(pos_reg[plane], val);
822 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
824 const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
825 DISPC_VID_PICTURE_SIZE(0),
826 DISPC_VID_PICTURE_SIZE(1) };
827 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
828 dispc_write_reg(siz_reg[plane], val);
831 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
834 const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
837 BUG_ON(plane == OMAP_DSS_GFX);
839 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
840 dispc_write_reg(vsi_reg[plane-1], val);
843 static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
845 if (!dss_has_feature(FEAT_PRE_MULT_ALPHA))
848 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
849 plane == OMAP_DSS_VIDEO1)
852 REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 28, 28);
855 static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
857 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
860 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
861 plane == OMAP_DSS_VIDEO1)
864 if (plane == OMAP_DSS_GFX)
865 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
866 else if (plane == OMAP_DSS_VIDEO2)
867 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
870 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
872 const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
873 DISPC_VID_PIXEL_INC(0),
874 DISPC_VID_PIXEL_INC(1) };
876 dispc_write_reg(ri_reg[plane], inc);
879 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
881 const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
882 DISPC_VID_ROW_INC(0),
883 DISPC_VID_ROW_INC(1) };
885 dispc_write_reg(ri_reg[plane], inc);
888 static void _dispc_set_color_mode(enum omap_plane plane,
889 enum omap_color_mode color_mode)
893 switch (color_mode) {
894 case OMAP_DSS_COLOR_CLUT1:
896 case OMAP_DSS_COLOR_CLUT2:
898 case OMAP_DSS_COLOR_CLUT4:
900 case OMAP_DSS_COLOR_CLUT8:
902 case OMAP_DSS_COLOR_RGB12U:
904 case OMAP_DSS_COLOR_ARGB16:
906 case OMAP_DSS_COLOR_RGB16:
908 case OMAP_DSS_COLOR_RGB24U:
910 case OMAP_DSS_COLOR_RGB24P:
912 case OMAP_DSS_COLOR_YUV2:
914 case OMAP_DSS_COLOR_UYVY:
916 case OMAP_DSS_COLOR_ARGB32:
918 case OMAP_DSS_COLOR_RGBA32:
920 case OMAP_DSS_COLOR_RGBX32:
926 REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
929 static void _dispc_set_channel_out(enum omap_plane plane,
930 enum omap_channel channel)
934 int chan = 0, chan2 = 0;
940 case OMAP_DSS_VIDEO1:
941 case OMAP_DSS_VIDEO2:
949 val = dispc_read_reg(dispc_reg_att[plane]);
950 if (dss_has_feature(FEAT_MGR_LCD2)) {
952 case OMAP_DSS_CHANNEL_LCD:
956 case OMAP_DSS_CHANNEL_DIGIT:
960 case OMAP_DSS_CHANNEL_LCD2:
968 val = FLD_MOD(val, chan, shift, shift);
969 val = FLD_MOD(val, chan2, 31, 30);
971 val = FLD_MOD(val, channel, shift, shift);
973 dispc_write_reg(dispc_reg_att[plane], val);
976 void dispc_set_burst_size(enum omap_plane plane,
977 enum omap_burst_size burst_size)
988 case OMAP_DSS_VIDEO1:
989 case OMAP_DSS_VIDEO2:
997 val = dispc_read_reg(dispc_reg_att[plane]);
998 val = FLD_MOD(val, burst_size, shift+1, shift);
999 dispc_write_reg(dispc_reg_att[plane], val);
1004 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
1008 BUG_ON(plane == OMAP_DSS_GFX);
1010 val = dispc_read_reg(dispc_reg_att[plane]);
1011 val = FLD_MOD(val, enable, 9, 9);
1012 dispc_write_reg(dispc_reg_att[plane], val);
1015 void dispc_enable_replication(enum omap_plane plane, bool enable)
1019 if (plane == OMAP_DSS_GFX)
1025 REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit);
1029 void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
1032 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1033 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1035 dispc_write_reg(DISPC_SIZE_LCD(channel), val);
1039 void dispc_set_digit_size(u16 width, u16 height)
1042 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1043 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1045 dispc_write_reg(DISPC_SIZE_DIG, val);
1049 static void dispc_read_plane_fifo_sizes(void)
1051 const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
1052 DISPC_VID_FIFO_SIZE_STATUS(0),
1053 DISPC_VID_FIFO_SIZE_STATUS(1) };
1060 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1062 for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
1063 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), start, end);
1064 dispc.fifo_size[plane] = size;
1070 u32 dispc_get_plane_fifo_size(enum omap_plane plane)
1072 return dispc.fifo_size[plane];
1075 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
1077 const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
1078 DISPC_VID_FIFO_THRESHOLD(0),
1079 DISPC_VID_FIFO_THRESHOLD(1) };
1080 u8 hi_start, hi_end, lo_start, lo_end;
1084 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1086 REG_GET(ftrs_reg[plane], 11, 0),
1087 REG_GET(ftrs_reg[plane], 27, 16),
1090 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1091 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1093 dispc_write_reg(ftrs_reg[plane],
1094 FLD_VAL(high, hi_start, hi_end) |
1095 FLD_VAL(low, lo_start, lo_end));
1100 void dispc_enable_fifomerge(bool enable)
1104 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1105 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1110 static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
1113 const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
1115 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1117 BUG_ON(plane == OMAP_DSS_GFX);
1119 dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
1120 dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
1122 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1123 FLD_VAL(hinc, hinc_start, hinc_end);
1125 dispc_write_reg(fir_reg[plane-1], val);
1128 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1131 const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1132 DISPC_VID_ACCU0(1) };
1134 BUG_ON(plane == OMAP_DSS_GFX);
1136 val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1137 dispc_write_reg(ac0_reg[plane-1], val);
1140 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1143 const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1144 DISPC_VID_ACCU1(1) };
1146 BUG_ON(plane == OMAP_DSS_GFX);
1148 val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1149 dispc_write_reg(ac1_reg[plane-1], val);
1153 static void _dispc_set_scaling(enum omap_plane plane,
1154 u16 orig_width, u16 orig_height,
1155 u16 out_width, u16 out_height,
1156 bool ilace, bool five_taps,
1161 int hscaleup, vscaleup;
1166 BUG_ON(plane == OMAP_DSS_GFX);
1168 hscaleup = orig_width <= out_width;
1169 vscaleup = orig_height <= out_height;
1171 _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1173 if (!orig_width || orig_width == out_width)
1176 fir_hinc = 1024 * orig_width / out_width;
1178 if (!orig_height || orig_height == out_height)
1181 fir_vinc = 1024 * orig_height / out_height;
1183 _dispc_set_fir(plane, fir_hinc, fir_vinc);
1185 l = dispc_read_reg(dispc_reg_att[plane]);
1186 l &= ~((0x0f << 5) | (0x3 << 21));
1188 l |= fir_hinc ? (1 << 5) : 0;
1189 l |= fir_vinc ? (1 << 6) : 0;
1191 l |= hscaleup ? 0 : (1 << 7);
1192 l |= vscaleup ? 0 : (1 << 8);
1194 l |= five_taps ? (1 << 21) : 0;
1195 l |= five_taps ? (1 << 22) : 0;
1197 dispc_write_reg(dispc_reg_att[plane], l);
1200 * field 0 = even field = bottom field
1201 * field 1 = odd field = top field
1203 if (ilace && !fieldmode) {
1205 accu0 = (fir_vinc / 2) & 0x3ff;
1206 if (accu0 >= 1024/2) {
1212 _dispc_set_vid_accu0(plane, 0, accu0);
1213 _dispc_set_vid_accu1(plane, 0, accu1);
1216 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1217 bool mirroring, enum omap_color_mode color_mode)
1219 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1220 color_mode == OMAP_DSS_COLOR_UYVY) {
1225 case OMAP_DSS_ROT_0:
1228 case OMAP_DSS_ROT_90:
1231 case OMAP_DSS_ROT_180:
1234 case OMAP_DSS_ROT_270:
1240 case OMAP_DSS_ROT_0:
1243 case OMAP_DSS_ROT_90:
1246 case OMAP_DSS_ROT_180:
1249 case OMAP_DSS_ROT_270:
1255 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1257 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1258 REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
1260 REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
1262 REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
1263 REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
1267 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1269 switch (color_mode) {
1270 case OMAP_DSS_COLOR_CLUT1:
1272 case OMAP_DSS_COLOR_CLUT2:
1274 case OMAP_DSS_COLOR_CLUT4:
1276 case OMAP_DSS_COLOR_CLUT8:
1278 case OMAP_DSS_COLOR_RGB12U:
1279 case OMAP_DSS_COLOR_RGB16:
1280 case OMAP_DSS_COLOR_ARGB16:
1281 case OMAP_DSS_COLOR_YUV2:
1282 case OMAP_DSS_COLOR_UYVY:
1284 case OMAP_DSS_COLOR_RGB24P:
1286 case OMAP_DSS_COLOR_RGB24U:
1287 case OMAP_DSS_COLOR_ARGB32:
1288 case OMAP_DSS_COLOR_RGBA32:
1289 case OMAP_DSS_COLOR_RGBX32:
1296 static s32 pixinc(int pixels, u8 ps)
1300 else if (pixels > 1)
1301 return 1 + (pixels - 1) * ps;
1302 else if (pixels < 0)
1303 return 1 - (-pixels + 1) * ps;
1308 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1310 u16 width, u16 height,
1311 enum omap_color_mode color_mode, bool fieldmode,
1312 unsigned int field_offset,
1313 unsigned *offset0, unsigned *offset1,
1314 s32 *row_inc, s32 *pix_inc)
1318 /* FIXME CLUT formats */
1319 switch (color_mode) {
1320 case OMAP_DSS_COLOR_CLUT1:
1321 case OMAP_DSS_COLOR_CLUT2:
1322 case OMAP_DSS_COLOR_CLUT4:
1323 case OMAP_DSS_COLOR_CLUT8:
1326 case OMAP_DSS_COLOR_YUV2:
1327 case OMAP_DSS_COLOR_UYVY:
1331 ps = color_mode_to_bpp(color_mode) / 8;
1335 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1339 * field 0 = even field = bottom field
1340 * field 1 = odd field = top field
1342 switch (rotation + mirror * 4) {
1343 case OMAP_DSS_ROT_0:
1344 case OMAP_DSS_ROT_180:
1346 * If the pixel format is YUV or UYVY divide the width
1347 * of the image by 2 for 0 and 180 degree rotation.
1349 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1350 color_mode == OMAP_DSS_COLOR_UYVY)
1352 case OMAP_DSS_ROT_90:
1353 case OMAP_DSS_ROT_270:
1356 *offset0 = field_offset * screen_width * ps;
1360 *row_inc = pixinc(1 + (screen_width - width) +
1361 (fieldmode ? screen_width : 0),
1363 *pix_inc = pixinc(1, ps);
1366 case OMAP_DSS_ROT_0 + 4:
1367 case OMAP_DSS_ROT_180 + 4:
1368 /* If the pixel format is YUV or UYVY divide the width
1369 * of the image by 2 for 0 degree and 180 degree
1371 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1372 color_mode == OMAP_DSS_COLOR_UYVY)
1374 case OMAP_DSS_ROT_90 + 4:
1375 case OMAP_DSS_ROT_270 + 4:
1378 *offset0 = field_offset * screen_width * ps;
1381 *row_inc = pixinc(1 - (screen_width + width) -
1382 (fieldmode ? screen_width : 0),
1384 *pix_inc = pixinc(1, ps);
1392 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1394 u16 width, u16 height,
1395 enum omap_color_mode color_mode, bool fieldmode,
1396 unsigned int field_offset,
1397 unsigned *offset0, unsigned *offset1,
1398 s32 *row_inc, s32 *pix_inc)
1403 /* FIXME CLUT formats */
1404 switch (color_mode) {
1405 case OMAP_DSS_COLOR_CLUT1:
1406 case OMAP_DSS_COLOR_CLUT2:
1407 case OMAP_DSS_COLOR_CLUT4:
1408 case OMAP_DSS_COLOR_CLUT8:
1412 ps = color_mode_to_bpp(color_mode) / 8;
1416 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1419 /* width & height are overlay sizes, convert to fb sizes */
1421 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1430 * field 0 = even field = bottom field
1431 * field 1 = odd field = top field
1433 switch (rotation + mirror * 4) {
1434 case OMAP_DSS_ROT_0:
1437 *offset0 = *offset1 + field_offset * screen_width * ps;
1439 *offset0 = *offset1;
1440 *row_inc = pixinc(1 + (screen_width - fbw) +
1441 (fieldmode ? screen_width : 0),
1443 *pix_inc = pixinc(1, ps);
1445 case OMAP_DSS_ROT_90:
1446 *offset1 = screen_width * (fbh - 1) * ps;
1448 *offset0 = *offset1 + field_offset * ps;
1450 *offset0 = *offset1;
1451 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1452 (fieldmode ? 1 : 0), ps);
1453 *pix_inc = pixinc(-screen_width, ps);
1455 case OMAP_DSS_ROT_180:
1456 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1458 *offset0 = *offset1 - field_offset * screen_width * ps;
1460 *offset0 = *offset1;
1461 *row_inc = pixinc(-1 -
1462 (screen_width - fbw) -
1463 (fieldmode ? screen_width : 0),
1465 *pix_inc = pixinc(-1, ps);
1467 case OMAP_DSS_ROT_270:
1468 *offset1 = (fbw - 1) * ps;
1470 *offset0 = *offset1 - field_offset * ps;
1472 *offset0 = *offset1;
1473 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1474 (fieldmode ? 1 : 0), ps);
1475 *pix_inc = pixinc(screen_width, ps);
1479 case OMAP_DSS_ROT_0 + 4:
1480 *offset1 = (fbw - 1) * ps;
1482 *offset0 = *offset1 + field_offset * screen_width * ps;
1484 *offset0 = *offset1;
1485 *row_inc = pixinc(screen_width * 2 - 1 +
1486 (fieldmode ? screen_width : 0),
1488 *pix_inc = pixinc(-1, ps);
1491 case OMAP_DSS_ROT_90 + 4:
1494 *offset0 = *offset1 + field_offset * ps;
1496 *offset0 = *offset1;
1497 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1498 (fieldmode ? 1 : 0),
1500 *pix_inc = pixinc(screen_width, ps);
1503 case OMAP_DSS_ROT_180 + 4:
1504 *offset1 = screen_width * (fbh - 1) * ps;
1506 *offset0 = *offset1 - field_offset * screen_width * ps;
1508 *offset0 = *offset1;
1509 *row_inc = pixinc(1 - screen_width * 2 -
1510 (fieldmode ? screen_width : 0),
1512 *pix_inc = pixinc(1, ps);
1515 case OMAP_DSS_ROT_270 + 4:
1516 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1518 *offset0 = *offset1 - field_offset * ps;
1520 *offset0 = *offset1;
1521 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1522 (fieldmode ? 1 : 0),
1524 *pix_inc = pixinc(-screen_width, ps);
1532 static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1533 u16 height, u16 out_width, u16 out_height,
1534 enum omap_color_mode color_mode)
1537 /* FIXME venc pclk? */
1538 u64 tmp, pclk = dispc_pclk_rate(channel);
1540 if (height > out_height) {
1541 /* FIXME get real display PPL */
1542 unsigned int ppl = 800;
1544 tmp = pclk * height * out_width;
1545 do_div(tmp, 2 * out_height * ppl);
1548 if (height > 2 * out_height) {
1549 if (ppl == out_width)
1552 tmp = pclk * (height - 2 * out_height) * out_width;
1553 do_div(tmp, 2 * out_height * (ppl - out_width));
1554 fclk = max(fclk, (u32) tmp);
1558 if (width > out_width) {
1560 do_div(tmp, out_width);
1561 fclk = max(fclk, (u32) tmp);
1563 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1570 static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1571 u16 height, u16 out_width, u16 out_height)
1573 unsigned int hf, vf;
1576 * FIXME how to determine the 'A' factor
1577 * for the no downscaling case ?
1580 if (width > 3 * out_width)
1582 else if (width > 2 * out_width)
1584 else if (width > out_width)
1589 if (height > out_height)
1594 /* FIXME venc pclk? */
1595 return dispc_pclk_rate(channel) * vf * hf;
1598 void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
1601 _dispc_set_channel_out(plane, channel_out);
1605 static int _dispc_setup_plane(enum omap_plane plane,
1606 u32 paddr, u16 screen_width,
1607 u16 pos_x, u16 pos_y,
1608 u16 width, u16 height,
1609 u16 out_width, u16 out_height,
1610 enum omap_color_mode color_mode,
1612 enum omap_dss_rotation_type rotation_type,
1613 u8 rotation, int mirror,
1614 u8 global_alpha, u8 pre_mult_alpha,
1615 enum omap_channel channel)
1617 const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1621 unsigned offset0, offset1;
1624 u16 frame_height = height;
1625 unsigned int field_offset = 0;
1630 if (ilace && height == out_height)
1639 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1641 height, pos_y, out_height);
1644 if (!dss_feat_color_mode_supported(plane, color_mode))
1647 if (plane == OMAP_DSS_GFX) {
1648 if (width != out_width || height != out_height)
1653 unsigned long fclk = 0;
1655 if (out_width < width / maxdownscale ||
1656 out_width > width * 8)
1659 if (out_height < height / maxdownscale ||
1660 out_height > height * 8)
1663 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1664 color_mode == OMAP_DSS_COLOR_UYVY)
1667 /* Must use 5-tap filter? */
1668 five_taps = height > out_height * 2;
1671 fclk = calc_fclk(channel, width, height, out_width,
1674 /* Try 5-tap filter if 3-tap fclk is too high */
1675 if (cpu_is_omap34xx() && height > out_height &&
1676 fclk > dispc_fclk_rate())
1680 if (width > (2048 >> five_taps)) {
1681 DSSERR("failed to set up scaling, fclk too low\n");
1686 fclk = calc_fclk_five_taps(channel, width, height,
1687 out_width, out_height, color_mode);
1689 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1690 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1692 if (!fclk || fclk > dispc_fclk_rate()) {
1693 DSSERR("failed to set up scaling, "
1694 "required fclk rate = %lu Hz, "
1695 "current fclk rate = %lu Hz\n",
1696 fclk, dispc_fclk_rate());
1701 if (ilace && !fieldmode) {
1703 * when downscaling the bottom field may have to start several
1704 * source lines below the top field. Unfortunately ACCUI
1705 * registers will only hold the fractional part of the offset
1706 * so the integer part must be added to the base address of the
1709 if (!height || height == out_height)
1712 field_offset = height / out_height / 2;
1715 /* Fields are independent but interleaved in memory. */
1719 if (rotation_type == OMAP_DSS_ROT_DMA)
1720 calc_dma_rotation_offset(rotation, mirror,
1721 screen_width, width, frame_height, color_mode,
1722 fieldmode, field_offset,
1723 &offset0, &offset1, &row_inc, &pix_inc);
1725 calc_vrfb_rotation_offset(rotation, mirror,
1726 screen_width, width, frame_height, color_mode,
1727 fieldmode, field_offset,
1728 &offset0, &offset1, &row_inc, &pix_inc);
1730 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1731 offset0, offset1, row_inc, pix_inc);
1733 _dispc_set_color_mode(plane, color_mode);
1735 _dispc_set_plane_ba0(plane, paddr + offset0);
1736 _dispc_set_plane_ba1(plane, paddr + offset1);
1738 _dispc_set_row_inc(plane, row_inc);
1739 _dispc_set_pix_inc(plane, pix_inc);
1741 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1742 out_width, out_height);
1744 _dispc_set_plane_pos(plane, pos_x, pos_y);
1746 _dispc_set_pic_size(plane, width, height);
1748 if (plane != OMAP_DSS_GFX) {
1749 _dispc_set_scaling(plane, width, height,
1750 out_width, out_height,
1751 ilace, five_taps, fieldmode);
1752 _dispc_set_vid_size(plane, out_width, out_height);
1753 _dispc_set_vid_color_conv(plane, cconv);
1756 _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1758 _dispc_set_pre_mult_alpha(plane, pre_mult_alpha);
1759 _dispc_setup_global_alpha(plane, global_alpha);
1764 static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1766 REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1769 static void dispc_disable_isr(void *data, u32 mask)
1771 struct completion *compl = data;
1775 static void _enable_lcd_out(enum omap_channel channel, bool enable)
1777 if (channel == OMAP_DSS_CHANNEL_LCD2)
1778 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1780 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1783 static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
1785 struct completion frame_done_completion;
1792 /* When we disable LCD output, we need to wait until frame is done.
1793 * Otherwise the DSS is still working, and turning off the clocks
1794 * prevents DSS from going to OFF mode */
1795 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1796 REG_GET(DISPC_CONTROL2, 0, 0) :
1797 REG_GET(DISPC_CONTROL, 0, 0);
1799 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1800 DISPC_IRQ_FRAMEDONE;
1802 if (!enable && is_on) {
1803 init_completion(&frame_done_completion);
1805 r = omap_dispc_register_isr(dispc_disable_isr,
1806 &frame_done_completion, irq);
1809 DSSERR("failed to register FRAMEDONE isr\n");
1812 _enable_lcd_out(channel, enable);
1814 if (!enable && is_on) {
1815 if (!wait_for_completion_timeout(&frame_done_completion,
1816 msecs_to_jiffies(100)))
1817 DSSERR("timeout waiting for FRAME DONE\n");
1819 r = omap_dispc_unregister_isr(dispc_disable_isr,
1820 &frame_done_completion, irq);
1823 DSSERR("failed to unregister FRAMEDONE isr\n");
1829 static void _enable_digit_out(bool enable)
1831 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1834 static void dispc_enable_digit_out(bool enable)
1836 struct completion frame_done_completion;
1841 if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1847 unsigned long flags;
1848 /* When we enable digit output, we'll get an extra digit
1849 * sync lost interrupt, that we need to ignore */
1850 spin_lock_irqsave(&dispc.irq_lock, flags);
1851 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1852 _omap_dispc_set_irqs();
1853 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1856 /* When we disable digit output, we need to wait until fields are done.
1857 * Otherwise the DSS is still working, and turning off the clocks
1858 * prevents DSS from going to OFF mode. And when enabling, we need to
1859 * wait for the extra sync losts */
1860 init_completion(&frame_done_completion);
1862 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1863 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1865 DSSERR("failed to register EVSYNC isr\n");
1867 _enable_digit_out(enable);
1869 /* XXX I understand from TRM that we should only wait for the
1870 * current field to complete. But it seems we have to wait
1871 * for both fields */
1872 if (!wait_for_completion_timeout(&frame_done_completion,
1873 msecs_to_jiffies(100)))
1874 DSSERR("timeout waiting for EVSYNC\n");
1876 if (!wait_for_completion_timeout(&frame_done_completion,
1877 msecs_to_jiffies(100)))
1878 DSSERR("timeout waiting for EVSYNC\n");
1880 r = omap_dispc_unregister_isr(dispc_disable_isr,
1881 &frame_done_completion,
1882 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1884 DSSERR("failed to unregister EVSYNC isr\n");
1887 unsigned long flags;
1888 spin_lock_irqsave(&dispc.irq_lock, flags);
1889 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
1890 if (dss_has_feature(FEAT_MGR_LCD2))
1891 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
1892 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1893 _omap_dispc_set_irqs();
1894 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1900 bool dispc_is_channel_enabled(enum omap_channel channel)
1902 if (channel == OMAP_DSS_CHANNEL_LCD)
1903 return !!REG_GET(DISPC_CONTROL, 0, 0);
1904 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1905 return !!REG_GET(DISPC_CONTROL, 1, 1);
1906 else if (channel == OMAP_DSS_CHANNEL_LCD2)
1907 return !!REG_GET(DISPC_CONTROL2, 0, 0);
1912 void dispc_enable_channel(enum omap_channel channel, bool enable)
1914 if (channel == OMAP_DSS_CHANNEL_LCD ||
1915 channel == OMAP_DSS_CHANNEL_LCD2)
1916 dispc_enable_lcd_out(channel, enable);
1917 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1918 dispc_enable_digit_out(enable);
1923 void dispc_lcd_enable_signal_polarity(bool act_high)
1925 if (!dss_has_feature(FEAT_LCDENABLEPOL))
1929 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1933 void dispc_lcd_enable_signal(bool enable)
1935 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
1939 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1943 void dispc_pck_free_enable(bool enable)
1945 if (!dss_has_feature(FEAT_PCKFREEENABLE))
1949 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1953 void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
1956 if (channel == OMAP_DSS_CHANNEL_LCD2)
1957 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
1959 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
1964 void dispc_set_lcd_display_type(enum omap_channel channel,
1965 enum omap_lcd_display_type type)
1970 case OMAP_DSS_LCD_DISPLAY_STN:
1974 case OMAP_DSS_LCD_DISPLAY_TFT:
1984 if (channel == OMAP_DSS_CHANNEL_LCD2)
1985 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
1987 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
1991 void dispc_set_loadmode(enum omap_dss_load_mode mode)
1994 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1999 void dispc_set_default_color(enum omap_channel channel, u32 color)
2002 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2006 u32 dispc_get_default_color(enum omap_channel channel)
2010 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2011 channel != OMAP_DSS_CHANNEL_LCD &&
2012 channel != OMAP_DSS_CHANNEL_LCD2);
2015 l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
2021 void dispc_set_trans_key(enum omap_channel ch,
2022 enum omap_dss_trans_key_type type,
2026 if (ch == OMAP_DSS_CHANNEL_LCD)
2027 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2028 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2029 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2030 else /* OMAP_DSS_CHANNEL_LCD2 */
2031 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
2033 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2037 void dispc_get_trans_key(enum omap_channel ch,
2038 enum omap_dss_trans_key_type *type,
2043 if (ch == OMAP_DSS_CHANNEL_LCD)
2044 *type = REG_GET(DISPC_CONFIG, 11, 11);
2045 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2046 *type = REG_GET(DISPC_CONFIG, 13, 13);
2047 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2048 *type = REG_GET(DISPC_CONFIG2, 11, 11);
2054 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
2058 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
2061 if (ch == OMAP_DSS_CHANNEL_LCD)
2062 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2063 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2064 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2065 else /* OMAP_DSS_CHANNEL_LCD2 */
2066 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
2069 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
2071 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2075 if (ch == OMAP_DSS_CHANNEL_LCD)
2076 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2077 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2078 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2079 else /* OMAP_DSS_CHANNEL_LCD2 */
2080 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
2083 bool dispc_alpha_blending_enabled(enum omap_channel ch)
2087 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2091 if (ch == OMAP_DSS_CHANNEL_LCD)
2092 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2093 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2094 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2095 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2096 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
2105 bool dispc_trans_key_enabled(enum omap_channel ch)
2110 if (ch == OMAP_DSS_CHANNEL_LCD)
2111 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2112 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2113 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2114 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2115 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
2124 void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2128 switch (data_lines) {
2147 if (channel == OMAP_DSS_CHANNEL_LCD2)
2148 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2150 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2154 void dispc_set_parallel_interface_mode(enum omap_channel channel,
2155 enum omap_parallel_interface_mode mode)
2163 case OMAP_DSS_PARALLELMODE_BYPASS:
2168 case OMAP_DSS_PARALLELMODE_RFBI:
2173 case OMAP_DSS_PARALLELMODE_DSI:
2185 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2186 l = dispc_read_reg(DISPC_CONTROL2);
2187 l = FLD_MOD(l, stallmode, 11, 11);
2188 dispc_write_reg(DISPC_CONTROL2, l);
2190 l = dispc_read_reg(DISPC_CONTROL);
2191 l = FLD_MOD(l, stallmode, 11, 11);
2192 l = FLD_MOD(l, gpout0, 15, 15);
2193 l = FLD_MOD(l, gpout1, 16, 16);
2194 dispc_write_reg(DISPC_CONTROL, l);
2200 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2201 int vsw, int vfp, int vbp)
2203 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2204 if (hsw < 1 || hsw > 64 ||
2205 hfp < 1 || hfp > 256 ||
2206 hbp < 1 || hbp > 256 ||
2207 vsw < 1 || vsw > 64 ||
2208 vfp < 0 || vfp > 255 ||
2209 vbp < 0 || vbp > 255)
2212 if (hsw < 1 || hsw > 256 ||
2213 hfp < 1 || hfp > 4096 ||
2214 hbp < 1 || hbp > 4096 ||
2215 vsw < 1 || vsw > 256 ||
2216 vfp < 0 || vfp > 4095 ||
2217 vbp < 0 || vbp > 4095)
2224 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2226 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2227 timings->hbp, timings->vsw,
2228 timings->vfp, timings->vbp);
2231 static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
2232 int hfp, int hbp, int vsw, int vfp, int vbp)
2234 u32 timing_h, timing_v;
2236 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2237 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2238 FLD_VAL(hbp-1, 27, 20);
2240 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2241 FLD_VAL(vbp, 27, 20);
2243 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2244 FLD_VAL(hbp-1, 31, 20);
2246 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2247 FLD_VAL(vbp, 31, 20);
2251 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2252 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2256 /* change name to mode? */
2257 void dispc_set_lcd_timings(enum omap_channel channel,
2258 struct omap_video_timings *timings)
2260 unsigned xtot, ytot;
2261 unsigned long ht, vt;
2263 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2264 timings->hbp, timings->vsw,
2265 timings->vfp, timings->vbp))
2268 _dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
2269 timings->hbp, timings->vsw, timings->vfp,
2272 dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
2274 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2275 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2277 ht = (timings->pixel_clock * 1000) / xtot;
2278 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2280 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2282 DSSDBG("pck %u\n", timings->pixel_clock);
2283 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2284 timings->hsw, timings->hfp, timings->hbp,
2285 timings->vsw, timings->vfp, timings->vbp);
2287 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2290 static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2293 BUG_ON(lck_div < 1);
2294 BUG_ON(pck_div < 2);
2297 dispc_write_reg(DISPC_DIVISOR(channel),
2298 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2302 static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2306 l = dispc_read_reg(DISPC_DIVISOR(channel));
2307 *lck_div = FLD_GET(l, 23, 16);
2308 *pck_div = FLD_GET(l, 7, 0);
2311 unsigned long dispc_fclk_rate(void)
2313 unsigned long r = 0;
2315 if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK)
2316 r = dss_clk_get_rate(DSS_CLK_FCK);
2318 #ifdef CONFIG_OMAP2_DSS_DSI
2319 r = dsi_get_dsi1_pll_rate();
2326 unsigned long dispc_lclk_rate(enum omap_channel channel)
2332 l = dispc_read_reg(DISPC_DIVISOR(channel));
2334 lcd = FLD_GET(l, 23, 16);
2336 r = dispc_fclk_rate();
2341 unsigned long dispc_pclk_rate(enum omap_channel channel)
2347 l = dispc_read_reg(DISPC_DIVISOR(channel));
2349 lcd = FLD_GET(l, 23, 16);
2350 pcd = FLD_GET(l, 7, 0);
2352 r = dispc_fclk_rate();
2354 return r / lcd / pcd;
2357 void dispc_dump_clocks(struct seq_file *s)
2363 seq_printf(s, "- DISPC -\n");
2365 seq_printf(s, "dispc fclk source = %s\n",
2366 dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
2367 "dss1_alwon_fclk" : "dsi1_pll_fclk");
2369 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2371 seq_printf(s, "- LCD1 -\n");
2373 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2375 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2376 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2377 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2378 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2379 if (dss_has_feature(FEAT_MGR_LCD2)) {
2380 seq_printf(s, "- LCD2 -\n");
2382 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
2384 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2385 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2386 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2387 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2392 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2393 void dispc_dump_irqs(struct seq_file *s)
2395 unsigned long flags;
2396 struct dispc_irq_stats stats;
2398 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2400 stats = dispc.irq_stats;
2401 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2402 dispc.irq_stats.last_reset = jiffies;
2404 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2406 seq_printf(s, "period %u ms\n",
2407 jiffies_to_msecs(jiffies - stats.last_reset));
2409 seq_printf(s, "irqs %d\n", stats.irq_count);
2411 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2417 PIS(ACBIAS_COUNT_STAT);
2419 PIS(GFX_FIFO_UNDERFLOW);
2421 PIS(PAL_GAMMA_MASK);
2423 PIS(VID1_FIFO_UNDERFLOW);
2425 PIS(VID2_FIFO_UNDERFLOW);
2428 PIS(SYNC_LOST_DIGIT);
2430 if (dss_has_feature(FEAT_MGR_LCD2)) {
2433 PIS(ACBIAS_COUNT_STAT2);
2440 void dispc_dump_regs(struct seq_file *s)
2442 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
2444 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
2446 DUMPREG(DISPC_REVISION);
2447 DUMPREG(DISPC_SYSCONFIG);
2448 DUMPREG(DISPC_SYSSTATUS);
2449 DUMPREG(DISPC_IRQSTATUS);
2450 DUMPREG(DISPC_IRQENABLE);
2451 DUMPREG(DISPC_CONTROL);
2452 DUMPREG(DISPC_CONFIG);
2453 DUMPREG(DISPC_CAPABLE);
2454 DUMPREG(DISPC_DEFAULT_COLOR(0));
2455 DUMPREG(DISPC_DEFAULT_COLOR(1));
2456 DUMPREG(DISPC_TRANS_COLOR(0));
2457 DUMPREG(DISPC_TRANS_COLOR(1));
2458 DUMPREG(DISPC_LINE_STATUS);
2459 DUMPREG(DISPC_LINE_NUMBER);
2460 DUMPREG(DISPC_TIMING_H(0));
2461 DUMPREG(DISPC_TIMING_V(0));
2462 DUMPREG(DISPC_POL_FREQ(0));
2463 DUMPREG(DISPC_DIVISOR(0));
2464 DUMPREG(DISPC_GLOBAL_ALPHA);
2465 DUMPREG(DISPC_SIZE_DIG);
2466 DUMPREG(DISPC_SIZE_LCD(0));
2467 if (dss_has_feature(FEAT_MGR_LCD2)) {
2468 DUMPREG(DISPC_CONTROL2);
2469 DUMPREG(DISPC_CONFIG2);
2470 DUMPREG(DISPC_DEFAULT_COLOR(2));
2471 DUMPREG(DISPC_TRANS_COLOR(2));
2472 DUMPREG(DISPC_TIMING_H(2));
2473 DUMPREG(DISPC_TIMING_V(2));
2474 DUMPREG(DISPC_POL_FREQ(2));
2475 DUMPREG(DISPC_DIVISOR(2));
2476 DUMPREG(DISPC_SIZE_LCD(2));
2479 DUMPREG(DISPC_GFX_BA0);
2480 DUMPREG(DISPC_GFX_BA1);
2481 DUMPREG(DISPC_GFX_POSITION);
2482 DUMPREG(DISPC_GFX_SIZE);
2483 DUMPREG(DISPC_GFX_ATTRIBUTES);
2484 DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
2485 DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
2486 DUMPREG(DISPC_GFX_ROW_INC);
2487 DUMPREG(DISPC_GFX_PIXEL_INC);
2488 DUMPREG(DISPC_GFX_WINDOW_SKIP);
2489 DUMPREG(DISPC_GFX_TABLE_BA);
2491 DUMPREG(DISPC_DATA_CYCLE1(0));
2492 DUMPREG(DISPC_DATA_CYCLE2(0));
2493 DUMPREG(DISPC_DATA_CYCLE3(0));
2495 DUMPREG(DISPC_CPR_COEF_R(0));
2496 DUMPREG(DISPC_CPR_COEF_G(0));
2497 DUMPREG(DISPC_CPR_COEF_B(0));
2498 if (dss_has_feature(FEAT_MGR_LCD2)) {
2499 DUMPREG(DISPC_DATA_CYCLE1(2));
2500 DUMPREG(DISPC_DATA_CYCLE2(2));
2501 DUMPREG(DISPC_DATA_CYCLE3(2));
2503 DUMPREG(DISPC_CPR_COEF_R(2));
2504 DUMPREG(DISPC_CPR_COEF_G(2));
2505 DUMPREG(DISPC_CPR_COEF_B(2));
2508 DUMPREG(DISPC_GFX_PRELOAD);
2510 DUMPREG(DISPC_VID_BA0(0));
2511 DUMPREG(DISPC_VID_BA1(0));
2512 DUMPREG(DISPC_VID_POSITION(0));
2513 DUMPREG(DISPC_VID_SIZE(0));
2514 DUMPREG(DISPC_VID_ATTRIBUTES(0));
2515 DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
2516 DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
2517 DUMPREG(DISPC_VID_ROW_INC(0));
2518 DUMPREG(DISPC_VID_PIXEL_INC(0));
2519 DUMPREG(DISPC_VID_FIR(0));
2520 DUMPREG(DISPC_VID_PICTURE_SIZE(0));
2521 DUMPREG(DISPC_VID_ACCU0(0));
2522 DUMPREG(DISPC_VID_ACCU1(0));
2524 DUMPREG(DISPC_VID_BA0(1));
2525 DUMPREG(DISPC_VID_BA1(1));
2526 DUMPREG(DISPC_VID_POSITION(1));
2527 DUMPREG(DISPC_VID_SIZE(1));
2528 DUMPREG(DISPC_VID_ATTRIBUTES(1));
2529 DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
2530 DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
2531 DUMPREG(DISPC_VID_ROW_INC(1));
2532 DUMPREG(DISPC_VID_PIXEL_INC(1));
2533 DUMPREG(DISPC_VID_FIR(1));
2534 DUMPREG(DISPC_VID_PICTURE_SIZE(1));
2535 DUMPREG(DISPC_VID_ACCU0(1));
2536 DUMPREG(DISPC_VID_ACCU1(1));
2538 DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
2539 DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
2540 DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
2541 DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
2542 DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
2543 DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
2544 DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
2545 DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
2546 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
2547 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
2548 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
2549 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
2550 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
2551 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
2552 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
2553 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
2554 DUMPREG(DISPC_VID_CONV_COEF(0, 0));
2555 DUMPREG(DISPC_VID_CONV_COEF(0, 1));
2556 DUMPREG(DISPC_VID_CONV_COEF(0, 2));
2557 DUMPREG(DISPC_VID_CONV_COEF(0, 3));
2558 DUMPREG(DISPC_VID_CONV_COEF(0, 4));
2559 DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
2560 DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
2561 DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
2562 DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
2563 DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
2564 DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
2565 DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
2566 DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
2568 DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2569 DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2570 DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2571 DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2572 DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2573 DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2574 DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2575 DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2576 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2577 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2578 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2579 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2580 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2581 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2582 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2583 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2584 DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2585 DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2586 DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2587 DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2588 DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2589 DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2590 DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2591 DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2592 DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2593 DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2594 DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2595 DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2596 DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2598 DUMPREG(DISPC_VID_PRELOAD(0));
2599 DUMPREG(DISPC_VID_PRELOAD(1));
2601 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
2605 static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
2606 bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, u8 acb)
2610 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2611 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2613 l |= FLD_VAL(onoff, 17, 17);
2614 l |= FLD_VAL(rf, 16, 16);
2615 l |= FLD_VAL(ieo, 15, 15);
2616 l |= FLD_VAL(ipc, 14, 14);
2617 l |= FLD_VAL(ihs, 13, 13);
2618 l |= FLD_VAL(ivs, 12, 12);
2619 l |= FLD_VAL(acbi, 11, 8);
2620 l |= FLD_VAL(acb, 7, 0);
2623 dispc_write_reg(DISPC_POL_FREQ(channel), l);
2627 void dispc_set_pol_freq(enum omap_channel channel,
2628 enum omap_panel_config config, u8 acbi, u8 acb)
2630 _dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
2631 (config & OMAP_DSS_LCD_RF) != 0,
2632 (config & OMAP_DSS_LCD_IEO) != 0,
2633 (config & OMAP_DSS_LCD_IPC) != 0,
2634 (config & OMAP_DSS_LCD_IHS) != 0,
2635 (config & OMAP_DSS_LCD_IVS) != 0,
2639 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2640 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2641 struct dispc_clock_info *cinfo)
2643 u16 pcd_min = is_tft ? 2 : 3;
2644 unsigned long best_pck;
2645 u16 best_ld, cur_ld;
2646 u16 best_pd, cur_pd;
2652 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2653 unsigned long lck = fck / cur_ld;
2655 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2656 unsigned long pck = lck / cur_pd;
2657 long old_delta = abs(best_pck - req_pck);
2658 long new_delta = abs(pck - req_pck);
2660 if (best_pck == 0 || new_delta < old_delta) {
2673 if (lck / pcd_min < req_pck)
2678 cinfo->lck_div = best_ld;
2679 cinfo->pck_div = best_pd;
2680 cinfo->lck = fck / cinfo->lck_div;
2681 cinfo->pck = cinfo->lck / cinfo->pck_div;
2684 /* calculate clock rates using dividers in cinfo */
2685 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2686 struct dispc_clock_info *cinfo)
2688 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2690 if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2693 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2694 cinfo->pck = cinfo->lck / cinfo->pck_div;
2699 int dispc_set_clock_div(enum omap_channel channel,
2700 struct dispc_clock_info *cinfo)
2702 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2703 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2705 dispc_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
2710 int dispc_get_clock_div(enum omap_channel channel,
2711 struct dispc_clock_info *cinfo)
2715 fck = dispc_fclk_rate();
2717 cinfo->lck_div = REG_GET(DISPC_DIVISOR(channel), 23, 16);
2718 cinfo->pck_div = REG_GET(DISPC_DIVISOR(channel), 7, 0);
2720 cinfo->lck = fck / cinfo->lck_div;
2721 cinfo->pck = cinfo->lck / cinfo->pck_div;
2726 /* dispc.irq_lock has to be locked by the caller */
2727 static void _omap_dispc_set_irqs(void)
2732 struct omap_dispc_isr_data *isr_data;
2734 mask = dispc.irq_error_mask;
2736 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2737 isr_data = &dispc.registered_isr[i];
2739 if (isr_data->isr == NULL)
2742 mask |= isr_data->mask;
2747 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2748 /* clear the irqstatus for newly enabled irqs */
2749 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2751 dispc_write_reg(DISPC_IRQENABLE, mask);
2756 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2760 unsigned long flags;
2761 struct omap_dispc_isr_data *isr_data;
2766 spin_lock_irqsave(&dispc.irq_lock, flags);
2768 /* check for duplicate entry */
2769 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2770 isr_data = &dispc.registered_isr[i];
2771 if (isr_data->isr == isr && isr_data->arg == arg &&
2772 isr_data->mask == mask) {
2781 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2782 isr_data = &dispc.registered_isr[i];
2784 if (isr_data->isr != NULL)
2787 isr_data->isr = isr;
2788 isr_data->arg = arg;
2789 isr_data->mask = mask;
2795 _omap_dispc_set_irqs();
2797 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2801 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2805 EXPORT_SYMBOL(omap_dispc_register_isr);
2807 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2810 unsigned long flags;
2812 struct omap_dispc_isr_data *isr_data;
2814 spin_lock_irqsave(&dispc.irq_lock, flags);
2816 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2817 isr_data = &dispc.registered_isr[i];
2818 if (isr_data->isr != isr || isr_data->arg != arg ||
2819 isr_data->mask != mask)
2822 /* found the correct isr */
2824 isr_data->isr = NULL;
2825 isr_data->arg = NULL;
2833 _omap_dispc_set_irqs();
2835 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2839 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2842 static void print_irq_status(u32 status)
2844 if ((status & dispc.irq_error_mask) == 0)
2847 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2850 if (status & DISPC_IRQ_##x) \
2852 PIS(GFX_FIFO_UNDERFLOW);
2854 PIS(VID1_FIFO_UNDERFLOW);
2855 PIS(VID2_FIFO_UNDERFLOW);
2857 PIS(SYNC_LOST_DIGIT);
2858 if (dss_has_feature(FEAT_MGR_LCD2))
2866 /* Called from dss.c. Note that we don't touch clocks here,
2867 * but we presume they are on because we got an IRQ. However,
2868 * an irq handler may turn the clocks off, so we may not have
2869 * clock later in the function. */
2870 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
2873 u32 irqstatus, irqenable;
2874 u32 handledirqs = 0;
2875 u32 unhandled_errors;
2876 struct omap_dispc_isr_data *isr_data;
2877 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2879 spin_lock(&dispc.irq_lock);
2881 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2882 irqenable = dispc_read_reg(DISPC_IRQENABLE);
2884 /* IRQ is not for us */
2885 if (!(irqstatus & irqenable)) {
2886 spin_unlock(&dispc.irq_lock);
2890 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2891 spin_lock(&dispc.irq_stats_lock);
2892 dispc.irq_stats.irq_count++;
2893 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2894 spin_unlock(&dispc.irq_stats_lock);
2899 print_irq_status(irqstatus);
2901 /* Ack the interrupt. Do it here before clocks are possibly turned
2903 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2904 /* flush posted write */
2905 dispc_read_reg(DISPC_IRQSTATUS);
2907 /* make a copy and unlock, so that isrs can unregister
2909 memcpy(registered_isr, dispc.registered_isr,
2910 sizeof(registered_isr));
2912 spin_unlock(&dispc.irq_lock);
2914 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2915 isr_data = ®istered_isr[i];
2920 if (isr_data->mask & irqstatus) {
2921 isr_data->isr(isr_data->arg, irqstatus);
2922 handledirqs |= isr_data->mask;
2926 spin_lock(&dispc.irq_lock);
2928 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2930 if (unhandled_errors) {
2931 dispc.error_irqs |= unhandled_errors;
2933 dispc.irq_error_mask &= ~unhandled_errors;
2934 _omap_dispc_set_irqs();
2936 schedule_work(&dispc.error_work);
2939 spin_unlock(&dispc.irq_lock);
2944 static void dispc_error_worker(struct work_struct *work)
2948 unsigned long flags;
2950 spin_lock_irqsave(&dispc.irq_lock, flags);
2951 errors = dispc.error_irqs;
2952 dispc.error_irqs = 0;
2953 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2955 if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2956 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2957 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2958 struct omap_overlay *ovl;
2959 ovl = omap_dss_get_overlay(i);
2961 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2965 dispc_enable_plane(ovl->id, 0);
2966 dispc_go(ovl->manager->id);
2973 if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2974 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2975 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2976 struct omap_overlay *ovl;
2977 ovl = omap_dss_get_overlay(i);
2979 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2983 dispc_enable_plane(ovl->id, 0);
2984 dispc_go(ovl->manager->id);
2991 if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
2992 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
2993 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2994 struct omap_overlay *ovl;
2995 ovl = omap_dss_get_overlay(i);
2997 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3001 dispc_enable_plane(ovl->id, 0);
3002 dispc_go(ovl->manager->id);
3009 if (errors & DISPC_IRQ_SYNC_LOST) {
3010 struct omap_overlay_manager *manager = NULL;
3011 bool enable = false;
3013 DSSERR("SYNC_LOST, disabling LCD\n");
3015 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3016 struct omap_overlay_manager *mgr;
3017 mgr = omap_dss_get_overlay_manager(i);
3019 if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
3021 enable = mgr->device->state ==
3022 OMAP_DSS_DISPLAY_ACTIVE;
3023 mgr->device->driver->disable(mgr->device);
3029 struct omap_dss_device *dssdev = manager->device;
3030 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3031 struct omap_overlay *ovl;
3032 ovl = omap_dss_get_overlay(i);
3034 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3037 if (ovl->id != 0 && ovl->manager == manager)
3038 dispc_enable_plane(ovl->id, 0);
3041 dispc_go(manager->id);
3044 dssdev->driver->enable(dssdev);
3048 if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
3049 struct omap_overlay_manager *manager = NULL;
3050 bool enable = false;
3052 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
3054 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3055 struct omap_overlay_manager *mgr;
3056 mgr = omap_dss_get_overlay_manager(i);
3058 if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
3060 enable = mgr->device->state ==
3061 OMAP_DSS_DISPLAY_ACTIVE;
3062 mgr->device->driver->disable(mgr->device);
3068 struct omap_dss_device *dssdev = manager->device;
3069 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3070 struct omap_overlay *ovl;
3071 ovl = omap_dss_get_overlay(i);
3073 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3076 if (ovl->id != 0 && ovl->manager == manager)
3077 dispc_enable_plane(ovl->id, 0);
3080 dispc_go(manager->id);
3083 dssdev->driver->enable(dssdev);
3087 if (errors & DISPC_IRQ_SYNC_LOST2) {
3088 struct omap_overlay_manager *manager = NULL;
3089 bool enable = false;
3091 DSSERR("SYNC_LOST for LCD2, disabling LCD2\n");
3093 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3094 struct omap_overlay_manager *mgr;
3095 mgr = omap_dss_get_overlay_manager(i);
3097 if (mgr->id == OMAP_DSS_CHANNEL_LCD2) {
3099 enable = mgr->device->state ==
3100 OMAP_DSS_DISPLAY_ACTIVE;
3101 mgr->device->driver->disable(mgr->device);
3107 struct omap_dss_device *dssdev = manager->device;
3108 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3109 struct omap_overlay *ovl;
3110 ovl = omap_dss_get_overlay(i);
3112 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3115 if (ovl->id != 0 && ovl->manager == manager)
3116 dispc_enable_plane(ovl->id, 0);
3119 dispc_go(manager->id);
3122 dssdev->driver->enable(dssdev);
3126 if (errors & DISPC_IRQ_OCP_ERR) {
3127 DSSERR("OCP_ERR\n");
3128 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3129 struct omap_overlay_manager *mgr;
3130 mgr = omap_dss_get_overlay_manager(i);
3132 if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
3133 mgr->device->driver->disable(mgr->device);
3137 spin_lock_irqsave(&dispc.irq_lock, flags);
3138 dispc.irq_error_mask |= errors;
3139 _omap_dispc_set_irqs();
3140 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3143 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3145 void dispc_irq_wait_handler(void *data, u32 mask)
3147 complete((struct completion *)data);
3151 DECLARE_COMPLETION_ONSTACK(completion);
3153 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3159 timeout = wait_for_completion_timeout(&completion, timeout);
3161 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3166 if (timeout == -ERESTARTSYS)
3167 return -ERESTARTSYS;
3172 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3173 unsigned long timeout)
3175 void dispc_irq_wait_handler(void *data, u32 mask)
3177 complete((struct completion *)data);
3181 DECLARE_COMPLETION_ONSTACK(completion);
3183 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3189 timeout = wait_for_completion_interruptible_timeout(&completion,
3192 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3197 if (timeout == -ERESTARTSYS)
3198 return -ERESTARTSYS;
3203 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3204 void dispc_fake_vsync_irq(void)
3206 u32 irqstatus = DISPC_IRQ_VSYNC;
3209 WARN_ON(!in_interrupt());
3211 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3212 struct omap_dispc_isr_data *isr_data;
3213 isr_data = &dispc.registered_isr[i];
3218 if (isr_data->mask & irqstatus)
3219 isr_data->isr(isr_data->arg, irqstatus);
3224 static void _omap_dispc_initialize_irq(void)
3226 unsigned long flags;
3228 spin_lock_irqsave(&dispc.irq_lock, flags);
3230 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3232 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3233 if (dss_has_feature(FEAT_MGR_LCD2))
3234 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3236 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3238 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3240 _omap_dispc_set_irqs();
3242 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3245 void dispc_enable_sidle(void)
3247 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3250 void dispc_disable_sidle(void)
3252 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3255 static void _omap_dispc_initial_config(void)
3259 l = dispc_read_reg(DISPC_SYSCONFIG);
3260 l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */
3261 l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */
3262 l = FLD_MOD(l, 1, 2, 2); /* ENWAKEUP */
3263 l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */
3264 dispc_write_reg(DISPC_SYSCONFIG, l);
3267 if (dss_has_feature(FEAT_FUNCGATED))
3268 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3270 /* L3 firewall setting: enable access to OCM RAM */
3271 /* XXX this should be somewhere in plat-omap */
3272 if (cpu_is_omap24xx())
3273 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3275 _dispc_setup_color_conv_coef();
3277 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3279 dispc_read_plane_fifo_sizes();
3282 int dispc_enable_plane(enum omap_plane plane, bool enable)
3284 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3287 _dispc_enable_plane(plane, enable);
3293 int dispc_setup_plane(enum omap_plane plane,
3294 u32 paddr, u16 screen_width,
3295 u16 pos_x, u16 pos_y,
3296 u16 width, u16 height,
3297 u16 out_width, u16 out_height,
3298 enum omap_color_mode color_mode,
3300 enum omap_dss_rotation_type rotation_type,
3301 u8 rotation, bool mirror, u8 global_alpha,
3302 u8 pre_mult_alpha, enum omap_channel channel)
3306 DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
3307 "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
3308 plane, paddr, screen_width, pos_x, pos_y,
3310 out_width, out_height,
3312 rotation, mirror, channel);
3316 r = _dispc_setup_plane(plane,
3317 paddr, screen_width,
3320 out_width, out_height,
3325 pre_mult_alpha, channel);
3332 /* DISPC HW IP initialisation */
3333 static int omap_dispchw_probe(struct platform_device *pdev)
3337 struct resource *dispc_mem;
3341 spin_lock_init(&dispc.irq_lock);
3343 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3344 spin_lock_init(&dispc.irq_stats_lock);
3345 dispc.irq_stats.last_reset = jiffies;
3348 INIT_WORK(&dispc.error_work, dispc_error_worker);
3350 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3352 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3356 dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
3358 DSSERR("can't ioremap DISPC\n");
3362 dispc.irq = platform_get_irq(dispc.pdev, 0);
3363 if (dispc.irq < 0) {
3364 DSSERR("platform_get_irq failed\n");
3369 r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3370 "OMAP DISPC", dispc.pdev);
3372 DSSERR("request_irq failed\n");
3378 _omap_dispc_initial_config();
3380 _omap_dispc_initialize_irq();
3382 dispc_save_context();
3384 rev = dispc_read_reg(DISPC_REVISION);
3385 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3386 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3392 iounmap(dispc.base);
3397 static int omap_dispchw_remove(struct platform_device *pdev)
3399 free_irq(dispc.irq, dispc.pdev);
3400 iounmap(dispc.base);
3404 static struct platform_driver omap_dispchw_driver = {
3405 .probe = omap_dispchw_probe,
3406 .remove = omap_dispchw_remove,
3408 .name = "omapdss_dispc",
3409 .owner = THIS_MODULE,
3413 int dispc_init_platform_driver(void)
3415 return platform_driver_register(&omap_dispchw_driver);
3418 void dispc_uninit_platform_driver(void)
3420 return platform_driver_unregister(&omap_dispchw_driver);